diff options
29 files changed, 12387 insertions, 0 deletions
diff --git a/share/man/man4/Makefile b/share/man/man4/Makefile index ee2c4d1..33929ba 100644 --- a/share/man/man4/Makefile +++ b/share/man/man4/Makefile @@ -113,8 +113,10 @@ MAN= aac.4 \ ipfirewall.4 \ ips.4 \ ipsec.4 \ + ipw.4 \ isp.4 \ ispfw.4 \ + iwi.4 \ ixgb.4 \ joy.4 \ kame.4 \ @@ -236,6 +238,7 @@ MAN= aac.4 \ pt.4 \ pty.4 \ puc.4 \ + ral.4 \ random.4 \ rc.4 \ re.4 \ @@ -338,6 +341,7 @@ MAN= aac.4 \ ums.4 \ unix.4 \ uplcom.4 \ + ural.4 \ urio.4 \ usb.4 \ uscanner.4 \ @@ -410,6 +414,8 @@ MLINKS+=ip.4 rawip.4 MLINKS+=ipfirewall.4 ipaccounting.4 \ ipfirewall.4 ipacct.4 \ ipfirewall.4 ipfw.4 +MLINKS+=ipw.4 if_ipw.4 +MLINKS+=iwi.4 if_iwi.4 MLINKS+=kue.4 if_kue.4 MLINKS+=lge.4 if_lge.4 MLINKS+=lo.4 loop.4 @@ -428,6 +434,7 @@ MLINKS+=pcm.4 snd.4 \ MLINKS+=pcn.4 if_pcn.4 MLINKS+=pcvt.4 vt.4 MLINKS+=ppp.4 if_ppp.4 +MLINKS+=ral.4 if_ral.4 MLINKS+=re.4 if_re.4 MLINKS+=rl.4 if_rl.4 MLINKS+=rue.4 if_rue.4 @@ -454,6 +461,7 @@ MLINKS+=tun.4 if_tun.4 MLINKS+=tx.4 if_tx.4 MLINKS+=txp.4 if_txp.4 MLINKS+=udav.4 if_udav.4 +MLINKS+=ural.4 if_ural.4 MLINKS+=vge.4 if_vge.4 MLINKS+=vlan.4 if_vlan.4 MLINKS+=vpo.4 imm.4 diff --git a/share/man/man4/ipw.4 b/share/man/man4/ipw.4 new file mode 100644 index 0000000..e1f5750 --- /dev/null +++ b/share/man/man4/ipw.4 @@ -0,0 +1,94 @@ +.\" $FreeBSD$ +.\" +.\" Copyright (c) 2004 +.\" Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. +.\" +.\" Redistribution and use in source and binary forms, with or without +.\" modification, are permitted provided that the following conditions +.\" are met: +.\" 1. Redistributions of source code must retain the above copyright +.\" notice unmodified, this list of conditions, and the following +.\" disclaimer. +.\" 2. Redistributions in binary form must reproduce the above copyright +.\" notice, this list of conditions and the following disclaimer in the +.\" documentation and/or other materials provided with the distribution. +.\" +.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +.\" SUCH DAMAGE. +.\" +.Dd May 02, 2005 +.Os +.Dt IPW 4 +.Sh NAME +.Nm ipw +.Nd Intel PRO/Wireless 2100 IEEE 802.11 driver +.Sh SYNOPSIS +.Cd "device ipw" +.Cd "device pci" +.Cd "device wlan" +.Sh DESCRIPTION +The +.Nm +driver provides support for the +.Tn Intel +PRO/Wireless 2100 MiniPCI network adapter. +.Pp +By default, the +.Nm +driver configures the adapter for BSS operation (aka infrastructure mode). +This mode requires the use of an access point. +.Pp +For more information on configuring this device, see +.Xr ifconfig 8 . +.Sh EXAMPLES +Join an existing BSS network (ie: connect to an access point): +.Pp +.Dl "ifconfig ipw0 inet 192.168.0.20 netmask 0xffffff00" +.Pp +Join a specific BSS network with network name +.Dq Li my_net : +.Pp +.Dl "ifconfig ipw0 inet 192.168.0.20 netmask 0xffffff00 ssid my_net" +.Pp +Join a specific BSS network with 40bit WEP encryption: +.Bd -literal -offset indent +ifconfig ipw0 inet 192.168.0.20 netmask 0xffffff00 ssid my_net \e + wepmode on wepkey 0x1234567890 +.Ed +.Pp +Join a specific BSS network with 104bit WEP encryption: +.Bd -literal -offset indent +ifconfig ipw0 inet 192.168.0.20 netmask 0xffffff00 ssid my_net \e + wepmode on wepkey 0x01020304050607080910111213 +.Ed +.Sh DIAGNOSTICS +.Bl -diag +.It "ipw%d: device timeout" +The driver will reset the hardware. This should not happen. +.El +.Sh SEE ALSO +.Xr an 4 , +.Xr ath 4 , +.Xr pci 4 , +.Xr wi 4 , +.Xr wlan 4 , +.Xr ifconfig 8 , +.Xr ipwcontrol 8 +.Rs +.%T The IPW Web Page +.%O http://damien.bergamini.free.fr/ipw/ +.Re +.Sh AUTHORS +The +.Nm +driver was written by +.An Damien Bergamini Aq damien@freebsd.org . diff --git a/share/man/man4/iwi.4 b/share/man/man4/iwi.4 new file mode 100644 index 0000000..32bf4cc --- /dev/null +++ b/share/man/man4/iwi.4 @@ -0,0 +1,96 @@ +.\" $FreeBSD$ +.\" +.\" Copyright (c) 2004, 2005 +.\" Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. +.\" +.\" Redistribution and use in source and binary forms, with or without +.\" modification, are permitted provided that the following conditions +.\" are met: +.\" 1. Redistributions of source code must retain the above copyright +.\" notice unmodified, this list of conditions, and the following +.\" disclaimer. +.\" 2. Redistributions in binary form must reproduce the above copyright +.\" notice, this list of conditions and the following disclaimer in the +.\" documentation and/or other materials provided with the distribution. +.\" +.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +.\" SUCH DAMAGE. +.\" +.Dd May 02, 2005 +.Os +.Dt IWI 4 +.Sh NAME +.Nm iwi +.Nd Intel PRO/Wireless 2200BG/2225BG/2915ABG IEEE 802.11 driver +.Sh SYNOPSIS +.Cd "device iwi" +.Cd "device pci" +.Cd "device wlan" +.Sh DESCRIPTION +The +.Nm +driver provides support for +.Tn Intel +PRO/Wireless 2200BG/2915ABG MiniPCI and 2225BG PCI network adapters. +.Pp +By default, the +.Nm +driver configures the adapter for BSS operation (aka infrastructure mode). +This mode requires the use of an access point. +.Pp +For more information on configuring this device, see +.Xr ifconfig 8 . +.Sh EXAMPLES +Join an existing BSS network (ie: connect to an access point): +.Pp +.Dl "ifconfig iwi0 inet 192.168.0.20 netmask 0xffffff00" +.Pp +Join a specific BSS network with network name +.Dq Li my_net : +.Pp +.Dl "ifconfig iwi0 inet 192.168.0.20 netmask 0xffffff00 ssid my_net" +.Pp +Join a specific BSS network with 64 bits WEP encryption: +.Bd -literal -offset indent +ifconfig iwi0 inet 192.168.0.20 netmask 0xffffff00 ssid my_net \e + wepmode on wepkey 0x1234567890 +.Ed +.Pp +Join a specific BSS network with 128bits WEP encryption: +.Bd -literal -offset indent +ifconfig iwi0 inet 192.168.0.20 netmask 0xffffff00 ssid my_net \e + wepmode on wepkey 0x01020304050607080910111213 +.Ed +.Sh DIAGNOSTICS +.Bl -diag +.It "iwi%d: device timeout" +The driver will reset the hardware. This should not happen. +.El +.Sh SEE ALSO +.Xr an 4 , +.Xr ath 4 , +.Xr ipw 4 , +.Xr pci 4 , +.Xr wi 4 , +.Xr wlan 4 , +.Xr ifconfig 8 , +.Xr iwicontrol 8, +.Xr wicontrol 8 +.Rs +.%T The IWI Web Page +.%O http://damien.bergamini.free.fr/ipw/ +.Re +.Sh AUTHORS +The +.Nm +driver was written by +.An Damien Bergamini Aq damien@freebsd.org . diff --git a/share/man/man4/ral.4 b/share/man/man4/ral.4 new file mode 100644 index 0000000..cc34be2 --- /dev/null +++ b/share/man/man4/ral.4 @@ -0,0 +1,182 @@ +.\" $FreeBSD$ +.\" +.\" Copyright (c) 2005 +.\" Damien Bergamini <damien.bergamini@free.fr> +.\" +.\" Permission to use, copy, modify, and distribute this software for any +.\" purpose with or without fee is hereby granted, provided that the above +.\" copyright notice and this permission notice appear in all copies. +.\" +.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +.\" +.Dd May 02, 2005 +.Os +.Dt RAL 4 +.Sh NAME +.Nm ral +.Nd Ralink Technology RT2500 IEEE 802.11 driver +.Sh SYNOPSIS +.Cd "device ral" +.Cd "device wlan" +.Sh DESCRIPTION +The +.Nm +driver supports PCI/CardBus wireless adapters based on the Ralink RT2500 +chipset. +.Pp +The RT2500 chipset consists of two integrated chips, a RT2560 MAC/BBP and a +radio transceiver (the model of which depends on the card revision). +.Pp +The RT2522, RT2523, RT2524, RT2525, RT2525e and RT2526 radio transceivers +operate in the 2.4GHz band (802.11b/g) whereas the RT5222 is a dual-band radio +transceiver that can operate in the 2.4GHz and 5.2GHz bands (802.11a). +.Pp +The transmit speed is user-selectable or can be adapted automatically by the +driver depending on the received-signal strength. +.Sh HARDWARE +The following adapters should work: +.Pp +.Bl -column -compact "Atlantis Land A02-PCM-W54" "Bus" +.It Em "Card Bus" +.It Li "A-Link WL54H" Ta PCI +.It Li "A-Link WL54PC" Ta CardBus +.It Li "Amigo AWI-914W" Ta CardBus +.It Li "Amigo AWI-922W" Ta mini-PCI +.It Li "Amigo AWI-926W" Ta PCI +.It Li "AMIT WL531C" Ta CardBus +.It Li "AMIT WL531P" Ta PCI +.It Li "AOpen AOI-831" Ta PCI +.It Li "ASUS WL-107G" Ta CardBus +.It Li "ASUS WL-130g" Ta PCI +.It Li "Atlantis Land A02-PCI-W54" Ta PCI +.It Li "Atlantis Land A02-PCM-W54" Ta CardBus +.It Li "Belkin F5D7000 v3" Ta PCI +.It Li "Belkin F5D7010 v2" Ta CardBus +.It Li "Billionton MIWLGRL" Ta mini-PCI +.It Li "Canyon CN-WF511" Ta PCI +.It Li "Canyon CN-WF513" Ta CardBus +.It Li "CC&C WL-2102" Ta CardBus +.It Li "CNet CWC-854" Ta CardBus +.It Li "CNet CWP-854" Ta PCI +.It Li "Compex WL54G" Ta CardBus +.It Li "Compex WLP54G" Ta PCI +.It Li "Conceptronic C54RC" Ta CardBus +.It Li "Conceptronic C54Ri" Ta PCI +.It Li "Digitus DN-7001G-RA" Ta CardBus +.It Li "Digitus DN-7006G-RA" Ta PCI +.It Li "E-Tech WGPC02" Ta CardBus +.It Li "E-Tech WGPI02" Ta PCI +.It Li "Edimax EW-7108PCg" Ta CardBus +.It Li "Edimax EW-7128g" Ta PCI +.It Li "Eminent EM3036" Ta CardBus +.It Li "Eminent EM3037" Ta PCI +.It Li "Encore ENLWI-G-RLAM" Ta PCI +.It Li "Encore ENPWI-G-RLAM" Ta CardBus +.It Li "Fiberline WL-400P" Ta PCI +.It Li "Fibreline WL-400X" Ta CardBus +.It Li "Gigabyte GN-WIKG" Ta mini-PCI +.It Li "Gigabyte GN-WMKG" Ta CardBus +.It Li "Gigabyte GN-WPKG" Ta PCI +.It Li "Hawking HWC54GR" Ta CardBus +.It Li "Hawking HWP54GR" Ta PCI +.It Li "iNexQ CR054g-009 (R03)" Ta PCI +.It Li "JAHT WN-4054P" Ta CardBus +.It Li "JAHT WN-4054PCI" Ta PCI +.It Li "LevelOne WNC-0301 v2" Ta PCI +.It Li "LevelOne WPC-0301 v2" Ta CardBus +.It Li "Linksys WMP54G v4" Ta PCI +.It Li "Micronet SP906GK" Ta PCI +.It Li "Micronet SP908GK V3" Ta CardBus +.It Li "Minitar MN54GCB-R" Ta CardBus +.It Li "Minitar MN54GPC-R" Ta PCI +.It Li "MSI CB54G2" Ta CardBus +.It Li "MSI MP54G2" Ta mini-PCI +.It Li "MSI PC54G2" Ta PCI +.It Li "OvisLink EVO-W54PCI" Ta PCI +.It Li "PheeNet HWL-PCIG/RA" Ta PCI +.It Li "Pro-Nets CB80211G" Ta CardBus +.It Li "Pro-Nets PC80211G" Ta PCI +.It Li "Repotec RP-WB7108" Ta CardBus +.It Li "Repotec RP-WP0854" Ta PCI +.It Li "SATech SN-54C" Ta CardBus +.It Li "SATech SN-54P" Ta PCI +.It Li "Sitecom WL-112" Ta CardBus +.It Li "Sitecom WL-115" Ta PCI +.It Li "SparkLAN WL-685R" Ta CardBus +.It Li "Surecom EP-9321-g" Ta PCI +.It Li "Surecom EP-9321-g1" Ta PCI +.It Li "Surecom EP-9428-g" Ta CardBus +.It Li "Sweex LC500050" Ta CardBus +.It Li "Sweex LC700030" Ta PCI +.It Li "TekComm NE-9321-g" Ta PCI +.It Li "TekComm NE-9428-g" Ta CardBus +.It Li "Unex CR054g-R02" Ta PCI +.It Li "Unex MR054g-R02" Ta CardBus +.It Li "Zinwell ZWX-G160" Ta CardBus +.It Li "Zinwell ZWX-G360" Ta mini-PCI +.It Li "Zinwell ZWX-G361" Ta PCI +.It Li "Zonet ZEW1500" Ta CardBus +.It Li "Zonet ZEW1600" Ta PCI +.El +.Pp +An up to date list can be found at +.Pa http://damien.bergamini.free.fr/ral/list.html +.Sh EXAMPLES +Join an existing BSS network (ie: connect to an access point): +.Pp +.Dl "ifconfig ral0 inet 192.168.0.20 netmask 0xffffff00" +.Pp +Join a specific BSS network with network name +.Dq Li my_net : +.Pp +.Dl "ifconfig ral0 inet 192.168.0.20 netmask 0xffffff00 ssid my_net" +.Pp +Join a specific BSS network with 40bit WEP encryption: +.Bd -literal -offset indent +ifconfig ral0 inet 192.168.0.20 netmask 0xffffff00 ssid my_net \e + wepmode on wepkey 0x1234567890 +.Ed +.Pp +Join a specific BSS network with 104bit WEP encryption: +.Bd -literal -offset indent +ifconfig ral0 inet 192.168.0.20 netmask 0xffffff00 ssid my_net \e + wepmode on wepkey 0x01020304050607080910111213 +.Ed +.Sh DIAGNOSTICS +.Bl -diag +.It "ral%d: device timeout" +The driver will reset the hardware. +This should not happen. +.El +.Sh SEE ALSO +.Xr arp 4 , +.Xr cardbus 4 , +.Xr netintro 4 , +.Xr pci 4 , +.Xr wlan 4 , +.Xr ifconfig 8 +.Rs +.%T Ralink Technology +.%O http://www.ralinktech.com +.Re +.Sh AUTHORS +The +.Nm +driver was written by +.An Damien Bergamini Aq damien@freebsd.org . +.Sh HISTORY +The +.Nm +driver first appeared in +.Ox 3.7 . +.Sh CAVEATS +PCI +.Nm +adapters seem to require a PCI 2.2 compliant motherboard and will likely not +work with PCI 2.1 only motherboard. diff --git a/share/man/man4/ural.4 b/share/man/man4/ural.4 new file mode 100644 index 0000000..d33bb6f --- /dev/null +++ b/share/man/man4/ural.4 @@ -0,0 +1,118 @@ +.\" $FreeBSD$ +.\" +.\" Copyright (c) 2005 +.\" Damien Bergamini <damien.bergamini@free.fr> +.\" +.\" Permission to use, copy, modify, and distribute this software for any +.\" purpose with or without fee is hereby granted, provided that the above +.\" copyright notice and this permission notice appear in all copies. +.\" +.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. +.\" +.Dd May 02, 2005 +.Os +.Dt URAL 4 +.Sh NAME +.Nm ural +.Nd Ralink Technology RT2500USB IEEE 802.11 driver +.Sh SYNOPSIS +.Cd "device ehci" +.Cd "device uhci" +.Cd "device ohci" +.Cd "device usb" +.Cd "device ural" +.Cd "device wlan" +.Sh DESCRIPTION +The +.Nm +driver supports USB 2.0 wireless adapters based on the RT2500USB chipset. +.Pp +The RT2500USB chipset consists of two integrated chips, a RT2570 MAC/BBP +and a radio transceiver (the model of which depends on the card revision). +.Pp +The RT2522, RT2523, RT2524, RT2525, RT2525e and RT2526 radio transceivers +operate in the 2.4GHz band (802.11b/g) whereas the RT5222 is a dual-band radio +transceiver that can operate in the 2.4GHz and 5.2GHz bands (802.11a). +.Sh HARDWARE +The following adapters should work: +.Pp +.Bl -column -compact "Atlantis Land A02-PCM-W54" "Bus" +.It Em "Card Bus" +.It Li "AMIT WL532U" Ta USB +.It Li "ASUS WL-167g" Ta USB +.It Li "Buffalo WLI-U2-KG54-AI" Ta USB +.It Li "CNet CWD-854" Ta USB +.It Li "Compex WLU54G" Ta USB +.It Li "Conceptronic C54RU" Ta USB +.It Li "D-Link DWL-G122 b1" Ta USB +.It Li "E-Tech WGUS02" Ta USB +.It Li "Gigabyte GN-WBKG" Ta USB +.It Li "Linksys WUSB54G v4" Ta USB +.It Li "Linksys WUSB54GP v4" Ta USB +.It Li "MSI MS-6861" Ta USB +.It Li "MSI MS-6865" Ta USB +.It Li "MSI MS-6869" Ta USB +.It Li "Repotec RP-WU0402" Ta USB +.It Li "Surecom EP-9001-g" Ta USB +.El +.Pp +An up to date list can be found at +.Pa http://damien.bergamini.free.fr/ral/list.html +.Sh EXAMPLES +Join an existing BSS network (ie: connect to an access point): +.Pp +.Dl "ifconfig ural0 inet 192.168.0.20 netmask 0xffffff00" +.Pp +Join a specific BSS network with network name +.Dq Li my_net : +.Pp +.Dl "ifconfig ural0 inet 192.168.0.20 netmask 0xffffff00 ssid my_net" +.Pp +Join a specific BSS network with 40bit WEP encryption: +.Bd -literal -offset indent +ifconfig ural0 inet 192.168.0.20 netmask 0xffffff00 ssid my_net \e + wepmode on wepkey 0x1234567890 +.Ed +.Pp +Join a specific BSS network with 104bit WEP encryption: +.Bd -literal -offset indent +ifconfig ural0 inet 192.168.0.20 netmask 0xffffff00 ssid my_net \e + wepmode on wepkey 0x01020304050607080910111213 +.Ed +.Sh DIAGNOSTICS +.Bl -diag +.It "ural%d: device timeout" +The driver will reset the hardware. +This should not happen. +.El +.Sh SEE ALSO +.Xr arp 4 , +.Xr netintro 4 , +.Xr usb 4 , +.Xr wlan 4 , +.Xr ifconfig 8 +.Rs +.%T Ralink Technology +.%O http://www.ralinktech.com +.Re +.Sh AUTHORS +The +.Nm +driver was written by +.An Damien Bergamini Aq damien@freebsd.org . +.Sh HISTORY +The +.Nm +driver first appeared in +.Ox 3.7 . +.Sh CAVEATS +.Pp +The +.Nm +driver does not support automatic adaptation of the transmit speed. diff --git a/sys/conf/files b/sys/conf/files index a6399d4..ccf3ac7 100644 --- a/sys/conf/files +++ b/sys/conf/files @@ -585,12 +585,14 @@ dev/ips/ips_commands.c optional ips dev/ips/ips_disk.c optional ips dev/ips/ips_ioctl.c optional ips dev/ips/ips_pci.c optional ips pci +dev/ipw/if_ipw.c optional ipw dev/isp/isp.c optional isp dev/isp/isp_freebsd.c optional isp dev/isp/isp_pci.c optional isp pci dev/isp/isp_sbus.c optional isp sbus dev/isp/isp_target.c optional isp dev/ispfw/ispfw.c optional ispfw +dev/iwi/if_iwi.c optional iwi dev/ixgb/if_ixgb.c optional ixgb dev/ixgb/ixgb_ee.c optional ixgb dev/ixgb/ixgb_hw.c optional ixgb @@ -707,6 +709,10 @@ dev/puc/puc_pci.c optional puc pci dev/puc/puc_sbus.c optional puc fhc dev/puc/puc_sbus.c optional puc sbus dev/puc/pucdata.c optional puc pci +dev/ral/if_ral.c optional ral +dev/ral/if_ralrate.c optional ral +dev/ral/if_ral_pccard.c optional ral pccard +dev/ral/if_ral_pci.c optional ral pci dev/random/harvest.c standard dev/random/hash.c optional random dev/random/probe.c optional random @@ -857,6 +863,7 @@ dev/usb/if_axe.c optional axe dev/usb/if_cdce.c optional cdce dev/usb/if_cue.c optional cue dev/usb/if_kue.c optional kue +dev/usb/if_ural.c optional ural dev/usb/if_rue.c optional rue dev/usb/if_udav.c optional udav dev/usb/ohci.c optional ohci diff --git a/sys/dev/ipw/if_ipw.c b/sys/dev/ipw/if_ipw.c new file mode 100644 index 0000000..af98b83 --- /dev/null +++ b/sys/dev/ipw/if_ipw.c @@ -0,0 +1,2195 @@ +/* $FreeBSD$ */ + +/*- + * Copyright (c) 2004, 2005 + * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice unmodified, this list of conditions, and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +/*- + * Intel(R) PRO/Wireless 2100 MiniPCI driver + * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm + */ + +#include <sys/param.h> +#include <sys/sysctl.h> +#include <sys/sockio.h> +#include <sys/mbuf.h> +#include <sys/kernel.h> +#include <sys/socket.h> +#include <sys/systm.h> +#include <sys/malloc.h> +#include <sys/module.h> +#include <sys/bus.h> +#include <sys/endian.h> + +#include <machine/bus.h> +#include <machine/resource.h> +#include <machine/clock.h> +#include <sys/rman.h> + +#include <dev/pci/pcireg.h> +#include <dev/pci/pcivar.h> + +#include <net/bpf.h> +#include <net/if.h> +#include <net/if_arp.h> +#include <net/ethernet.h> +#include <net/if_dl.h> +#include <net/if_media.h> +#include <net/if_types.h> + +#include <netinet/in.h> +#include <netinet/in_systm.h> +#include <netinet/in_var.h> +#include <netinet/ip.h> +#include <netinet/if_ether.h> + +#include <net80211/ieee80211_var.h> +#include <net80211/ieee80211_radiotap.h> + +#include <dev/ipw/if_ipwreg.h> +#include <dev/ipw/if_ipwvar.h> + +#ifdef IPW_DEBUG +#define DPRINTF(x) do { if (ipw_debug > 0) printf x; } while (0) +#define DPRINTFN(n, x) do { if (ipw_debug >= (n)) printf x; } while (0) +int ipw_debug = 0; +SYSCTL_INT(_debug, OID_AUTO, ipw, CTLFLAG_RW, &ipw_debug, 0, "ipw debug level"); +#else +#define DPRINTF(x) +#define DPRINTFN(n, x) +#endif + +MODULE_DEPEND(ipw, pci, 1, 1, 1); +MODULE_DEPEND(ipw, wlan, 1, 1, 1); + +struct ipw_ident { + uint16_t vendor; + uint16_t device; + const char *name; +}; + +static const struct ipw_ident ipw_ident_table[] = { + { 0x8086, 0x1043, "Intel(R) PRO/Wireless 2100 MiniPCI" }, + + { 0, 0, NULL } +}; + +static int ipw_dma_alloc(struct ipw_softc *); +static void ipw_release(struct ipw_softc *); +static int ipw_media_change(struct ifnet *); +static void ipw_media_status(struct ifnet *, struct ifmediareq *); +static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int); +static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t); +static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *); +static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *); +static void ipw_data_intr(struct ipw_softc *, struct ipw_status *, + struct ipw_soft_bd *, struct ipw_soft_buf *); +static void ipw_rx_intr(struct ipw_softc *); +static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *); +static void ipw_tx_intr(struct ipw_softc *); +static void ipw_intr(void *); +static void ipw_dma_map_addr(void *, bus_dma_segment_t *, int, int); +static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t); +static int ipw_tx_start(struct ifnet *, struct mbuf *, + struct ieee80211_node *); +static void ipw_start(struct ifnet *); +static void ipw_watchdog(struct ifnet *); +static int ipw_ioctl(struct ifnet *, u_long, caddr_t); +static void ipw_stop_master(struct ipw_softc *); +static int ipw_reset(struct ipw_softc *); +static int ipw_load_ucode(struct ipw_softc *, u_char *, int); +static int ipw_load_firmware(struct ipw_softc *, u_char *, int); +static int ipw_cache_firmware(struct ipw_softc *, void *); +static void ipw_free_firmware(struct ipw_softc *); +static int ipw_config(struct ipw_softc *); +static void ipw_init(void *); +static void ipw_stop(void *); +#ifdef IPW_DEBUG +static int ipw_sysctl_stats(SYSCTL_HANDLER_ARGS); +#endif +static int ipw_sysctl_radio(SYSCTL_HANDLER_ARGS); +static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t); +static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t); +static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, + uint32_t *); +static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, + bus_size_t); +static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *, + bus_size_t); + +static int ipw_probe(device_t); +static int ipw_attach(device_t); +static int ipw_detach(device_t); +static int ipw_shutdown(device_t); +static int ipw_suspend(device_t); +static int ipw_resume(device_t); + +static device_method_t ipw_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, ipw_probe), + DEVMETHOD(device_attach, ipw_attach), + DEVMETHOD(device_detach, ipw_detach), + DEVMETHOD(device_shutdown, ipw_shutdown), + DEVMETHOD(device_suspend, ipw_suspend), + DEVMETHOD(device_resume, ipw_resume), + + { 0, 0 } +}; + +static driver_t ipw_driver = { + "ipw", + ipw_methods, + sizeof (struct ipw_softc) +}; + +static devclass_t ipw_devclass; + +DRIVER_MODULE(ipw, pci, ipw_driver, ipw_devclass, 0, 0); + +/* + * Supported rates for 802.11b mode (in 500Kbps unit). + */ +static const struct ieee80211_rateset ipw_rateset_11b = + { 4, { 2, 4, 11, 22 } }; + +static __inline uint8_t +MEM_READ_1(struct ipw_softc *sc, uint32_t addr) +{ + CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); + return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA); +} + +static __inline uint32_t +MEM_READ_4(struct ipw_softc *sc, uint32_t addr) +{ + CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr); + return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); +} + +static int +ipw_probe(device_t dev) +{ + const struct ipw_ident *ident; + + for (ident = ipw_ident_table; ident->name != NULL; ident++) { + if (pci_get_vendor(dev) == ident->vendor && + pci_get_device(dev) == ident->device) { + device_set_desc(dev, ident->name); + return 0; + } + } + return ENXIO; +} + +/* Base Address Register */ +#define IPW_PCI_BAR0 0x10 + +static int +ipw_attach(device_t dev) +{ + struct ipw_softc *sc = device_get_softc(dev); + struct ifnet *ifp = &sc->sc_arp.ac_if; + struct ieee80211com *ic = &sc->sc_ic; + uint16_t val; + int error, i; + + sc->sc_dev = dev; + + mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, + MTX_DEF | MTX_RECURSE); + + if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { + device_printf(dev, "chip is in D%d power mode " + "-- setting to D0\n", pci_get_powerstate(dev)); + pci_set_powerstate(dev, PCI_POWERSTATE_D0); + } + + /* enable bus-mastering */ + pci_enable_busmaster(dev); + + sc->mem_rid = IPW_PCI_BAR0; + sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, + RF_ACTIVE); + if (sc->mem == NULL) { + device_printf(dev, "could not allocate memory resource\n"); + goto fail; + } + + sc->sc_st = rman_get_bustag(sc->mem); + sc->sc_sh = rman_get_bushandle(sc->mem); + + sc->irq_rid = 0; + sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, + RF_ACTIVE | RF_SHAREABLE); + if (sc->irq == NULL) { + device_printf(dev, "could not allocate interrupt resource\n"); + goto fail; + } + + if (ipw_reset(sc) != 0) { + device_printf(dev, "could not reset adapter\n"); + goto fail; + } + + if (ipw_dma_alloc(sc) != 0) { + device_printf(dev, "could not allocate DMA resources\n"); + goto fail; + } + + ifp->if_softc = sc; + if_initname(ifp, device_get_name(dev), device_get_unit(dev)); + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; + ifp->if_init = ipw_init; + ifp->if_ioctl = ipw_ioctl; + ifp->if_start = ipw_start; + ifp->if_watchdog = ipw_watchdog; + IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); + ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; + IFQ_SET_READY(&ifp->if_snd); + + ic->ic_ifp = ifp; + ic->ic_phytype = IEEE80211_T_DS; + ic->ic_opmode = IEEE80211_M_STA; + ic->ic_state = IEEE80211_S_INIT; + + /* set device capabilities */ + ic->ic_caps = IEEE80211_C_SHPREAMBLE | IEEE80211_C_TXPMGT | + IEEE80211_C_PMGT | IEEE80211_C_IBSS | IEEE80211_C_MONITOR | + IEEE80211_C_WPA; + + /* read MAC address from EEPROM */ + val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); + ic->ic_myaddr[0] = val >> 8; + ic->ic_myaddr[1] = val & 0xff; + val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1); + ic->ic_myaddr[2] = val >> 8; + ic->ic_myaddr[3] = val & 0xff; + val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2); + ic->ic_myaddr[4] = val >> 8; + ic->ic_myaddr[5] = val & 0xff; + + /* set supported .11b rates */ + ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b; + + /* set supported .11b channels (read from EEPROM) */ + if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) + val = 0x7ff; /* default to channels 1-11 */ + val <<= 1; + for (i = 1; i < 16; i++) { + if (val & (1 << i)) { + ic->ic_channels[i].ic_freq = + ieee80211_ieee2mhz(i, IEEE80211_CHAN_B); + ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B; + } + } + + /* check support for radio transmitter switch in EEPROM */ + if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8)) + sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH; + + ieee80211_ifattach(ic); + /* override state transition machine */ + sc->sc_newstate = ic->ic_newstate; + ic->ic_newstate = ipw_newstate; + ieee80211_media_init(ic, ipw_media_change, ipw_media_status); + + bpfattach2(ifp, DLT_IEEE802_11_RADIO, + sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); + + sc->sc_rxtap_len = sizeof sc->sc_rxtapu; + sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); + sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT); + + sc->sc_txtap_len = sizeof sc->sc_txtapu; + sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); + sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT); + + /* + * Add a few sysctl knobs. + */ + sc->dwelltime = 100; + + SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "radio", + CTLTYPE_INT | CTLFLAG_RD, sc, 0, ipw_sysctl_radio, "I", + "radio transmitter switch state (0=off, 1=on)"); + +#ifdef IPW_DEBUG + SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "stats", + CTLTYPE_OPAQUE | CTLFLAG_RD, sc, 0, ipw_sysctl_stats, "S", + "statistics"); +#endif + + SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "dwell", + CTLFLAG_RW, &sc->dwelltime, 0, + "channel dwell time (ms) for AP/station scanning"); + + /* + * Hook our interrupt after all initialization is complete. + */ + error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, + ipw_intr, sc, &sc->sc_ih); + if (error != 0) { + device_printf(dev, "could not set up interrupt\n"); + goto fail; + } + + if (bootverbose) + ieee80211_announce(ic); + + return 0; + +fail: ipw_detach(dev); + return ENXIO; +} + +static int +ipw_detach(device_t dev) +{ + struct ipw_softc *sc = device_get_softc(dev); + struct ieee80211com *ic = &sc->sc_ic; + struct ifnet *ifp = ic->ic_ifp; + + IPW_LOCK(sc); + + ipw_stop(sc); + ipw_free_firmware(sc); + + IPW_UNLOCK(sc); + + bpfdetach(ifp); + ieee80211_ifdetach(ic); + + ipw_release(sc); + + if (sc->irq != NULL) { + bus_teardown_intr(dev, sc->irq, sc->sc_ih); + bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq); + } + + if (sc->mem != NULL) + bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem); + + mtx_destroy(&sc->sc_mtx); + + return 0; +} + +static int +ipw_dma_alloc(struct ipw_softc *sc) +{ + struct ipw_soft_bd *sbd; + struct ipw_soft_hdr *shdr; + struct ipw_soft_buf *sbuf; + bus_addr_t physaddr; + int error, i; + + /* + * Allocate and map tx ring. + */ + error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, + BUS_SPACE_MAXADDR, NULL, NULL, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, NULL, + NULL, &sc->tbd_dmat); + if (error != 0) { + device_printf(sc->sc_dev, "could not create tx ring DMA tag\n"); + goto fail; + } + + error = bus_dmamem_alloc(sc->tbd_dmat, (void **)&sc->tbd_list, + BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->tbd_map); + if (error != 0) { + device_printf(sc->sc_dev, + "could not allocate tx ring DMA memory\n"); + goto fail; + } + + error = bus_dmamap_load(sc->tbd_dmat, sc->tbd_map, sc->tbd_list, + IPW_TBD_SZ, ipw_dma_map_addr, &sc->tbd_phys, 0); + if (error != 0) { + device_printf(sc->sc_dev, "could not map tx ring DMA memory\n"); + goto fail; + } + + /* + * Allocate and map rx ring. + */ + error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, + BUS_SPACE_MAXADDR, NULL, NULL, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, NULL, + NULL, &sc->rbd_dmat); + if (error != 0) { + device_printf(sc->sc_dev, "could not create rx ring DMA tag\n"); + goto fail; + } + + error = bus_dmamem_alloc(sc->rbd_dmat, (void **)&sc->rbd_list, + BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->rbd_map); + if (error != 0) { + device_printf(sc->sc_dev, + "could not allocate rx ring DMA memory\n"); + goto fail; + } + + error = bus_dmamap_load(sc->rbd_dmat, sc->rbd_map, sc->rbd_list, + IPW_RBD_SZ, ipw_dma_map_addr, &sc->rbd_phys, 0); + if (error != 0) { + device_printf(sc->sc_dev, "could not map rx ring DMA memory\n"); + goto fail; + } + + /* + * Allocate and map status ring. + */ + error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, + BUS_SPACE_MAXADDR, NULL, NULL, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 0, + NULL, NULL, &sc->status_dmat); + if (error != 0) { + device_printf(sc->sc_dev, + "could not create status ring DMA tag\n"); + goto fail; + } + + error = bus_dmamem_alloc(sc->status_dmat, (void **)&sc->status_list, + BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->status_map); + if (error != 0) { + device_printf(sc->sc_dev, + "could not allocate status ring DMA memory\n"); + goto fail; + } + + error = bus_dmamap_load(sc->status_dmat, sc->status_map, + sc->status_list, IPW_STATUS_SZ, ipw_dma_map_addr, &sc->status_phys, + 0); + if (error != 0) { + device_printf(sc->sc_dev, + "could not map status ring DMA memory\n"); + goto fail; + } + + /* + * Allocate command DMA map. + */ + error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, + BUS_SPACE_MAXADDR, NULL, NULL, sizeof (struct ipw_cmd), 1, + sizeof (struct ipw_cmd), 0, NULL, NULL, &sc->cmd_dmat); + if (error != 0) { + device_printf(sc->sc_dev, "could not create command DMA tag\n"); + goto fail; + } + + error = bus_dmamap_create(sc->cmd_dmat, 0, &sc->cmd_map); + if (error != 0) { + device_printf(sc->sc_dev, + "could not create command DMA map\n"); + goto fail; + } + + /* + * Allocate headers DMA maps. + */ + error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, + BUS_SPACE_MAXADDR, NULL, NULL, sizeof (struct ipw_hdr), 1, + sizeof (struct ipw_hdr), 0, NULL, NULL, &sc->hdr_dmat); + if (error != 0) { + device_printf(sc->sc_dev, "could not create header DMA tag\n"); + goto fail; + } + + SLIST_INIT(&sc->free_shdr); + for (i = 0; i < IPW_NDATA; i++) { + shdr = &sc->shdr_list[i]; + error = bus_dmamap_create(sc->hdr_dmat, 0, &shdr->map); + if (error != 0) { + device_printf(sc->sc_dev, + "could not create header DMA map\n"); + goto fail; + } + SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); + } + + /* + * Allocate tx buffers DMA maps. + */ + error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, + BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, IPW_MAX_NSEG, MCLBYTES, 0, + NULL, NULL, &sc->txbuf_dmat); + if (error != 0) { + device_printf(sc->sc_dev, "could not create tx DMA tag\n"); + goto fail; + } + + SLIST_INIT(&sc->free_sbuf); + for (i = 0; i < IPW_NDATA; i++) { + sbuf = &sc->tx_sbuf_list[i]; + error = bus_dmamap_create(sc->txbuf_dmat, 0, &sbuf->map); + if (error != 0) { + device_printf(sc->sc_dev, + "could not create tx DMA map\n"); + goto fail; + } + SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); + } + + /* + * Initialize tx ring. + */ + for (i = 0; i < IPW_NTBD; i++) { + sbd = &sc->stbd_list[i]; + sbd->bd = &sc->tbd_list[i]; + sbd->type = IPW_SBD_TYPE_NOASSOC; + } + + /* + * Pre-allocate rx buffers and DMA maps. + */ + error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, + BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, IPW_NRBD, MCLBYTES, 0, + NULL, NULL, &sc->rxbuf_dmat); + if (error != 0) { + device_printf(sc->sc_dev, "could not create rx DMA tag\n"); + goto fail; + } + + for (i = 0; i < IPW_NRBD; i++) { + sbd = &sc->srbd_list[i]; + sbuf = &sc->rx_sbuf_list[i]; + sbd->bd = &sc->rbd_list[i]; + + sbuf->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + if (sbuf->m == NULL) { + device_printf(sc->sc_dev, + "could not allocate rx mbuf\n"); + error = ENOMEM; + goto fail; + } + + error = bus_dmamap_create(sc->rxbuf_dmat, 0, &sbuf->map); + if (error != 0) { + device_printf(sc->sc_dev, + "could not create rx DMA map\n"); + goto fail; + } + + error = bus_dmamap_load(sc->rxbuf_dmat, sbuf->map, + mtod(sbuf->m, void *), MCLBYTES, ipw_dma_map_addr, + &physaddr, 0); + if (error != 0) { + device_printf(sc->sc_dev, + "could not map rx DMA memory\n"); + goto fail; + } + + sbd->type = IPW_SBD_TYPE_DATA; + sbd->priv = sbuf; + sbd->bd->physaddr = htole32(physaddr); + sbd->bd->len = htole32(MCLBYTES); + } + + bus_dmamap_sync(sc->rbd_dmat, sc->rbd_map, BUS_DMASYNC_PREWRITE); + + return 0; + +fail: ipw_release(sc); + return error; +} + +static void +ipw_release(struct ipw_softc *sc) +{ + struct ipw_soft_buf *sbuf; + int i; + + if (sc->tbd_dmat != NULL) { + if (sc->stbd_list != NULL) { + bus_dmamap_unload(sc->tbd_dmat, sc->tbd_map); + bus_dmamem_free(sc->tbd_dmat, sc->tbd_list, + sc->tbd_map); + } + bus_dma_tag_destroy(sc->tbd_dmat); + } + + if (sc->rbd_dmat != NULL) { + if (sc->rbd_list != NULL) { + bus_dmamap_unload(sc->rbd_dmat, sc->rbd_map); + bus_dmamem_free(sc->rbd_dmat, sc->rbd_list, + sc->rbd_map); + } + bus_dma_tag_destroy(sc->rbd_dmat); + } + + if (sc->status_dmat != NULL) { + if (sc->status_list != NULL) { + bus_dmamap_unload(sc->status_dmat, sc->status_map); + bus_dmamem_free(sc->status_dmat, sc->status_list, + sc->status_map); + } + bus_dma_tag_destroy(sc->status_dmat); + } + + for (i = 0; i < IPW_NTBD; i++) + ipw_release_sbd(sc, &sc->stbd_list[i]); + + if (sc->cmd_dmat != NULL) { + bus_dmamap_destroy(sc->cmd_dmat, sc->cmd_map); + bus_dma_tag_destroy(sc->cmd_dmat); + } + + if (sc->hdr_dmat != NULL) { + for (i = 0; i < IPW_NDATA; i++) + bus_dmamap_destroy(sc->hdr_dmat, sc->shdr_list[i].map); + bus_dma_tag_destroy(sc->hdr_dmat); + } + + if (sc->txbuf_dmat != NULL) { + for (i = 0; i < IPW_NDATA; i++) { + bus_dmamap_destroy(sc->txbuf_dmat, + sc->tx_sbuf_list[i].map); + } + bus_dma_tag_destroy(sc->txbuf_dmat); + } + + if (sc->rxbuf_dmat != NULL) { + for (i = 0; i < IPW_NRBD; i++) { + sbuf = &sc->rx_sbuf_list[i]; + if (sbuf->m != NULL) { + bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, + BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->rxbuf_dmat, sbuf->map); + m_freem(sbuf->m); + } + bus_dmamap_destroy(sc->rxbuf_dmat, sbuf->map); + } + bus_dma_tag_destroy(sc->rxbuf_dmat); + } +} + +static int +ipw_shutdown(device_t dev) +{ + struct ipw_softc *sc = device_get_softc(dev); + + ipw_stop(sc); + + return 0; +} + +static int +ipw_suspend(device_t dev) +{ + struct ipw_softc *sc = device_get_softc(dev); + + ipw_stop(sc); + + return 0; +} + +static int +ipw_resume(device_t dev) +{ + struct ipw_softc *sc = device_get_softc(dev); + struct ifnet *ifp = sc->sc_ic.ic_ifp; + + IPW_LOCK(sc); + + if (ifp->if_flags & IFF_UP) { + ifp->if_init(ifp->if_softc); + if (ifp->if_flags & IFF_RUNNING) + ifp->if_start(ifp); + } + + IPW_UNLOCK(sc); + + return 0; +} + +static int +ipw_media_change(struct ifnet *ifp) +{ + struct ipw_softc *sc = ifp->if_softc; + int error; + + IPW_LOCK(sc); + + error = ieee80211_media_change(ifp); + if (error != ENETRESET) { + IPW_UNLOCK(sc); + return error; + } + + if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) + ipw_init(sc); + + IPW_UNLOCK(sc); + + return 0; +} + +/* + * The firmware automaticly adapt the transmit speed. We report the current + * transmit speed here. + */ +static void +ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr) +{ +#define N(a) (sizeof (a) / sizeof (a[0])) + struct ipw_softc *sc = ifp->if_softc; + struct ieee80211com *ic = &sc->sc_ic; + static const struct { + uint32_t val; + int rate; + } rates[] = { + { IPW_RATE_DS1, 2 }, + { IPW_RATE_DS2, 4 }, + { IPW_RATE_DS5, 11 }, + { IPW_RATE_DS11, 22 }, + }; + uint32_t val; + int rate, i; + + imr->ifm_status = IFM_AVALID; + imr->ifm_active = IFM_IEEE80211; + if (ic->ic_state == IEEE80211_S_RUN) + imr->ifm_status |= IFM_ACTIVE; + + /* read current transmission rate from adapter */ + val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf; + + /* convert ipw rate to 802.11 rate */ + for (i = 0; i < N(rates) && rates[i].val != val; i++); + rate = (i < N(rates)) ? rates[i].rate : 0; + + imr->ifm_active |= IFM_IEEE80211_11B; + imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B); + switch (ic->ic_opmode) { + case IEEE80211_M_STA: + break; + + case IEEE80211_M_IBSS: + imr->ifm_active |= IFM_IEEE80211_IBSS; + break; + + case IEEE80211_M_MONITOR: + imr->ifm_active |= IFM_IEEE80211_MONITOR; + break; + + case IEEE80211_M_AHDEMO: + case IEEE80211_M_HOSTAP: + /* should not get there */ + break; + } +#undef N +} + +static int +ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) +{ + struct ifnet *ifp = ic->ic_ifp; + struct ipw_softc *sc = ifp->if_softc; + struct ieee80211_node *ni; + uint8_t macaddr[IEEE80211_ADDR_LEN]; + uint32_t len; + + switch (nstate) { + case IEEE80211_S_RUN: + DELAY(200); /* firmware needs a short delay here */ + + len = IEEE80211_ADDR_LEN; + ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len); + + ni = ieee80211_find_node(&ic->ic_scan, macaddr); + if (ni == NULL) + break; + + ieee80211_ref_node(ni); + ieee80211_sta_join(ic, ni); + ieee80211_node_authorize(ic, ni); + + if (ic->ic_opmode == IEEE80211_M_STA) + ieee80211_notify_node_join(ic, ni, 1); + break; + + case IEEE80211_S_INIT: + case IEEE80211_S_SCAN: + case IEEE80211_S_AUTH: + case IEEE80211_S_ASSOC: + break; + } + + ic->ic_state = nstate; + return 0; +} + +/* + * Read 16 bits at address 'addr' from the serial EEPROM. + */ +static uint16_t +ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr) +{ + uint32_t tmp; + uint16_t val; + int n; + + /* clock C once before the first command */ + IPW_EEPROM_CTL(sc, 0); + IPW_EEPROM_CTL(sc, IPW_EEPROM_S); + IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); + IPW_EEPROM_CTL(sc, IPW_EEPROM_S); + + /* write start bit (1) */ + IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); + IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); + + /* write READ opcode (10) */ + IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D); + IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C); + IPW_EEPROM_CTL(sc, IPW_EEPROM_S); + IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); + + /* write address A7-A0 */ + for (n = 7; n >= 0; n--) { + IPW_EEPROM_CTL(sc, IPW_EEPROM_S | + (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D)); + IPW_EEPROM_CTL(sc, IPW_EEPROM_S | + (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C); + } + + IPW_EEPROM_CTL(sc, IPW_EEPROM_S); + + /* read data Q15-Q0 */ + val = 0; + for (n = 15; n >= 0; n--) { + IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C); + IPW_EEPROM_CTL(sc, IPW_EEPROM_S); + tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL); + val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n; + } + + IPW_EEPROM_CTL(sc, 0); + + /* clear Chip Select and clock C */ + IPW_EEPROM_CTL(sc, IPW_EEPROM_S); + IPW_EEPROM_CTL(sc, 0); + IPW_EEPROM_CTL(sc, IPW_EEPROM_C); + + return le16toh(val); +} + +static void +ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) +{ + struct ipw_cmd *cmd; + + bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, BUS_DMASYNC_POSTREAD); + + cmd = mtod(sbuf->m, struct ipw_cmd *); + + DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type), + le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len), + le32toh(cmd->status))); + + wakeup(sc); +} + +static void +ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf) +{ + struct ieee80211com *ic = &sc->sc_ic; + uint32_t state; + + bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, BUS_DMASYNC_POSTREAD); + + state = le32toh(*mtod(sbuf->m, uint32_t *)); + + DPRINTFN(2, ("entering state %u\n", state)); + + switch (state) { + case IPW_STATE_ASSOCIATED: + ieee80211_new_state(ic, IEEE80211_S_RUN, -1); + break; + + case IPW_STATE_SCANNING: + /* don't leave run state on background scan */ + if (ic->ic_state != IEEE80211_S_RUN) + ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); + + ic->ic_flags |= IEEE80211_F_SCAN; + break; + + case IPW_STATE_SCAN_COMPLETE: + ieee80211_notify_scan_done(ic); + ic->ic_flags &= ~IEEE80211_F_SCAN; + break; + + case IPW_STATE_ASSOCIATION_LOST: + ieee80211_new_state(ic, IEEE80211_S_INIT, -1); + break; + + case IPW_STATE_RADIO_DISABLED: + ic->ic_ifp->if_flags &= ~IFF_UP; + ipw_stop(sc); + break; + } +} + +/* + * XXX: Hack to set the current channel to the value advertised in beacons or + * probe responses. Only used during AP detection. + */ +static void +ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m) +{ + struct ieee80211_frame *wh; + uint8_t subtype; + uint8_t *frm, *efrm; + + wh = mtod(m, struct ieee80211_frame *); + + if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) + return; + + subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; + + if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && + subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) + return; + + frm = (uint8_t *)(wh + 1); + efrm = mtod(m, uint8_t *) + m->m_len; + + frm += 12; /* skip tstamp, bintval and capinfo fields */ + while (frm < efrm) { + if (*frm == IEEE80211_ELEMID_DSPARMS) +#if IEEE80211_CHAN_MAX < 255 + if (frm[2] <= IEEE80211_CHAN_MAX) +#endif + ic->ic_bss->ni_chan = &ic->ic_channels[frm[2]]; + + frm += frm[1] + 2; + } +} + +static void +ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, + struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf) +{ + struct ieee80211com *ic = &sc->sc_ic; + struct ifnet *ifp = ic->ic_ifp; + struct mbuf *m; + struct ieee80211_frame *wh; + struct ieee80211_node *ni; + bus_addr_t physaddr; + int error; + + bus_dmamap_sync(sc->rxbuf_dmat, sbuf->map, BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->rxbuf_dmat, sbuf->map); + + /* finalize mbuf */ + m = sbuf->m; + m->m_pkthdr.rcvif = ifp; + m->m_pkthdr.len = m->m_len = le32toh(status->len); + + if (sc->sc_drvbpf != NULL) { + struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap; + + tap->wr_flags = 0; + tap->wr_antsignal = status->rssi; + tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); + tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); + + bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); + } + + if (ic->ic_state == IEEE80211_S_SCAN) + ipw_fix_channel(ic, m); + + wh = mtod(m, struct ieee80211_frame *); + ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); + + /* send the frame to the 802.11 layer */ + ieee80211_input(ic, m, ni, status->rssi, 0); + + /* node is no longer needed */ + ieee80211_free_node(ni); + + m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + if (m == NULL) { + device_printf(sc->sc_dev, "could not allocate rx mbuf\n"); + sbuf->m = NULL; + return; + } + + error = bus_dmamap_load(sc->rxbuf_dmat, sbuf->map, mtod(m, void *), + MCLBYTES, ipw_dma_map_addr, &physaddr, 0); + if (error != 0) { + device_printf(sc->sc_dev, "could not map rx DMA memory\n"); + m_freem(m); + sbuf->m = NULL; + return; + } + + sbuf->m = m; + sbd->bd->physaddr = htole32(physaddr); + + DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len), + status->rssi)); + + bus_dmamap_sync(sc->rbd_dmat, sc->rbd_map, BUS_DMASYNC_PREWRITE); +} + +static void +ipw_rx_intr(struct ipw_softc *sc) +{ + struct ipw_status *status; + struct ipw_soft_bd *sbd; + struct ipw_soft_buf *sbuf; + uint32_t r, i; + + if (!(sc->flags & IPW_FLAG_FW_INITED)) + return; + + r = CSR_READ_4(sc, IPW_CSR_RX_READ); + + bus_dmamap_sync(sc->status_dmat, sc->status_map, BUS_DMASYNC_POSTREAD); + + for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) { + status = &sc->status_list[i]; + sbd = &sc->srbd_list[i]; + sbuf = sbd->priv; + + switch (le16toh(status->code) & 0xf) { + case IPW_STATUS_CODE_COMMAND: + ipw_command_intr(sc, sbuf); + break; + + case IPW_STATUS_CODE_NEWSTATE: + ipw_newstate_intr(sc, sbuf); + break; + + case IPW_STATUS_CODE_DATA_802_3: + case IPW_STATUS_CODE_DATA_802_11: + ipw_data_intr(sc, status, sbd, sbuf); + break; + + case IPW_STATUS_CODE_NOTIFICATION: + DPRINTFN(2, ("received notification\n")); + break; + + default: + device_printf(sc->sc_dev, "unknown status code %u\n", + le16toh(status->code)); + } + + /* firmware was killed, stop processing received frames */ + if (!(sc->flags & IPW_FLAG_FW_INITED)) + return; + + sbd->bd->flags = 0; + } + + bus_dmamap_sync(sc->rbd_dmat, sc->rbd_map, BUS_DMASYNC_PREWRITE); + + /* kick the firmware */ + sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; + CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); +} + +static void +ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd) +{ + struct ipw_soft_hdr *shdr; + struct ipw_soft_buf *sbuf; + + switch (sbd->type) { + case IPW_SBD_TYPE_COMMAND: + bus_dmamap_sync(sc->cmd_dmat, sc->cmd_map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->cmd_dmat, sc->cmd_map); + break; + + case IPW_SBD_TYPE_HEADER: + shdr = sbd->priv; + bus_dmamap_sync(sc->hdr_dmat, shdr->map, BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->hdr_dmat, shdr->map); + SLIST_INSERT_HEAD(&sc->free_shdr, shdr, next); + break; + + case IPW_SBD_TYPE_DATA: + sbuf = sbd->priv; + bus_dmamap_sync(sc->txbuf_dmat, sbuf->map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->txbuf_dmat, sbuf->map); + SLIST_INSERT_HEAD(&sc->free_sbuf, sbuf, next); + + m_freem(sbuf->m); + ieee80211_free_node(sbuf->ni); + + sc->sc_tx_timer = 0; + break; + } + + sbd->type = IPW_SBD_TYPE_NOASSOC; +} + +static void +ipw_tx_intr(struct ipw_softc *sc) +{ + struct ifnet *ifp = sc->sc_ic.ic_ifp; + struct ipw_soft_bd *sbd; + uint32_t r, i; + + if (!(sc->flags & IPW_FLAG_FW_INITED)) + return; + + r = CSR_READ_4(sc, IPW_CSR_TX_READ); + + for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) { + sbd = &sc->stbd_list[i]; + + if (sbd->type == IPW_SBD_TYPE_DATA) + ifp->if_opackets++; + + ipw_release_sbd(sc, sbd); + sc->txfree++; + } + + /* remember what the firmware has processed */ + sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; + + ifp->if_flags &= ~IFF_OACTIVE; + ipw_start(ifp); +} + +static void +ipw_intr(void *arg) +{ + struct ipw_softc *sc = arg; + uint32_t r; + + IPW_LOCK(sc); + + if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0 || r == 0xffffffff) { + IPW_UNLOCK(sc); + return; + } + + /* disable interrupts */ + CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); + + if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) { + device_printf(sc->sc_dev, "fatal error\n"); + sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; + ipw_stop(sc); + } + + if (r & IPW_INTR_FW_INIT_DONE) { + if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR))) + wakeup(sc); + } + + if (r & IPW_INTR_RX_TRANSFER) + ipw_rx_intr(sc); + + if (r & IPW_INTR_TX_TRANSFER) + ipw_tx_intr(sc); + + /* acknowledge all interrupts */ + CSR_WRITE_4(sc, IPW_CSR_INTR, r); + + /* re-enable interrupts */ + CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); + + IPW_UNLOCK(sc); +} + +static void +ipw_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) +{ + if (error != 0) + return; + + KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); + + *(bus_addr_t *)arg = segs[0].ds_addr; +} + +/* + * Send a command to the firmware and wait for the acknowledgement. + */ +static int +ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len) +{ + struct ipw_soft_bd *sbd; + bus_addr_t physaddr; + int error; + + sbd = &sc->stbd_list[sc->txcur]; + + error = bus_dmamap_load(sc->cmd_dmat, sc->cmd_map, &sc->cmd, + sizeof (struct ipw_cmd), ipw_dma_map_addr, &physaddr, 0); + if (error != 0) { + device_printf(sc->sc_dev, "could not map command DMA memory\n"); + return error; + } + + sc->cmd.type = htole32(type); + sc->cmd.subtype = 0; + sc->cmd.len = htole32(len); + sc->cmd.seq = 0; + bcopy(data, sc->cmd.data, len); + + sbd->type = IPW_SBD_TYPE_COMMAND; + sbd->bd->physaddr = htole32(physaddr); + sbd->bd->len = htole32(sizeof (struct ipw_cmd)); + sbd->bd->nfrag = 1; + sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND | + IPW_BD_FLAG_TX_LAST_FRAGMENT; + + bus_dmamap_sync(sc->cmd_dmat, sc->cmd_map, BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(sc->tbd_dmat, sc->tbd_map, BUS_DMASYNC_PREWRITE); + + DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len)); + + /* kick firmware */ + sc->txfree--; + sc->txcur = (sc->txcur + 1) % IPW_NTBD; + CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); + + /* wait at most one second for command to complete */ + return msleep(sc, &sc->sc_mtx, 0, "ipwcmd", hz); +} + +static int +ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) +{ + struct ipw_softc *sc = ifp->if_softc; + struct ieee80211com *ic = &sc->sc_ic; + struct ieee80211_frame *wh; + struct ipw_soft_bd *sbd; + struct ipw_soft_hdr *shdr; + struct ipw_soft_buf *sbuf; + struct ieee80211_key *k; + struct mbuf *mnew; + bus_dma_segment_t segs[IPW_MAX_NSEG]; + bus_addr_t physaddr; + int nsegs, error, i; + + wh = mtod(m0, struct ieee80211_frame *); + + if (wh->i_fc[1] & IEEE80211_FC1_WEP) { + k = ieee80211_crypto_encap(ic, ni, m0); + if (k == NULL) + return ENOBUFS; + + /* packet header may have moved, reset our local pointer */ + wh = mtod(m0, struct ieee80211_frame *); + } + + if (sc->sc_drvbpf != NULL) { + struct ipw_tx_radiotap_header *tap = &sc->sc_txtap; + + tap->wt_flags = 0; + tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); + tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); + + bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); + } + + shdr = SLIST_FIRST(&sc->free_shdr); + sbuf = SLIST_FIRST(&sc->free_sbuf); + KASSERT(shdr != NULL && sbuf != NULL, ("empty sw hdr/buf pool")); + + shdr->hdr.type = htole32(IPW_HDR_TYPE_SEND); + shdr->hdr.subtype = 0; + shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0; + shdr->hdr.encrypt = 0; + shdr->hdr.keyidx = 0; + shdr->hdr.keysz = 0; + shdr->hdr.fragmentsz = 0; + IEEE80211_ADDR_COPY(shdr->hdr.src_addr, wh->i_addr2); + if (ic->ic_opmode == IEEE80211_M_STA) + IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr3); + else + IEEE80211_ADDR_COPY(shdr->hdr.dst_addr, wh->i_addr1); + + /* trim IEEE802.11 header */ + m_adj(m0, sizeof (struct ieee80211_frame)); + + error = bus_dmamap_load_mbuf_sg(sc->txbuf_dmat, sbuf->map, m0, segs, + &nsegs, 0); + if (error != 0 && error != EFBIG) { + device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", + error); + m_freem(m0); + return error; + } + if (error != 0) { + mnew = m_defrag(m0, M_DONTWAIT); + if (mnew == NULL) { + device_printf(sc->sc_dev, + "could not defragment mbuf\n"); + m_freem(m0); + return ENOBUFS; + } + m0 = mnew; + + error = bus_dmamap_load_mbuf_sg(sc->txbuf_dmat, sbuf->map, m0, + segs, &nsegs, 0); + if (error != 0) { + device_printf(sc->sc_dev, + "could not map mbuf (error %d)\n", error); + m_freem(m0); + return error; + } + } + + error = bus_dmamap_load(sc->hdr_dmat, shdr->map, &shdr->hdr, + sizeof (struct ipw_hdr), ipw_dma_map_addr, &physaddr, 0); + if (error != 0) { + device_printf(sc->sc_dev, "could not map header DMA memory\n"); + bus_dmamap_unload(sc->txbuf_dmat, sbuf->map); + m_freem(m0); + return error; + } + + SLIST_REMOVE_HEAD(&sc->free_sbuf, next); + SLIST_REMOVE_HEAD(&sc->free_shdr, next); + + sbd = &sc->stbd_list[sc->txcur]; + sbd->type = IPW_SBD_TYPE_HEADER; + sbd->priv = shdr; + sbd->bd->physaddr = htole32(physaddr); + sbd->bd->len = htole32(sizeof (struct ipw_hdr)); + sbd->bd->nfrag = 1 + nsegs; + sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 | + IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; + + DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, %6D, %6D)\n", + shdr->hdr.type, shdr->hdr.subtype, shdr->hdr.encrypted, + shdr->hdr.encrypt, shdr->hdr.src_addr, ":", shdr->hdr.dst_addr, + ":")); + + sc->txfree--; + sc->txcur = (sc->txcur + 1) % IPW_NTBD; + + sbuf->m = m0; + sbuf->ni = ni; + + for (i = 0; i < nsegs; i++) { + sbd = &sc->stbd_list[sc->txcur]; + + sbd->bd->physaddr = htole32(segs[i].ds_addr); + sbd->bd->len = htole32(segs[i].ds_len); + sbd->bd->nfrag = 0; + sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3; + if (i == nsegs - 1) { + sbd->type = IPW_SBD_TYPE_DATA; + sbd->priv = sbuf; + sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT; + } else { + sbd->type = IPW_SBD_TYPE_NOASSOC; + sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT; + } + + DPRINTFN(5, ("sending fragment (%d, %d)\n", i, segs[i].ds_len)); + + sc->txfree--; + sc->txcur = (sc->txcur + 1) % IPW_NTBD; + } + + bus_dmamap_sync(sc->hdr_dmat, shdr->map, BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(sc->txbuf_dmat, sbuf->map, BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(sc->tbd_dmat, sc->tbd_map, BUS_DMASYNC_PREWRITE); + + /* kick firmware */ + CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); + + return 0; +} + +static void +ipw_start(struct ifnet *ifp) +{ + struct ipw_softc *sc = ifp->if_softc; + struct ieee80211com *ic = &sc->sc_ic; + struct mbuf *m0; + struct ether_header *eh; + struct ieee80211_node *ni; + + IPW_LOCK(sc); + + if (ic->ic_state != IEEE80211_S_RUN) { + IPW_UNLOCK(sc); + return; + } + + for (;;) { + IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); + if (m0 == NULL) + break; + + if (sc->txfree < 1 + IPW_MAX_NSEG) { + IFQ_DRV_PREPEND(&ifp->if_snd, m0); + ifp->if_flags |= IFF_OACTIVE; + break; + } + + if (m0->m_len < sizeof (struct ether_header) && + (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) + continue; + + eh = mtod(m0, struct ether_header *); + ni = ieee80211_find_txnode(ic, eh->ether_dhost); + if (ni == NULL) { + m_freem(m0); + continue; + } + BPF_MTAP(ifp, m0); + + m0 = ieee80211_encap(ic, m0, ni); + if (m0 == NULL) { + ieee80211_free_node(ni); + continue; + } + + if (ic->ic_rawbpf != NULL) + bpf_mtap(ic->ic_rawbpf, m0); + + if (ipw_tx_start(ifp, m0, ni) != 0) { + ieee80211_free_node(ni); + ifp->if_oerrors++; + break; + } + + /* start watchdog timer */ + sc->sc_tx_timer = 5; + ifp->if_timer = 1; + } + + IPW_UNLOCK(sc); +} + +static void +ipw_watchdog(struct ifnet *ifp) +{ + struct ipw_softc *sc = ifp->if_softc; + struct ieee80211com *ic = &sc->sc_ic; + + ifp->if_timer = 0; + + if (sc->sc_tx_timer > 0) { + if (--sc->sc_tx_timer == 0) { + if_printf(ifp, "device timeout\n"); + ifp->if_oerrors++; + ifp->if_flags &= ~IFF_UP; + ipw_stop(sc); + return; + } + ifp->if_timer = 1; + } + + ieee80211_watchdog(ic); +} + +static int +ipw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) +{ + struct ipw_softc *sc = ifp->if_softc; + struct ieee80211com *ic = &sc->sc_ic; + struct ifreq *ifr; + int error = 0; + + IPW_LOCK(sc); + + switch (cmd) { + case SIOCSIFFLAGS: + if (ifp->if_flags & IFF_UP) { + if (!(ifp->if_flags & IFF_RUNNING)) + ipw_init(sc); + } else { + if (ifp->if_flags & IFF_RUNNING) + ipw_stop(sc); + } + break; + + case SIOCSLOADFW: + /* only super-user can do that! */ + if ((error = suser(curthread)) != 0) + break; + + ifr = (struct ifreq *)data; + error = ipw_cache_firmware(sc, ifr->ifr_data); + break; + + case SIOCSKILLFW: + /* only super-user can do that! */ + if ((error = suser(curthread)) != 0) + break; + + ifp->if_flags &= ~IFF_UP; + ipw_stop(sc); + ipw_free_firmware(sc); + break; + + default: + error = ieee80211_ioctl(ic, cmd, data); + } + + if (error == ENETRESET) { + if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == + (IFF_UP | IFF_RUNNING)) + ipw_init(sc); + error = 0; + } + + IPW_UNLOCK(sc); + + return error; +} + +static void +ipw_stop_master(struct ipw_softc *sc) +{ + int ntries; + + /* disable interrupts */ + CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); + + CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER); + for (ntries = 0; ntries < 50; ntries++) { + if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) + break; + DELAY(10); + } + if (ntries == 50) + device_printf(sc->sc_dev, "timeout waiting for master\n"); + + CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | + IPW_RST_PRINCETON_RESET); + + sc->flags &= ~IPW_FLAG_FW_INITED; +} + +static int +ipw_reset(struct ipw_softc *sc) +{ + int ntries; + + ipw_stop_master(sc); + + /* move adapter to D0 state */ + CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | + IPW_CTL_INIT); + + /* wait for clock stabilization */ + for (ntries = 0; ntries < 1000; ntries++) { + if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) + break; + DELAY(200); + } + if (ntries == 1000) + return EIO; + + CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) | + IPW_RST_SW_RESET); + + DELAY(10); + + CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | + IPW_CTL_INIT); + + return 0; +} + +/* + * Upload the microcode to the device. + */ +static int +ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size) +{ + int ntries; + + MEM_WRITE_4(sc, 0x3000e0, 0x80000000); + CSR_WRITE_4(sc, IPW_CSR_RST, 0); + + MEM_WRITE_2(sc, 0x220000, 0x0703); + MEM_WRITE_2(sc, 0x220000, 0x0707); + + MEM_WRITE_1(sc, 0x210014, 0x72); + MEM_WRITE_1(sc, 0x210014, 0x72); + + MEM_WRITE_1(sc, 0x210000, 0x40); + MEM_WRITE_1(sc, 0x210000, 0x00); + MEM_WRITE_1(sc, 0x210000, 0x40); + + MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); + + MEM_WRITE_1(sc, 0x210000, 0x00); + MEM_WRITE_1(sc, 0x210000, 0x00); + MEM_WRITE_1(sc, 0x210000, 0x80); + + MEM_WRITE_2(sc, 0x220000, 0x0703); + MEM_WRITE_2(sc, 0x220000, 0x0707); + + MEM_WRITE_1(sc, 0x210014, 0x72); + MEM_WRITE_1(sc, 0x210014, 0x72); + + MEM_WRITE_1(sc, 0x210000, 0x00); + MEM_WRITE_1(sc, 0x210000, 0x80); + + for (ntries = 0; ntries < 10; ntries++) { + if (MEM_READ_1(sc, 0x210000) & 1) + break; + DELAY(10); + } + if (ntries == 10) { + device_printf(sc->sc_dev, + "timeout waiting for ucode to initialize\n"); + return EIO; + } + + MEM_WRITE_4(sc, 0x3000e0, 0); + + return 0; +} + +/* set of macros to handle unaligned little endian data in firmware image */ +#define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) +#define GETLE16(p) ((p)[0] | (p)[1] << 8) +static int +ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size) +{ + u_char *p, *end; + uint32_t dst; + uint16_t len; + int error; + + p = fw; + end = fw + size; + while (p < end) { + dst = GETLE32(p); p += 4; + len = GETLE16(p); p += 2; + + ipw_write_mem_1(sc, dst, p, len); + p += len; + } + + CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK | + IPW_IO_LED_OFF); + + /* enable interrupts */ + CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK); + + /* kick the firmware */ + CSR_WRITE_4(sc, IPW_CSR_RST, 0); + + CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) | + IPW_CTL_ALLOW_STANDBY); + + /* wait at most one second for firmware initialization to complete */ + if ((error = msleep(sc, &sc->sc_mtx, 0, "ipwinit", hz)) != 0) { + device_printf(sc->sc_dev, "timeout waiting for firmware " + "initialization to complete\n"); + return error; + } + + CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) | + IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK); + + return 0; +} + +/* + * Store firmware into kernel memory so we can download it when we need to, + * e.g when the adapter wakes up from suspend mode. + */ +static int +ipw_cache_firmware(struct ipw_softc *sc, void *data) +{ + struct ipw_firmware *fw = &sc->fw; + struct ipw_firmware_hdr hdr; + u_char *p = data; + int error; + + ipw_free_firmware(sc); + + IPW_UNLOCK(sc); + + if ((error = copyin(data, &hdr, sizeof hdr)) != 0) + goto fail1; + + fw->main_size = le32toh(hdr.main_size); + fw->ucode_size = le32toh(hdr.ucode_size); + p += sizeof hdr; + + fw->main = malloc(fw->main_size, M_DEVBUF, M_NOWAIT); + if (fw->main == NULL) { + error = ENOMEM; + goto fail1; + } + + fw->ucode = malloc(fw->ucode_size, M_DEVBUF, M_NOWAIT); + if (fw->ucode == NULL) { + error = ENOMEM; + goto fail2; + } + + if ((error = copyin(p, fw->main, fw->main_size)) != 0) + goto fail3; + + p += fw->main_size; + if ((error = copyin(p, fw->ucode, fw->ucode_size)) != 0) + goto fail3; + + DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size, + fw->ucode_size)); + + IPW_LOCK(sc); + + sc->flags |= IPW_FLAG_FW_CACHED; + + return 0; + +fail3: free(fw->ucode, M_DEVBUF); +fail2: free(fw->main, M_DEVBUF); +fail1: IPW_LOCK(sc); + + return error; +} + +static void +ipw_free_firmware(struct ipw_softc *sc) +{ + if (!(sc->flags & IPW_FLAG_FW_CACHED)) + return; + + free(sc->fw.main, M_DEVBUF); + free(sc->fw.ucode, M_DEVBUF); + + sc->flags &= ~IPW_FLAG_FW_CACHED; +} + +static int +ipw_config(struct ipw_softc *sc) +{ + struct ieee80211com *ic = &sc->sc_ic; + struct ifnet *ifp = ic->ic_ifp; + struct ipw_security security; + struct ieee80211_key *k; + struct ipw_wep_key wepkey; + struct ipw_scan_options options; + struct ipw_configuration config; + uint32_t data; + int error, i; + + switch (ic->ic_opmode) { + case IEEE80211_M_STA: + case IEEE80211_M_HOSTAP: + data = htole32(IPW_MODE_BSS); + break; + + case IEEE80211_M_IBSS: + case IEEE80211_M_AHDEMO: + data = htole32(IPW_MODE_IBSS); + break; + + case IEEE80211_M_MONITOR: + data = htole32(IPW_MODE_MONITOR); + break; + } + DPRINTF(("Setting mode to %u\n", le32toh(data))); + error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data); + if (error != 0) + return error; + + if (ic->ic_opmode == IEEE80211_M_IBSS || + ic->ic_opmode == IEEE80211_M_MONITOR) { + data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan)); + DPRINTF(("Setting channel to %u\n", le32toh(data))); + error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data); + if (error != 0) + return error; + } + + if (ic->ic_opmode == IEEE80211_M_MONITOR) { + DPRINTF(("Enabling adapter\n")); + return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); + } + + IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); + DPRINTF(("Setting MAC address to %6D\n", ic->ic_myaddr, ":")); + error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, + IEEE80211_ADDR_LEN); + if (error != 0) + return error; + + config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK | + IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE); + if (ic->ic_opmode == IEEE80211_M_IBSS) + config.flags |= htole32(IPW_CFG_IBSS_AUTO_START); + if (ifp->if_flags & IFF_PROMISC) + config.flags |= htole32(IPW_CFG_PROMISCUOUS); + config.bss_chan = htole32(0x3fff); /* channels 1-14 */ + config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ + DPRINTF(("Setting configuration to 0x%x\n", le32toh(config.flags))); + error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config); + if (error != 0) + return error; + + data = htole32(0x3); /* 1, 2 */ + DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); + error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data); + if (error != 0) + return error; + + data = htole32(0xf); /* 1, 2, 5.5, 11 */ + DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); + error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data); + if (error != 0) + return error; + + data = htole32(IPW_POWER_MODE_CAM); + DPRINTF(("Setting power mode to %u\n", le32toh(data))); + error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data); + if (error != 0) + return error; + + if (ic->ic_opmode == IEEE80211_M_IBSS) { + data = htole32(32); /* default value */ + DPRINTF(("Setting tx power index to %u\n", le32toh(data))); + error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data, + sizeof data); + if (error != 0) + return error; + } + + data = htole32(ic->ic_rtsthreshold); + DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); + error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data); + if (error != 0) + return error; + + data = htole32(ic->ic_fragthreshold); + DPRINTF(("Setting frag threshold to %u\n", le32toh(data))); + error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data); + if (error != 0) + return error; + +#ifdef IPW_DEBUG + if (ipw_debug > 0) { + printf("Setting ESSID to "); + ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen); + printf("\n"); + } +#endif + error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid, + ic->ic_des_esslen); + if (error != 0) + return error; + + /* no mandatory BSSID */ + DPRINTF(("Setting mandatory BSSID to null\n")); + error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); + if (error != 0) + return error; + + if (ic->ic_flags & IEEE80211_F_DESBSSID) { + DPRINTF(("Setting desired BSSID to %6D\n", ic->ic_des_bssid, + ":")); + error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID, + ic->ic_des_bssid, IEEE80211_ADDR_LEN); + if (error != 0) + return error; + } + + bzero(&security, sizeof security); + security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ? + IPW_AUTH_SHARED : IPW_AUTH_OPEN; + security.ciphers = htole32(IPW_CIPHER_NONE); + DPRINTF(("Setting authmode to %u\n", security.authmode)); + error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security, + sizeof security); + if (error != 0) + return error; + + if (ic->ic_flags & IEEE80211_F_PRIVACY) { + k = ic->ic_crypto.cs_nw_keys; + for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) { + if (k->wk_keylen == 0) + continue; + + wepkey.idx = i; + wepkey.len = k->wk_keylen; + bzero(wepkey.key, sizeof wepkey.key); + bcopy(k->wk_key, wepkey.key, k->wk_keylen); + DPRINTF(("Setting wep key index %u len %u\n", + wepkey.idx, wepkey.len)); + error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey, + sizeof wepkey); + if (error != 0) + return error; + } + + data = htole32(ic->ic_crypto.cs_def_txkey); + DPRINTF(("Setting wep tx key index to %u\n", le32toh(data))); + error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data, + sizeof data); + if (error != 0) + return error; + } + + data = htole32((ic->ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); + DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); + error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data); + if (error != 0) + return error; + +#if 0 + struct ipw_wpa_ie ie; + + bzero(&ie, sizeof ie); + ie.len = htole32(sizeof (struct ieee80211_ie_wpa)); + DPRINTF(("Setting wpa ie\n")); + error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie); + if (error != 0) + return error; +#endif + + if (ic->ic_opmode == IEEE80211_M_IBSS) { + data = htole32(ic->ic_lintval); + DPRINTF(("Setting beacon interval to %u\n", le32toh(data))); + error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data, + sizeof data); + if (error != 0) + return error; + } + + options.flags = 0; + options.channels = htole32(0x3fff); /* scan channels 1-14 */ + DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags))); + error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options); + if (error != 0) + return error; + + /* finally, enable adapter (start scanning for an access point) */ + DPRINTF(("Enabling adapter\n")); + return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); +} + +static void +ipw_init(void *priv) +{ + struct ipw_softc *sc = priv; + struct ieee80211com *ic = &sc->sc_ic; + struct ifnet *ifp = ic->ic_ifp; + struct ipw_firmware *fw = &sc->fw; + + /* exit immediately if firmware has not been ioctl'd */ + if (!(sc->flags & IPW_FLAG_FW_CACHED)) { + ifp->if_flags &= ~IFF_UP; + return; + } + + ipw_stop(sc); + + if (ipw_reset(sc) != 0) { + device_printf(sc->sc_dev, "could not reset adapter\n"); + goto fail; + } + + if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) { + device_printf(sc->sc_dev, "could not load microcode\n"); + goto fail; + } + + ipw_stop_master(sc); + + /* + * Setup tx, rx and status rings. + */ + sc->txold = IPW_NTBD - 1; + sc->txcur = 0; + sc->txfree = IPW_NTBD - 2; + sc->rxcur = IPW_NRBD - 1; + + CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_phys); + CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD); + CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); + CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur); + + CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_phys); + CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD); + CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); + CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur); + + CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_phys); + + if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) { + device_printf(sc->sc_dev, "could not load firmware\n"); + goto fail; + } + + sc->flags |= IPW_FLAG_FW_INITED; + + /* retrieve information tables base addresses */ + sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE); + sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE); + + ipw_write_table1(sc, IPW_INFO_LOCK, 0); + + if (ipw_config(sc) != 0) { + device_printf(sc->sc_dev, "device configuration failed\n"); + goto fail; + } + + ifp->if_flags &= ~IFF_OACTIVE; + ifp->if_flags |= IFF_RUNNING; + + return; + +fail: ifp->if_flags &= ~IFF_UP; + ipw_stop(sc); +} + +static void +ipw_stop(void *priv) +{ + struct ipw_softc *sc = priv; + struct ieee80211com *ic = &sc->sc_ic; + struct ifnet *ifp = ic->ic_ifp; + int i; + + ipw_stop_master(sc); + + CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET); + + /* + * Release tx buffers. + */ + for (i = 0; i < IPW_NTBD; i++) + ipw_release_sbd(sc, &sc->stbd_list[i]); + + sc->sc_tx_timer = 0; + ifp->if_timer = 0; + ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); + + ieee80211_new_state(ic, IEEE80211_S_INIT, -1); +} + +#ifdef IPW_DEBUG +static int +ipw_sysctl_stats(SYSCTL_HANDLER_ARGS) +{ + struct ipw_softc *sc = arg1; + uint32_t i, size, buf[256]; + + if (!(sc->flags & IPW_FLAG_FW_INITED)) { + bzero(buf, sizeof buf); + return SYSCTL_OUT(req, buf, sizeof buf); + } + + CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base); + + size = min(CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA), 256); + for (i = 1; i < size; i++) + buf[i] = MEM_READ_4(sc, CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA)); + + return SYSCTL_OUT(req, buf, sizeof buf); +} +#endif + +static int +ipw_sysctl_radio(SYSCTL_HANDLER_ARGS) +{ + struct ipw_softc *sc = arg1; + int val; + + val = !((sc->flags & IPW_FLAG_HAS_RADIO_SWITCH) && + (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED)); + + return SYSCTL_OUT(req, &val, sizeof val); +} + +static uint32_t +ipw_read_table1(struct ipw_softc *sc, uint32_t off) +{ + return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off)); +} + +static void +ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info) +{ + MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info); +} + +static int +ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len) +{ + uint32_t addr, info; + uint16_t count, size; + uint32_t total; + + /* addr[4] + count[2] + size[2] */ + addr = MEM_READ_4(sc, sc->table2_base + off); + info = MEM_READ_4(sc, sc->table2_base + off + 4); + + count = info >> 16; + size = info & 0xffff; + total = count * size; + + if (total > *len) { + *len = total; + return EINVAL; + } + + *len = total; + ipw_read_mem_1(sc, addr, buf, total); + + return 0; +} + +static void +ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, + bus_size_t count) +{ + for (; count > 0; offset++, datap++, count--) { + CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); + *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3)); + } +} + +static void +ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap, + bus_size_t count) +{ + for (; count > 0; offset++, datap++, count--) { + CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3); + CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap); + } +} diff --git a/sys/dev/ipw/if_ipwreg.h b/sys/dev/ipw/if_ipwreg.h new file mode 100644 index 0000000..9cbd62f --- /dev/null +++ b/sys/dev/ipw/if_ipwreg.h @@ -0,0 +1,361 @@ +/* $FreeBSD$ */ + +/*- + * Copyright (c) 2004, 2005 + * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice unmodified, this list of conditions, and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#define IPW_NTBD 128 +#define IPW_TBD_SZ (IPW_NTBD * sizeof (struct ipw_bd)) +#define IPW_NDATA (IPW_NTBD / 2) +#define IPW_NRBD 128 +#define IPW_RBD_SZ (IPW_NRBD * sizeof (struct ipw_bd)) +#define IPW_STATUS_SZ (IPW_NRBD * sizeof (struct ipw_status)) + +#define IPW_CSR_INTR 0x0008 +#define IPW_CSR_INTR_MASK 0x000c +#define IPW_CSR_INDIRECT_ADDR 0x0010 +#define IPW_CSR_INDIRECT_DATA 0x0014 +#define IPW_CSR_AUTOINC_ADDR 0x0018 +#define IPW_CSR_AUTOINC_DATA 0x001c +#define IPW_CSR_RST 0x0020 +#define IPW_CSR_CTL 0x0024 +#define IPW_CSR_IO 0x0030 +#define IPW_CSR_TX_BASE 0x0200 +#define IPW_CSR_TX_SIZE 0x0204 +#define IPW_CSR_RX_BASE 0x0240 +#define IPW_CSR_STATUS_BASE 0x0244 +#define IPW_CSR_RX_SIZE 0x0248 +#define IPW_CSR_TX_READ 0x0280 +#define IPW_CSR_RX_READ 0x02a0 +#define IPW_CSR_TABLE1_BASE 0x0380 +#define IPW_CSR_TABLE2_BASE 0x0384 +#define IPW_CSR_TX_WRITE 0x0f80 +#define IPW_CSR_RX_WRITE 0x0fa0 + +/* possible flags for register IPW_CSR_INTR */ +#define IPW_INTR_TX_TRANSFER 0x00000001 +#define IPW_INTR_RX_TRANSFER 0x00000002 +#define IPW_INTR_STATUS_CHANGE 0x00000010 +#define IPW_INTR_COMMAND_DONE 0x00010000 +#define IPW_INTR_FW_INIT_DONE 0x01000000 +#define IPW_INTR_FATAL_ERROR 0x40000000 +#define IPW_INTR_PARITY_ERROR 0x80000000 + +#define IPW_INTR_MASK \ + (IPW_INTR_TX_TRANSFER | IPW_INTR_RX_TRANSFER | \ + IPW_INTR_STATUS_CHANGE | IPW_INTR_COMMAND_DONE | \ + IPW_INTR_FW_INIT_DONE | IPW_INTR_FATAL_ERROR | \ + IPW_INTR_PARITY_ERROR) + +/* possible flags for register IPW_CSR_RST */ +#define IPW_RST_PRINCETON_RESET 0x00000001 +#define IPW_RST_SW_RESET 0x00000080 +#define IPW_RST_MASTER_DISABLED 0x00000100 +#define IPW_RST_STOP_MASTER 0x00000200 + +/* possible flags for register IPW_CSR_CTL */ +#define IPW_CTL_CLOCK_READY 0x00000001 +#define IPW_CTL_ALLOW_STANDBY 0x00000002 +#define IPW_CTL_INIT 0x00000004 + +/* possible flags for register IPW_CSR_IO */ +#define IPW_IO_GPIO1_ENABLE 0x00000008 +#define IPW_IO_GPIO1_MASK 0x0000000c +#define IPW_IO_GPIO3_MASK 0x000000c0 +#define IPW_IO_LED_OFF 0x00002000 +#define IPW_IO_RADIO_DISABLED 0x00010000 + +#define IPW_STATE_ASSOCIATED 0x0004 +#define IPW_STATE_ASSOCIATION_LOST 0x0008 +#define IPW_STATE_SCAN_COMPLETE 0x0020 +#define IPW_STATE_RADIO_DISABLED 0x0100 +#define IPW_STATE_DISABLED 0x0200 +#define IPW_STATE_SCANNING 0x0800 + +/* table1 offsets */ +#define IPW_INFO_LOCK 480 +#define IPW_INFO_APS_CNT 604 +#define IPW_INFO_APS_BASE 608 +#define IPW_INFO_CARD_DISABLED 628 +#define IPW_INFO_CURRENT_CHANNEL 756 +#define IPW_INFO_CURRENT_TX_RATE 768 + +/* table2 offsets */ +#define IPW_INFO_CURRENT_SSID 48 +#define IPW_INFO_CURRENT_BSSID 112 + +/* supported rates */ +#define IPW_RATE_DS1 1 +#define IPW_RATE_DS2 2 +#define IPW_RATE_DS5 4 +#define IPW_RATE_DS11 8 + +/* firmware binary image header */ +struct ipw_firmware_hdr { + u_int32_t version; + u_int32_t main_size; /* firmware size */ + u_int32_t ucode_size; /* microcode size */ +} __packed; + +/* buffer descriptor */ +struct ipw_bd { + u_int32_t physaddr; + u_int32_t len; + u_int8_t flags; +#define IPW_BD_FLAG_TX_FRAME_802_3 0x00 +#define IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT 0x01 +#define IPW_BD_FLAG_TX_FRAME_COMMAND 0x02 +#define IPW_BD_FLAG_TX_FRAME_802_11 0x04 +#define IPW_BD_FLAG_TX_LAST_FRAGMENT 0x08 + u_int8_t nfrag; /* number of fragments */ + u_int8_t reserved[6]; +} __packed; + +/* status */ +struct ipw_status { + u_int32_t len; + u_int16_t code; +#define IPW_STATUS_CODE_COMMAND 0 +#define IPW_STATUS_CODE_NEWSTATE 1 +#define IPW_STATUS_CODE_DATA_802_11 2 +#define IPW_STATUS_CODE_DATA_802_3 3 +#define IPW_STATUS_CODE_NOTIFICATION 4 + u_int8_t flags; +#define IPW_STATUS_FLAG_DECRYPTED 0x01 +#define IPW_STATUS_FLAG_WEP_ENCRYPTED 0x02 + u_int8_t rssi; /* received signal strength indicator */ +} __packed; + +/* data header */ +struct ipw_hdr { + u_int32_t type; +#define IPW_HDR_TYPE_SEND 33 + u_int32_t subtype; + u_int8_t encrypted; + u_int8_t encrypt; + u_int8_t keyidx; + u_int8_t keysz; + u_int8_t key[IEEE80211_KEYBUF_SIZE]; + u_int8_t reserved[10]; + u_int8_t src_addr[IEEE80211_ADDR_LEN]; + u_int8_t dst_addr[IEEE80211_ADDR_LEN]; + u_int16_t fragmentsz; +} __packed; + +/* command */ +struct ipw_cmd { + u_int32_t type; +#define IPW_CMD_ENABLE 2 +#define IPW_CMD_SET_CONFIGURATION 6 +#define IPW_CMD_SET_ESSID 8 +#define IPW_CMD_SET_MANDATORY_BSSID 9 +#define IPW_CMD_SET_MAC_ADDRESS 11 +#define IPW_CMD_SET_MODE 12 +#define IPW_CMD_SET_CHANNEL 14 +#define IPW_CMD_SET_RTS_THRESHOLD 15 +#define IPW_CMD_SET_FRAG_THRESHOLD 16 +#define IPW_CMD_SET_POWER_MODE 17 +#define IPW_CMD_SET_TX_RATES 18 +#define IPW_CMD_SET_BASIC_TX_RATES 19 +#define IPW_CMD_SET_WEP_KEY 20 +#define IPW_CMD_SET_WEP_KEY_INDEX 25 +#define IPW_CMD_SET_WEP_FLAGS 26 +#define IPW_CMD_ADD_MULTICAST 27 +#define IPW_CMD_SET_BEACON_INTERVAL 29 +#define IPW_CMD_SET_TX_POWER_INDEX 36 +#define IPW_CMD_BROADCAST_SCAN 43 +#define IPW_CMD_DISABLE 44 +#define IPW_CMD_SET_DESIRED_BSSID 45 +#define IPW_CMD_SET_SCAN_OPTIONS 46 +#define IPW_CMD_PREPARE_POWER_DOWN 58 +#define IPW_CMD_DISABLE_PHY 61 +#define IPW_CMD_SET_SECURITY_INFORMATION 67 +#define IPW_CMD_SET_WPA_IE 69 + u_int32_t subtype; + u_int32_t seq; + u_int32_t len; + u_int8_t data[400]; + u_int32_t status; + u_int8_t reserved[68]; +} __packed; + +/* possible values for command IPW_CMD_SET_POWER_MODE */ +#define IPW_POWER_MODE_CAM 0 +#define IPW_POWER_AUTOMATIC 6 + +/* possible values for command IPW_CMD_SET_MODE */ +#define IPW_MODE_BSS 0 +#define IPW_MODE_IBSS 1 +#define IPW_MODE_MONITOR 2 + +/* possible flags for command IPW_CMD_SET_WEP_FLAGS */ +#define IPW_WEPON 0x8 + +/* structure for command IPW_CMD_SET_WEP_KEY */ +struct ipw_wep_key { + u_int8_t idx; + u_int8_t len; + u_int8_t key[13]; +} __packed; + +/* structure for command IPW_CMD_SET_SECURITY_INFORMATION */ +struct ipw_security { + u_int32_t ciphers; +#define IPW_CIPHER_NONE 0x00000001 +#define IPW_CIPHER_WEP40 0x00000002 +#define IPW_CIPHER_TKIP 0x00000004 +#define IPW_CIPHER_CCMP 0x00000010 +#define IPW_CIPHER_WEP104 0x00000020 +#define IPW_CIPHER_CKIP 0x00000040 + u_int16_t reserved1; + u_int8_t authmode; +#define IPW_AUTH_OPEN 0 +#define IPW_AUTH_SHARED 1 + u_int16_t reserved2; +} __packed; + +/* structure for command IPW_CMD_SET_SCAN_OPTIONS */ +struct ipw_scan_options { + u_int32_t flags; +#define IPW_SCAN_DO_NOT_ASSOCIATE 0x00000001 +#define IPW_SCAN_PASSIVE 0x00000008 + u_int32_t channels; +} __packed; + +/* structure for command IPW_CMD_SET_CONFIGURATION */ +struct ipw_configuration { + u_int32_t flags; +#define IPW_CFG_PROMISCUOUS 0x00000004 +#define IPW_CFG_PREAMBLE_AUTO 0x00000010 +#define IPW_CFG_IBSS_AUTO_START 0x00000020 +#define IPW_CFG_802_1x_ENABLE 0x00004000 +#define IPW_CFG_BSS_MASK 0x00008000 +#define IPW_CFG_IBSS_MASK 0x00010000 + u_int32_t bss_chan; + u_int32_t ibss_chan; +} __packed; + +/* structure for command IPW_CMD_SET_WPA_IE */ +struct ipw_wpa_ie { + u_int16_t mask; + u_int16_t capinfo; + u_int16_t lintval; + u_int8_t bssid[IEEE80211_ADDR_LEN]; + u_int32_t len; + struct ieee80211_ie_wpa ie; +} __packed; + +/* element in AP table */ +struct ipw_node { + u_int32_t reserved1[2]; + u_int8_t bssid[IEEE80211_ADDR_LEN]; + u_int8_t chan; + u_int8_t rates; + u_int16_t reserved2; + u_int16_t capinfo; + u_int16_t reserved3; + u_int16_t intval; + u_int8_t reserved4[28]; + u_int8_t essid[IEEE80211_NWID_LEN]; + u_int16_t reserved5; + u_int8_t esslen; + u_int8_t reserved6[7]; + u_int8_t rssi; +} __packed; + +/* EEPROM = Electrically Erasable Programmable Read-Only Memory */ + +#define IPW_MEM_EEPROM_CTL 0x00300040 + +#define IPW_EEPROM_RADIO 0x11 +#define IPW_EEPROM_MAC 0x21 +#define IPW_EEPROM_CHANNEL_LIST 0x37 + +#define IPW_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ + +#define IPW_EEPROM_C (1 << 0) /* Serial Clock */ +#define IPW_EEPROM_S (1 << 1) /* Chip Select */ +#define IPW_EEPROM_D (1 << 2) /* Serial data input */ +#define IPW_EEPROM_Q (1 << 4) /* Serial data output */ + +#define IPW_EEPROM_SHIFT_D 2 +#define IPW_EEPROM_SHIFT_Q 4 + +/* + * control and status registers access macros + */ +#define CSR_READ_1(sc, reg) \ + bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) + +#define CSR_READ_2(sc, reg) \ + bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) + +#define CSR_READ_4(sc, reg) \ + bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) + +#define CSR_WRITE_1(sc, reg, val) \ + bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) + +#define CSR_WRITE_2(sc, reg, val) \ + bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) + +#define CSR_WRITE_4(sc, reg, val) \ + bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) + +#define CSR_WRITE_MULTI_1(sc, reg, buf, len) \ + bus_space_write_multi_1((sc)->sc_st, (sc)->sc_sh, (reg), \ + (buf), (len)) + +/* + * indirect memory space access macros + */ +#define MEM_WRITE_1(sc, addr, val) do { \ + CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ + CSR_WRITE_1((sc), IPW_CSR_INDIRECT_DATA, (val)); \ +} while (/* CONSTCOND */0) + +#define MEM_WRITE_2(sc, addr, val) do { \ + CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ + CSR_WRITE_2((sc), IPW_CSR_INDIRECT_DATA, (val)); \ +} while (/* CONSTCOND */0) + +#define MEM_WRITE_4(sc, addr, val) do { \ + CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ + CSR_WRITE_4((sc), IPW_CSR_INDIRECT_DATA, (val)); \ +} while (/* CONSTCOND */0) + +#define MEM_WRITE_MULTI_1(sc, addr, buf, len) do { \ + CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ + CSR_WRITE_MULTI_1((sc), IPW_CSR_INDIRECT_DATA, (buf), (len)); \ +} while (/* CONSTCOND */0) + +/* + * EEPROM access macro + */ +#define IPW_EEPROM_CTL(sc, val) do { \ + MEM_WRITE_4((sc), IPW_MEM_EEPROM_CTL, (val)); \ + DELAY(IPW_EEPROM_DELAY); \ +} while (0) diff --git a/sys/dev/ipw/if_ipwvar.h b/sys/dev/ipw/if_ipwvar.h new file mode 100644 index 0000000..c03f5d7 --- /dev/null +++ b/sys/dev/ipw/if_ipwvar.h @@ -0,0 +1,173 @@ +/* $FreeBSD$ */ + +/*- + * Copyright (c) 2004, 2005 + * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice unmodified, this list of conditions, and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +struct ipw_firmware { + void *main; + int main_size; + void *ucode; + int ucode_size; +}; + +#define IPW_MAX_NSEG 1 + +struct ipw_soft_bd { + struct ipw_bd *bd; + int type; +#define IPW_SBD_TYPE_NOASSOC 0 +#define IPW_SBD_TYPE_COMMAND 1 +#define IPW_SBD_TYPE_HEADER 2 +#define IPW_SBD_TYPE_DATA 3 + void *priv; +}; + +struct ipw_soft_hdr { + struct ipw_hdr hdr; + bus_dmamap_t map; + SLIST_ENTRY(ipw_soft_hdr) next; +}; + +struct ipw_soft_buf { + struct mbuf *m; + struct ieee80211_node *ni; + bus_dmamap_t map; + SLIST_ENTRY(ipw_soft_buf) next; +}; + +struct ipw_rx_radiotap_header { + struct ieee80211_radiotap_header wr_ihdr; + uint8_t wr_flags; + uint16_t wr_chan_freq; + uint16_t wr_chan_flags; + uint8_t wr_antsignal; +}; + +#define IPW_RX_RADIOTAP_PRESENT \ + ((1 << IEEE80211_RADIOTAP_FLAGS) | \ + (1 << IEEE80211_RADIOTAP_CHANNEL) | \ + (1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL)) + +struct ipw_tx_radiotap_header { + struct ieee80211_radiotap_header wt_ihdr; + uint8_t wt_flags; + uint16_t wt_chan_freq; + uint16_t wt_chan_flags; +}; + +#define IPW_TX_RADIOTAP_PRESENT \ + ((1 << IEEE80211_RADIOTAP_FLAGS) | \ + (1 << IEEE80211_RADIOTAP_CHANNEL)) + +struct ipw_softc { + struct arpcom sc_arp; + struct ieee80211com sc_ic; + int (*sc_newstate)(struct ieee80211com *, + enum ieee80211_state, int); + device_t sc_dev; + + struct mtx sc_mtx; + + struct ipw_firmware fw; + uint32_t flags; +#define IPW_FLAG_FW_CACHED (1 << 0) +#define IPW_FLAG_FW_INITED (1 << 1) +#define IPW_FLAG_HAS_RADIO_SWITCH (1 << 2) + + int irq_rid; + int mem_rid; + struct resource *irq; + struct resource *mem; + bus_space_tag_t sc_st; + bus_space_handle_t sc_sh; + void *sc_ih; + + int sc_tx_timer; + + bus_dma_tag_t tbd_dmat; + bus_dma_tag_t rbd_dmat; + bus_dma_tag_t status_dmat; + bus_dma_tag_t cmd_dmat; + bus_dma_tag_t hdr_dmat; + bus_dma_tag_t txbuf_dmat; + bus_dma_tag_t rxbuf_dmat; + + bus_dmamap_t tbd_map; + bus_dmamap_t rbd_map; + bus_dmamap_t status_map; + bus_dmamap_t cmd_map; + + bus_addr_t tbd_phys; + bus_addr_t rbd_phys; + bus_addr_t status_phys; + + struct ipw_bd *tbd_list; + struct ipw_bd *rbd_list; + struct ipw_status *status_list; + + struct ipw_cmd cmd; + struct ipw_soft_bd stbd_list[IPW_NTBD]; + struct ipw_soft_buf tx_sbuf_list[IPW_NDATA]; + struct ipw_soft_hdr shdr_list[IPW_NDATA]; + struct ipw_soft_bd srbd_list[IPW_NRBD]; + struct ipw_soft_buf rx_sbuf_list[IPW_NRBD]; + + SLIST_HEAD(, ipw_soft_hdr) free_shdr; + SLIST_HEAD(, ipw_soft_buf) free_sbuf; + + uint32_t table1_base; + uint32_t table2_base; + + uint32_t txcur; + uint32_t txold; + uint32_t rxcur; + int txfree; + + int dwelltime; + + struct bpf_if *sc_drvbpf; + + union { + struct ipw_rx_radiotap_header th; + uint8_t pad[64]; + } sc_rxtapu; +#define sc_rxtap sc_rxtapu.th + int sc_rxtap_len; + + union { + struct ipw_tx_radiotap_header th; + uint8_t pad[64]; + } sc_txtapu; +#define sc_txtap sc_txtapu.th + int sc_txtap_len; +}; + +#define SIOCSLOADFW _IOW('i', 137, struct ifreq) +#define SIOCSKILLFW _IOW('i', 138, struct ifreq) + +#define IPW_LOCK(sc) mtx_lock(&(sc)->sc_mtx) +#define IPW_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) diff --git a/sys/dev/iwi/if_iwi.c b/sys/dev/iwi/if_iwi.c new file mode 100644 index 0000000..92d6a66 --- /dev/null +++ b/sys/dev/iwi/if_iwi.c @@ -0,0 +1,2223 @@ +/* $FreeBSD$ */ + +/*- + * Copyright (c) 2004, 2005 + * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice unmodified, this list of conditions, and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +/*- + * Intel(R) PRO/Wireless 2200BG/2225BG/2915ABG driver + * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm + */ + +#include <sys/param.h> +#include <sys/sysctl.h> +#include <sys/sockio.h> +#include <sys/mbuf.h> +#include <sys/kernel.h> +#include <sys/socket.h> +#include <sys/systm.h> +#include <sys/malloc.h> +#include <sys/module.h> +#include <sys/bus.h> +#include <sys/endian.h> + +#include <machine/bus.h> +#include <machine/resource.h> +#include <machine/clock.h> +#include <sys/rman.h> + +#include <dev/pci/pcireg.h> +#include <dev/pci/pcivar.h> + +#include <net/bpf.h> +#include <net/if.h> +#include <net/if_arp.h> +#include <net/ethernet.h> +#include <net/if_dl.h> +#include <net/if_media.h> +#include <net/if_types.h> + +#include <net80211/ieee80211_var.h> +#include <net80211/ieee80211_radiotap.h> + +#include <netinet/in.h> +#include <netinet/in_systm.h> +#include <netinet/in_var.h> +#include <netinet/ip.h> +#include <netinet/if_ether.h> + +#include <dev/iwi/if_iwireg.h> +#include <dev/iwi/if_iwivar.h> + +#ifdef IWI_DEBUG +#define DPRINTF(x) do { if (iwi_debug > 0) printf x; } while (0) +#define DPRINTFN(n, x) do { if (iwi_debug >= (n)) printf x; } while (0) +int iwi_debug = 0; +SYSCTL_INT(_debug, OID_AUTO, iwi, CTLFLAG_RW, &iwi_debug, 0, "iwi debug level"); +#else +#define DPRINTF(x) +#define DPRINTFN(n, x) +#endif + +MODULE_DEPEND(iwi, pci, 1, 1, 1); +MODULE_DEPEND(iwi, wlan, 1, 1, 1); + +struct iwi_ident { + uint16_t vendor; + uint16_t device; + const char *name; +}; + +static const struct iwi_ident iwi_ident_table[] = { + { 0x8086, 0x4220, "Intel(R) PRO/Wireless 2200BG" }, + { 0x8086, 0x4221, "Intel(R) PRO/Wireless 2225BG" }, + { 0x8086, 0x4223, "Intel(R) PRO/Wireless 2915ABG" }, + { 0x8086, 0x4224, "Intel(R) PRO/Wireless 2915ABG" }, + + { 0, 0, NULL } +}; + +static void iwi_dma_map_addr(void *, bus_dma_segment_t *, int, int); +static int iwi_alloc_cmd_ring(struct iwi_softc *, struct iwi_cmd_ring *, + int); +static void iwi_reset_cmd_ring(struct iwi_softc *, struct iwi_cmd_ring *); +static void iwi_free_cmd_ring(struct iwi_softc *, struct iwi_cmd_ring *); +static int iwi_alloc_tx_ring(struct iwi_softc *, struct iwi_tx_ring *, + int); +static void iwi_reset_tx_ring(struct iwi_softc *, struct iwi_tx_ring *); +static void iwi_free_tx_ring(struct iwi_softc *, struct iwi_tx_ring *); +static int iwi_alloc_rx_ring(struct iwi_softc *, struct iwi_rx_ring *, + int); +static void iwi_reset_rx_ring(struct iwi_softc *, struct iwi_rx_ring *); +static void iwi_free_rx_ring(struct iwi_softc *, struct iwi_rx_ring *); +static int iwi_media_change(struct ifnet *); +static void iwi_media_status(struct ifnet *, struct ifmediareq *); +static int iwi_newstate(struct ieee80211com *, enum ieee80211_state, int); +static uint16_t iwi_read_prom_word(struct iwi_softc *, uint8_t); +static void iwi_fix_channel(struct ieee80211com *, struct mbuf *); +static void iwi_frame_intr(struct iwi_softc *, struct iwi_rx_data *, int, + struct iwi_frame *); +static void iwi_notification_intr(struct iwi_softc *, struct iwi_notif *); +static void iwi_rx_intr(struct iwi_softc *); +static void iwi_tx_intr(struct iwi_softc *); +static void iwi_intr(void *); +static int iwi_cmd(struct iwi_softc *, uint8_t, void *, uint8_t, int); +static int iwi_tx_start(struct ifnet *, struct mbuf *, + struct ieee80211_node *); +static void iwi_start(struct ifnet *); +static void iwi_watchdog(struct ifnet *); +static int iwi_ioctl(struct ifnet *, u_long, caddr_t); +static void iwi_stop_master(struct iwi_softc *); +static int iwi_reset(struct iwi_softc *); +static int iwi_load_ucode(struct iwi_softc *, void *, int); +static int iwi_load_firmware(struct iwi_softc *, void *, int); +static int iwi_cache_firmware(struct iwi_softc *, void *); +static void iwi_free_firmware(struct iwi_softc *); +static int iwi_config(struct iwi_softc *); +static int iwi_scan(struct iwi_softc *); +static int iwi_auth_and_assoc(struct iwi_softc *); +static void iwi_init(void *); +static void iwi_stop(void *); +#ifdef IWI_DEBUG +static int iwi_sysctl_stats(SYSCTL_HANDLER_ARGS); +#endif +static int iwi_sysctl_radio(SYSCTL_HANDLER_ARGS); + +static int iwi_probe(device_t); +static int iwi_attach(device_t); +static int iwi_detach(device_t); +static int iwi_shutdown(device_t); +static int iwi_suspend(device_t); +static int iwi_resume(device_t); + +static device_method_t iwi_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, iwi_probe), + DEVMETHOD(device_attach, iwi_attach), + DEVMETHOD(device_detach, iwi_detach), + DEVMETHOD(device_shutdown, iwi_shutdown), + DEVMETHOD(device_suspend, iwi_suspend), + DEVMETHOD(device_resume, iwi_resume), + + { 0, 0 } +}; + +static driver_t iwi_driver = { + "iwi", + iwi_methods, + sizeof (struct iwi_softc) +}; + +static devclass_t iwi_devclass; + +DRIVER_MODULE(iwi, pci, iwi_driver, iwi_devclass, 0, 0); + +/* + * Supported rates for 802.11a/b/g modes (in 500Kbps unit). + */ +static const struct ieee80211_rateset iwi_rateset_11a = + { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; + +static const struct ieee80211_rateset iwi_rateset_11b = + { 4, { 2, 4, 11, 22 } }; + +static const struct ieee80211_rateset iwi_rateset_11g = + { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; + +static __inline uint8_t +MEM_READ_1(struct iwi_softc *sc, uint32_t addr) +{ + CSR_WRITE_4(sc, IWI_CSR_INDIRECT_ADDR, addr); + return CSR_READ_1(sc, IWI_CSR_INDIRECT_DATA); +} + +static __inline uint32_t +MEM_READ_4(struct iwi_softc *sc, uint32_t addr) +{ + CSR_WRITE_4(sc, IWI_CSR_INDIRECT_ADDR, addr); + return CSR_READ_4(sc, IWI_CSR_INDIRECT_DATA); +} + +static int +iwi_probe(device_t dev) +{ + const struct iwi_ident *ident; + + for (ident = iwi_ident_table; ident->name != NULL; ident++) { + if (pci_get_vendor(dev) == ident->vendor && + pci_get_device(dev) == ident->device) { + device_set_desc(dev, ident->name); + return 0; + } + } + return ENXIO; +} + +/* Base Address Register */ +#define IWI_PCI_BAR0 0x10 + +static int +iwi_attach(device_t dev) +{ + struct iwi_softc *sc = device_get_softc(dev); + struct ifnet *ifp = &sc->sc_arp.ac_if; + struct ieee80211com *ic = &sc->sc_ic; + uint16_t val; + int error, i; + + sc->sc_dev = dev; + + mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, + MTX_DEF | MTX_RECURSE); + + if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { + device_printf(dev, "chip is in D%d power mode " + "-- setting to D0\n", pci_get_powerstate(dev)); + pci_set_powerstate(dev, PCI_POWERSTATE_D0); + } + + /* enable bus-mastering */ + pci_enable_busmaster(dev); + + sc->mem_rid = IWI_PCI_BAR0; + sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, + RF_ACTIVE); + if (sc->mem == NULL) { + device_printf(dev, "could not allocate memory resource\n"); + goto fail; + } + + sc->sc_st = rman_get_bustag(sc->mem); + sc->sc_sh = rman_get_bushandle(sc->mem); + + sc->irq_rid = 0; + sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, + RF_ACTIVE | RF_SHAREABLE); + if (sc->irq == NULL) { + device_printf(dev, "could not allocate interrupt resource\n"); + goto fail; + } + + if (iwi_reset(sc) != 0) { + device_printf(dev, "could not reset adapter\n"); + goto fail; + } + + /* + * Allocate rings. + */ + if (iwi_alloc_cmd_ring(sc, &sc->cmdq, IWI_CMD_RING_COUNT) != 0) { + device_printf(dev, "could not allocate Cmd ring\n"); + goto fail; + } + + if (iwi_alloc_tx_ring(sc, &sc->txq, IWI_TX_RING_COUNT) != 0) { + device_printf(dev, "could not allocate Tx ring\n"); + goto fail; + } + + if (iwi_alloc_rx_ring(sc, &sc->rxq, IWI_RX_RING_COUNT) != 0) { + device_printf(dev, "could not allocate Rx ring\n"); + goto fail; + } + + ifp->if_softc = sc; + if_initname(ifp, device_get_name(dev), device_get_unit(dev)); + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; + ifp->if_init = iwi_init; + ifp->if_ioctl = iwi_ioctl; + ifp->if_start = iwi_start; + ifp->if_watchdog = iwi_watchdog; + IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); + ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; + IFQ_SET_READY(&ifp->if_snd); + + ic->ic_ifp = ifp; + ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ + ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ + ic->ic_state = IEEE80211_S_INIT; + + /* set device capabilities */ + ic->ic_caps = IEEE80211_C_WEP | IEEE80211_C_PMGT | IEEE80211_C_TXPMGT | + IEEE80211_C_SHPREAMBLE; + + /* read MAC address from EEPROM */ + val = iwi_read_prom_word(sc, IWI_EEPROM_MAC + 0); + ic->ic_myaddr[0] = val >> 8; + ic->ic_myaddr[1] = val & 0xff; + val = iwi_read_prom_word(sc, IWI_EEPROM_MAC + 1); + ic->ic_myaddr[2] = val >> 8; + ic->ic_myaddr[3] = val & 0xff; + val = iwi_read_prom_word(sc, IWI_EEPROM_MAC + 2); + ic->ic_myaddr[4] = val >> 8; + ic->ic_myaddr[5] = val & 0xff; + + if (pci_get_device(dev) >= 0x4223) { + /* set supported .11a rates (2915ABG only) */ + ic->ic_sup_rates[IEEE80211_MODE_11A] = iwi_rateset_11a; + + /* set supported .11a channels */ + for (i = 36; i <= 64; i += 4) { + ic->ic_channels[i].ic_freq = + ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); + ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; + } + for (i = 149; i <= 165; i += 4) { + ic->ic_channels[i].ic_freq = + ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); + ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; + } + } + + /* set supported .11b and .11g rates */ + ic->ic_sup_rates[IEEE80211_MODE_11B] = iwi_rateset_11b; + ic->ic_sup_rates[IEEE80211_MODE_11G] = iwi_rateset_11g; + + /* set supported .11b and .11g channels (1 through 14) */ + for (i = 1; i <= 14; i++) { + ic->ic_channels[i].ic_freq = + ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); + ic->ic_channels[i].ic_flags = + IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | + IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; + } + + ieee80211_ifattach(ic); + /* override state transition machine */ + sc->sc_newstate = ic->ic_newstate; + ic->ic_newstate = iwi_newstate; + ieee80211_media_init(ic, iwi_media_change, iwi_media_status); + + bpfattach2(ifp, DLT_IEEE802_11_RADIO, + sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); + + sc->sc_rxtap_len = sizeof sc->sc_rxtapu; + sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); + sc->sc_rxtap.wr_ihdr.it_present = htole32(IWI_RX_RADIOTAP_PRESENT); + + sc->sc_txtap_len = sizeof sc->sc_txtapu; + sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); + sc->sc_txtap.wt_ihdr.it_present = htole32(IWI_TX_RADIOTAP_PRESENT); + + /* + * Add a few sysctl knobs. + */ + sc->dwelltime = 100; + sc->bluetooth = 1; + + SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "radio", + CTLTYPE_INT | CTLFLAG_RD, sc, 0, iwi_sysctl_radio, "I", + "radio transmitter switch state (0=off, 1=on)"); + +#ifdef IWI_DEBUG + SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "stats", + CTLTYPE_OPAQUE | CTLFLAG_RD, sc, 0, iwi_sysctl_stats, "S", + "statistics"); +#endif + + SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "dwell", + CTLFLAG_RW, &sc->dwelltime, 0, + "channel dwell time (ms) for AP/station scanning"); + + SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "bluetooth", + CTLFLAG_RW, &sc->bluetooth, 0, "bluetooth coexistence"); + + /* + * Hook our interrupt after all initialization is complete. + */ + error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, + iwi_intr, sc, &sc->sc_ih); + if (error != 0) { + device_printf(dev, "could not set up interrupt\n"); + goto fail; + } + + if (bootverbose) + ieee80211_announce(ic); + + return 0; + +fail: iwi_detach(dev); + return ENXIO; +} + +static int +iwi_detach(device_t dev) +{ + struct iwi_softc *sc = device_get_softc(dev); + struct ieee80211com *ic = &sc->sc_ic; + struct ifnet *ifp = ic->ic_ifp; + + iwi_stop(sc); + + iwi_free_firmware(sc); + + bpfdetach(ifp); + ieee80211_ifdetach(ic); + + iwi_free_cmd_ring(sc, &sc->cmdq); + iwi_free_tx_ring(sc, &sc->txq); + iwi_free_rx_ring(sc, &sc->rxq); + + if (sc->irq != NULL) { + bus_teardown_intr(dev, sc->irq, sc->sc_ih); + bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq); + } + + if (sc->mem != NULL) + bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem); + + mtx_destroy(&sc->sc_mtx); + + return 0; +} + +static void +iwi_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) +{ + if (error != 0) + return; + + KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); + + *(bus_addr_t *)arg = segs[0].ds_addr; +} + +static int +iwi_alloc_cmd_ring(struct iwi_softc *sc, struct iwi_cmd_ring *ring, int count) +{ + int error; + + ring->count = count; + ring->queued = 0; + ring->cur = ring->next = 0; + + error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, + BUS_SPACE_MAXADDR, NULL, NULL, count * IWI_CMD_DESC_SIZE, 1, + count * IWI_CMD_DESC_SIZE, 0, NULL, NULL, &ring->desc_dmat); + if (error != 0) { + device_printf(sc->sc_dev, "could not create desc DMA tag\n"); + goto fail; + } + + error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, + BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); + if (error != 0) { + device_printf(sc->sc_dev, "could not allocate DMA memory\n"); + goto fail; + } + + error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, + count * IWI_CMD_DESC_SIZE, iwi_dma_map_addr, &ring->physaddr, 0); + if (error != 0) { + device_printf(sc->sc_dev, "could not load desc DMA map\n"); + goto fail; + } + + return 0; + +fail: iwi_free_cmd_ring(sc, ring); + return error; +} + +static void +iwi_reset_cmd_ring(struct iwi_softc *sc, struct iwi_cmd_ring *ring) +{ + ring->queued = 0; + ring->cur = ring->next = 0; +} + +static void +iwi_free_cmd_ring(struct iwi_softc *sc, struct iwi_cmd_ring *ring) +{ + if (ring->desc != NULL) { + bus_dmamap_sync(ring->desc_dmat, ring->desc_map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(ring->desc_dmat, ring->desc_map); + bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); + } + + if (ring->desc_dmat != NULL) + bus_dma_tag_destroy(ring->desc_dmat); +} + +static int +iwi_alloc_tx_ring(struct iwi_softc *sc, struct iwi_tx_ring *ring, int count) +{ + int i, error; + + ring->count = count; + ring->queued = 0; + ring->cur = ring->next = 0; + + error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, + BUS_SPACE_MAXADDR, NULL, NULL, count * IWI_TX_DESC_SIZE, 1, + count * IWI_TX_DESC_SIZE, 0, NULL, NULL, &ring->desc_dmat); + if (error != 0) { + device_printf(sc->sc_dev, "could not create desc DMA tag\n"); + goto fail; + } + + error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, + BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); + if (error != 0) { + device_printf(sc->sc_dev, "could not allocate DMA memory\n"); + goto fail; + } + + error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, + count * IWI_TX_DESC_SIZE, iwi_dma_map_addr, &ring->physaddr, 0); + if (error != 0) { + device_printf(sc->sc_dev, "could not load desc DMA map\n"); + goto fail; + } + + ring->data = malloc(count * sizeof (struct iwi_tx_data), M_DEVBUF, + M_NOWAIT | M_ZERO); + if (ring->data == NULL) { + device_printf(sc->sc_dev, "could not allocate soft data\n"); + error = ENOMEM; + goto fail; + } + + error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, + BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, NULL, + NULL, &ring->data_dmat); + if (error != 0) { + device_printf(sc->sc_dev, "could not create data DMA tag\n"); + goto fail; + } + + for (i = 0; i < count; i++) { + error = bus_dmamap_create(ring->data_dmat, 0, + &ring->data[i].map); + if (error != 0) { + device_printf(sc->sc_dev, "could not create DMA map\n"); + goto fail; + } + } + + return 0; + +fail: iwi_free_tx_ring(sc, ring); + return error; +} + +static void +iwi_reset_tx_ring(struct iwi_softc *sc, struct iwi_tx_ring *ring) +{ + struct iwi_tx_data *data; + int i; + + for (i = 0; i < ring->count; i++) { + data = &ring->data[i]; + + if (data->m != NULL) { + bus_dmamap_sync(ring->data_dmat, data->map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(ring->data_dmat, data->map); + m_freem(data->m); + data->m = NULL; + } + + if (data->ni != NULL) { + ieee80211_free_node(data->ni); + data->ni = NULL; + } + } + + ring->queued = 0; + ring->cur = ring->next = 0; +} + +static void +iwi_free_tx_ring(struct iwi_softc *sc, struct iwi_tx_ring *ring) +{ + struct iwi_tx_data *data; + int i; + + if (ring->desc != NULL) { + bus_dmamap_sync(ring->desc_dmat, ring->desc_map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(ring->desc_dmat, ring->desc_map); + bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); + } + + if (ring->desc_dmat != NULL) + bus_dma_tag_destroy(ring->desc_dmat); + + if (ring->data != NULL) { + for (i = 0; i < ring->count; i++) { + data = &ring->data[i]; + + if (data->m != NULL) { + bus_dmamap_sync(ring->data_dmat, data->map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(ring->data_dmat, data->map); + m_freem(data->m); + } + + if (data->ni != NULL) + ieee80211_free_node(data->ni); + + if (data->map != NULL) + bus_dmamap_destroy(ring->data_dmat, data->map); + } + + free(ring->data, M_DEVBUF); + } + + if (ring->data_dmat != NULL) + bus_dma_tag_destroy(ring->data_dmat); +} + +static int +iwi_alloc_rx_ring(struct iwi_softc *sc, struct iwi_rx_ring *ring, int count) +{ + struct iwi_rx_data *data; + int i, error; + + ring->count = count; + ring->cur = 0; + + ring->data = malloc(count * sizeof (struct iwi_rx_data), M_DEVBUF, + M_NOWAIT | M_ZERO); + if (ring->data == NULL) { + device_printf(sc->sc_dev, "could not allocate soft data\n"); + error = ENOMEM; + goto fail; + } + + error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, + BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, NULL, + NULL, &ring->data_dmat); + if (error != 0) { + device_printf(sc->sc_dev, "could not create data DMA tag\n"); + goto fail; + } + + for (i = 0; i < count; i++) { + data = &ring->data[i]; + + error = bus_dmamap_create(ring->data_dmat, 0, &data->map); + if (error != 0) { + device_printf(sc->sc_dev, "could not create DMA map\n"); + goto fail; + } + + data->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + if (data->m == NULL) { + device_printf(sc->sc_dev, + "could not allocate rx mbuf\n"); + error = ENOMEM; + goto fail; + } + + error = bus_dmamap_load(ring->data_dmat, data->map, + mtod(data->m, void *), MCLBYTES, iwi_dma_map_addr, + &data->physaddr, 0); + if (error != 0) { + device_printf(sc->sc_dev, + "could not load rx buf DMA map"); + goto fail; + } + + data->reg = IWI_CSR_RX_BASE + i * 4; + } + + return 0; + +fail: iwi_free_rx_ring(sc, ring); + return error; +} + +static void +iwi_reset_rx_ring(struct iwi_softc *sc, struct iwi_rx_ring *ring) +{ + ring->cur = 0; +} + +static void +iwi_free_rx_ring(struct iwi_softc *sc, struct iwi_rx_ring *ring) +{ + struct iwi_rx_data *data; + int i; + + if (ring->data != NULL) { + for (i = 0; i < ring->count; i++) { + data = &ring->data[i]; + + if (data->m != NULL) { + bus_dmamap_sync(ring->data_dmat, data->map, + BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(ring->data_dmat, data->map); + m_freem(data->m); + } + + if (data->map != NULL) + bus_dmamap_destroy(ring->data_dmat, data->map); + } + + free(ring->data, M_DEVBUF); + } + + if (ring->data_dmat != NULL) + bus_dma_tag_destroy(ring->data_dmat); +} + +static int +iwi_shutdown(device_t dev) +{ + struct iwi_softc *sc = device_get_softc(dev); + + iwi_stop(sc); + + return 0; +} + +static int +iwi_suspend(device_t dev) +{ + struct iwi_softc *sc = device_get_softc(dev); + + iwi_stop(sc); + + return 0; +} + +static int +iwi_resume(device_t dev) +{ + struct iwi_softc *sc = device_get_softc(dev); + struct ifnet *ifp = sc->sc_ic.ic_ifp; + + IWI_LOCK(sc); + + if (ifp->if_flags & IFF_UP) { + ifp->if_init(ifp->if_softc); + if (ifp->if_flags & IFF_RUNNING) + ifp->if_start(ifp); + } + + IWI_UNLOCK(sc); + + return 0; +} + +static int +iwi_media_change(struct ifnet *ifp) +{ + struct iwi_softc *sc = ifp->if_softc; + int error; + + IWI_LOCK(sc); + + error = ieee80211_media_change(ifp); + if (error != ENETRESET) { + IWI_UNLOCK(sc); + return error; + } + + if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) + iwi_init(sc); + + IWI_UNLOCK(sc); + + return 0; +} + +/* + * The firmware automaticly adapt the transmit speed. We report the current + * transmit speed here. + */ +static void +iwi_media_status(struct ifnet *ifp, struct ifmediareq *imr) +{ + struct iwi_softc *sc = ifp->if_softc; + struct ieee80211com *ic = &sc->sc_ic; +#define N(a) (sizeof (a) / sizeof (a[0])) + static const struct { + uint32_t val; + int rate; + } rates[] = { + { IWI_RATE_DS1, 2 }, + { IWI_RATE_DS2, 4 }, + { IWI_RATE_DS5, 11 }, + { IWI_RATE_DS11, 22 }, + { IWI_RATE_OFDM6, 12 }, + { IWI_RATE_OFDM9, 18 }, + { IWI_RATE_OFDM12, 24 }, + { IWI_RATE_OFDM18, 36 }, + { IWI_RATE_OFDM24, 48 }, + { IWI_RATE_OFDM36, 72 }, + { IWI_RATE_OFDM48, 96 }, + { IWI_RATE_OFDM54, 108 }, + }; + uint32_t val; + int rate, i; + + imr->ifm_status = IFM_AVALID; + imr->ifm_active = IFM_IEEE80211; + if (ic->ic_state == IEEE80211_S_RUN) + imr->ifm_status |= IFM_ACTIVE; + + /* read current transmission rate from adapter */ + val = CSR_READ_4(sc, IWI_CSR_CURRENT_TX_RATE); + + /* convert rate to 802.11 rate */ + for (i = 0; i < N(rates) && rates[i].val != val; i++); + rate = (i < N(rates)) ? rates[i].rate : 0; + + imr->ifm_active |= ieee80211_rate2media(ic, rate, ic->ic_curmode); + switch (ic->ic_opmode) { + case IEEE80211_M_STA: + break; + + case IEEE80211_M_IBSS: + imr->ifm_active |= IFM_IEEE80211_ADHOC; + break; + + case IEEE80211_M_MONITOR: + imr->ifm_active |= IFM_IEEE80211_MONITOR; + break; + + case IEEE80211_M_AHDEMO: + case IEEE80211_M_HOSTAP: + /* should not get there */ + break; + } +#undef N +} + +static int +iwi_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) +{ + struct ifnet *ifp = ic->ic_ifp; + struct iwi_softc *sc = ifp->if_softc; + + switch (nstate) { + case IEEE80211_S_SCAN: + iwi_scan(sc); + break; + + case IEEE80211_S_AUTH: + iwi_auth_and_assoc(sc); + break; + + case IEEE80211_S_RUN: + if (ic->ic_opmode == IEEE80211_M_IBSS) + ieee80211_new_state(ic, IEEE80211_S_AUTH, -1); + break; + + case IEEE80211_S_ASSOC: + case IEEE80211_S_INIT: + break; + } + + ic->ic_state = nstate; + return 0; +} + +/* + * Read 16 bits at address 'addr' from the serial EEPROM. + */ +static uint16_t +iwi_read_prom_word(struct iwi_softc *sc, uint8_t addr) +{ + uint32_t tmp; + uint16_t val; + int n; + + /* clock C once before the first command */ + IWI_EEPROM_CTL(sc, 0); + IWI_EEPROM_CTL(sc, IWI_EEPROM_S); + IWI_EEPROM_CTL(sc, IWI_EEPROM_S | IWI_EEPROM_C); + IWI_EEPROM_CTL(sc, IWI_EEPROM_S); + + /* write start bit (1) */ + IWI_EEPROM_CTL(sc, IWI_EEPROM_S | IWI_EEPROM_D); + IWI_EEPROM_CTL(sc, IWI_EEPROM_S | IWI_EEPROM_D | IWI_EEPROM_C); + + /* write READ opcode (10) */ + IWI_EEPROM_CTL(sc, IWI_EEPROM_S | IWI_EEPROM_D); + IWI_EEPROM_CTL(sc, IWI_EEPROM_S | IWI_EEPROM_D | IWI_EEPROM_C); + IWI_EEPROM_CTL(sc, IWI_EEPROM_S); + IWI_EEPROM_CTL(sc, IWI_EEPROM_S | IWI_EEPROM_C); + + /* write address A7-A0 */ + for (n = 7; n >= 0; n--) { + IWI_EEPROM_CTL(sc, IWI_EEPROM_S | + (((addr >> n) & 1) << IWI_EEPROM_SHIFT_D)); + IWI_EEPROM_CTL(sc, IWI_EEPROM_S | + (((addr >> n) & 1) << IWI_EEPROM_SHIFT_D) | IWI_EEPROM_C); + } + + IWI_EEPROM_CTL(sc, IWI_EEPROM_S); + + /* read data Q15-Q0 */ + val = 0; + for (n = 15; n >= 0; n--) { + IWI_EEPROM_CTL(sc, IWI_EEPROM_S | IWI_EEPROM_C); + IWI_EEPROM_CTL(sc, IWI_EEPROM_S); + tmp = MEM_READ_4(sc, IWI_MEM_EEPROM_CTL); + val |= ((tmp & IWI_EEPROM_Q) >> IWI_EEPROM_SHIFT_Q) << n; + } + + IWI_EEPROM_CTL(sc, 0); + + /* clear Chip Select and clock C */ + IWI_EEPROM_CTL(sc, IWI_EEPROM_S); + IWI_EEPROM_CTL(sc, 0); + IWI_EEPROM_CTL(sc, IWI_EEPROM_C); + + return be16toh(val); +} + +/* + * XXX: Hack to set the current channel to the value advertised in beacons or + * probe responses. Only used during AP detection. + */ +static void +iwi_fix_channel(struct ieee80211com *ic, struct mbuf *m) +{ + struct ieee80211_frame *wh; + uint8_t subtype; + uint8_t *frm, *efrm; + + wh = mtod(m, struct ieee80211_frame *); + + if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT) + return; + + subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; + + if (subtype != IEEE80211_FC0_SUBTYPE_BEACON && + subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP) + return; + + frm = (uint8_t *)(wh + 1); + efrm = mtod(m, uint8_t *) + m->m_len; + + frm += 12; /* skip tstamp, bintval and capinfo fields */ + while (frm < efrm) { + if (*frm == IEEE80211_ELEMID_DSPARMS) +#if IEEE80211_CHAN_MAX < 255 + if (frm[2] <= IEEE80211_CHAN_MAX) +#endif + ic->ic_bss->ni_chan = &ic->ic_channels[frm[2]]; + + frm += frm[1] + 2; + } +} + +static void +iwi_frame_intr(struct iwi_softc *sc, struct iwi_rx_data *data, int i, + struct iwi_frame *frame) +{ + struct ieee80211com *ic = &sc->sc_ic; + struct ifnet *ifp = ic->ic_ifp; + struct mbuf *m; + struct ieee80211_frame *wh; + struct ieee80211_node *ni; + int error; + + DPRINTFN(5, ("received frame len=%u chan=%u rssi=%u\n", + le16toh(frame->len), frame->chan, frame->rssi_dbm)); + + bus_dmamap_unload(sc->rxq.data_dmat, data->map); + + /* finalize mbuf */ + m = data->m; + m->m_pkthdr.rcvif = ifp; + m->m_pkthdr.len = m->m_len = sizeof (struct iwi_hdr) + + sizeof (struct iwi_frame) + le16toh(frame->len); + + m_adj(m, sizeof (struct iwi_hdr) + sizeof (struct iwi_frame)); + + if (ic->ic_state == IEEE80211_S_SCAN) + iwi_fix_channel(ic, m); + + if (sc->sc_drvbpf != NULL) { + struct iwi_rx_radiotap_header *tap = &sc->sc_rxtap; + + tap->wr_flags = 0; + tap->wr_rate = frame->rate; + tap->wr_chan_freq = + htole16(ic->ic_channels[frame->chan].ic_freq); + tap->wr_chan_flags = + htole16(ic->ic_channels[frame->chan].ic_flags); + tap->wr_antsignal = frame->signal; + tap->wr_antenna = frame->antenna; + + bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); + } + + wh = mtod(m, struct ieee80211_frame *); + ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); + + /* send the frame to the 802.11 layer */ + ieee80211_input(ic, m, ni, IWI_RSSIDBM2RAW(frame->rssi_dbm), 0); + + /* node is no longer needed */ + ieee80211_free_node(ni); + + data->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + if (data->m == NULL) { + device_printf(sc->sc_dev, "could not allocate rx mbuf\n"); + return; + } + + error = bus_dmamap_load(sc->rxq.data_dmat, data->map, + mtod(data->m, void *), MCLBYTES, iwi_dma_map_addr, &data->physaddr, + 0); + if (error != 0) { + device_printf(sc->sc_dev, "could not load rx buf DMA map\n"); + m_freem(data->m); + data->m = NULL; + return; + } + + CSR_WRITE_4(sc, data->reg, data->physaddr); +} + +static void +iwi_notification_intr(struct iwi_softc *sc, struct iwi_notif *notif) +{ + struct ieee80211com *ic = &sc->sc_ic; + struct iwi_notif_scan_channel *chan; + struct iwi_notif_scan_complete *scan; + struct iwi_notif_authentication *auth; + struct iwi_notif_association *assoc; + + switch (notif->type) { + case IWI_NOTIF_TYPE_SCAN_CHANNEL: + chan = (struct iwi_notif_scan_channel *)(notif + 1); + + DPRINTFN(2, ("Scanning channel (%u)\n", chan->nchan)); + break; + + case IWI_NOTIF_TYPE_SCAN_COMPLETE: + scan = (struct iwi_notif_scan_complete *)(notif + 1); + + DPRINTFN(2, ("Scan completed (%u, %u)\n", scan->nchan, + scan->status)); + + ieee80211_end_scan(ic); + break; + + case IWI_NOTIF_TYPE_AUTHENTICATION: + auth = (struct iwi_notif_authentication *)(notif + 1); + + DPRINTFN(2, ("Authentication (%u)\n", auth->state)); + + switch (auth->state) { + case IWI_AUTHENTICATED: + ieee80211_node_authorize(ic, ic->ic_bss); + ieee80211_new_state(ic, IEEE80211_S_ASSOC, -1); + break; + + case IWI_DEAUTHENTICATED: + break; + + default: + device_printf(sc->sc_dev, + "unknown authentication state %u\n", auth->state); + } + break; + + case IWI_NOTIF_TYPE_ASSOCIATION: + assoc = (struct iwi_notif_association *)(notif + 1); + + DPRINTFN(2, ("Association (%u, %u)\n", assoc->state, + assoc->status)); + + switch (assoc->state) { + case IWI_AUTHENTICATED: + /* re-association, do nothing */ + break; + + case IWI_ASSOCIATED: + ieee80211_new_state(ic, IEEE80211_S_RUN, -1); + break; + + case IWI_DEASSOCIATED: + ieee80211_begin_scan(ic, 1); + break; + + default: + device_printf(sc->sc_dev, + "unknown association state %u\n", assoc->state); + } + break; + + case IWI_NOTIF_TYPE_CALIBRATION: + case IWI_NOTIF_TYPE_BEACON: + case IWI_NOTIF_TYPE_NOISE: + DPRINTFN(5, ("Notification (%u)\n", notif->type)); + break; + + default: + device_printf(sc->sc_dev, "unknown notification type %u\n", + notif->type); + } +} + +static void +iwi_rx_intr(struct iwi_softc *sc) +{ + struct iwi_rx_data *data; + struct iwi_hdr *hdr; + uint32_t hw; + + hw = CSR_READ_4(sc, IWI_CSR_RX_RIDX); + + for (; sc->rxq.cur != hw;) { + data = &sc->rxq.data[sc->rxq.cur]; + + bus_dmamap_sync(sc->rxq.data_dmat, data->map, + BUS_DMASYNC_POSTREAD); + + hdr = mtod(data->m, struct iwi_hdr *); + + switch (hdr->type) { + case IWI_HDR_TYPE_FRAME: + iwi_frame_intr(sc, data, sc->rxq.cur, + (struct iwi_frame *)(hdr + 1)); + break; + + case IWI_HDR_TYPE_NOTIF: + iwi_notification_intr(sc, + (struct iwi_notif *)(hdr + 1)); + break; + + default: + device_printf(sc->sc_dev, "unknown hdr type %u\n", + hdr->type); + } + + DPRINTFN(15, ("rx done idx=%u\n", sc->rxq.cur)); + + sc->rxq.cur = (sc->rxq.cur + 1) % IWI_RX_RING_COUNT; + } + + /* tell the firmware what we have processed */ + hw = (hw == 0) ? IWI_RX_RING_COUNT - 1 : hw - 1; + CSR_WRITE_4(sc, IWI_CSR_RX_WIDX, hw); +} + +static void +iwi_tx_intr(struct iwi_softc *sc) +{ + struct ieee80211com *ic = &sc->sc_ic; + struct ifnet *ifp = ic->ic_ifp; + struct iwi_tx_data *data; + uint32_t hw; + + hw = CSR_READ_4(sc, IWI_CSR_TX1_RIDX); + + for (; sc->txq.next != hw;) { + data = &sc->txq.data[sc->txq.next]; + + bus_dmamap_sync(sc->txq.data_dmat, data->map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->txq.data_dmat, data->map); + m_freem(data->m); + data->m = NULL; + ieee80211_free_node(data->ni); + data->ni = NULL; + + DPRINTFN(15, ("tx done idx=%u\n", sc->txq.next)); + + ifp->if_opackets++; + + sc->txq.queued--; + sc->txq.next = (sc->txq.next + 1) % IWI_TX_RING_COUNT; + } + + sc->sc_tx_timer = 0; + ifp->if_flags &= ~IFF_OACTIVE; + iwi_start(ifp); +} + +static void +iwi_intr(void *arg) +{ + struct iwi_softc *sc = arg; + uint32_t r; + + IWI_LOCK(sc); + + if ((r = CSR_READ_4(sc, IWI_CSR_INTR)) == 0 || r == 0xffffffff) { + IWI_UNLOCK(sc); + return; + } + + /* disable interrupts */ + CSR_WRITE_4(sc, IWI_CSR_INTR_MASK, 0); + + if (r & (IWI_INTR_FATAL_ERROR | IWI_INTR_PARITY_ERROR)) { + device_printf(sc->sc_dev, "fatal error\n"); + sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; + iwi_stop(sc); + } + + if (r & IWI_INTR_FW_INITED) { + if (!(r & (IWI_INTR_FATAL_ERROR | IWI_INTR_PARITY_ERROR))) + wakeup(sc); + } + + if (r & IWI_INTR_RADIO_OFF) { + DPRINTF(("radio transmitter turned off\n")); + sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP; + iwi_stop(sc); + } + + if (r & IWI_INTR_RX_DONE) + iwi_rx_intr(sc); + + if (r & IWI_INTR_CMD_DONE) + wakeup(sc); + + if (r & IWI_INTR_TX1_DONE) + iwi_tx_intr(sc); + + /* acknowledge interrupts */ + CSR_WRITE_4(sc, IWI_CSR_INTR, r); + + /* re-enable interrupts */ + CSR_WRITE_4(sc, IWI_CSR_INTR_MASK, IWI_INTR_MASK); + + IWI_UNLOCK(sc); +} + +static int +iwi_cmd(struct iwi_softc *sc, uint8_t type, void *data, uint8_t len, int async) +{ + struct iwi_cmd_desc *desc; + + desc = &sc->cmdq.desc[sc->cmdq.cur]; + + desc->hdr.type = IWI_HDR_TYPE_COMMAND; + desc->hdr.flags = IWI_HDR_FLAG_IRQ; + desc->type = type; + desc->len = len; + memcpy(desc->data, data, len); + + bus_dmamap_sync(sc->cmdq.desc_dmat, sc->cmdq.desc_map, + BUS_DMASYNC_PREWRITE); + + DPRINTFN(2, ("sending command idx=%u type=%u len=%u\n", sc->cmdq.cur, + type, len)); + + sc->cmdq.cur = (sc->cmdq.cur + 1) % IWI_CMD_RING_COUNT; + CSR_WRITE_4(sc, IWI_CSR_CMD_WIDX, sc->cmdq.cur); + + return async ? 0 : msleep(sc, &sc->sc_mtx, 0, "iwicmd", hz); +} + +static int +iwi_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni) +{ + struct iwi_softc *sc = ifp->if_softc; + struct ieee80211com *ic = &sc->sc_ic; + struct ieee80211_frame *wh; + struct iwi_tx_data *data; + struct iwi_tx_desc *desc; + struct mbuf *mnew; + bus_dma_segment_t segs[IWI_MAX_NSEG]; + int nsegs, error, i; + + if (sc->sc_drvbpf != NULL) { + struct iwi_tx_radiotap_header *tap = &sc->sc_txtap; + + tap->wt_flags = 0; + tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); + tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); + + bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); + } + + data = &sc->txq.data[sc->txq.cur]; + desc = &sc->txq.desc[sc->txq.cur]; + + wh = mtod(m0, struct ieee80211_frame *); + + /* trim IEEE802.11 header */ + m_adj(m0, sizeof (struct ieee80211_frame)); + + error = bus_dmamap_load_mbuf_sg(sc->txq.data_dmat, data->map, m0, segs, + &nsegs, 0); + if (error != 0 && error != EFBIG) { + device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", + error); + m_freem(m0); + return error; + } + if (error != 0) { + mnew = m_defrag(m0, M_DONTWAIT); + if (mnew == NULL) { + device_printf(sc->sc_dev, + "could not defragment mbuf\n"); + m_freem(m0); + return ENOBUFS; + } + m0 = mnew; + + error = bus_dmamap_load_mbuf_sg(sc->txq.data_dmat, data->map, + m0, segs, &nsegs, 0); + if (error != 0) { + device_printf(sc->sc_dev, + "could not map mbuf (error %d)\n", error); + m_freem(m0); + return error; + } + } + + data->m = m0; + data->ni = ni; + + desc->hdr.type = IWI_HDR_TYPE_DATA; + desc->hdr.flags = IWI_HDR_FLAG_IRQ; + desc->cmd = IWI_DATA_CMD_TX; + desc->len = htole16(m0->m_pkthdr.len); + memcpy(&desc->wh, wh, sizeof (struct ieee80211_frame)); + desc->flags = 0; + + if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) + desc->flags |= IWI_DATA_FLAG_NEED_ACK; + + if (ic->ic_flags & IEEE80211_F_PRIVACY) { + wh->i_fc[1] |= IEEE80211_FC1_WEP; + desc->wep_txkey = ic->ic_crypto.cs_def_txkey; + } else + desc->flags |= IWI_DATA_FLAG_NO_WEP; + + if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) + desc->flags |= IWI_DATA_FLAG_SHPREAMBLE; + + desc->nseg = htole32(nsegs); + for (i = 0; i < nsegs; i++) { + desc->seg_addr[i] = htole32(segs[i].ds_addr); + desc->seg_len[i] = htole32(segs[i].ds_len); + } + + bus_dmamap_sync(sc->txq.data_dmat, data->map, BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(sc->txq.desc_dmat, sc->txq.desc_map, + BUS_DMASYNC_PREWRITE); + + DPRINTFN(5, ("sending data frame idx=%u len=%u nseg=%u\n", sc->txq.cur, + desc->len, desc->nseg)); + + sc->txq.queued++; + sc->txq.cur = (sc->txq.cur + 1) % IWI_TX_RING_COUNT; + CSR_WRITE_4(sc, IWI_CSR_TX1_WIDX, sc->txq.cur); + + return 0; +} + +static void +iwi_start(struct ifnet *ifp) +{ + struct iwi_softc *sc = ifp->if_softc; + struct ieee80211com *ic = &sc->sc_ic; + struct mbuf *m0; + struct ether_header *eh; + struct ieee80211_node *ni; + + IWI_LOCK(sc); + + if (ic->ic_state != IEEE80211_S_RUN) { + IWI_UNLOCK(sc); + return; + } + + for (;;) { + IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); + if (m0 == NULL) + break; + + if (sc->txq.queued >= IWI_TX_RING_COUNT - 4) { + IFQ_DRV_PREPEND(&ifp->if_snd, m0); + ifp->if_flags |= IFF_OACTIVE; + break; + } + + if (m0->m_len < sizeof (struct ether_header) && + (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL) + continue; + + eh = mtod(m0, struct ether_header *); + ni = ieee80211_find_txnode(ic, eh->ether_dhost); + if (ni == NULL) { + m_freem(m0); + continue; + } + BPF_MTAP(ifp, m0); + + m0 = ieee80211_encap(ic, m0, ni); + if (m0 == NULL) + continue; + + if (ic->ic_rawbpf != NULL) + bpf_mtap(ic->ic_rawbpf, m0); + + if (iwi_tx_start(ifp, m0, ni) != 0) { + ieee80211_free_node(ni); + ifp->if_oerrors++; + break; + } + + sc->sc_tx_timer = 5; + ifp->if_timer = 1; + } + + IWI_UNLOCK(sc); +} + +static void +iwi_watchdog(struct ifnet *ifp) +{ + struct iwi_softc *sc = ifp->if_softc; + struct ieee80211com *ic = &sc->sc_ic; + + IWI_LOCK(sc); + + ifp->if_timer = 0; + + if (sc->sc_tx_timer > 0) { + if (--sc->sc_tx_timer == 0) { + if_printf(ifp, "device timeout\n"); + ifp->if_oerrors++; + ifp->if_flags &= ~IFF_UP; + iwi_stop(sc); + IWI_UNLOCK(sc); + return; + } + ifp->if_timer = 1; + } + + ieee80211_watchdog(ic); + + IWI_UNLOCK(sc); +} + +static int +iwi_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) +{ + struct iwi_softc *sc = ifp->if_softc; + struct ieee80211com *ic = &sc->sc_ic; + struct ifreq *ifr; + int error = 0; + + IWI_LOCK(sc); + + switch (cmd) { + case SIOCSIFFLAGS: + if (ifp->if_flags & IFF_UP) { + if (!(ifp->if_flags & IFF_RUNNING)) + iwi_init(sc); + } else { + if (ifp->if_flags & IFF_RUNNING) + iwi_stop(sc); + } + break; + + case SIOCSLOADFW: + /* only super-user can do that! */ + if ((error = suser(curthread)) != 0) + break; + + ifr = (struct ifreq *)data; + error = iwi_cache_firmware(sc, ifr->ifr_data); + break; + + case SIOCSKILLFW: + /* only super-user can do that! */ + if ((error = suser(curthread)) != 0) + break; + + ifp->if_flags &= ~IFF_UP; + iwi_stop(sc); + iwi_free_firmware(sc); + break; + + default: + error = ieee80211_ioctl(ic, cmd, data); + } + + if (error == ENETRESET) { + if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == + (IFF_UP | IFF_RUNNING)) + iwi_init(sc); + error = 0; + } + + IWI_UNLOCK(sc); + + return error; +} + +static void +iwi_stop_master(struct iwi_softc *sc) +{ + uint32_t tmp; + int ntries; + + /* disable interrupts */ + CSR_WRITE_4(sc, IWI_CSR_INTR_MASK, 0); + + CSR_WRITE_4(sc, IWI_CSR_RST, IWI_RST_STOP_MASTER); + for (ntries = 0; ntries < 5; ntries++) { + if (CSR_READ_4(sc, IWI_CSR_RST) & IWI_RST_MASTER_DISABLED) + break; + DELAY(10); + } + if (ntries == 5) + device_printf(sc->sc_dev, "timeout waiting for master\n"); + + tmp = CSR_READ_4(sc, IWI_CSR_RST); + CSR_WRITE_4(sc, IWI_CSR_RST, tmp | IWI_RST_PRINCETON_RESET); + + sc->flags &= ~IWI_FLAG_FW_INITED; +} + +static int +iwi_reset(struct iwi_softc *sc) +{ + uint32_t tmp; + int i, ntries; + + iwi_stop_master(sc); + + tmp = CSR_READ_4(sc, IWI_CSR_CTL); + CSR_WRITE_4(sc, IWI_CSR_CTL, tmp | IWI_CTL_INIT); + + CSR_WRITE_4(sc, IWI_CSR_READ_INT, IWI_READ_INT_INIT_HOST); + + /* wait for clock stabilization */ + for (ntries = 0; ntries < 1000; ntries++) { + if (CSR_READ_4(sc, IWI_CSR_CTL) & IWI_CTL_CLOCK_READY) + break; + DELAY(200); + } + if (ntries == 1000) { + device_printf(sc->sc_dev, + "timeout waiting for clock stabilization\n"); + return EIO; + } + + tmp = CSR_READ_4(sc, IWI_CSR_RST); + CSR_WRITE_4(sc, IWI_CSR_RST, tmp | IWI_RST_SOFT_RESET); + + DELAY(10); + + tmp = CSR_READ_4(sc, IWI_CSR_CTL); + CSR_WRITE_4(sc, IWI_CSR_CTL, tmp | IWI_CTL_INIT); + + /* clear NIC memory */ + CSR_WRITE_4(sc, IWI_CSR_AUTOINC_ADDR, 0); + for (i = 0; i < 0xc000; i++) + CSR_WRITE_4(sc, IWI_CSR_AUTOINC_DATA, 0); + + return 0; +} + +static int +iwi_load_ucode(struct iwi_softc *sc, void *uc, int size) +{ + uint32_t tmp; + uint16_t *w; + int ntries, i; + + CSR_WRITE_4(sc, IWI_CSR_RST, CSR_READ_4(sc, IWI_CSR_RST) | + IWI_RST_STOP_MASTER); + for (ntries = 0; ntries < 5; ntries++) { + if (CSR_READ_4(sc, IWI_CSR_RST) & IWI_RST_MASTER_DISABLED) + break; + DELAY(10); + } + if (ntries == 5) { + device_printf(sc->sc_dev, "timeout waiting for master\n"); + return EIO; + } + + MEM_WRITE_4(sc, 0x3000e0, 0x80000000); + DELAY(5000); + + tmp = CSR_READ_4(sc, IWI_CSR_RST); + tmp &= ~IWI_RST_PRINCETON_RESET; + CSR_WRITE_4(sc, IWI_CSR_RST, tmp); + + DELAY(5000); + MEM_WRITE_4(sc, 0x3000e0, 0); + DELAY(1000); + MEM_WRITE_4(sc, 0x300004, 1); + DELAY(1000); + MEM_WRITE_4(sc, 0x300004, 0); + DELAY(1000); + MEM_WRITE_1(sc, 0x200000, 0x00); + MEM_WRITE_1(sc, 0x200000, 0x40); + DELAY(1000); + + /* write microcode into adapter memory */ + for (w = uc; size > 0; w++, size -= 2) + MEM_WRITE_2(sc, 0x200010, *w); + + MEM_WRITE_1(sc, 0x200000, 0x00); + MEM_WRITE_1(sc, 0x200000, 0x80); + + /* wait until we get an answer */ + for (ntries = 0; ntries < 100; ntries++) { + if (MEM_READ_1(sc, 0x200000) & 1) + break; + DELAY(100); + } + if (ntries == 100) { + device_printf(sc->sc_dev, + "timeout waiting for ucode to initialize\n"); + return EIO; + } + + /* read the answer or the firmware will not initialize properly */ + for (i = 0; i < 7; i++) + MEM_READ_4(sc, 0x200004); + + MEM_WRITE_1(sc, 0x200000, 0x00); + + return 0; +} + +/* macro to handle unaligned little endian data in firmware image */ +#define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24) + +static int +iwi_load_firmware(struct iwi_softc *sc, void *fw, int size) +{ + bus_dma_tag_t dmat; + bus_dmamap_t map; + bus_addr_t physaddr; + void *virtaddr; + u_char *p, *end; + uint32_t sentinel, ctl, src, dst, sum, len, mlen, tmp; + int ntries, error = 0; + + /* allocate DMA memory for mapping firmware image */ + error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, + BUS_SPACE_MAXADDR, NULL, NULL, size, 1, size, 0, NULL, NULL, &dmat); + if (error != 0) { + device_printf(sc->sc_dev, + "could not create firmware DMA tag\n"); + goto fail1; + } + + error = bus_dmamem_alloc(dmat, &virtaddr, BUS_DMA_NOWAIT, &map); + if (error != 0) { + device_printf(sc->sc_dev, + "could not allocate firmware DMA memory\n"); + goto fail2; + } + + error = bus_dmamap_load(dmat, map, virtaddr, size, iwi_dma_map_addr, + &physaddr, 0); + if (error != 0) { + device_printf(sc->sc_dev, "could not load firmware DMA map\n"); + goto fail3; + } + + /* copy firmware image to DMA memory */ + memcpy(virtaddr, fw, size); + + /* make sure the adapter will get up-to-date values */ + bus_dmamap_sync(dmat, map, BUS_DMASYNC_PREWRITE); + + /* tell the adapter where the command blocks are stored */ + MEM_WRITE_4(sc, 0x3000a0, 0x27000); + + /* + * Store command blocks into adapter's internal memory using register + * indirections. The adapter will read the firmware image through DMA + * using information stored in command blocks. + */ + src = physaddr; + p = virtaddr; + end = p + size; + CSR_WRITE_4(sc, IWI_CSR_AUTOINC_ADDR, 0x27000); + + while (p < end) { + dst = GETLE32(p); p += 4; src += 4; + len = GETLE32(p); p += 4; src += 4; + p += len; + + while (len > 0) { + mlen = min(len, IWI_CB_MAXDATALEN); + + ctl = IWI_CB_DEFAULT_CTL | mlen; + sum = ctl ^ src ^ dst; + + /* write a command block */ + CSR_WRITE_4(sc, IWI_CSR_AUTOINC_DATA, ctl); + CSR_WRITE_4(sc, IWI_CSR_AUTOINC_DATA, src); + CSR_WRITE_4(sc, IWI_CSR_AUTOINC_DATA, dst); + CSR_WRITE_4(sc, IWI_CSR_AUTOINC_DATA, sum); + + src += mlen; + dst += mlen; + len -= mlen; + } + } + + /* write a fictive final command block (sentinel) */ + sentinel = CSR_READ_4(sc, IWI_CSR_AUTOINC_ADDR); + CSR_WRITE_4(sc, IWI_CSR_AUTOINC_DATA, 0); + + tmp = CSR_READ_4(sc, IWI_CSR_RST); + tmp &= ~(IWI_RST_MASTER_DISABLED | IWI_RST_STOP_MASTER); + CSR_WRITE_4(sc, IWI_CSR_RST, tmp); + + /* tell the adapter to start processing command blocks */ + MEM_WRITE_4(sc, 0x3000a4, 0x540100); + + /* wait until the adapter reach the sentinel */ + for (ntries = 0; ntries < 400; ntries++) { + if (MEM_READ_4(sc, 0x3000d0) >= sentinel) + break; + DELAY(100); + } + if (ntries == 400) { + device_printf(sc->sc_dev, + "timeout processing command blocks\n"); + error = EIO; + goto fail4; + } + + /* we're done with command blocks processing */ + MEM_WRITE_4(sc, 0x3000a4, 0x540c00); + + /* allow interrupts so we know when the firmware is inited */ + CSR_WRITE_4(sc, IWI_CSR_INTR_MASK, IWI_INTR_MASK); + + /* tell the adapter to initialize the firmware */ + CSR_WRITE_4(sc, IWI_CSR_RST, 0); + + tmp = CSR_READ_4(sc, IWI_CSR_CTL); + CSR_WRITE_4(sc, IWI_CSR_CTL, tmp | IWI_CTL_ALLOW_STANDBY); + + /* wait at most one second for firmware initialization to complete */ + if ((error = msleep(sc, &sc->sc_mtx, 0, "iwiinit", hz)) != 0) { + device_printf(sc->sc_dev, "timeout waiting for firmware " + "initialization to complete\n"); + goto fail4; + } + +fail4: bus_dmamap_sync(dmat, map, BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(dmat, map); +fail3: bus_dmamem_free(dmat, virtaddr, map); +fail2: bus_dma_tag_destroy(dmat); +fail1: + return error; +} + +/* + * Store firmware into kernel memory so we can download it when we need to, + * e.g when the adapter wakes up from suspend mode. + */ +static int +iwi_cache_firmware(struct iwi_softc *sc, void *data) +{ + struct iwi_firmware *kfw = &sc->fw; + struct iwi_firmware ufw; + int error; + + iwi_free_firmware(sc); + + IWI_UNLOCK(sc); + + if ((error = copyin(data, &ufw, sizeof ufw)) != 0) + goto fail1; + + kfw->boot_size = ufw.boot_size; + kfw->ucode_size = ufw.ucode_size; + kfw->main_size = ufw.main_size; + + kfw->boot = malloc(kfw->boot_size, M_DEVBUF, M_NOWAIT); + if (kfw->boot == NULL) { + error = ENOMEM; + goto fail1; + } + + kfw->ucode = malloc(kfw->ucode_size, M_DEVBUF, M_NOWAIT); + if (kfw->ucode == NULL) { + error = ENOMEM; + goto fail2; + } + + kfw->main = malloc(kfw->main_size, M_DEVBUF, M_NOWAIT); + if (kfw->main == NULL) { + error = ENOMEM; + goto fail3; + } + + if ((error = copyin(ufw.boot, kfw->boot, kfw->boot_size)) != 0) + goto fail4; + + if ((error = copyin(ufw.ucode, kfw->ucode, kfw->ucode_size)) != 0) + goto fail4; + + if ((error = copyin(ufw.main, kfw->main, kfw->main_size)) != 0) + goto fail4; + + DPRINTF(("Firmware cached: boot %u, ucode %u, main %u\n", + kfw->boot_size, kfw->ucode_size, kfw->main_size)); + + IWI_LOCK(sc); + + sc->flags |= IWI_FLAG_FW_CACHED; + + return 0; + +fail4: free(kfw->boot, M_DEVBUF); +fail3: free(kfw->ucode, M_DEVBUF); +fail2: free(kfw->main, M_DEVBUF); +fail1: IWI_LOCK(sc); + + return error; +} + +static void +iwi_free_firmware(struct iwi_softc *sc) +{ + if (!(sc->flags & IWI_FLAG_FW_CACHED)) + return; + + free(sc->fw.boot, M_DEVBUF); + free(sc->fw.ucode, M_DEVBUF); + free(sc->fw.main, M_DEVBUF); + + sc->flags &= ~IWI_FLAG_FW_CACHED; +} + +static int +iwi_config(struct iwi_softc *sc) +{ + struct ieee80211com *ic = &sc->sc_ic; + struct ifnet *ifp = ic->ic_ifp; + struct iwi_configuration config; + struct iwi_rateset rs; + struct iwi_txpower power; + struct ieee80211_key *wk; + struct iwi_wep_key wepkey; + uint32_t data; + int error, i; + + IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); + DPRINTF(("Setting MAC address to %6D\n", ic->ic_myaddr, ":")); + error = iwi_cmd(sc, IWI_CMD_SET_MAC_ADDRESS, ic->ic_myaddr, + IEEE80211_ADDR_LEN, 0); + if (error != 0) + return error; + + memset(&config, 0, sizeof config); + config.bluetooth_coexistence = sc->bluetooth; + config.multicast_enabled = 1; + DPRINTF(("Configuring adapter\n")); + error = iwi_cmd(sc, IWI_CMD_SET_CONFIG, &config, sizeof config, 0); + if (error != 0) + return error; + + data = htole32(IWI_POWER_MODE_CAM); + DPRINTF(("Setting power mode to %u\n", le32toh(data))); + error = iwi_cmd(sc, IWI_CMD_SET_POWER_MODE, &data, sizeof data, 0); + if (error != 0) + return error; + + data = htole32(ic->ic_rtsthreshold); + DPRINTF(("Setting RTS threshold to %u\n", le32toh(data))); + error = iwi_cmd(sc, IWI_CMD_SET_RTS_THRESHOLD, &data, sizeof data, 0); + if (error != 0) + return error; + + if (ic->ic_opmode == IEEE80211_M_IBSS) { + power.mode = IWI_MODE_11B; + power.nchan = 11; + for (i = 0; i < 11; i++) { + power.chan[i].chan = i + 1; + power.chan[i].power = IWI_TXPOWER_MAX; + } + DPRINTF(("Setting .11b channels tx power\n")); + error = iwi_cmd(sc, IWI_CMD_SET_TX_POWER, &power, sizeof power, + 0); + if (error != 0) + return error; + + power.mode = IWI_MODE_11G; + DPRINTF(("Setting .11g channels tx power\n")); + error = iwi_cmd(sc, IWI_CMD_SET_TX_POWER, &power, sizeof power, + 0); + if (error != 0) + return error; + } + + rs.mode = IWI_MODE_11G; + rs.type = IWI_RATESET_TYPE_SUPPORTED; + rs.nrates = ic->ic_sup_rates[IEEE80211_MODE_11G].rs_nrates; + memcpy(rs.rates, ic->ic_sup_rates[IEEE80211_MODE_11G].rs_rates, + rs.nrates); + DPRINTF(("Setting .11bg supported rates (%u)\n", rs.nrates)); + error = iwi_cmd(sc, IWI_CMD_SET_RATES, &rs, sizeof rs, 0); + if (error != 0) + return error; + + rs.mode = IWI_MODE_11A; + rs.type = IWI_RATESET_TYPE_SUPPORTED; + rs.nrates = ic->ic_sup_rates[IEEE80211_MODE_11A].rs_nrates; + memcpy(rs.rates, ic->ic_sup_rates[IEEE80211_MODE_11A].rs_rates, + rs.nrates); + DPRINTF(("Setting .11a supported rates (%u)\n", rs.nrates)); + error = iwi_cmd(sc, IWI_CMD_SET_RATES, &rs, sizeof rs, 0); + if (error != 0) + return error; + + data = htole32(arc4random()); + DPRINTF(("Setting initialization vector to %u\n", le32toh(data))); + error = iwi_cmd(sc, IWI_CMD_SET_IV, &data, sizeof data, 0); + if (error != 0) + return error; + + for (i = 0; i < IEEE80211_WEP_NKID; i++) { + wk = &ic->ic_crypto.cs_nw_keys[i]; + + wepkey.cmd = IWI_WEP_KEY_CMD_SETKEY; + wepkey.idx = i; + wepkey.len = wk->wk_keylen; + memset(wepkey.key, 0, sizeof wepkey.key); + memcpy(wepkey.key, wk->wk_key, wk->wk_keylen); + DPRINTF(("Setting wep key index %u len %u\n", wepkey.idx, + wepkey.len)); + error = iwi_cmd(sc, IWI_CMD_SET_WEP_KEY, &wepkey, + sizeof wepkey, 0); + if (error != 0) + return error; + } + + /* enable adapter */ + DPRINTF(("Enabling adapter\n")); + return iwi_cmd(sc, IWI_CMD_ENABLE, NULL, 0, 0); +} + +static int +iwi_scan(struct iwi_softc *sc) +{ + struct ieee80211com *ic = &sc->sc_ic; + struct iwi_scan scan; + uint8_t *p; + int i, count; + + memset(&scan, 0, sizeof scan); + scan.type = IWI_SCAN_TYPE_BROADCAST; + scan.intval = htole16(sc->dwelltime); + + p = scan.channels; + count = 0; + for (i = 0; i <= IEEE80211_CHAN_MAX; i++) { + if (IEEE80211_IS_CHAN_5GHZ(&ic->ic_channels[i]) && + isset(ic->ic_chan_active, i)) { + *++p = i; + count++; + } + } + *(p - count) = IWI_CHAN_5GHZ | count; + + count = 0; + for (i = 0; i <= IEEE80211_CHAN_MAX; i++) { + if (IEEE80211_IS_CHAN_2GHZ(&ic->ic_channels[i]) && + isset(ic->ic_chan_active, i)) { + *++p = i; + count++; + } + } + *(p - count) = IWI_CHAN_2GHZ | count; + + DPRINTF(("Start scanning\n")); + return iwi_cmd(sc, IWI_CMD_SCAN, &scan, sizeof scan, 1); +} + +static int +iwi_auth_and_assoc(struct iwi_softc *sc) +{ + struct ieee80211com *ic = &sc->sc_ic; + struct ifnet *ifp = ic->ic_ifp; + struct ieee80211_node *ni = ic->ic_bss; + struct iwi_configuration config; + struct iwi_associate assoc; + struct iwi_rateset rs; + uint32_t data; + int error; + + if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) { + memset(&config, 0, sizeof config); + config.bluetooth_coexistence = sc->bluetooth; + config.multicast_enabled = 1; + config.use_protection = 1; + DPRINTF(("Configuring adapter\n")); + error = iwi_cmd(sc, IWI_CMD_SET_CONFIG, &config, sizeof config, + 1); + if (error != 0) + return error; + } + +#ifdef IWI_DEBUG + if (iwi_debug > 0) { + printf("Setting ESSID to "); + ieee80211_print_essid(ni->ni_essid, ni->ni_esslen); + printf("\n"); + } +#endif + error = iwi_cmd(sc, IWI_CMD_SET_ESSID, ni->ni_essid, ni->ni_esslen, 1); + if (error != 0) + return error; + + /* the rate set has already been "negociated" */ + rs.mode = IEEE80211_IS_CHAN_5GHZ(ni->ni_chan) ? IWI_MODE_11A : + IWI_MODE_11G; + rs.type = IWI_RATESET_TYPE_NEGOCIATED; + rs.nrates = ni->ni_rates.rs_nrates; + memcpy(rs.rates, ni->ni_rates.rs_rates, rs.nrates); + DPRINTF(("Setting negociated rates (%u)\n", rs.nrates)); + error = iwi_cmd(sc, IWI_CMD_SET_RATES, &rs, sizeof rs, 1); + if (error != 0) + return error; + + data = htole32(ni->ni_rssi); + DPRINTF(("Setting sensitivity to %d\n", (int8_t)ni->ni_rssi)); + error = iwi_cmd(sc, IWI_CMD_SET_SENSITIVITY, &data, sizeof data, 1); + if (error != 0) + return error; + + memset(&assoc, 0, sizeof assoc); + assoc.mode = IEEE80211_IS_CHAN_5GHZ(ni->ni_chan) ? IWI_MODE_11A : + IWI_MODE_11G; + assoc.chan = ieee80211_chan2ieee(ic, ni->ni_chan); + if (ni->ni_authmode == IEEE80211_AUTH_SHARED) + assoc.auth = ic->ic_crypto.cs_def_txkey << 4 | IWI_AUTH_SHARED; + memcpy(assoc.tstamp, ni->ni_tstamp.data, 8); + assoc.capinfo = htole16(ni->ni_capinfo); + assoc.lintval = htole16(ic->ic_lintval); + assoc.intval = htole16(ni->ni_intval); + IEEE80211_ADDR_COPY(assoc.bssid, ni->ni_bssid); + if (ic->ic_opmode == IEEE80211_M_IBSS) + IEEE80211_ADDR_COPY(assoc.dst, ifp->if_broadcastaddr); + else + IEEE80211_ADDR_COPY(assoc.dst, ni->ni_bssid); + + DPRINTF(("Trying to associate to %6D channel %u auth %u\n", + assoc.bssid, ":", assoc.chan, assoc.auth)); + return iwi_cmd(sc, IWI_CMD_ASSOCIATE, &assoc, sizeof assoc, 1); +} + +static void +iwi_init(void *priv) +{ + struct iwi_softc *sc = priv; + struct ieee80211com *ic = &sc->sc_ic; + struct ifnet *ifp = ic->ic_ifp; + struct iwi_firmware *fw = &sc->fw; + struct iwi_rx_data *data; + int i; + + /* exit immediately if firmware has not been ioctl'd */ + if (!(sc->flags & IWI_FLAG_FW_CACHED)) { + ifp->if_flags &= ~IFF_UP; + return; + } + + iwi_stop(sc); + + if (iwi_reset(sc) != 0) { + device_printf(sc->sc_dev, "could not reset adapter\n"); + goto fail; + } + + if (iwi_load_firmware(sc, fw->boot, fw->boot_size) != 0) { + device_printf(sc->sc_dev, "could not load boot firmware\n"); + goto fail; + } + + if (iwi_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) { + device_printf(sc->sc_dev, "could not load microcode\n"); + goto fail; + } + + iwi_stop_master(sc); + + CSR_WRITE_4(sc, IWI_CSR_CMD_BASE, sc->cmdq.physaddr); + CSR_WRITE_4(sc, IWI_CSR_CMD_SIZE, sc->cmdq.count); + CSR_WRITE_4(sc, IWI_CSR_CMD_WIDX, sc->cmdq.cur); + + CSR_WRITE_4(sc, IWI_CSR_TX1_BASE, sc->txq.physaddr); + CSR_WRITE_4(sc, IWI_CSR_TX1_SIZE, sc->txq.count); + CSR_WRITE_4(sc, IWI_CSR_TX1_WIDX, sc->txq.cur); + + CSR_WRITE_4(sc, IWI_CSR_TX2_BASE, sc->txq.physaddr); + CSR_WRITE_4(sc, IWI_CSR_TX2_SIZE, sc->txq.count); + CSR_WRITE_4(sc, IWI_CSR_TX2_WIDX, sc->txq.cur); + + CSR_WRITE_4(sc, IWI_CSR_TX3_BASE, sc->txq.physaddr); + CSR_WRITE_4(sc, IWI_CSR_TX3_SIZE, sc->txq.count); + CSR_WRITE_4(sc, IWI_CSR_TX3_WIDX, sc->txq.cur); + + CSR_WRITE_4(sc, IWI_CSR_TX4_BASE, sc->txq.physaddr); + CSR_WRITE_4(sc, IWI_CSR_TX4_SIZE, sc->txq.count); + CSR_WRITE_4(sc, IWI_CSR_TX4_WIDX, sc->txq.cur); + + for (i = 0; i < sc->rxq.count; i++) { + data = &sc->rxq.data[i]; + CSR_WRITE_4(sc, data->reg, data->physaddr); + } + + CSR_WRITE_4(sc, IWI_CSR_RX_WIDX, sc->rxq.count - 1); + + if (iwi_load_firmware(sc, fw->main, fw->main_size) != 0) { + device_printf(sc->sc_dev, "could not load main firmware\n"); + goto fail; + } + + sc->flags |= IWI_FLAG_FW_INITED; + + if (iwi_config(sc) != 0) { + device_printf(sc->sc_dev, "device configuration failed\n"); + goto fail; + } + + ieee80211_begin_scan(ic, 1); + + ifp->if_flags &= ~IFF_OACTIVE; + ifp->if_flags |= IFF_RUNNING; + + return; + +fail: ifp->if_flags &= ~IFF_UP; + iwi_stop(sc); +} + +static void +iwi_stop(void *priv) +{ + struct iwi_softc *sc = priv; + struct ieee80211com *ic = &sc->sc_ic; + struct ifnet *ifp = ic->ic_ifp; + + iwi_stop_master(sc); + + CSR_WRITE_4(sc, IWI_CSR_RST, IWI_RST_SOFT_RESET); + + /* reset rings */ + iwi_reset_cmd_ring(sc, &sc->cmdq); + iwi_reset_tx_ring(sc, &sc->txq); + iwi_reset_rx_ring(sc, &sc->rxq); + + sc->sc_tx_timer = 0; + ifp->if_timer = 0; + ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); + + ieee80211_new_state(ic, IEEE80211_S_INIT, -1); +} + +#ifdef IWI_DEBUG +static int +iwi_sysctl_stats(SYSCTL_HANDLER_ARGS) +{ + struct iwi_softc *sc = arg1; + uint32_t size, buf[128]; + + if (!(sc->flags & IWI_FLAG_FW_INITED)) { + memset(buf, 0, sizeof buf); + return SYSCTL_OUT(req, buf, sizeof buf); + } + + size = min(CSR_READ_4(sc, IWI_CSR_TABLE0_SIZE), 128 - 1); + CSR_READ_REGION_4(sc, IWI_CSR_TABLE0_BASE, &buf[1], size); + + return SYSCTL_OUT(req, buf, sizeof buf); +} +#endif + +static int +iwi_sysctl_radio(SYSCTL_HANDLER_ARGS) +{ + struct iwi_softc *sc = arg1; + int val; + + val = (CSR_READ_4(sc, IWI_CSR_IO) & IWI_IO_RADIO_ENABLED) ? 1 : 0; + + return SYSCTL_OUT(req, &val, sizeof val); +} diff --git a/sys/dev/iwi/if_iwireg.h b/sys/dev/iwi/if_iwireg.h new file mode 100644 index 0000000..7a0b2af --- /dev/null +++ b/sys/dev/iwi/if_iwireg.h @@ -0,0 +1,439 @@ +/* $FreeBSD$ */ + +/*- + * Copyright (c) 2004, 2005 + * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice unmodified, this list of conditions, and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#define IWI_CMD_RING_COUNT 16 +#define IWI_TX_RING_COUNT 64 +#define IWI_RX_RING_COUNT 32 + +#define IWI_TX_DESC_SIZE (sizeof (struct iwi_tx_desc)) +#define IWI_CMD_DESC_SIZE (sizeof (struct iwi_cmd_desc)) + +#define IWI_CSR_INTR 0x0008 +#define IWI_CSR_INTR_MASK 0x000c +#define IWI_CSR_INDIRECT_ADDR 0x0010 +#define IWI_CSR_INDIRECT_DATA 0x0014 +#define IWI_CSR_AUTOINC_ADDR 0x0018 +#define IWI_CSR_AUTOINC_DATA 0x001c +#define IWI_CSR_RST 0x0020 +#define IWI_CSR_CTL 0x0024 +#define IWI_CSR_IO 0x0030 +#define IWI_CSR_CMD_BASE 0x0200 +#define IWI_CSR_CMD_SIZE 0x0204 +#define IWI_CSR_TX1_BASE 0x0208 +#define IWI_CSR_TX1_SIZE 0x020c +#define IWI_CSR_TX2_BASE 0x0210 +#define IWI_CSR_TX2_SIZE 0x0214 +#define IWI_CSR_TX3_BASE 0x0218 +#define IWI_CSR_TX3_SIZE 0x021c +#define IWI_CSR_TX4_BASE 0x0220 +#define IWI_CSR_TX4_SIZE 0x0224 +#define IWI_CSR_CMD_RIDX 0x0280 +#define IWI_CSR_TX1_RIDX 0x0284 +#define IWI_CSR_TX2_RIDX 0x0288 +#define IWI_CSR_TX3_RIDX 0x028c +#define IWI_CSR_TX4_RIDX 0x0290 +#define IWI_CSR_RX_RIDX 0x02a0 +#define IWI_CSR_RX_BASE 0x0500 +#define IWI_CSR_TABLE0_SIZE 0x0700 +#define IWI_CSR_TABLE0_BASE 0x0704 +#define IWI_CSR_CMD_WIDX 0x0f80 +#define IWI_CSR_TX1_WIDX 0x0f84 +#define IWI_CSR_TX2_WIDX 0x0f88 +#define IWI_CSR_TX3_WIDX 0x0f8c +#define IWI_CSR_TX4_WIDX 0x0f90 +#define IWI_CSR_RX_WIDX 0x0fa0 +#define IWI_CSR_READ_INT 0x0ff4 + +/* aliases */ +#define IWI_CSR_CURRENT_TX_RATE IWI_CSR_TABLE0_BASE + +/* flags for IWI_CSR_INTR */ +#define IWI_INTR_RX_DONE 0x00000002 +#define IWI_INTR_CMD_DONE 0x00000800 +#define IWI_INTR_TX1_DONE 0x00001000 +#define IWI_INTR_TX2_DONE 0x00002000 +#define IWI_INTR_TX3_DONE 0x00004000 +#define IWI_INTR_TX4_DONE 0x00008000 +#define IWI_INTR_FW_INITED 0x01000000 +#define IWI_INTR_RADIO_OFF 0x04000000 +#define IWI_INTR_FATAL_ERROR 0x40000000 +#define IWI_INTR_PARITY_ERROR 0x80000000 + +#define IWI_INTR_MASK \ + (IWI_INTR_RX_DONE | IWI_INTR_CMD_DONE | IWI_INTR_TX1_DONE | \ + IWI_INTR_TX2_DONE | IWI_INTR_TX3_DONE | IWI_INTR_TX4_DONE | \ + IWI_INTR_FW_INITED | IWI_INTR_RADIO_OFF | \ + IWI_INTR_FATAL_ERROR | IWI_INTR_PARITY_ERROR) + +/* flags for IWI_CSR_RST */ +#define IWI_RST_PRINCETON_RESET 0x00000001 +#define IWI_RST_SOFT_RESET 0x00000080 +#define IWI_RST_MASTER_DISABLED 0x00000100 +#define IWI_RST_STOP_MASTER 0x00000200 + +/* flags for IWI_CSR_CTL */ +#define IWI_CTL_CLOCK_READY 0x00000001 +#define IWI_CTL_ALLOW_STANDBY 0x00000002 +#define IWI_CTL_INIT 0x00000004 + +/* flags for IWI_CSR_IO */ +#define IWI_IO_RADIO_ENABLED 0x00010000 + +/* flags for IWI_CSR_READ_INT */ +#define IWI_READ_INT_INIT_HOST 0x20000000 + +/* constants for command blocks */ +#define IWI_CB_DEFAULT_CTL 0x8cea0000 +#define IWI_CB_MAXDATALEN 8191 + +/* supported rates */ +#define IWI_RATE_DS1 10 +#define IWI_RATE_DS2 20 +#define IWI_RATE_DS5 55 +#define IWI_RATE_DS11 110 +#define IWI_RATE_OFDM6 13 +#define IWI_RATE_OFDM9 15 +#define IWI_RATE_OFDM12 5 +#define IWI_RATE_OFDM18 7 +#define IWI_RATE_OFDM24 9 +#define IWI_RATE_OFDM36 11 +#define IWI_RATE_OFDM48 1 +#define IWI_RATE_OFDM54 3 + +struct iwi_hdr { + uint8_t type; +#define IWI_HDR_TYPE_DATA 0 +#define IWI_HDR_TYPE_COMMAND 1 +#define IWI_HDR_TYPE_NOTIF 3 +#define IWI_HDR_TYPE_FRAME 9 + + uint8_t seq; + uint8_t flags; +#define IWI_HDR_FLAG_IRQ 0x04 + + uint8_t reserved; +} __packed; + +struct iwi_notif { + uint32_t reserved[2]; + uint8_t type; +#define IWI_NOTIF_TYPE_ASSOCIATION 10 +#define IWI_NOTIF_TYPE_AUTHENTICATION 11 +#define IWI_NOTIF_TYPE_SCAN_CHANNEL 12 +#define IWI_NOTIF_TYPE_SCAN_COMPLETE 13 +#define IWI_NOTIF_TYPE_BEACON 17 +#define IWI_NOTIF_TYPE_CALIBRATION 20 +#define IWI_NOTIF_TYPE_NOISE 25 + + uint8_t flags; + uint16_t len; +} __packed; + +/* structure for notification IWI_NOTIF_TYPE_AUTHENTICATION */ +struct iwi_notif_authentication { + uint8_t state; +#define IWI_DEAUTHENTICATED 0 +#define IWI_AUTHENTICATED 9 +} __packed; + +/* structure for notification IWI_NOTIF_TYPE_ASSOCIATION */ +struct iwi_notif_association { + uint8_t state; +#define IWI_DEASSOCIATED 0 +#define IWI_ASSOCIATED 12 + + struct ieee80211_frame frame; + uint16_t capinfo; + uint16_t status; + uint16_t associd; +} __packed; + +/* structure for notification IWI_NOTIF_TYPE_SCAN_CHANNEL */ +struct iwi_notif_scan_channel { + uint8_t nchan; + uint8_t reserved[47]; +} __packed; + +/* structure for notification IWI_NOTIF_TYPE_SCAN_COMPLETE */ +struct iwi_notif_scan_complete { + uint8_t type; + uint8_t nchan; + uint8_t status; + uint8_t reserved; +} __packed; + +/* received frame header */ +struct iwi_frame { + uint32_t reserved1[2]; + uint8_t chan; + uint8_t status; + uint8_t rate; + uint8_t rssi; + uint8_t agc; + uint8_t rssi_dbm; + uint16_t signal; + uint16_t noise; + uint8_t antenna; + uint8_t control; + uint8_t reserved2[2]; + uint16_t len; +} __packed; + +/* header for transmission */ +struct iwi_tx_desc { + struct iwi_hdr hdr; + uint32_t reserved1; + uint8_t station; + uint8_t reserved2[3]; + uint8_t cmd; +#define IWI_DATA_CMD_TX 0x0b + + uint8_t seq; + uint16_t len; + uint8_t priority; + uint8_t flags; +#define IWI_DATA_FLAG_SHPREAMBLE 0x04 +#define IWI_DATA_FLAG_NO_WEP 0x20 +#define IWI_DATA_FLAG_NEED_ACK 0x80 + + uint8_t xflags; + uint8_t wep_txkey; + uint8_t wepkey[IEEE80211_KEYBUF_SIZE]; + uint8_t rate; + uint8_t antenna; + uint8_t reserved3[10]; + struct ieee80211_qosframe_addr4 wh; + uint32_t iv; + uint32_t eiv; + uint32_t nseg; +#define IWI_MAX_NSEG 6 + + uint32_t seg_addr[IWI_MAX_NSEG]; + uint16_t seg_len[IWI_MAX_NSEG]; +} __packed; + +/* command */ +struct iwi_cmd_desc { + struct iwi_hdr hdr; + uint8_t type; +#define IWI_CMD_ENABLE 2 +#define IWI_CMD_SET_CONFIG 6 +#define IWI_CMD_SET_ESSID 8 +#define IWI_CMD_SET_MAC_ADDRESS 11 +#define IWI_CMD_SET_RTS_THRESHOLD 15 +#define IWI_CMD_SET_POWER_MODE 17 +#define IWI_CMD_SET_WEP_KEY 18 +#define IWI_CMD_SCAN 20 +#define IWI_CMD_ASSOCIATE 21 +#define IWI_CMD_SET_RATES 22 +#define IWI_CMD_DISABLE 33 +#define IWI_CMD_SET_IV 34 +#define IWI_CMD_SET_TX_POWER 35 +#define IWI_CMD_SET_SENSITIVITY 42 + + uint8_t len; + uint16_t reserved; + uint8_t data[120]; +} __packed; + +/* constants for 'mode' fields */ +#define IWI_MODE_11A 0 +#define IWI_MODE_11B 1 +#define IWI_MODE_11G 2 + +/* macro for command IWI_CMD_SET_SENSITIVITY */ +#define IWI_RSSIDBM2RAW(rssi) ((rssi) - 112) + +/* possible values for command IWI_CMD_SET_POWER_MODE */ +#define IWI_POWER_MODE_CAM 0 + +/* structure for command IWI_CMD_SET_RATES */ +struct iwi_rateset { + uint8_t mode; + uint8_t nrates; + uint8_t type; +#define IWI_RATESET_TYPE_NEGOCIATED 0 +#define IWI_RATESET_TYPE_SUPPORTED 1 + + uint8_t reserved; + uint8_t rates[12]; +} __packed; + +/* structure for command IWI_CMD_SET_TX_POWER */ +struct iwi_txpower { + uint8_t nchan; + uint8_t mode; + struct { + uint8_t chan; + uint8_t power; +#define IWI_TXPOWER_MAX 20 +#define IWI_TXPOWER_RATIO (IEEE80211_TXPOWER_MAX / IWI_TXPOWER_MAX) + } __packed chan[37]; +} __packed; + +/* structure for command IWI_CMD_ASSOCIATE */ +struct iwi_associate { + uint8_t chan; + uint8_t auth; +#define IWI_AUTH_OPEN 0 +#define IWI_AUTH_SHARED 1 +#define IWI_AUTH_NONE 3 + + uint8_t type; + uint8_t reserved1; + uint16_t reserved2; + uint8_t plen; + uint8_t mode; + uint8_t bssid[IEEE80211_ADDR_LEN]; + uint8_t tstamp[8]; + uint16_t capinfo; + uint16_t lintval; + uint16_t intval; + uint8_t dst[IEEE80211_ADDR_LEN]; + uint32_t reserved3; + uint16_t reserved4; +} __packed; + +/* structure for command IWI_CMD_SCAN */ +struct iwi_scan { + uint8_t type; +#define IWI_SCAN_TYPE_BROADCAST 3 + + uint16_t intval; + uint8_t channels[54]; +#define IWI_CHAN_5GHZ (0 << 6) +#define IWI_CHAN_2GHZ (1 << 6) + + uint8_t reserved[3]; +} __packed; + +/* structure for command IWI_CMD_SET_CONFIG */ +struct iwi_configuration { + uint8_t bluetooth_coexistence; + uint8_t reserved1; + uint8_t answer_broadcast_probe_req; + uint8_t allow_invalid_frames; + uint8_t multicast_enabled; + uint8_t exclude_unicast_unencrypted; + uint8_t disable_unicast_decryption; + uint8_t exclude_multicast_unencrypted; + uint8_t disable_multicast_decryption; + uint8_t antenna; + uint8_t reserved2; + uint8_t use_protection; + uint8_t protection_ctsonly; + uint8_t enable_multicast_filtering; + uint8_t bluetooth_threshold; + uint8_t reserved4; + uint8_t allow_beacon_and_probe_resp; + uint8_t allow_mgt; + uint8_t noise_reported; + uint8_t reserved5; +} __packed; + +/* structure for command IWI_CMD_SET_WEP_KEY */ +struct iwi_wep_key { + uint8_t cmd; +#define IWI_WEP_KEY_CMD_SETKEY 0x08 + + uint8_t seq; + uint8_t idx; + uint8_t len; + uint8_t key[IEEE80211_KEYBUF_SIZE]; +} __packed; + +#define IWI_MEM_EEPROM_CTL 0x00300040 + +#define IWI_EEPROM_MAC 0x21 + +#define IWI_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ + +#define IWI_EEPROM_C (1 << 0) /* Serial Clock */ +#define IWI_EEPROM_S (1 << 1) /* Chip Select */ +#define IWI_EEPROM_D (1 << 2) /* Serial data input */ +#define IWI_EEPROM_Q (1 << 4) /* Serial data output */ + +#define IWI_EEPROM_SHIFT_D 2 +#define IWI_EEPROM_SHIFT_Q 4 + +/* + * control and status registers access macros + */ +#define CSR_READ_1(sc, reg) \ + bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) + +#define CSR_READ_2(sc, reg) \ + bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) + +#define CSR_READ_4(sc, reg) \ + bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) + +#define CSR_READ_REGION_4(sc, offset, datap, count) \ + bus_space_read_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ + (datap), (count)) + +#define CSR_WRITE_1(sc, reg, val) \ + bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) + +#define CSR_WRITE_2(sc, reg, val) \ + bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) + +#define CSR_WRITE_4(sc, reg, val) \ + bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) + +/* + * indirect memory space access macros + */ +#define MEM_WRITE_1(sc, addr, val) do { \ + CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ + CSR_WRITE_1((sc), IWI_CSR_INDIRECT_DATA, (val)); \ +} while (/* CONSTCOND */0) + +#define MEM_WRITE_2(sc, addr, val) do { \ + CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ + CSR_WRITE_2((sc), IWI_CSR_INDIRECT_DATA, (val)); \ +} while (/* CONSTCOND */0) + +#define MEM_WRITE_4(sc, addr, val) do { \ + CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ + CSR_WRITE_4((sc), IWI_CSR_INDIRECT_DATA, (val)); \ +} while (/* CONSTCOND */0) + +#define MEM_WRITE_MULTI_1(sc, addr, buf, len) do { \ + CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ + CSR_WRITE_MULTI_1((sc), IWI_CSR_INDIRECT_DATA, (buf), (len)); \ +} while (/* CONSTCOND */0) + +/* + * EEPROM access macro + */ +#define IWI_EEPROM_CTL(sc, val) do { \ + MEM_WRITE_4((sc), IWI_MEM_EEPROM_CTL, (val)); \ + DELAY(IWI_EEPROM_DELAY); \ +} while (/* CONSTCOND */0) diff --git a/sys/dev/iwi/if_iwivar.h b/sys/dev/iwi/if_iwivar.h new file mode 100644 index 0000000..a280c24 --- /dev/null +++ b/sys/dev/iwi/if_iwivar.h @@ -0,0 +1,163 @@ +/* $FreeBSD$ */ + +/*- + * Copyright (c) 2004, 2005 + * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice unmodified, this list of conditions, and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +struct iwi_firmware { + void *boot; + int boot_size; + void *ucode; + int ucode_size; + void *main; + int main_size; +}; + +struct iwi_rx_radiotap_header { + struct ieee80211_radiotap_header wr_ihdr; + uint8_t wr_flags; + uint8_t wr_rate; + uint16_t wr_chan_freq; + uint16_t wr_chan_flags; + uint8_t wr_antsignal; + uint8_t wr_antenna; +}; + +#define IWI_RX_RADIOTAP_PRESENT \ + ((1 << IEEE80211_RADIOTAP_FLAGS) | \ + (1 << IEEE80211_RADIOTAP_RATE) | \ + (1 << IEEE80211_RADIOTAP_CHANNEL) | \ + (1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL) | \ + (1 << IEEE80211_RADIOTAP_ANTENNA)) + +struct iwi_tx_radiotap_header { + struct ieee80211_radiotap_header wt_ihdr; + uint8_t wt_flags; + uint16_t wt_chan_freq; + uint16_t wt_chan_flags; +}; + +#define IWI_TX_RADIOTAP_PRESENT \ + ((1 << IEEE80211_RADIOTAP_FLAGS) | \ + (1 << IEEE80211_RADIOTAP_CHANNEL)) + +struct iwi_cmd_ring { + bus_dma_tag_t desc_dmat; + bus_dmamap_t desc_map; + bus_addr_t physaddr; + struct iwi_cmd_desc *desc; + int count; + int queued; + int cur; + int next; +}; + +struct iwi_tx_data { + bus_dmamap_t map; + struct mbuf *m; + struct ieee80211_node *ni; +}; + +struct iwi_tx_ring { + bus_dma_tag_t desc_dmat; + bus_dma_tag_t data_dmat; + bus_dmamap_t desc_map; + bus_addr_t physaddr; + struct iwi_tx_desc *desc; + struct iwi_tx_data *data; + int count; + int queued; + int cur; + int next; +}; + +struct iwi_rx_data { + bus_dmamap_t map; + bus_addr_t physaddr; + uint32_t reg; + struct mbuf *m; +}; + +struct iwi_rx_ring { + bus_dma_tag_t data_dmat; + struct iwi_rx_data *data; + int count; + int cur; +}; + +struct iwi_softc { + struct arpcom sc_arp; + struct ieee80211com sc_ic; + int (*sc_newstate)(struct ieee80211com *, + enum ieee80211_state, int); + device_t sc_dev; + + struct mtx sc_mtx; + + struct iwi_firmware fw; + uint32_t flags; +#define IWI_FLAG_FW_CACHED (1 << 0) +#define IWI_FLAG_FW_INITED (1 << 1) + + struct iwi_cmd_ring cmdq; + struct iwi_tx_ring txq; + struct iwi_rx_ring rxq; + + struct resource *irq; + struct resource *mem; + bus_space_tag_t sc_st; + bus_space_handle_t sc_sh; + void *sc_ih; + int mem_rid; + int irq_rid; + + int dwelltime; + int bluetooth; + + int sc_tx_timer; + + struct bpf_if *sc_drvbpf; + + union { + struct iwi_rx_radiotap_header th; + uint8_t pad[64]; + } sc_rxtapu; +#define sc_rxtap sc_rxtapu.th + int sc_rxtap_len; + + union { + struct iwi_tx_radiotap_header th; + uint8_t pad[64]; + } sc_txtapu; +#define sc_txtap sc_txtapu.th + int sc_txtap_len; +}; + +#define SIOCSLOADFW _IOW('i', 137, struct ifreq) +#define SIOCSKILLFW _IOW('i', 138, struct ifreq) + +#define IWI_LOCK(sc) mtx_lock(&(sc)->sc_mtx) +#define IWI_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) diff --git a/sys/dev/pccard/pccarddevs b/sys/dev/pccard/pccarddevs index f61b151..03520ba 100644 --- a/sys/dev/pccard/pccarddevs +++ b/sys/dev/pccard/pccarddevs @@ -154,6 +154,7 @@ vendor ELSA 0xd601 Elsa vendor NEWMEDIA2 0x10cd NewMedia vendor PLANEX 0x14ea PLANEX vendor ACTIONTEC 0x1668 ACTIONTEC +vendor RALINK 0x1814 Ralink Technology /* * The following vendor IDs are not, as far as I can tell, actually @@ -455,6 +456,9 @@ product RATOC REX_R280_9530 0x0001 RATOC REX-R280/REX-9530 product RACORE ETHERNET 0x2216 Racore PC Card Ethernet product RACORE FASTENET 0x2328 Racore PC Card Fast Ethernet +/* Ralink Technology products */ +product RALINK RT2560 0x0201 RT2500 wireless adapter + /* Raylink/WebGear */ product RAYTHEON WLAN 0x0000 WLAN Adapter diff --git a/sys/dev/ral/if_ral.c b/sys/dev/ral/if_ral.c new file mode 100644 index 0000000..c17d86a --- /dev/null +++ b/sys/dev/ral/if_ral.c @@ -0,0 +1,2781 @@ +/* $FreeBSD$ */ + +/*- + * Copyright (c) 2005 + * Damien Bergamini <damien.bergamini@free.fr> + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +/*- + * Ralink Technology RT2500 chipset driver + * http://www.ralinktech.com/ + */ + +#include <sys/param.h> +#include <sys/sysctl.h> +#include <sys/sockio.h> +#include <sys/mbuf.h> +#include <sys/kernel.h> +#include <sys/socket.h> +#include <sys/systm.h> +#include <sys/malloc.h> +#include <sys/module.h> +#include <sys/bus.h> +#include <sys/endian.h> + +#include <machine/bus.h> +#include <machine/resource.h> +#include <machine/clock.h> +#include <sys/rman.h> + +#include <net/bpf.h> +#include <net/if.h> +#include <net/if_arp.h> +#include <net/ethernet.h> +#include <net/if_dl.h> +#include <net/if_media.h> +#include <net/if_types.h> + +#include <net80211/ieee80211_var.h> +#include <net80211/ieee80211_radiotap.h> + +#include <netinet/in.h> +#include <netinet/in_systm.h> +#include <netinet/in_var.h> +#include <netinet/ip.h> +#include <netinet/if_ether.h> + +#include <dev/ral/if_ralrate.h> +#include <dev/ral/if_ralreg.h> +#include <dev/ral/if_ralvar.h> + +#ifdef RAL_DEBUG +#define DPRINTF(x) do { if (ral_debug > 0) printf x; } while (0) +#define DPRINTFN(n, x) do { if (ral_debug >= (n)) printf x; } while (0) +int ral_debug = 0; +SYSCTL_INT(_debug, OID_AUTO, ral, CTLFLAG_RW, &ral_debug, 0, "ral debug level"); +#else +#define DPRINTF(x) +#define DPRINTFN(n, x) +#endif + +MODULE_DEPEND(ral, wlan, 1, 1, 1); + +static void ral_dma_map_addr(void *, bus_dma_segment_t *, int, int); +static int ral_alloc_tx_ring(struct ral_softc *, + struct ral_tx_ring *, int); +static void ral_reset_tx_ring(struct ral_softc *, + struct ral_tx_ring *); +static void ral_free_tx_ring(struct ral_softc *, + struct ral_tx_ring *); +static int ral_alloc_rx_ring(struct ral_softc *, + struct ral_rx_ring *, int); +static void ral_reset_rx_ring(struct ral_softc *, + struct ral_rx_ring *); +static void ral_free_rx_ring(struct ral_softc *, + struct ral_rx_ring *); +static struct ieee80211_node *ral_node_alloc( + struct ieee80211_node_table *); +static int ral_media_change(struct ifnet *); +static void ral_next_scan(void *); +static void ral_iter_func(void *, struct ieee80211_node *); +static void ral_update_rssadapt(void *); +static int ral_newstate(struct ieee80211com *, + enum ieee80211_state, int); +static uint16_t ral_eeprom_read(struct ral_softc *, uint8_t); +static void ral_encryption_intr(struct ral_softc *); +static void ral_tx_intr(struct ral_softc *); +static void ral_prio_intr(struct ral_softc *); +static void ral_decryption_intr(struct ral_softc *); +static void ral_rx_intr(struct ral_softc *); +static void ral_beacon_expire(struct ral_softc *); +static void ral_wakeup_expire(struct ral_softc *); +static void ral_intr(void *); +static int ral_ack_rate(int); +static uint16_t ral_txtime(int, int, uint32_t); +static uint8_t ral_plcp_signal(int); +static void ral_setup_tx_desc(struct ral_softc *, + struct ral_tx_desc *, uint32_t, int, int, int, + bus_addr_t); +static int ral_tx_bcn(struct ral_softc *, struct mbuf *, + struct ieee80211_node *); +static int ral_tx_mgt(struct ral_softc *, struct mbuf *, + struct ieee80211_node *); +static struct mbuf *ral_get_rts(struct ral_softc *, + struct ieee80211_frame *, uint16_t); +static int ral_tx_data(struct ral_softc *, struct mbuf *, + struct ieee80211_node *); +static void ral_start(struct ifnet *); +static void ral_watchdog(struct ifnet *); +static int ral_reset(struct ifnet *); +static int ral_ioctl(struct ifnet *, u_long, caddr_t); +static void ral_bbp_write(struct ral_softc *, uint8_t, uint8_t); +static uint8_t ral_bbp_read(struct ral_softc *, uint8_t); +static void ral_rf_write(struct ral_softc *, uint8_t, uint32_t); +static void ral_set_chan(struct ral_softc *, + struct ieee80211_channel *); +#if 0 +static void ral_disable_rf_tune(struct ral_softc *); +#endif +static void ral_enable_tsf_sync(struct ral_softc *); +static void ral_update_plcp(struct ral_softc *); +static void ral_update_slot(struct ifnet *); +static void ral_update_led(struct ral_softc *, int, int); +static void ral_set_bssid(struct ral_softc *, uint8_t *); +static void ral_set_macaddr(struct ral_softc *, uint8_t *); +static void ral_get_macaddr(struct ral_softc *, uint8_t *); +static void ral_update_promisc(struct ral_softc *); +static const char *ral_get_rf(int); +static void ral_read_eeprom(struct ral_softc *); +static int ral_bbp_init(struct ral_softc *); +static void ral_set_txantenna(struct ral_softc *, int); +static void ral_set_rxantenna(struct ral_softc *, int); +static void ral_init(void *); + +devclass_t ral_devclass; + +/* + * Supported rates for 802.11a/b/g modes (in 500Kbps unit). + */ +static const struct ieee80211_rateset ral_rateset_11a = + { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; + +static const struct ieee80211_rateset ral_rateset_11b = + { 4, { 2, 4, 11, 22 } }; + +static const struct ieee80211_rateset ral_rateset_11g = + { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; + +/* + * Default values for MAC registers; values taken from the reference driver. + */ +static const struct { + uint32_t reg; + uint32_t val; +} ral_def_mac[] = { + { RAL_PSCSR0, 0x00020002 }, + { RAL_PSCSR1, 0x00000002 }, + { RAL_PSCSR2, 0x00020002 }, + { RAL_PSCSR3, 0x00000002 }, + { RAL_TIMECSR, 0x00003f21 }, + { RAL_CSR9, 0x00000780 }, + { RAL_CSR11, 0x07041483 }, + { RAL_CNT3, 0x00000000 }, + { RAL_TXCSR1, 0x07614562 }, + { RAL_ARSP_PLCP_0, 0x8c8d8b8a }, + { RAL_ACKPCTCSR, 0x7038140a }, + { RAL_ARTCSR1, 0x1d21252d }, + { RAL_ARTCSR2, 0x1919191d }, + { RAL_RXCSR0, 0xffffffff }, + { RAL_RXCSR3, 0xb3aab3af }, + { RAL_PCICSR, 0x000003b8 }, + { RAL_PWRCSR0, 0x3f3b3100 }, + { RAL_GPIOCSR, 0x0000ff00 }, + { RAL_TESTCSR, 0x000000f0 }, + { RAL_PWRCSR1, 0x000001ff }, + { RAL_MACCSR0, 0x00213223 }, + { RAL_MACCSR1, 0x00235518 }, + { RAL_RLPWCSR, 0x00000040 }, + { RAL_RALINKCSR, 0x9a009a11 }, + { RAL_CSR7, 0xffffffff }, + { RAL_BBPCSR1, 0x82188200 }, + { RAL_TXACKCSR0, 0x00000020 }, + { RAL_SECCSR3, 0x0000e78f } +}; + +/* + * Default values for BBP registers; values taken from the reference driver. + */ +static const struct { + uint8_t reg; + uint8_t val; +} ral_def_bbp[] = { + { 3, 0x02 }, + { 4, 0x19 }, + { 14, 0x1c }, + { 15, 0x30 }, + { 16, 0xac }, + { 17, 0x48 }, + { 18, 0x18 }, + { 19, 0xff }, + { 20, 0x1e }, + { 21, 0x08 }, + { 22, 0x08 }, + { 23, 0x08 }, + { 24, 0x80 }, + { 25, 0x50 }, + { 26, 0x08 }, + { 27, 0x23 }, + { 30, 0x10 }, + { 31, 0x2b }, + { 32, 0xb9 }, + { 34, 0x12 }, + { 35, 0x50 }, + { 39, 0xc4 }, + { 40, 0x02 }, + { 41, 0x60 }, + { 53, 0x10 }, + { 54, 0x18 }, + { 56, 0x08 }, + { 57, 0x10 }, + { 58, 0x08 }, + { 61, 0x60 }, + { 62, 0x10 }, + { 75, 0xff } +}; + +/* + * Default values for RF register R2 indexed by channel numbers; values taken + * from the reference driver. + */ +static const uint32_t ral_rf2522_r2[] = { + 0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814, + 0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e +}; + +static const uint32_t ral_rf2523_r2[] = { + 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, + 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 +}; + +static const uint32_t ral_rf2524_r2[] = { + 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, + 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 +}; + +static const uint32_t ral_rf2525_r2[] = { + 0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d, + 0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346 +}; + +static const uint32_t ral_rf2525_hi_r2[] = { + 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345, + 0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e +}; + +static const uint32_t ral_rf2525e_r2[] = { + 0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463, + 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b +}; + +static const uint32_t ral_rf2526_hi_r2[] = { + 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d, + 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241 +}; + +static const uint32_t ral_rf2526_r2[] = { + 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229, + 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d +}; + +/* + * For dual-band RF, RF registers R1 and R4 also depend on channel number; + * values taken from the reference driver. + */ +static const struct { + uint8_t chan; + uint32_t r1; + uint32_t r2; + uint32_t r4; +} ral_rf5222[] = { + /* channels in the 2.4GHz band */ + { 1, 0x08808, 0x0044d, 0x00282 }, + { 2, 0x08808, 0x0044e, 0x00282 }, + { 3, 0x08808, 0x0044f, 0x00282 }, + { 4, 0x08808, 0x00460, 0x00282 }, + { 5, 0x08808, 0x00461, 0x00282 }, + { 6, 0x08808, 0x00462, 0x00282 }, + { 7, 0x08808, 0x00463, 0x00282 }, + { 8, 0x08808, 0x00464, 0x00282 }, + { 9, 0x08808, 0x00465, 0x00282 }, + { 10, 0x08808, 0x00466, 0x00282 }, + { 11, 0x08808, 0x00467, 0x00282 }, + { 12, 0x08808, 0x00468, 0x00282 }, + { 13, 0x08808, 0x00469, 0x00282 }, + { 14, 0x08808, 0x0046b, 0x00286 }, + + /* channels in the 5.2GHz band */ + { 36, 0x08804, 0x06225, 0x00287 }, + { 40, 0x08804, 0x06226, 0x00287 }, + { 44, 0x08804, 0x06227, 0x00287 }, + { 48, 0x08804, 0x06228, 0x00287 }, + { 52, 0x08804, 0x06229, 0x00287 }, + { 56, 0x08804, 0x0622a, 0x00287 }, + { 60, 0x08804, 0x0622b, 0x00287 }, + { 64, 0x08804, 0x0622c, 0x00287 }, + + { 100, 0x08804, 0x02200, 0x00283 }, + { 104, 0x08804, 0x02201, 0x00283 }, + { 108, 0x08804, 0x02202, 0x00283 }, + { 112, 0x08804, 0x02203, 0x00283 }, + { 116, 0x08804, 0x02204, 0x00283 }, + { 120, 0x08804, 0x02205, 0x00283 }, + { 124, 0x08804, 0x02206, 0x00283 }, + { 128, 0x08804, 0x02207, 0x00283 }, + { 132, 0x08804, 0x02208, 0x00283 }, + { 136, 0x08804, 0x02209, 0x00283 }, + { 140, 0x08804, 0x0220a, 0x00283 }, + + { 149, 0x08808, 0x02429, 0x00281 }, + { 153, 0x08808, 0x0242b, 0x00281 }, + { 157, 0x08808, 0x0242d, 0x00281 }, + { 161, 0x08808, 0x0242f, 0x00281 } +}; + +int +ral_attach(device_t dev) +{ + struct ral_softc *sc = device_get_softc(dev); + struct ifnet *ifp = &sc->sc_arp.ac_if; + struct ieee80211com *ic = &sc->sc_ic; + int error, i; + + sc->sc_dev = dev; + + mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, + MTX_DEF | MTX_RECURSE); + + callout_init(&sc->scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0); + callout_init(&sc->rssadapt_ch, CALLOUT_MPSAFE); + + /* retrieve RT2560 rev. no */ + sc->asic_rev = RAL_READ(sc, RAL_CSR0); + + /* retrieve MAC address */ + ral_get_macaddr(sc, ic->ic_myaddr); + + /* retrieve RF rev. no and various other things from EEPROM */ + ral_read_eeprom(sc); + + device_printf(dev, "MAC/BBP RT2560 (rev 0x%02x), RF %s\n", + sc->asic_rev, ral_get_rf(sc->rf_rev)); + + /* + * Allocate Tx and Rx rings. + */ + if (ral_alloc_tx_ring(sc, &sc->txq, RAL_TX_RING_COUNT) != 0) { + device_printf(sc->sc_dev, "could not allocate Tx ring\n"); + goto fail1; + } + + if (ral_alloc_tx_ring(sc, &sc->atimq, RAL_ATIM_RING_COUNT) != 0) { + device_printf(sc->sc_dev, "could not allocate ATIM ring\n"); + goto fail2; + } + + if (ral_alloc_tx_ring(sc, &sc->prioq, RAL_PRIO_RING_COUNT) != 0) { + device_printf(sc->sc_dev, "could not allocate Prio ring\n"); + goto fail3; + } + + if (ral_alloc_tx_ring(sc, &sc->bcnq, RAL_BEACON_RING_COUNT) != 0) { + device_printf(sc->sc_dev, "could not allocate Beacon ring\n"); + goto fail4; + } + + if (ral_alloc_rx_ring(sc, &sc->rxq, RAL_RX_RING_COUNT) != 0) { + device_printf(sc->sc_dev, "could not allocate Rx ring\n"); + goto fail5; + } + + ifp->if_softc = sc; + if_initname(ifp, device_get_name(dev), device_get_unit(dev)); + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; + ifp->if_init = ral_init; + ifp->if_ioctl = ral_ioctl; + ifp->if_start = ral_start; + ifp->if_watchdog = ral_watchdog; + IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); + ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; + IFQ_SET_READY(&ifp->if_snd); + + ic->ic_ifp = ifp; + ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ + ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ + ic->ic_state = IEEE80211_S_INIT; + + /* set device capabilities */ + ic->ic_caps = IEEE80211_C_MONITOR | IEEE80211_C_IBSS | + IEEE80211_C_HOSTAP | IEEE80211_C_SHPREAMBLE | IEEE80211_C_SHSLOT | + IEEE80211_C_PMGT | IEEE80211_C_TXPMGT | IEEE80211_C_WPA; + + if (sc->rf_rev == RAL_RF_5222) { + /* set supported .11a rates */ + ic->ic_sup_rates[IEEE80211_MODE_11A] = ral_rateset_11a; + + /* set supported .11a channels */ + for (i = 36; i <= 64; i += 4) { + ic->ic_channels[i].ic_freq = + ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); + ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; + } + for (i = 100; i <= 140; i += 4) { + ic->ic_channels[i].ic_freq = + ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); + ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; + } + for (i = 149; i <= 161; i += 4) { + ic->ic_channels[i].ic_freq = + ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); + ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; + } + } + + /* set supported .11b and .11g rates */ + ic->ic_sup_rates[IEEE80211_MODE_11B] = ral_rateset_11b; + ic->ic_sup_rates[IEEE80211_MODE_11G] = ral_rateset_11g; + + /* set supported .11b and .11g channels (1 through 14) */ + for (i = 1; i <= 14; i++) { + ic->ic_channels[i].ic_freq = + ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); + ic->ic_channels[i].ic_flags = + IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | + IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; + } + + ieee80211_ifattach(ic); + ic->ic_node_alloc = ral_node_alloc; + ic->ic_updateslot = ral_update_slot; + ic->ic_reset = ral_reset; + + /* override state transition machine */ + sc->sc_newstate = ic->ic_newstate; + ic->ic_newstate = ral_newstate; + ieee80211_media_init(ic, ral_media_change, ieee80211_media_status); + + bpfattach2(ifp, DLT_IEEE802_11_RADIO, + sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); + + sc->sc_rxtap_len = sizeof sc->sc_rxtapu; + sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); + sc->sc_rxtap.wr_ihdr.it_present = htole32(RAL_RX_RADIOTAP_PRESENT); + + sc->sc_txtap_len = sizeof sc->sc_txtapu; + sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); + sc->sc_txtap.wt_ihdr.it_present = htole32(RAL_TX_RADIOTAP_PRESENT); + + /* + * Add a few sysctl knobs. + */ + sc->dwelltime = 200; + + SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, + "txantenna", CTLFLAG_RW, &sc->tx_ant, 0, "tx antenna (0=auto)"); + + SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, + "rxantenna", CTLFLAG_RW, &sc->rx_ant, 0, "rx antenna (0=auto)"); + + SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "dwell", + CTLFLAG_RW, &sc->dwelltime, 0, + "channel dwell time (ms) for AP/station scanning"); + + /* + * Hook our interrupt after all initialization is complete. + */ + error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, + ral_intr, sc, &sc->sc_ih); + if (error != 0) { + device_printf(dev, "could not set up interrupt\n"); + goto fail6; + } + + if (bootverbose) + ieee80211_announce(ic); + + return 0; + +fail6: bpfdetach(ifp); + ieee80211_ifdetach(ic); + + ral_free_rx_ring(sc, &sc->rxq); +fail5: ral_free_tx_ring(sc, &sc->bcnq); +fail4: ral_free_tx_ring(sc, &sc->prioq); +fail3: ral_free_tx_ring(sc, &sc->atimq); +fail2: ral_free_tx_ring(sc, &sc->txq); +fail1: mtx_destroy(&sc->sc_mtx); + + return ENXIO; +} + +int +ral_detach(device_t dev) +{ + struct ral_softc *sc = device_get_softc(dev); + struct ieee80211com *ic = &sc->sc_ic; + struct ifnet *ifp = ic->ic_ifp; + + callout_stop(&sc->scan_ch); + callout_stop(&sc->rssadapt_ch); + + bpfdetach(ifp); + ieee80211_ifdetach(ic); + + ral_free_tx_ring(sc, &sc->txq); + ral_free_tx_ring(sc, &sc->atimq); + ral_free_tx_ring(sc, &sc->prioq); + ral_free_tx_ring(sc, &sc->bcnq); + ral_free_rx_ring(sc, &sc->rxq); + + bus_teardown_intr(dev, sc->irq, sc->sc_ih); + ral_free(dev); + + mtx_destroy(&sc->sc_mtx); + + return 0; +} + +void +ral_shutdown(device_t dev) +{ + struct ral_softc *sc = device_get_softc(dev); + + ral_stop(sc); +} + +int +ral_alloc(device_t dev, int rid) +{ + struct ral_softc *sc = device_get_softc(dev); + + sc->mem_rid = rid; + sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, + RF_ACTIVE); + if (sc->mem == NULL) { + device_printf(dev, "could not allocate memory resource\n"); + return ENXIO; + } + + sc->sc_st = rman_get_bustag(sc->mem); + sc->sc_sh = rman_get_bushandle(sc->mem); + + sc->irq_rid = 0; + sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid, + RF_ACTIVE | RF_SHAREABLE); + if (sc->irq == NULL) { + device_printf(dev, "could not allocate interrupt resource\n"); + ral_free(dev); + return ENXIO; + } + + return 0; +} + +void +ral_free(device_t dev) +{ + struct ral_softc *sc = device_get_softc(dev); + + if (sc->irq != NULL) { + bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq); + sc->irq = NULL; + } + + if (sc->mem != NULL) { + bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem); + sc->mem = NULL; + } +} + +static void +ral_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) +{ + if (error != 0) + return; + + KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); + + *(bus_addr_t *)arg = segs[0].ds_addr; +} + +static int +ral_alloc_tx_ring(struct ral_softc *sc, struct ral_tx_ring *ring, int count) +{ + int i, error; + + ring->count = count; + ring->queued = 0; + ring->cur = ring->next = 0; + ring->cur_encrypt = ring->next_encrypt = 0; + + error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, + BUS_SPACE_MAXADDR, NULL, NULL, count * RAL_TX_DESC_SIZE, 1, + count * RAL_TX_DESC_SIZE, 0, NULL, NULL, &ring->desc_dmat); + if (error != 0) { + device_printf(sc->sc_dev, "could not create desc DMA tag\n"); + goto fail; + } + + error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, + BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); + if (error != 0) { + device_printf(sc->sc_dev, "could not allocate DMA memory\n"); + goto fail; + } + + error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, + count * RAL_TX_DESC_SIZE, ral_dma_map_addr, &ring->physaddr, 0); + if (error != 0) { + device_printf(sc->sc_dev, "could not load desc DMA map\n"); + goto fail; + } + + ring->data = malloc(count * sizeof (struct ral_tx_data), M_DEVBUF, + M_NOWAIT | M_ZERO); + if (ring->data == NULL) { + device_printf(sc->sc_dev, "could not allocate soft data\n"); + error = ENOMEM; + goto fail; + } + + error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, + BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, RAL_MAX_SCATTER, MCLBYTES, + 0, NULL, NULL, &ring->data_dmat); + if (error != 0) { + device_printf(sc->sc_dev, "could not create data DMA tag\n"); + goto fail; + } + + for (i = 0; i < count; i++) { + error = bus_dmamap_create(ring->data_dmat, 0, + &ring->data[i].map); + if (error != 0) { + device_printf(sc->sc_dev, "could not create DMA map\n"); + goto fail; + } + } + + return 0; + +fail: ral_free_tx_ring(sc, ring); + return error; +} + +static void +ral_reset_tx_ring(struct ral_softc *sc, struct ral_tx_ring *ring) +{ + struct ral_tx_desc *desc; + struct ral_tx_data *data; + int i; + + for (i = 0; i < ring->count; i++) { + desc = &ring->desc[i]; + data = &ring->data[i]; + + if (data->m != NULL) { + bus_dmamap_sync(ring->data_dmat, data->map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(ring->data_dmat, data->map); + m_freem(data->m); + data->m = NULL; + } + + if (data->ni != NULL) { + ieee80211_free_node(data->ni); + data->ni = NULL; + } + + desc->flags = 0; + } + + bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); + + ring->queued = 0; + ring->cur = ring->next = 0; + ring->cur_encrypt = ring->next_encrypt = 0; +} + +static void +ral_free_tx_ring(struct ral_softc *sc, struct ral_tx_ring *ring) +{ + struct ral_tx_data *data; + int i; + + if (ring->desc != NULL) { + bus_dmamap_sync(ring->desc_dmat, ring->desc_map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(ring->desc_dmat, ring->desc_map); + bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); + } + + if (ring->desc_dmat != NULL) + bus_dma_tag_destroy(ring->desc_dmat); + + if (ring->data != NULL) { + for (i = 0; i < ring->count; i++) { + data = &ring->data[i]; + + if (data->m != NULL) { + bus_dmamap_sync(ring->data_dmat, data->map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(ring->data_dmat, data->map); + m_freem(data->m); + } + + if (data->ni != NULL) + ieee80211_free_node(data->ni); + + if (data->map != NULL) + bus_dmamap_destroy(ring->data_dmat, data->map); + } + + free(ring->data, M_DEVBUF); + } + + if (ring->data_dmat != NULL) + bus_dma_tag_destroy(ring->data_dmat); +} + +static int +ral_alloc_rx_ring(struct ral_softc *sc, struct ral_rx_ring *ring, int count) +{ + struct ral_rx_desc *desc; + struct ral_rx_data *data; + bus_addr_t physaddr; + int i, error; + + ring->count = count; + ring->cur = ring->next = 0; + ring->cur_decrypt = 0; + + error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT, + BUS_SPACE_MAXADDR, NULL, NULL, count * RAL_RX_DESC_SIZE, 1, + count * RAL_RX_DESC_SIZE, 0, NULL, NULL, &ring->desc_dmat); + if (error != 0) { + device_printf(sc->sc_dev, "could not create desc DMA tag\n"); + goto fail; + } + + error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, + BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); + if (error != 0) { + device_printf(sc->sc_dev, "could not allocate DMA memory\n"); + goto fail; + } + + error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, + count * RAL_RX_DESC_SIZE, ral_dma_map_addr, &ring->physaddr, 0); + if (error != 0) { + device_printf(sc->sc_dev, "could not load desc DMA map\n"); + goto fail; + } + + ring->data = malloc(count * sizeof (struct ral_rx_data), M_DEVBUF, + M_NOWAIT | M_ZERO); + if (ring->data == NULL) { + device_printf(sc->sc_dev, "could not allocate soft data\n"); + error = ENOMEM; + goto fail; + } + + /* + * Pre-allocate Rx buffers and populate Rx ring. + */ + error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, + BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, NULL, + NULL, &ring->data_dmat); + if (error != 0) { + device_printf(sc->sc_dev, "could not create data DMA tag\n"); + goto fail; + } + + for (i = 0; i < count; i++) { + desc = &sc->rxq.desc[i]; + data = &sc->rxq.data[i]; + + error = bus_dmamap_create(ring->data_dmat, 0, &data->map); + if (error != 0) { + device_printf(sc->sc_dev, "could not create DMA map\n"); + goto fail; + } + + data->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + if (data->m == NULL) { + device_printf(sc->sc_dev, + "could not allocate rx mbuf\n"); + error = ENOMEM; + goto fail; + } + + error = bus_dmamap_load(ring->data_dmat, data->map, + mtod(data->m, void *), MCLBYTES, ral_dma_map_addr, + &physaddr, 0); + if (error != 0) { + device_printf(sc->sc_dev, + "could not load rx buf DMA map"); + goto fail; + } + + desc->flags = htole32(RAL_RX_BUSY); + desc->physaddr = htole32(physaddr); + } + + bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); + + return 0; + +fail: ral_free_rx_ring(sc, ring); + return error; +} + +static void +ral_reset_rx_ring(struct ral_softc *sc, struct ral_rx_ring *ring) +{ + int i; + + for (i = 0; i < ring->count; i++) { + ring->desc[i].flags = htole32(RAL_RX_BUSY); + ring->data[i].drop = 0; + } + + bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); + + ring->cur = ring->next = 0; + ring->cur_decrypt = 0; +} + +static void +ral_free_rx_ring(struct ral_softc *sc, struct ral_rx_ring *ring) +{ + struct ral_rx_data *data; + int i; + + if (ring->desc != NULL) { + bus_dmamap_sync(ring->desc_dmat, ring->desc_map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(ring->desc_dmat, ring->desc_map); + bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); + } + + if (ring->desc_dmat != NULL) + bus_dma_tag_destroy(ring->desc_dmat); + + if (ring->data != NULL) { + for (i = 0; i < ring->count; i++) { + data = &ring->data[i]; + + if (data->m != NULL) { + bus_dmamap_sync(ring->data_dmat, data->map, + BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(ring->data_dmat, data->map); + m_freem(data->m); + } + + if (data->map != NULL) + bus_dmamap_destroy(ring->data_dmat, data->map); + } + + free(ring->data, M_DEVBUF); + } + + if (ring->data_dmat != NULL) + bus_dma_tag_destroy(ring->data_dmat); +} + +static struct ieee80211_node * +ral_node_alloc(struct ieee80211_node_table *nt) +{ + struct ral_node *rn; + + rn = malloc(sizeof (struct ral_node), M_80211_NODE, M_NOWAIT | M_ZERO); + + return (rn != NULL) ? &rn->ni : NULL; +} + +static int +ral_media_change(struct ifnet *ifp) +{ + int error; + + error = ieee80211_media_change(ifp); + if (error != ENETRESET) + return error; + + if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) + ral_init(ifp); + + return 0; +} + +/* + * This function is called periodically (every 200ms) during scanning to + * switch from one channel to another. + */ +static void +ral_next_scan(void *arg) +{ + struct ral_softc *sc = arg; + struct ieee80211com *ic = &sc->sc_ic; + + if (ic->ic_state == IEEE80211_S_SCAN) + ieee80211_next_scan(ic); +} + +/* + * This function is called for each node present in the node station table. + */ +static void +ral_iter_func(void *arg, struct ieee80211_node *ni) +{ + struct ral_node *rn = (struct ral_node *)ni; + + ral_rssadapt_updatestats(&rn->rssadapt); +} + +/* + * This function is called periodically (every 100ms) in RUN state to update + * the rate adaptation statistics. + */ +static void +ral_update_rssadapt(void *arg) +{ + struct ral_softc *sc = arg; + struct ieee80211com *ic = &sc->sc_ic; + + RAL_LOCK(sc); + + ieee80211_iterate_nodes(&ic->ic_sta, ral_iter_func, arg); + callout_reset(&sc->rssadapt_ch, hz / 10, ral_update_rssadapt, sc); + + RAL_UNLOCK(sc); +} + +static int +ral_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) +{ + struct ral_softc *sc = ic->ic_ifp->if_softc; + struct mbuf *m; + enum ieee80211_state ostate; + int error = 0; + + ostate = ic->ic_state; + callout_stop(&sc->scan_ch); + + switch (nstate) { + case IEEE80211_S_INIT: + callout_stop(&sc->rssadapt_ch); + + if (ostate == IEEE80211_S_RUN) { + /* abort TSF synchronization */ + RAL_WRITE(sc, RAL_CSR14, 0); + + /* turn association led off */ + ral_update_led(sc, 0, 0); + } + break; + + case IEEE80211_S_SCAN: + ral_set_chan(sc, ic->ic_bss->ni_chan); + callout_reset(&sc->scan_ch, (sc->dwelltime * hz) / 1000, + ral_next_scan, sc); + break; + + case IEEE80211_S_AUTH: + ral_set_chan(sc, ic->ic_bss->ni_chan); + break; + + case IEEE80211_S_ASSOC: + ral_set_chan(sc, ic->ic_bss->ni_chan); + break; + + case IEEE80211_S_RUN: + ral_set_chan(sc, ic->ic_bss->ni_chan); + + if (ic->ic_opmode != IEEE80211_M_MONITOR) + ral_set_bssid(sc, ic->ic_bss->ni_bssid); + + if (ic->ic_opmode == IEEE80211_M_HOSTAP || + ic->ic_opmode == IEEE80211_M_IBSS) { + m = ieee80211_beacon_alloc(ic, ic->ic_bss, &sc->sc_bo); + if (m == NULL) { + device_printf(sc->sc_dev, + "could not allocate beacon\n"); + error = ENOBUFS; + break; + } + + ieee80211_ref_node(ic->ic_bss); + error = ral_tx_bcn(sc, m, ic->ic_bss); + if (error != 0) + break; + } + + /* turn assocation led on */ + ral_update_led(sc, 1, 0); + + if (ic->ic_opmode != IEEE80211_M_MONITOR) { + callout_reset(&sc->rssadapt_ch, hz / 10, + ral_update_rssadapt, sc); + + ral_enable_tsf_sync(sc); + } + break; + } + + return (error != 0) ? error : sc->sc_newstate(ic, nstate, arg); +} + +/* + * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or + * 93C66). + */ +static uint16_t +ral_eeprom_read(struct ral_softc *sc, uint8_t addr) +{ + uint32_t tmp; + uint16_t val; + int n; + + /* clock C once before the first command */ + RAL_EEPROM_CTL(sc, 0); + + RAL_EEPROM_CTL(sc, RAL_EEPROM_S); + RAL_EEPROM_CTL(sc, RAL_EEPROM_S | RAL_EEPROM_C); + RAL_EEPROM_CTL(sc, RAL_EEPROM_S); + + /* write start bit (1) */ + RAL_EEPROM_CTL(sc, RAL_EEPROM_S | RAL_EEPROM_D); + RAL_EEPROM_CTL(sc, RAL_EEPROM_S | RAL_EEPROM_D | RAL_EEPROM_C); + + /* write READ opcode (10) */ + RAL_EEPROM_CTL(sc, RAL_EEPROM_S | RAL_EEPROM_D); + RAL_EEPROM_CTL(sc, RAL_EEPROM_S | RAL_EEPROM_D | RAL_EEPROM_C); + RAL_EEPROM_CTL(sc, RAL_EEPROM_S); + RAL_EEPROM_CTL(sc, RAL_EEPROM_S | RAL_EEPROM_C); + + /* write address (A5-A0 or A7-A0) */ + n = (RAL_READ(sc, RAL_CSR21) & RAL_EEPROM_93C46) ? 5 : 7; + for (; n >= 0; n--) { + RAL_EEPROM_CTL(sc, RAL_EEPROM_S | + (((addr >> n) & 1) << RAL_EEPROM_SHIFT_D)); + RAL_EEPROM_CTL(sc, RAL_EEPROM_S | + (((addr >> n) & 1) << RAL_EEPROM_SHIFT_D) | RAL_EEPROM_C); + } + + RAL_EEPROM_CTL(sc, RAL_EEPROM_S); + + /* read data Q15-Q0 */ + val = 0; + for (n = 15; n >= 0; n--) { + RAL_EEPROM_CTL(sc, RAL_EEPROM_S | RAL_EEPROM_C); + tmp = RAL_READ(sc, RAL_CSR21); + val |= ((tmp & RAL_EEPROM_Q) >> RAL_EEPROM_SHIFT_Q) << n; + RAL_EEPROM_CTL(sc, RAL_EEPROM_S); + } + + RAL_EEPROM_CTL(sc, 0); + + /* clear Chip Select and clock C */ + RAL_EEPROM_CTL(sc, RAL_EEPROM_S); + RAL_EEPROM_CTL(sc, 0); + RAL_EEPROM_CTL(sc, RAL_EEPROM_C); + + return le16toh(val); +} + +/* + * Some frames were processed by the hardware cipher engine and are ready for + * transmission. + */ +static void +ral_encryption_intr(struct ral_softc *sc) +{ + struct ral_tx_desc *desc; + int hw; + + /* retrieve last descriptor index processed by cipher engine */ + hw = (RAL_READ(sc, RAL_SECCSR1) - sc->txq.physaddr) / RAL_TX_DESC_SIZE; + + bus_dmamap_sync(sc->txq.desc_dmat, sc->txq.desc_map, + BUS_DMASYNC_POSTREAD); + + for (; sc->txq.next_encrypt != hw;) { + desc = &sc->txq.desc[sc->txq.next_encrypt]; + + if ((le32toh(desc->flags) & RAL_TX_BUSY) || + (le32toh(desc->flags) & RAL_TX_CIPHER_BUSY)) + break; + + /* for TKIP, swap eiv field to fix a bug in ASIC */ + if ((le32toh(desc->flags) & RAL_TX_CIPHER_MASK) == + RAL_TX_CIPHER_TKIP) + desc->eiv = bswap32(desc->eiv); + + /* mark the frame ready for transmission */ + desc->flags |= htole32(RAL_TX_BUSY | RAL_TX_VALID); + + DPRINTFN(15, ("encryption done idx=%u\n", + sc->txq.next_encrypt)); + + sc->txq.next_encrypt = + (sc->txq.next_encrypt + 1) % RAL_TX_RING_COUNT; + } + + bus_dmamap_sync(sc->txq.desc_dmat, sc->txq.desc_map, + BUS_DMASYNC_PREWRITE); + + /* kick Tx */ + RAL_WRITE(sc, RAL_TXCSR0, RAL_KICK_TX); +} + +static void +ral_tx_intr(struct ral_softc *sc) +{ + struct ieee80211com *ic = &sc->sc_ic; + struct ifnet *ifp = ic->ic_ifp; + struct ral_tx_desc *desc; + struct ral_tx_data *data; + struct ral_node *rn; + + bus_dmamap_sync(sc->txq.desc_dmat, sc->txq.desc_map, + BUS_DMASYNC_POSTREAD); + + for (;;) { + desc = &sc->txq.desc[sc->txq.next]; + data = &sc->txq.data[sc->txq.next]; + + if ((le32toh(desc->flags) & RAL_TX_BUSY) || + (le32toh(desc->flags) & RAL_TX_CIPHER_BUSY) || + !(le32toh(desc->flags) & RAL_TX_VALID)) + break; + + rn = (struct ral_node *)data->ni; + + switch (le32toh(desc->flags) & RAL_TX_RESULT_MASK) { + case RAL_TX_SUCCESS: + DPRINTFN(10, ("data frame sent successfully\n")); + if (data->id.id_node != NULL) { + ral_rssadapt_raise_rate(ic, &rn->rssadapt, + &data->id); + } + ifp->if_opackets++; + break; + + case RAL_TX_SUCCESS_RETRY: + DPRINTFN(9, ("data frame sent after %u retries\n", + (le32toh(desc->flags) >> 5) & 0x7)); + ifp->if_opackets++; + break; + + case RAL_TX_FAIL_RETRY: + DPRINTFN(9, ("sending data frame failed (too much " + "retries)\n")); + if (data->id.id_node != NULL) { + ral_rssadapt_lower_rate(ic, data->ni, + &rn->rssadapt, &data->id); + } + ifp->if_oerrors++; + break; + + case RAL_TX_FAIL_INVALID: + case RAL_TX_FAIL_OTHER: + default: + device_printf(sc->sc_dev, "sending data frame failed " + "0x%08x\n", le32toh(desc->flags)); + ifp->if_oerrors++; + } + + bus_dmamap_sync(sc->txq.data_dmat, data->map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->txq.data_dmat, data->map); + m_freem(data->m); + data->m = NULL; + ieee80211_free_node(data->ni); + data->ni = NULL; + + /* descriptor is no longer valid */ + desc->flags &= ~htole32(RAL_TX_VALID); + + DPRINTFN(15, ("tx done idx=%u\n", sc->txq.next)); + + sc->txq.queued--; + sc->txq.next = (sc->txq.next + 1) % RAL_TX_RING_COUNT; + } + + bus_dmamap_sync(sc->txq.desc_dmat, sc->txq.desc_map, + BUS_DMASYNC_PREWRITE); + + sc->sc_tx_timer = 0; + ifp->if_flags &= ~IFF_OACTIVE; + ral_start(ifp); +} + +static void +ral_prio_intr(struct ral_softc *sc) +{ + struct ieee80211com *ic = &sc->sc_ic; + struct ifnet *ifp = ic->ic_ifp; + struct ral_tx_desc *desc; + struct ral_tx_data *data; + + bus_dmamap_sync(sc->prioq.desc_dmat, sc->prioq.desc_map, + BUS_DMASYNC_POSTREAD); + + for (;;) { + desc = &sc->prioq.desc[sc->prioq.next]; + data = &sc->prioq.data[sc->prioq.next]; + + if ((le32toh(desc->flags) & RAL_TX_BUSY) || + !(le32toh(desc->flags) & RAL_TX_VALID)) + break; + + switch (le32toh(desc->flags) & RAL_TX_RESULT_MASK) { + case RAL_TX_SUCCESS: + DPRINTFN(10, ("mgt frame sent successfully\n")); + break; + + case RAL_TX_SUCCESS_RETRY: + DPRINTFN(9, ("mgt frame sent after %u retries\n", + (le32toh(desc->flags) >> 5) & 0x7)); + break; + + case RAL_TX_FAIL_RETRY: + DPRINTFN(9, ("sending mgt frame failed (too much " + "retries)\n")); + break; + + case RAL_TX_FAIL_INVALID: + case RAL_TX_FAIL_OTHER: + default: + device_printf(sc->sc_dev, "sending mgt frame failed " + "0x%08x\n", le32toh(desc->flags)); + } + + bus_dmamap_sync(sc->prioq.data_dmat, data->map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->prioq.data_dmat, data->map); + m_freem(data->m); + data->m = NULL; + ieee80211_free_node(data->ni); + data->ni = NULL; + + /* descriptor is no longer valid */ + desc->flags &= ~htole32(RAL_TX_VALID); + + DPRINTFN(15, ("prio done idx=%u\n", sc->prioq.next)); + + sc->prioq.queued--; + sc->prioq.next = (sc->prioq.next + 1) % RAL_PRIO_RING_COUNT; + } + + bus_dmamap_sync(sc->prioq.desc_dmat, sc->prioq.desc_map, + BUS_DMASYNC_PREWRITE); + + sc->sc_tx_timer = 0; + ifp->if_flags &= ~IFF_OACTIVE; + ral_start(ifp); +} + +/* + * Some frames were processed by the hardware cipher engine and are ready for + * transmission to the IEEE802.11 layer. + */ +static void +ral_decryption_intr(struct ral_softc *sc) +{ + struct ieee80211com *ic = &sc->sc_ic; + struct ifnet *ifp = ic->ic_ifp; + struct ral_rx_desc *desc; + struct ral_rx_data *data; + bus_addr_t physaddr; + struct ieee80211_frame *wh; + struct ieee80211_node *ni; + struct ral_node *rn; + struct mbuf *m; + int hw, error; + + /* retrieve last decriptor index processed by cipher engine */ + hw = (RAL_READ(sc, RAL_SECCSR0) - sc->rxq.physaddr) / RAL_RX_DESC_SIZE; + + bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, + BUS_DMASYNC_POSTREAD); + + for (; sc->rxq.cur_decrypt != hw;) { + desc = &sc->rxq.desc[sc->rxq.cur_decrypt]; + data = &sc->rxq.data[sc->rxq.cur_decrypt]; + + if ((le32toh(desc->flags) & RAL_RX_BUSY) || + (le32toh(desc->flags) & RAL_RX_CIPHER_BUSY)) + break; + + if (data->drop) { + ifp->if_ierrors++; + goto skip; + } + + if ((le32toh(desc->flags) & RAL_RX_CIPHER_MASK) != 0 && + (le32toh(desc->flags) & RAL_RX_ICV_ERROR)) { + ifp->if_ierrors++; + goto skip; + } + + bus_dmamap_sync(sc->rxq.data_dmat, data->map, + BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->rxq.data_dmat, data->map); + + /* finalize mbuf */ + m = data->m; + m->m_pkthdr.rcvif = ifp; + m->m_pkthdr.len = m->m_len = + (le32toh(desc->flags) >> 16) & 0xfff; + + if (sc->sc_drvbpf != NULL) { + struct ral_rx_radiotap_header *tap = &sc->sc_rxtap; + uint32_t tsf_lo, tsf_hi; + + /* get timestamp (low and high 32 bits) */ + tsf_lo = RAL_READ(sc, RAL_CSR16); + tsf_hi = RAL_READ(sc, RAL_CSR17); + + tap->wr_tsf = + htole64(((uint64_t)tsf_hi << 32) | tsf_lo); + tap->wr_flags = 0; + tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); + tap->wr_chan_flags = + htole16(ic->ic_ibss_chan->ic_flags); + tap->wr_antenna = sc->rx_ant; + tap->wr_antsignal = desc->rssi; + + bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m); + } + + wh = mtod(m, struct ieee80211_frame *); + ni = ieee80211_find_rxnode(ic, + (struct ieee80211_frame_min *)wh); + + /* send the frame to the 802.11 layer */ + ieee80211_input(ic, m, ni, desc->rssi, 0); + + /* give rssi to the rate adatation algorithm */ + rn = (struct ral_node *)ni; + ral_rssadapt_input(ic, ni, &rn->rssadapt, desc->rssi); + + /* node is no longer needed */ + ieee80211_free_node(ni); + + data->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + if (data->m == NULL) { + device_printf(sc->sc_dev, + "could not allocate rx mbuf\n"); + break; + } + + error = bus_dmamap_load(sc->rxq.data_dmat, data->map, + mtod(data->m, void *), MCLBYTES, ral_dma_map_addr, + &physaddr, 0); + if (error != 0) { + device_printf(sc->sc_dev, + "could not load rx buf DMA map\n"); + m_freem(data->m); + data->m = NULL; + break; + } + + desc->physaddr = htole32(physaddr); +skip: desc->flags = htole32(RAL_RX_BUSY); + + DPRINTFN(15, ("decryption done idx=%u\n", sc->rxq.cur_decrypt)); + + sc->rxq.cur_decrypt = + (sc->rxq.cur_decrypt + 1) % RAL_RX_RING_COUNT; + } + + bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, + BUS_DMASYNC_PREWRITE); +} + +/* + * Some frames were received. Pass them to the hardware cipher engine before + * sending them to the 802.11 layer. + */ +static void +ral_rx_intr(struct ral_softc *sc) +{ + struct ral_rx_desc *desc; + struct ral_rx_data *data; + + bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, + BUS_DMASYNC_POSTREAD); + + for (;;) { + desc = &sc->rxq.desc[sc->rxq.cur]; + data = &sc->rxq.data[sc->rxq.cur]; + + if ((le32toh(desc->flags) & RAL_RX_BUSY) || + (le32toh(desc->flags) & RAL_RX_CIPHER_BUSY)) + break; + + data->drop = 0; + + if ((le32toh(desc->flags) & RAL_RX_PHY_ERROR) || + (le32toh(desc->flags) & RAL_RX_CRC_ERROR)) { + /* + * This should not happen since we did not request + * to receive those frames when we filled RXCSR0. + */ + DPRINTFN(5, ("PHY or CRC error flags 0x%08x\n", + le32toh(desc->flags))); + data->drop = 1; + } + + if (((le32toh(desc->flags) >> 16) & 0xfff) > MCLBYTES) { + DPRINTFN(5, ("bad length\n")); + data->drop = 1; + } + + /* mark the frame for decryption */ + desc->flags |= htole32(RAL_RX_CIPHER_BUSY); + + DPRINTFN(15, ("rx done idx=%u\n", sc->rxq.cur)); + + sc->rxq.cur = (sc->rxq.cur + 1) % RAL_RX_RING_COUNT; + } + + bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, + BUS_DMASYNC_PREWRITE); + + /* kick decrypt */ + RAL_WRITE(sc, RAL_SECCSR0, RAL_KICK_DECRYPT); +} + +/* + * This function is called periodically in IBSS mode when a new beacon must be + * sent out. + */ +static void +ral_beacon_expire(struct ral_softc *sc) +{ + struct ieee80211com *ic = &sc->sc_ic; + struct ral_tx_data *data; + + if (ic->ic_opmode != IEEE80211_M_IBSS && + ic->ic_opmode != IEEE80211_M_HOSTAP) + return; + + data = &sc->bcnq.data[sc->bcnq.next]; + + bus_dmamap_sync(sc->bcnq.data_dmat, data->map, BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->bcnq.data_dmat, data->map); + + ieee80211_beacon_update(ic, data->ni, &sc->sc_bo, data->m, 1); + + if (ic->ic_rawbpf != NULL) + bpf_mtap(ic->ic_rawbpf, data->m); + + ral_tx_bcn(sc, data->m, data->ni); + + DPRINTFN(15, ("beacon expired\n")); + + sc->bcnq.next = (sc->bcnq.next + 1) % RAL_BEACON_RING_COUNT; +} + +static void +ral_wakeup_expire(struct ral_softc *sc) +{ + DPRINTFN(2, ("wakeup expired\n")); +} + +static void +ral_intr(void *arg) +{ + struct ral_softc *sc = arg; + uint32_t r; + + RAL_LOCK(sc); + + /* disable interrupts */ + RAL_WRITE(sc, RAL_CSR8, 0xffffffff); + + r = RAL_READ(sc, RAL_CSR7); + RAL_WRITE(sc, RAL_CSR7, r); + + if (r & RAL_BEACON_EXPIRE) + ral_beacon_expire(sc); + + if (r & RAL_WAKEUP_EXPIRE) + ral_wakeup_expire(sc); + + if (r & RAL_ENCRYPTION_DONE) + ral_encryption_intr(sc); + + if (r & RAL_TX_DONE) + ral_tx_intr(sc); + + if (r & RAL_PRIO_DONE) + ral_prio_intr(sc); + + if (r & RAL_DECRYPTION_DONE) + ral_decryption_intr(sc); + + if (r & RAL_RX_DONE) + ral_rx_intr(sc); + + /* re-enable interrupts */ + RAL_WRITE(sc, RAL_CSR8, RAL_INTR_MASK); + + RAL_UNLOCK(sc); +} + +/* quickly determine if a given rate is CCK or OFDM */ +#define RAL_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22) + +#define RAL_ACK_SIZE 14 /* 10 + 4(FCS) */ +#define RAL_CTS_SIZE 14 /* 10 + 4(FCS) */ +#define RAL_SIFS 10 + +/* + * Return the expected ack rate for a frame transmitted at rate `rate'. + * XXX: this should depend on the destination node basic rate set. + */ +static int +ral_ack_rate(int rate) +{ + switch (rate) { + /* CCK rates */ + case 2: + return 2; + case 4: + case 11: + case 22: + return 4; + + /* OFDM rates */ + case 12: + case 18: + return 12; + case 24: + case 36: + return 24; + case 48: + case 72: + case 96: + case 108: + return 48; + } + + /* default to 1Mbps */ + return 2; +} + +/* + * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'. + * The function automatically determines the operating mode depending on the + * given rate. `flags' indicates whether short preamble is in use or not. + */ +static uint16_t +ral_txtime(int len, int rate, uint32_t flags) +{ + uint16_t txtime; + int ceil, dbps; + + if (RAL_RATE_IS_OFDM(rate)) { + /* + * OFDM TXTIME calculation. + * From IEEE Std 802.11a-1999, pp. 37. + */ + dbps = rate * 2; /* data bits per OFDM symbol */ + + ceil = (16 + 8 * len + 6) / dbps; + if ((16 + 8 * len + 6) % dbps != 0) + ceil++; + + txtime = 16 + 4 + 4 * ceil + 6; + } else { + /* + * High Rate TXTIME calculation. + * From IEEE Std 802.11b-1999, pp. 28. + */ + ceil = (8 * len * 2) / rate; + if ((8 * len * 2) % rate != 0) + ceil++; + + if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE)) + txtime = 72 + 24 + ceil; + else + txtime = 144 + 48 + ceil; + } + + return txtime; +} + +static uint8_t +ral_plcp_signal(int rate) +{ + switch (rate) { + /* CCK rates (returned values are device-dependent) */ + case 2: return 0x0; + case 4: return 0x1; + case 11: return 0x2; + case 22: return 0x3; + + /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ + case 12: return 0xb; + case 18: return 0xf; + case 24: return 0xa; + case 36: return 0xe; + case 48: return 0x9; + case 72: return 0xd; + case 96: return 0x8; + case 108: return 0xc; + + /* unsupported rates (should not get there) */ + default: return 0xff; + } +} + +static void +ral_setup_tx_desc(struct ral_softc *sc, struct ral_tx_desc *desc, + uint32_t flags, int len, int rate, int encrypt, bus_addr_t physaddr) +{ + struct ieee80211com *ic = &sc->sc_ic; + uint16_t plcp_length; + int remainder; + + desc->flags = htole32(flags); + desc->flags |= htole32(len << 16); + desc->flags |= encrypt ? htole32(RAL_TX_CIPHER_BUSY) : + htole32(RAL_TX_BUSY | RAL_TX_VALID); + if (RAL_RATE_IS_OFDM(rate)) + desc->flags |= htole32(RAL_TX_OFDM); + + desc->physaddr = htole32(physaddr); + desc->wme = htole16(RAL_LOGCWMAX(8) | RAL_LOGCWMIN(3) | RAL_AIFSN(2)); + + /* + * Fill PLCP fields. + */ + desc->plcp_service = 4; + + len += 4; /* account for FCS */ + if (RAL_RATE_IS_OFDM(rate)) { + /* + * PLCP length field (LENGTH). + * From IEEE Std 802.11a-1999, pp. 14. + */ + plcp_length = len & 0xfff; + desc->plcp_length = htole16((plcp_length >> 6) << 8 | + (plcp_length & 0x3f)); + } else { + /* + * Long PLCP LENGTH field. + * From IEEE Std 802.11b-1999, pp. 16. + */ + plcp_length = (8 * len * 2) / rate; + remainder = (8 * len * 2) % rate; + if (remainder != 0) { + if (rate == 22 && (rate - remainder) / 16 != 0) + desc->plcp_service |= RAL_PLCP_LENGEXT; + plcp_length++; + } + desc->plcp_length = htole16(plcp_length); + } + + desc->plcp_signal = ral_plcp_signal(rate); + if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) + desc->plcp_signal |= 0x08; +} + +static int +ral_tx_bcn(struct ral_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) +{ + struct ieee80211com *ic = &sc->sc_ic; + struct ral_tx_desc *desc; + struct ral_tx_data *data; + bus_dma_segment_t segs[RAL_MAX_SCATTER]; + int nsegs, rate, error; + + desc = &sc->bcnq.desc[sc->bcnq.cur]; + data = &sc->bcnq.data[sc->bcnq.cur]; + + rate = IEEE80211_IS_CHAN_5GHZ(ni->ni_chan) ? 12 : 4; + + error = bus_dmamap_load_mbuf_sg(sc->bcnq.data_dmat, data->map, m0, + segs, &nsegs, BUS_DMA_NOWAIT); + if (error != 0) { + device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", + error); + m_freem(m0); + return error; + } + + if (sc->sc_drvbpf != NULL) { + struct ral_tx_radiotap_header *tap = &sc->sc_txtap; + + tap->wt_flags = 0; + tap->wt_rate = rate; + tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); + tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); + tap->wt_antenna = sc->tx_ant; + + bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); + } + + data->m = m0; + data->ni = ni; + + ral_setup_tx_desc(sc, desc, RAL_TX_IFS_NEWBACKOFF | RAL_TX_TIMESTAMP, + m0->m_pkthdr.len, rate, 0, segs->ds_addr); + + DPRINTFN(10, ("sending beacon frame len=%u idx=%u rate=%u\n", + m0->m_pkthdr.len, sc->bcnq.cur, rate)); + + bus_dmamap_sync(sc->bcnq.data_dmat, data->map, BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(sc->bcnq.desc_dmat, sc->bcnq.desc_map, + BUS_DMASYNC_PREWRITE); + + sc->bcnq.cur = (sc->bcnq.cur + 1) % RAL_BEACON_RING_COUNT; + + return 0; +} + +static int +ral_tx_mgt(struct ral_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) +{ + struct ieee80211com *ic = &sc->sc_ic; + struct ral_tx_desc *desc; + struct ral_tx_data *data; + struct ieee80211_frame *wh; + bus_dma_segment_t segs[RAL_MAX_SCATTER]; + uint16_t dur; + uint32_t flags = 0; + int nsegs, rate, error; + + desc = &sc->prioq.desc[sc->prioq.cur]; + data = &sc->prioq.data[sc->prioq.cur]; + + rate = IEEE80211_IS_CHAN_5GHZ(ni->ni_chan) ? 12 : 4; + + error = bus_dmamap_load_mbuf_sg(sc->prioq.data_dmat, data->map, m0, + segs, &nsegs, 0); + if (error != 0) { + device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", + error); + m_freem(m0); + return error; + } + + if (sc->sc_drvbpf != NULL) { + struct ral_tx_radiotap_header *tap = &sc->sc_txtap; + + tap->wt_flags = 0; + tap->wt_rate = rate; + tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); + tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); + tap->wt_antenna = sc->tx_ant; + + bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); + } + + data->m = m0; + data->ni = ni; + + wh = mtod(m0, struct ieee80211_frame *); + + if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { + flags |= RAL_TX_ACK; + + dur = ral_txtime(RAL_ACK_SIZE, rate, ic->ic_flags) + RAL_SIFS; + *(uint16_t *)wh->i_dur = htole16(dur); + + /* tell hardware to add timestamp for probe responses */ + if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == + IEEE80211_FC0_TYPE_MGT && + (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == + IEEE80211_FC0_SUBTYPE_PROBE_RESP) + flags |= RAL_TX_TIMESTAMP; + } + + ral_setup_tx_desc(sc, desc, flags, m0->m_pkthdr.len, rate, 0, + segs->ds_addr); + + bus_dmamap_sync(sc->prioq.data_dmat, data->map, BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(sc->prioq.desc_dmat, sc->prioq.desc_map, + BUS_DMASYNC_PREWRITE); + + DPRINTFN(10, ("sending mgt frame len=%u idx=%u rate=%u\n", + m0->m_pkthdr.len, sc->prioq.cur, rate)); + + /* kick prio */ + sc->prioq.queued++; + sc->prioq.cur = (sc->prioq.cur + 1) % RAL_PRIO_RING_COUNT; + RAL_WRITE(sc, RAL_TXCSR0, RAL_KICK_PRIO); + + return 0; +} + +/* + * Build a RTS control frame. + */ +static struct mbuf * +ral_get_rts(struct ral_softc *sc, struct ieee80211_frame *wh, uint16_t dur) +{ + struct ieee80211_frame_rts *rts; + struct mbuf *m; + + MGETHDR(m, M_DONTWAIT, MT_DATA); + if (m == NULL) { + sc->sc_ic.ic_stats.is_tx_nobuf++; + device_printf(sc->sc_dev, "could not allocate RTS frame\n"); + return NULL; + } + + rts = mtod(m, struct ieee80211_frame_rts *); + + rts->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_CTL | + IEEE80211_FC0_SUBTYPE_RTS; + rts->i_fc[1] = IEEE80211_FC1_DIR_NODS; + *(uint16_t *)rts->i_dur = htole16(dur); + IEEE80211_ADDR_COPY(rts->i_ra, wh->i_addr1); + IEEE80211_ADDR_COPY(rts->i_ta, wh->i_addr2); + + m->m_pkthdr.len = m->m_len = sizeof (struct ieee80211_frame_rts); + + return m; +} + +static int +ral_tx_data(struct ral_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) +{ + struct ieee80211com *ic = &sc->sc_ic; + struct ral_tx_desc *desc; + struct ral_tx_data *data; + struct ral_node *rn; + struct ieee80211_rateset *rs; + struct ieee80211_frame *wh; + struct ieee80211_key *k; + struct mbuf *mnew; + bus_dma_segment_t segs[RAL_MAX_SCATTER]; + uint16_t dur; + uint32_t flags = 0; + int nsegs, rate, error; + + wh = mtod(m0, struct ieee80211_frame *); + + if (ic->ic_fixed_rate != -1) { + rs = &ic->ic_sup_rates[ic->ic_curmode]; + rate = rs->rs_rates[ic->ic_fixed_rate]; + } else { + rs = &ni->ni_rates; + rn = (struct ral_node *)ni; + ni->ni_txrate = ral_rssadapt_choose(&rn->rssadapt, rs, + wh, m0->m_pkthdr.len, NULL, 0); + rate = rs->rs_rates[ni->ni_txrate]; + } + rate &= IEEE80211_RATE_VAL; + + if (wh->i_fc[1] & IEEE80211_FC1_WEP) { + k = ieee80211_crypto_encap(ic, ni, m0); + if (k == NULL) + return ENOBUFS; + + /* packet header may have moved, reset our local pointer */ + wh = mtod(m0, struct ieee80211_frame *); + } + + /* + * IEEE Std 802.11-1999, pp 82: "A STA shall use an RTS/CTS exchange + * for directed frames only when the length of the MPDU is greater + * than the length threshold indicated by [...]" ic_rtsthreshold. + */ + if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && + m0->m_pkthdr.len > ic->ic_rtsthreshold) { + struct mbuf *m; + uint16_t dur; + int rtsrate, ackrate; + + rtsrate = IEEE80211_IS_CHAN_5GHZ(ni->ni_chan) ? 12 : 4; + ackrate = ral_ack_rate(rate); + + dur = ral_txtime(m0->m_pkthdr.len + 4, rate, ic->ic_flags) + + ral_txtime(RAL_CTS_SIZE, rtsrate, ic->ic_flags) + + ral_txtime(RAL_ACK_SIZE, ackrate, ic->ic_flags) + + 3 * RAL_SIFS; + + m = ral_get_rts(sc, wh, dur); + + desc = &sc->txq.desc[sc->txq.cur_encrypt]; + data = &sc->txq.data[sc->txq.cur_encrypt]; + + error = bus_dmamap_load_mbuf_sg(sc->txq.data_dmat, data->map, + m, segs, &nsegs, 0); + if (error != 0) { + device_printf(sc->sc_dev, + "could not map mbuf (error %d)\n", error); + m_freem(m); + m_freem(m0); + return error; + } + + /* avoid multiple free() of the same node for each fragment */ + ieee80211_ref_node(ni); + + data->m = m; + data->ni = ni; + + /* RTS frames are not taken into account for rssadapt */ + data->id.id_node = NULL; + + ral_setup_tx_desc(sc, desc, RAL_TX_ACK | RAL_TX_MORE_FRAG, + m->m_pkthdr.len, rtsrate, 1, segs->ds_addr); + + bus_dmamap_sync(sc->txq.data_dmat, data->map, + BUS_DMASYNC_PREWRITE); + + sc->txq.queued++; + sc->txq.cur_encrypt = + (sc->txq.cur_encrypt + 1) % RAL_TX_RING_COUNT; + + /* + * IEEE Std 802.11-1999: when an RTS/CTS exchange is used, the + * asynchronous data frame shall be transmitted after the CTS + * frame and a SIFS period. + */ + flags |= RAL_TX_LONG_RETRY | RAL_TX_IFS_SIFS; + } + + data = &sc->txq.data[sc->txq.cur_encrypt]; + desc = &sc->txq.desc[sc->txq.cur_encrypt]; + + mnew = m_defrag(m0, M_DONTWAIT); + if (mnew == NULL) { + device_printf(sc->sc_dev, "could not defragment mbuf\n"); + m_freem(m0); + return ENOMEM; + } + m0 = mnew; + + error = bus_dmamap_load_mbuf_sg(sc->txq.data_dmat, data->map, m0, + segs, &nsegs, 0); + if (error != 0) { + device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", + error); + m_freem(m0); + return error; + } + + if (sc->sc_drvbpf != NULL) { + struct ral_tx_radiotap_header *tap = &sc->sc_txtap; + + tap->wt_flags = 0; + tap->wt_rate = rate; + tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); + tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); + tap->wt_antenna = sc->tx_ant; + + bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); + } + + data->m = m0; + data->ni = ni; + + /* remember link conditions for rate adaptation algorithm */ + if (ic->ic_fixed_rate == -1) { + data->id.id_len = m0->m_pkthdr.len; + data->id.id_rateidx = ni->ni_txrate; + data->id.id_node = ni; + data->id.id_rssi = ni->ni_rssi; + } else + data->id.id_node = NULL; + + if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { + flags |= RAL_TX_ACK; + + dur = ral_txtime(RAL_ACK_SIZE, ral_ack_rate(rate), + ic->ic_flags) + RAL_SIFS; + *(uint16_t *)wh->i_dur = htole16(dur); + } + + ral_setup_tx_desc(sc, desc, flags, m0->m_pkthdr.len, rate, 1, + segs->ds_addr); + + bus_dmamap_sync(sc->txq.data_dmat, data->map, BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(sc->txq.desc_dmat, sc->txq.desc_map, + BUS_DMASYNC_PREWRITE); + + DPRINTFN(10, ("sending data frame len=%u idx=%u rate=%u\n", + m0->m_pkthdr.len, sc->txq.cur_encrypt, rate)); + + /* kick encrypt */ + sc->txq.queued++; + sc->txq.cur_encrypt = (sc->txq.cur_encrypt + 1) % RAL_TX_RING_COUNT; + RAL_WRITE(sc, RAL_SECCSR1, RAL_KICK_ENCRYPT); + + return 0; +} + +static void +ral_start(struct ifnet *ifp) +{ + struct ral_softc *sc = ifp->if_softc; + struct ieee80211com *ic = &sc->sc_ic; + struct mbuf *m0; + struct ether_header *eh; + struct ieee80211_node *ni; + + RAL_LOCK(sc); + + for (;;) { + IF_POLL(&ic->ic_mgtq, m0); + if (m0 != NULL) { + if (sc->prioq.queued >= RAL_PRIO_RING_COUNT) { + ifp->if_flags |= IFF_OACTIVE; + break; + } + IF_DEQUEUE(&ic->ic_mgtq, m0); + + ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; + m0->m_pkthdr.rcvif = NULL; + + if (ic->ic_rawbpf != NULL) + bpf_mtap(ic->ic_rawbpf, m0); + + if (ral_tx_mgt(sc, m0, ni) != 0) + break; + + } else { + if (ic->ic_state != IEEE80211_S_RUN) + break; + IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); + if (m0 == NULL) + break; + if (sc->txq.queued >= RAL_TX_RING_COUNT - 1) { + IFQ_DRV_PREPEND(&ifp->if_snd, m0); + ifp->if_flags |= IFF_OACTIVE; + break; + } + + if (m0->m_len < sizeof (struct ether_header) && + !(m0 = m_pullup(m0, sizeof (struct ether_header)))) + continue; + + eh = mtod(m0, struct ether_header *); + ni = ieee80211_find_txnode(ic, eh->ether_dhost); + if (ni == NULL) { + m_freem(m0); + continue; + } + BPF_MTAP(ifp, m0); + + m0 = ieee80211_encap(ic, m0, ni); + if (m0 == NULL) + continue; + + if (ic->ic_rawbpf != NULL) + bpf_mtap(ic->ic_rawbpf, m0); + + if (ral_tx_data(sc, m0, ni) != 0) { + ieee80211_free_node(ni); + ifp->if_oerrors++; + break; + } + } + + sc->sc_tx_timer = 5; + ifp->if_timer = 1; + } + + RAL_UNLOCK(sc); +} + +static void +ral_watchdog(struct ifnet *ifp) +{ + struct ral_softc *sc = ifp->if_softc; + struct ieee80211com *ic = &sc->sc_ic; + + RAL_LOCK(sc); + + ifp->if_timer = 0; + + if (sc->sc_tx_timer > 0) { + if (--sc->sc_tx_timer == 0) { + device_printf(sc->sc_dev, "device timeout\n"); + ral_init(sc); + ifp->if_oerrors++; + RAL_UNLOCK(sc); + return; + } + ifp->if_timer = 1; + } + + ieee80211_watchdog(ic); + + RAL_UNLOCK(sc); +} + +/* + * This function allows for fast channel switching in monitor mode (used by + * net-mgmt/kismet). In IBSS mode, we must explicitly reset the interface to + * generate a new beacon frame. + */ +static int +ral_reset(struct ifnet *ifp) +{ + struct ral_softc *sc = ifp->if_softc; + struct ieee80211com *ic = &sc->sc_ic; + + if (ic->ic_opmode != IEEE80211_M_MONITOR) + return ENETRESET; + + ral_set_chan(sc, ic->ic_ibss_chan); + + return 0; +} + +static int +ral_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) +{ + struct ral_softc *sc = ifp->if_softc; + struct ieee80211com *ic = &sc->sc_ic; + int error = 0; + + RAL_LOCK(sc); + + switch (cmd) { + case SIOCSIFFLAGS: + if (ifp->if_flags & IFF_UP) { + if (ifp->if_flags & IFF_RUNNING) + ral_update_promisc(sc); + else + ral_init(sc); + } else { + if (ifp->if_flags & IFF_RUNNING) + ral_stop(sc); + } + break; + + default: + error = ieee80211_ioctl(ic, cmd, data); + } + + if (error == ENETRESET) { + if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == + (IFF_UP | IFF_RUNNING)) + ral_init(sc); + error = 0; + } + + RAL_UNLOCK(sc); + + return error; +} + +static void +ral_bbp_write(struct ral_softc *sc, uint8_t reg, uint8_t val) +{ + uint32_t tmp; + int ntries; + + for (ntries = 0; ntries < 100; ntries++) { + if (!(RAL_READ(sc, RAL_BBPCSR) & RAL_BBP_BUSY)) + break; + DELAY(1); + } + if (ntries == 100) { + device_printf(sc->sc_dev, "could not write to BBP\n"); + return; + } + + tmp = RAL_BBP_WRITE | RAL_BBP_BUSY | reg << 8 | val; + RAL_WRITE(sc, RAL_BBPCSR, tmp); + + DPRINTFN(15, ("BBP R%u <- 0x%02x\n", reg, val)); +} + +static uint8_t +ral_bbp_read(struct ral_softc *sc, uint8_t reg) +{ + uint32_t val; + int ntries; + + val = RAL_BBP_BUSY | reg << 8; + RAL_WRITE(sc, RAL_BBPCSR, val); + + for (ntries = 0; ntries < 100; ntries++) { + val = RAL_READ(sc, RAL_BBPCSR); + if (!(val & RAL_BBP_BUSY)) + return val & 0xff; + DELAY(1); + } + + device_printf(sc->sc_dev, "could not read from BBP\n"); + return 0; +} + +static void +ral_rf_write(struct ral_softc *sc, uint8_t reg, uint32_t val) +{ + uint32_t tmp; + int ntries; + + for (ntries = 0; ntries < 100; ntries++) { + if (!(RAL_READ(sc, RAL_RFCSR) & RAL_RF_BUSY)) + break; + DELAY(1); + } + if (ntries == 100) { + device_printf(sc->sc_dev, "could not write to RF\n"); + return; + } + + tmp = RAL_RF_BUSY | RAL_RF_20BIT | (val & 0xfffff) << 2 | (reg & 0x3); + RAL_WRITE(sc, RAL_RFCSR, tmp); + + /* remember last written value in sc */ + sc->rf_regs[reg] = val; + + DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff)); +} + +static void +ral_set_chan(struct ral_softc *sc, struct ieee80211_channel *c) +{ +#define N(a) (sizeof (a) / sizeof ((a)[0])) + struct ieee80211com *ic = &sc->sc_ic; + uint8_t power, tmp; + u_int i, chan; + + chan = ieee80211_chan2ieee(ic, c); + if (chan == 0 || chan == IEEE80211_CHAN_ANY) + return; + + if (IEEE80211_IS_CHAN_2GHZ(c)) + power = min(sc->txpow[chan - 1], 31); + else + power = 31; + + DPRINTFN(2, ("setting channel to %u, txpower to %u\n", chan, power)); + + switch (sc->rf_rev) { + case RAL_RF_2522: + ral_rf_write(sc, RAL_RF1, 0x00814); + ral_rf_write(sc, RAL_RF2, ral_rf2522_r2[chan - 1]); + ral_rf_write(sc, RAL_RF3, power << 7 | 0x00040); + break; + + case RAL_RF_2523: + ral_rf_write(sc, RAL_RF1, 0x08804); + ral_rf_write(sc, RAL_RF2, ral_rf2523_r2[chan - 1]); + ral_rf_write(sc, RAL_RF3, power << 7 | 0x38044); + ral_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); + break; + + case RAL_RF_2524: + ral_rf_write(sc, RAL_RF1, 0x0c808); + ral_rf_write(sc, RAL_RF2, ral_rf2524_r2[chan - 1]); + ral_rf_write(sc, RAL_RF3, power << 7 | 0x00040); + ral_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); + break; + + case RAL_RF_2525: + ral_rf_write(sc, RAL_RF1, 0x08808); + ral_rf_write(sc, RAL_RF2, ral_rf2525_hi_r2[chan - 1]); + ral_rf_write(sc, RAL_RF3, power << 7 | 0x18044); + ral_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); + + ral_rf_write(sc, RAL_RF1, 0x08808); + ral_rf_write(sc, RAL_RF2, ral_rf2525_r2[chan - 1]); + ral_rf_write(sc, RAL_RF3, power << 7 | 0x18044); + ral_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); + break; + + case RAL_RF_2525E: + ral_rf_write(sc, RAL_RF1, 0x08808); + ral_rf_write(sc, RAL_RF2, ral_rf2525e_r2[chan - 1]); + ral_rf_write(sc, RAL_RF3, power << 7 | 0x18044); + ral_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00286 : 0x00282); + break; + + case RAL_RF_2526: + ral_rf_write(sc, RAL_RF2, ral_rf2526_hi_r2[chan - 1]); + ral_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); + ral_rf_write(sc, RAL_RF1, 0x08804); + + ral_rf_write(sc, RAL_RF2, ral_rf2526_r2[chan - 1]); + ral_rf_write(sc, RAL_RF3, power << 7 | 0x18044); + ral_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); + break; + + /* dual-band RF */ + case RAL_RF_5222: + for (i = 0; i < N(ral_rf5222); i++) + if (ral_rf5222[i].chan == chan) + break; + + if (i < N(ral_rf5222)) { + ral_rf_write(sc, RAL_RF1, ral_rf5222[i].r1); + ral_rf_write(sc, RAL_RF2, ral_rf5222[i].r2); + ral_rf_write(sc, RAL_RF3, power << 7 | 0x00040); + ral_rf_write(sc, RAL_RF4, ral_rf5222[i].r4); + } + break; + } + + if (ic->ic_state != IEEE80211_S_SCAN) { + /* set Japan filter bit for channel 14 */ + tmp = ral_bbp_read(sc, 70); + + tmp &= ~RAL_JAPAN_FILTER; + if (chan == 14) + tmp |= RAL_JAPAN_FILTER; + + ral_bbp_write(sc, 70, tmp); + + /* clear CRC errors */ + RAL_READ(sc, RAL_CNT0); + } +#undef N +} + +#if 0 +/* + * Disable RF auto-tuning. + */ +static void +ral_disable_rf_tune(struct ral_softc *sc) +{ + uint32_t tmp; + + if (sc->rf_rev != RAL_RF_2523) { + tmp = sc->rf_regs[RAL_RF1] & ~RAL_RF1_AUTOTUNE; + ral_rf_write(sc, RAL_RF1, tmp); + } + + tmp = sc->rf_regs[RAL_RF3] & ~RAL_RF3_AUTOTUNE; + ral_rf_write(sc, RAL_RF3, tmp); + + DPRINTFN(2, ("disabling RF autotune\n")); +} +#endif + +/* + * Refer to IEEE Std 802.11-1999 pp. 123 for more information on TSF + * synchronization. + */ +static void +ral_enable_tsf_sync(struct ral_softc *sc) +{ + struct ieee80211com *ic = &sc->sc_ic; + uint16_t logcwmin, preload; + uint32_t tmp; + + /* first, disable TSF synchronization */ + RAL_WRITE(sc, RAL_CSR14, 0); + + tmp = 16 * ic->ic_bss->ni_intval; + RAL_WRITE(sc, RAL_CSR12, tmp); + + RAL_WRITE(sc, RAL_CSR13, 0); + + logcwmin = 5; + preload = (ic->ic_opmode == IEEE80211_M_STA) ? 384 : 1024; + tmp = logcwmin << 16 | preload; + RAL_WRITE(sc, RAL_BCNOCSR, tmp); + + /* finally, enable TSF synchronization */ + tmp = RAL_ENABLE_TSF | RAL_ENABLE_TBCN; + if (ic->ic_opmode == IEEE80211_M_STA) + tmp |= RAL_ENABLE_TSF_SYNC(1); + else + tmp |= RAL_ENABLE_TSF_SYNC(2) | RAL_ENABLE_BEACON_GENERATOR; + RAL_WRITE(sc, RAL_CSR14, tmp); + + DPRINTF(("enabling TSF synchronization\n")); +} + +static void +ral_update_plcp(struct ral_softc *sc) +{ + struct ieee80211com *ic = &sc->sc_ic; + + /* no short preamble for 1Mbps */ + RAL_WRITE(sc, RAL_PLCP1MCSR, 0x00700400); + + if (!(ic->ic_flags & IEEE80211_F_SHPREAMBLE)) { + /* values taken from the reference driver */ + RAL_WRITE(sc, RAL_PLCP2MCSR, 0x00380401); + RAL_WRITE(sc, RAL_PLCP5p5MCSR, 0x00150402); + RAL_WRITE(sc, RAL_PLCP11MCSR, 0x000b8403); + } else { + /* same values as above or'ed 0x8 */ + RAL_WRITE(sc, RAL_PLCP2MCSR, 0x00380409); + RAL_WRITE(sc, RAL_PLCP5p5MCSR, 0x0015040a); + RAL_WRITE(sc, RAL_PLCP11MCSR, 0x000b840b); + } + + DPRINTF(("updating PLCP for %s preamble\n", + (ic->ic_flags & IEEE80211_F_SHPREAMBLE) ? "short" : "long")); +} + +/* + * This function can be called by ieee80211_set_shortslottime(). Refer to + * IEEE Std 802.11-1999 pp. 85 to know how these values are computed. + */ +static void +ral_update_slot(struct ifnet *ifp) +{ + struct ral_softc *sc = ifp->if_softc; + struct ieee80211com *ic = &sc->sc_ic; + uint8_t slottime; + uint16_t sifs, pifs, difs, eifs; + uint32_t tmp; + + slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; + + /* update the MAC slot boundaries */ + sifs = RAL_SIFS; + pifs = sifs + slottime; + difs = sifs + 2 * slottime; + eifs = sifs + ral_txtime(RAL_ACK_SIZE, + (ic->ic_curmode == IEEE80211_MODE_11A) ? 12 : 2, 0) + difs; + + tmp = RAL_READ(sc, RAL_CSR11); + tmp = (tmp & ~0x1f00) | slottime << 8; + RAL_WRITE(sc, RAL_CSR11, tmp); + + tmp = pifs << 16 | sifs; + RAL_WRITE(sc, RAL_CSR18, tmp); + + tmp = eifs << 16 | difs; + RAL_WRITE(sc, RAL_CSR19, tmp); + + DPRINTF(("setting slottime to %uus\n", slottime)); +} + +static void +ral_update_led(struct ral_softc *sc, int led1, int led2) +{ + uint32_t tmp; + + /* set ON period to 70ms and OFF period to 30ms */ + tmp = led1 << 16 | led2 << 17 | 70 << 8 | 30; + RAL_WRITE(sc, RAL_LEDCSR, tmp); +} + +static void +ral_set_bssid(struct ral_softc *sc, uint8_t *bssid) +{ + uint32_t tmp; + + tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; + RAL_WRITE(sc, RAL_CSR5, tmp); + + tmp = bssid[4] | bssid[5] << 8; + RAL_WRITE(sc, RAL_CSR6, tmp); + + DPRINTF(("setting BSSID to %6D\n", bssid, ":")); +} + +static void +ral_set_macaddr(struct ral_softc *sc, uint8_t *addr) +{ + uint32_t tmp; + + tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; + RAL_WRITE(sc, RAL_CSR3, tmp); + + tmp = addr[4] | addr[5] << 8; + RAL_WRITE(sc, RAL_CSR4, tmp); + + DPRINTF(("setting MAC address to %6D\n", addr, ":")); +} + +static void +ral_get_macaddr(struct ral_softc *sc, uint8_t *addr) +{ + uint32_t tmp; + + tmp = RAL_READ(sc, RAL_CSR3); + addr[0] = tmp & 0xff; + addr[1] = (tmp >> 8) & 0xff; + addr[2] = (tmp >> 16) & 0xff; + addr[3] = (tmp >> 24); + + tmp = RAL_READ(sc, RAL_CSR4); + addr[4] = tmp & 0xff; + addr[5] = (tmp >> 8) & 0xff; +} + +static void +ral_update_promisc(struct ral_softc *sc) +{ + struct ifnet *ifp = sc->sc_ic.ic_ifp; + uint32_t tmp; + + tmp = RAL_READ(sc, RAL_RXCSR0); + + tmp &= ~RAL_DROP_NOT_TO_ME; + if (!(ifp->if_flags & IFF_PROMISC)) + tmp |= RAL_DROP_NOT_TO_ME; + + RAL_WRITE(sc, RAL_RXCSR0, tmp); + + DPRINTF(("%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? + "entering" : "leaving")); +} + +static const char * +ral_get_rf(int rev) +{ + switch (rev) { + case RAL_RF_2522: return "RT2522"; + case RAL_RF_2523: return "RT2523"; + case RAL_RF_2524: return "RT2524"; + case RAL_RF_2525: return "RT2525"; + case RAL_RF_2525E: return "RT2525e"; + case RAL_RF_2526: return "RT2526"; + case RAL_RF_5222: return "RT5222"; + default: return "unknown"; + } +} + +static void +ral_read_eeprom(struct ral_softc *sc) +{ + uint16_t val; + int i; + + val = ral_eeprom_read(sc, RAL_EEPROM_CONFIG0); + sc->rf_rev = (val >> 11) & 0x7; + sc->hw_radio = (val >> 10) & 0x1; + sc->led_mode = (val >> 6) & 0x7; + sc->rx_ant = (val >> 4) & 0x3; + sc->tx_ant = (val >> 2) & 0x3; + sc->nb_ant = val & 0x3; + + /* read default values for BBP registers */ + for (i = 0; i < 16; i++) { + val = ral_eeprom_read(sc, RAL_EEPROM_BBP_BASE + i); + sc->bbp_prom[i].reg = val >> 8; + sc->bbp_prom[i].val = val & 0xff; + } + + /* read Tx power for all b/g channels */ + for (i = 0; i < 14 / 2; i++) { + val = ral_eeprom_read(sc, RAL_EEPROM_TXPOWER + i); + sc->txpow[i * 2] = val >> 8; + sc->txpow[i * 2 + 1] = val & 0xff; + } +} + +static int +ral_bbp_init(struct ral_softc *sc) +{ +#define N(a) (sizeof (a) / sizeof ((a)[0])) + int i, ntries; + + /* wait for BBP to be ready */ + for (ntries = 0; ntries < 100; ntries++) { + if (ral_bbp_read(sc, RAL_BBP_VERSION) != 0) + break; + DELAY(1); + } + if (ntries == 100) { + device_printf(sc->sc_dev, "timeout waiting for BBP\n"); + return EIO; + } + + /* initialize BBP registers to default values */ + for (i = 0; i < N(ral_def_bbp); i++) + ral_bbp_write(sc, ral_def_bbp[i].reg, ral_def_bbp[i].val); + +#if 0 + /* initialize BBP registers to values stored in EEPROM */ + for (i = 0; i < 16; i++) { + if (sc->bbp_prom[i].reg == 0xff) + continue; + ral_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); + } +#endif + + return 0; +#undef N +} + +static void +ral_set_txantenna(struct ral_softc *sc, int antenna) +{ + uint32_t tmp; + uint8_t tx; + + tx = ral_bbp_read(sc, RAL_BBP_TX) & ~RAL_BBP_ANTMASK; + if (antenna == 1) + tx |= RAL_BBP_ANTA; + else if (antenna == 2) + tx |= RAL_BBP_ANTB; + else + tx |= RAL_BBP_DIVERSITY; + + /* need to force I/Q flip for RF 2525e, 2526 and 5222 */ + if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526 || + sc->rf_rev == RAL_RF_5222) + tx |= RAL_BBP_FLIPIQ; + + ral_bbp_write(sc, RAL_BBP_TX, tx); + + /* update values for CCK and OFDM in BBPCSR1 */ + tmp = RAL_READ(sc, RAL_BBPCSR1) & ~0x00070007; + tmp |= (tx & 0x7) << 16 | (tx & 0x7); + RAL_WRITE(sc, RAL_BBPCSR1, tmp); +} + +static void +ral_set_rxantenna(struct ral_softc *sc, int antenna) +{ + uint8_t rx; + + rx = ral_bbp_read(sc, RAL_BBP_RX) & ~RAL_BBP_ANTMASK; + if (antenna == 1) + rx |= RAL_BBP_ANTA; + else if (antenna == 2) + rx |= RAL_BBP_ANTB; + else + rx |= RAL_BBP_DIVERSITY; + + /* need to force no I/Q flip for RF 2525e and 2526 */ + if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526) + rx &= ~RAL_BBP_FLIPIQ; + + ral_bbp_write(sc, RAL_BBP_RX, rx); +} + +static void +ral_init(void *priv) +{ +#define N(a) (sizeof (a) / sizeof ((a)[0])) + struct ral_softc *sc = priv; + struct ieee80211com *ic = &sc->sc_ic; + struct ifnet *ifp = ic->ic_ifp; + uint32_t tmp; + int i; + + ral_stop(sc); + + /* setup tx rings */ + tmp = RAL_PRIO_RING_COUNT << 24 | + RAL_ATIM_RING_COUNT << 16 | + RAL_TX_RING_COUNT << 8 | + RAL_TX_DESC_SIZE; + + /* rings _must_ be initialized in this _exact_ order! */ + RAL_WRITE(sc, RAL_TXCSR2, tmp); + RAL_WRITE(sc, RAL_TXCSR3, sc->txq.physaddr); + RAL_WRITE(sc, RAL_TXCSR5, sc->prioq.physaddr); + RAL_WRITE(sc, RAL_TXCSR4, sc->atimq.physaddr); + RAL_WRITE(sc, RAL_TXCSR6, sc->bcnq.physaddr); + + /* setup rx ring */ + tmp = RAL_RX_RING_COUNT << 8 | RAL_RX_DESC_SIZE; + + RAL_WRITE(sc, RAL_RXCSR1, tmp); + RAL_WRITE(sc, RAL_RXCSR2, sc->rxq.physaddr); + + /* initialize MAC registers to default values */ + for (i = 0; i < N(ral_def_mac); i++) + RAL_WRITE(sc, ral_def_mac[i].reg, ral_def_mac[i].val); + + IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); + ral_set_macaddr(sc, ic->ic_myaddr); + + /* set supported basic rates (1, 2, 6, 12, 24) */ + RAL_WRITE(sc, RAL_ARSP_PLCP_1, 0x153); + + ral_set_txantenna(sc, sc->tx_ant); + ral_set_rxantenna(sc, sc->rx_ant); + ral_update_slot(ifp); + ral_update_plcp(sc); + ral_update_led(sc, 0, 0); + + RAL_WRITE(sc, RAL_CSR1, RAL_RESET_ASIC); + RAL_WRITE(sc, RAL_CSR1, RAL_HOST_READY); + + if (ral_bbp_init(sc) != 0) { + ral_stop(sc); + return; + } + + /* set default BSS channel */ + ic->ic_bss->ni_chan = ic->ic_ibss_chan; + ral_set_chan(sc, ic->ic_bss->ni_chan); + + /* kick Rx */ + tmp = RAL_DROP_PHY_ERROR | RAL_DROP_CRC_ERROR; + if (ic->ic_opmode != IEEE80211_M_MONITOR) { + tmp |= RAL_DROP_CTL | RAL_DROP_VERSION_ERROR; + if (ic->ic_opmode != IEEE80211_M_HOSTAP) + tmp |= RAL_DROP_TODS; + if (!(ifp->if_flags & IFF_PROMISC)) + tmp |= RAL_DROP_NOT_TO_ME; + } + RAL_WRITE(sc, RAL_RXCSR0, tmp); + + /* clear old FCS and Rx FIFO errors */ + RAL_READ(sc, RAL_CNT0); + RAL_READ(sc, RAL_CNT4); + + /* clear any pending interrupts */ + RAL_WRITE(sc, RAL_CSR7, 0xffffffff); + + /* enable interrupts */ + RAL_WRITE(sc, RAL_CSR8, RAL_INTR_MASK); + + ifp->if_flags &= ~IFF_OACTIVE; + ifp->if_flags |= IFF_RUNNING; + + if (ic->ic_opmode == IEEE80211_M_MONITOR) + ieee80211_new_state(ic, IEEE80211_S_RUN, -1); + else + ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); +#undef N +} + +void +ral_stop(void *priv) +{ + struct ral_softc *sc = priv; + struct ieee80211com *ic = &sc->sc_ic; + struct ifnet *ifp = ic->ic_ifp; + + ieee80211_new_state(ic, IEEE80211_S_INIT, -1); + + sc->sc_tx_timer = 0; + ifp->if_timer = 0; + ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); + + /* abort Tx */ + RAL_WRITE(sc, RAL_TXCSR0, RAL_ABORT_TX); + + /* disable Rx */ + RAL_WRITE(sc, RAL_RXCSR0, RAL_DISABLE_RX); + + /* reset ASIC (imply reset BBP) */ + RAL_WRITE(sc, RAL_CSR1, RAL_RESET_ASIC); + RAL_WRITE(sc, RAL_CSR1, 0); + + /* disable interrupts */ + RAL_WRITE(sc, RAL_CSR8, 0xffffffff); + + /* reset Tx and Rx rings */ + ral_reset_tx_ring(sc, &sc->txq); + ral_reset_tx_ring(sc, &sc->atimq); + ral_reset_tx_ring(sc, &sc->prioq); + ral_reset_tx_ring(sc, &sc->bcnq); + ral_reset_rx_ring(sc, &sc->rxq); +} diff --git a/sys/dev/ral/if_ral_pccard.c b/sys/dev/ral/if_ral_pccard.c new file mode 100644 index 0000000..9a7205d --- /dev/null +++ b/sys/dev/ral/if_ral_pccard.c @@ -0,0 +1,141 @@ +/* $FreeBSD$ */ + +/*- + * Copyright (c) 2005 + * Damien Bergamini <damien.bergamini@free.fr> + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +/* + * CardBus front-end for the Ralink RT2500 driver. + */ + +#include <sys/param.h> +#include <sys/sysctl.h> +#include <sys/sockio.h> +#include <sys/mbuf.h> +#include <sys/kernel.h> +#include <sys/socket.h> +#include <sys/systm.h> +#include <sys/malloc.h> +#include <sys/module.h> +#include <sys/bus.h> +#include <sys/endian.h> + +#include <machine/bus.h> +#include <machine/resource.h> +#include <sys/rman.h> + +#include <net/if.h> +#include <net/if_arp.h> +#include <net/ethernet.h> +#include <net/if_dl.h> +#include <net/if_media.h> +#include <net/if_types.h> + +#include <net80211/ieee80211_var.h> +#include <net80211/ieee80211_radiotap.h> + +#include <dev/pccard/pccardvar.h> +#include <dev/pccard/pccard_cis.h> + +#include <dev/ral/if_ralrate.h> +#include <dev/ral/if_ralreg.h> +#include <dev/ral/if_ralvar.h> + +#include "card_if.h" +#include "pccarddevs.h" + +MODULE_DEPEND(ral, pccard, 1, 1, 1); +MODULE_DEPEND(ral, wlan, 1, 1, 1); + +static const struct pccard_product ral_pccard_products[] = { + PCMCIA_CARD(RALINK, RT2560, 0), + + { NULL } +}; + +static int ral_pccard_match(device_t); +static int ral_pccard_probe(device_t); +static int ral_pccard_attach(device_t); + +static device_method_t ral_pccard_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, pccard_compat_probe), + DEVMETHOD(device_attach, pccard_compat_attach), + DEVMETHOD(device_detach, ral_detach), + DEVMETHOD(device_shutdown, ral_shutdown), + + /* Card interface */ + DEVMETHOD(card_compat_match, ral_pccard_match), + DEVMETHOD(card_compat_probe, ral_pccard_probe), + DEVMETHOD(card_compat_attach, ral_pccard_attach), + + { 0, 0 } +}; + +static driver_t ral_pccard_driver = { + "ral", + ral_pccard_methods, + sizeof (struct ral_softc) +}; + +DRIVER_MODULE(ral, pccard, ral_pccard_driver, ral_devclass, 0, 0); + +static int +ral_pccard_match(device_t dev) +{ + const struct pccard_product *pp; + + if ((pp = pccard_product_lookup(dev, ral_pccard_products, + sizeof (struct pccard_product), NULL)) != NULL) { + if (pp->pp_name != NULL) + device_set_desc(dev, pp->pp_name); + return 0; + } + return ENXIO; +} + +static int +ral_pccard_probe(device_t dev) +{ + int error; + + error = ral_alloc(dev, 0); + if (error != 0) + return error; + + ral_free(dev); + + return 0; +} + +static int +ral_pccard_attach(device_t dev) +{ + int error; + + error = ral_alloc(dev, 0); + if (error != 0) + return error; + + error = ral_attach(dev); + if (error != 0) + ral_free(dev); + + return error; +} diff --git a/sys/dev/ral/if_ral_pci.c b/sys/dev/ral/if_ral_pci.c new file mode 100644 index 0000000..3c1b7b1 --- /dev/null +++ b/sys/dev/ral/if_ral_pci.c @@ -0,0 +1,168 @@ +/* $FreeBSD$ */ + +/*- + * Copyright (c) 2005 + * Damien Bergamini <damien.bergamini@free.fr> + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +/* + * PCI front-end for the Ralink RT2500 driver. + */ + +#include <sys/param.h> +#include <sys/sysctl.h> +#include <sys/sockio.h> +#include <sys/mbuf.h> +#include <sys/kernel.h> +#include <sys/socket.h> +#include <sys/systm.h> +#include <sys/malloc.h> +#include <sys/module.h> +#include <sys/bus.h> +#include <sys/endian.h> + +#include <machine/bus.h> +#include <machine/resource.h> +#include <machine/clock.h> +#include <sys/rman.h> + +#include <net/bpf.h> +#include <net/if.h> +#include <net/if_arp.h> +#include <net/ethernet.h> +#include <net/if_dl.h> +#include <net/if_media.h> +#include <net/if_types.h> + +#include <net80211/ieee80211_var.h> +#include <net80211/ieee80211_radiotap.h> + +#include <dev/pci/pcireg.h> +#include <dev/pci/pcivar.h> + +#include <dev/ral/if_ralrate.h> +#include <dev/ral/if_ralreg.h> +#include <dev/ral/if_ralvar.h> + +MODULE_DEPEND(ral, pci, 1, 1, 1); +MODULE_DEPEND(ral, wlan, 1, 1, 1); + +struct ral_pci_ident { + uint16_t vendor; + uint16_t device; + const char *name; +}; + +static const struct ral_pci_ident ral_pci_ids[] = { + { 0x1814, 0x0201, "Ralink Technology RT2500" }, + + { 0, 0, NULL } +}; + +static int ral_pci_probe(device_t); +static int ral_pci_attach(device_t); +static int ral_pci_suspend(device_t); +static int ral_pci_resume(device_t); + +static device_method_t ral_pci_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, ral_pci_probe), + DEVMETHOD(device_attach, ral_pci_attach), + DEVMETHOD(device_detach, ral_detach), + DEVMETHOD(device_suspend, ral_pci_suspend), + DEVMETHOD(device_resume, ral_pci_resume), + + { 0, 0 } +}; + +static driver_t ral_pci_driver = { + "ral", + ral_pci_methods, + sizeof (struct ral_softc) +}; + +DRIVER_MODULE(ral, pci, ral_pci_driver, ral_devclass, 0, 0); +DRIVER_MODULE(ral, cardbus, ral_pci_driver, ral_devclass, 0, 0); + +static int +ral_pci_probe(device_t dev) +{ + const struct ral_pci_ident *ident; + + for (ident = ral_pci_ids; ident->name != NULL; ident++) { + if (pci_get_vendor(dev) == ident->vendor && + pci_get_device(dev) == ident->device) { + device_set_desc(dev, ident->name); + return 0; + } + } + return ENXIO; +} + +/* Base Address Register */ +#define RAL_PCI_BAR0 0x10 + +static int +ral_pci_attach(device_t dev) +{ + int error; + + if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { + device_printf(dev, "chip is in D%d power mode " + "-- setting to D0\n", pci_get_powerstate(dev)); + pci_set_powerstate(dev, PCI_POWERSTATE_D0); + } + + /* enable bus-mastering */ + pci_enable_busmaster(dev); + + error = ral_alloc(dev, RAL_PCI_BAR0); + if (error != 0) + return error; + + error = ral_attach(dev); + if (error != 0) + ral_free(dev); + + return error; +} + +static int +ral_pci_suspend(device_t dev) +{ + struct ral_softc *sc = device_get_softc(dev); + + ral_stop(sc); + + return 0; +} + +static int +ral_pci_resume(device_t dev) +{ + struct ral_softc *sc = device_get_softc(dev); + struct ifnet *ifp = sc->sc_ic.ic_ifp; + + if (ifp->if_flags & IFF_UP) { + ifp->if_init(ifp->if_softc); + if (ifp->if_flags & IFF_RUNNING) + ifp->if_start(ifp); + } + + return 0; +} diff --git a/sys/dev/ral/if_ralrate.c b/sys/dev/ral/if_ralrate.c new file mode 100644 index 0000000..b8922ba --- /dev/null +++ b/sys/dev/ral/if_ralrate.c @@ -0,0 +1,192 @@ +/* $FreeBSD$ */ +/* $NetBSD: ieee80211_rssadapt.c,v 1.9 2005/02/26 22:45:09 perry Exp $ */ +/*- + * Copyright (c) 2003, 2004 David Young. All rights reserved. + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of David Young may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David + * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + */ + +#include <sys/param.h> +#include <sys/sockio.h> +#include <sys/mbuf.h> +#include <sys/kernel.h> +#include <sys/socket.h> + +#include <net/if.h> +#include <net/if_arp.h> +#include <net/ethernet.h> +#include <net/if_dl.h> +#include <net/if_media.h> +#include <net/if_types.h> + +#include <net80211/ieee80211_var.h> + +#include <dev/ral/if_ralrate.h> + +#ifdef interpolate +#undef interpolate +#endif +#define interpolate(parm, old, new) ((parm##_old * (old) + \ + (parm##_denom - parm##_old) * (new)) / \ + parm##_denom) + +static struct ral_rssadapt_expavgctl master_expavgctl = { + rc_decay_denom : 16, + rc_decay_old : 15, + rc_thresh_denom : 8, + rc_thresh_old : 4, + rc_avgrssi_denom : 8, + rc_avgrssi_old : 4 +}; + +int +ral_rssadapt_choose(struct ral_rssadapt *ra, struct ieee80211_rateset *rs, + struct ieee80211_frame *wh, u_int len, const char *dvname, int do_not_adapt) +{ + u_int16_t (*thrs)[IEEE80211_RATE_SIZE]; + int flags = 0, i, rateidx = 0, thridx, top; + + if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_CTL) + flags |= IEEE80211_RATE_BASIC; + + for (i = 0, top = RAL_RSSADAPT_BKT0; + i < RAL_RSSADAPT_BKTS; + i++, top <<= RAL_RSSADAPT_BKTPOWER) { + thridx = i; + if (len <= top) + break; + } + + thrs = &ra->ra_rate_thresh[thridx]; + + i = rs->rs_nrates; + while (--i >= 0) { + rateidx = i; + if ((rs->rs_rates[i] & flags) != flags) + continue; + if (do_not_adapt) + break; + if ((*thrs)[i] < ra->ra_avg_rssi) + break; + } + + return rateidx; +} + +void +ral_rssadapt_updatestats(struct ral_rssadapt *ra) +{ + long interval; + + ra->ra_pktrate = + (ra->ra_pktrate + 10 * (ra->ra_nfail + ra->ra_nok)) / 2; + ra->ra_nfail = ra->ra_nok = 0; + + /* a node is eligible for its rate to be raised every 1/10 to 10 + * seconds, more eligible in proportion to recent packet rates. + */ + interval = MAX(100000, 10000000 / MAX(1, 10 * ra->ra_pktrate)); + ra->ra_raise_interval.tv_sec = interval / (1000 * 1000); + ra->ra_raise_interval.tv_usec = interval % (1000 * 1000); +} + +void +ral_rssadapt_input(struct ieee80211com *ic, struct ieee80211_node *ni, + struct ral_rssadapt *ra, int rssi) +{ + ra->ra_avg_rssi = interpolate(master_expavgctl.rc_avgrssi, + ra->ra_avg_rssi, (rssi << 8)); +} + +/* + * Adapt the data rate to suit the conditions. When a transmitted + * packet is dropped after RAL_RSSADAPT_RETRY_LIMIT retransmissions, + * raise the RSS threshold for transmitting packets of similar length at + * the same data rate. + */ +void +ral_rssadapt_lower_rate(struct ieee80211com *ic, struct ieee80211_node *ni, + struct ral_rssadapt *ra, struct ral_rssdesc *id) +{ + struct ieee80211_rateset *rs = &ni->ni_rates; + u_int16_t last_thr; + u_int i, thridx, top; + + ra->ra_nfail++; + + if (id->id_rateidx >= rs->rs_nrates) + return; + + for (i = 0, top = RAL_RSSADAPT_BKT0; + i < RAL_RSSADAPT_BKTS; + i++, top <<= RAL_RSSADAPT_BKTPOWER) { + thridx = i; + if (id->id_len <= top) + break; + } + + last_thr = ra->ra_rate_thresh[thridx][id->id_rateidx]; + ra->ra_rate_thresh[thridx][id->id_rateidx] = + interpolate(master_expavgctl.rc_thresh, last_thr, + (id->id_rssi << 8)); +} + +void +ral_rssadapt_raise_rate(struct ieee80211com *ic, struct ral_rssadapt *ra, + struct ral_rssdesc *id) +{ + u_int16_t (*thrs)[IEEE80211_RATE_SIZE], newthr, oldthr; + struct ieee80211_node *ni = id->id_node; + struct ieee80211_rateset *rs = &ni->ni_rates; + int i, rate, top; + + ra->ra_nok++; + + if (!ratecheck(&ra->ra_last_raise, &ra->ra_raise_interval)) + return; + + for (i = 0, top = RAL_RSSADAPT_BKT0; + i < RAL_RSSADAPT_BKTS; + i++, top <<= RAL_RSSADAPT_BKTPOWER) { + thrs = &ra->ra_rate_thresh[i]; + if (id->id_len <= top) + break; + } + + if (id->id_rateidx + 1 < rs->rs_nrates && + (*thrs)[id->id_rateidx + 1] > (*thrs)[id->id_rateidx]) { + rate = (rs->rs_rates[id->id_rateidx + 1] & IEEE80211_RATE_VAL); + + oldthr = (*thrs)[id->id_rateidx + 1]; + if ((*thrs)[id->id_rateidx] == 0) + newthr = ra->ra_avg_rssi; + else + newthr = (*thrs)[id->id_rateidx]; + (*thrs)[id->id_rateidx + 1] = + interpolate(master_expavgctl.rc_decay, oldthr, newthr); + } +} diff --git a/sys/dev/ral/if_ralrate.h b/sys/dev/ral/if_ralrate.h new file mode 100644 index 0000000..50eee44 --- /dev/null +++ b/sys/dev/ral/if_ralrate.h @@ -0,0 +1,98 @@ +/* $FreeBSD$ */ +/* $NetBSD: ieee80211_rssadapt.h,v 1.4 2005/02/26 22:45:09 perry Exp $ */ +/*- + * Copyright (c) 2003, 2004 David Young. All rights reserved. + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * 3. The name of David Young may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David + * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + */ + +/* Data-rate adaptation loosely based on "Link Adaptation Strategy + * for IEEE 802.11 WLAN via Received Signal Strength Measurement" + * by Javier del Prado Pavon and Sunghyun Choi. + */ + +/* Buckets for frames 0-128 bytes long, 129-1024, 1025-maximum. */ +#define RAL_RSSADAPT_BKTS 3 +#define RAL_RSSADAPT_BKT0 128 +#define RAL_RSSADAPT_BKTPOWER 3 /* 2**_BKTPOWER */ + +#define ral_rssadapt_thresh_new \ + (ral_rssadapt_thresh_denom - ral_rssadapt_thresh_old) +#define ral_rssadapt_decay_new \ + (ral_rssadapt_decay_denom - ral_rssadapt_decay_old) +#define ral_rssadapt_avgrssi_new \ + (ral_rssadapt_avgrssi_denom - ral_rssadapt_avgrssi_old) + +struct ral_rssadapt_expavgctl { + /* RSS threshold decay. */ + u_int rc_decay_denom; + u_int rc_decay_old; + /* RSS threshold update. */ + u_int rc_thresh_denom; + u_int rc_thresh_old; + /* RSS average update. */ + u_int rc_avgrssi_denom; + u_int rc_avgrssi_old; +}; + +struct ral_rssadapt { + /* exponential average RSSI << 8 */ + u_int16_t ra_avg_rssi; + /* Tx failures in this update interval */ + u_int32_t ra_nfail; + /* Tx successes in this update interval */ + u_int32_t ra_nok; + /* exponential average packets/second */ + u_int32_t ra_pktrate; + /* RSSI threshold for each Tx rate */ + u_int16_t ra_rate_thresh[RAL_RSSADAPT_BKTS] + [IEEE80211_RATE_SIZE]; + struct timeval ra_last_raise; + struct timeval ra_raise_interval; +}; + +/* Properties of a Tx packet, for link adaptation. */ +struct ral_rssdesc { + u_int id_len; /* Tx packet length */ + u_int id_rateidx; /* index into ni->ni_rates */ + struct ieee80211_node *id_node; /* destination STA MAC */ + u_int8_t id_rssi; /* destination STA avg RSS @ + * Tx time + */ +}; + +void ral_rssadapt_updatestats(struct ral_rssadapt *); +void ral_rssadapt_input(struct ieee80211com *, struct ieee80211_node *, + struct ral_rssadapt *, int); +void ral_rssadapt_lower_rate(struct ieee80211com *, + struct ieee80211_node *, struct ral_rssadapt *, + struct ral_rssdesc *); +void ral_rssadapt_raise_rate(struct ieee80211com *, + struct ral_rssadapt *, struct ral_rssdesc *); +int ral_rssadapt_choose(struct ral_rssadapt *, + struct ieee80211_rateset *, struct ieee80211_frame *, u_int, + const char *, int); diff --git a/sys/dev/ral/if_ralreg.h b/sys/dev/ral/if_ralreg.h new file mode 100644 index 0000000..bccd0db --- /dev/null +++ b/sys/dev/ral/if_ralreg.h @@ -0,0 +1,313 @@ +/* $FreeBSD$ */ + +/*- + * Copyright (c) 2005 + * Damien Bergamini <damien.bergamini@free.fr> + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#define RAL_TX_RING_COUNT 48 +#define RAL_ATIM_RING_COUNT 4 +#define RAL_PRIO_RING_COUNT 16 +#define RAL_BEACON_RING_COUNT 1 +#define RAL_RX_RING_COUNT 32 + +#define RAL_TX_DESC_SIZE (sizeof (struct ral_tx_desc)) +#define RAL_RX_DESC_SIZE (sizeof (struct ral_rx_desc)) + +#define RAL_MAX_SCATTER 1 + +/* + * Control and status registers. + */ +#define RAL_CSR0 0x0000 /* ASIC version number */ +#define RAL_CSR1 0x0004 /* System control */ +#define RAL_CSR3 0x000c /* STA MAC address 0 */ +#define RAL_CSR4 0x0010 /* STA MAC address 1 */ +#define RAL_CSR5 0x0014 /* BSSID 0 */ +#define RAL_CSR6 0x0018 /* BSSID 1 */ +#define RAL_CSR7 0x001c /* Interrupt source */ +#define RAL_CSR8 0x0020 /* Interrupt mask */ +#define RAL_CSR9 0x0024 /* Maximum frame length */ +#define RAL_SECCSR0 0x0028 /* WEP control */ +#define RAL_CSR11 0x002c /* Back-off control */ +#define RAL_CSR12 0x0030 /* Synchronization configuration 0 */ +#define RAL_CSR13 0x0034 /* Synchronization configuration 1 */ +#define RAL_CSR14 0x0038 /* Synchronization control */ +#define RAL_CSR15 0x003c /* Synchronization status */ +#define RAL_CSR16 0x0040 /* TSF timer 0 */ +#define RAL_CSR17 0x0044 /* TSF timer 1 */ +#define RAL_CSR18 0x0048 /* IFS timer 0 */ +#define RAL_CSR19 0x004c /* IFS timer 1 */ +#define RAL_CSR20 0x0050 /* WAKEUP timer */ +#define RAL_CSR21 0x0054 /* EEPROM control */ +#define RAL_CSR22 0x0058 /* CFP control */ +#define RAL_TXCSR0 0x0060 /* TX control */ +#define RAL_TXCSR1 0x0064 /* TX configuration */ +#define RAL_TXCSR2 0x0068 /* TX descriptor configuration */ +#define RAL_TXCSR3 0x006c /* TX ring base address */ +#define RAL_TXCSR4 0x0070 /* TX ATIM ring base address */ +#define RAL_TXCSR5 0x0074 /* TX PRIO ring base address */ +#define RAL_TXCSR6 0x0078 /* Beacon base address */ +#define RAL_TXCSR7 0x007c /* AutoResponder control */ +#define RAL_RXCSR0 0x0080 /* RX control */ +#define RAL_RXCSR1 0x0084 /* RX descriptor configuration */ +#define RAL_RXCSR2 0x0088 /* RX ring base address */ +#define RAL_PCICSR 0x008c /* PCI control */ +#define RAL_RXCSR3 0x0090 /* BBP ID 0 */ +#define RAL_TXCSR9 0x0094 /* OFDM TX BBP */ +#define RAL_ARSP_PLCP_0 0x0098 /* Auto Responder PLCP address */ +#define RAL_ARSP_PLCP_1 0x009c /* Auto Responder PLCP Basic Rate bit mask */ +#define RAL_CNT0 0x00a0 /* FCS error counter */ +#define RAL_CNT1 0x00ac /* PLCP error counter */ +#define RAL_CNT2 0x00b0 /* Long error counter */ +#define RAL_CNT3 0x00b8 /* CCA false alarm counter */ +#define RAL_CNT4 0x00bc /* RX FIFO Overflow counter */ +#define RAL_CNT5 0x00c0 /* Tx FIFO Underrun counter */ +#define RAL_PWRCSR0 0x00c4 /* Power mode configuration */ +#define RAL_PSCSR0 0x00c8 /* Power state transition time */ +#define RAL_PSCSR1 0x00cc /* Power state transition time */ +#define RAL_PSCSR2 0x00d0 /* Power state transition time */ +#define RAL_PSCSR3 0x00d4 /* Power state transition time */ +#define RAL_PWRCSR1 0x00d8 /* Manual power control/status */ +#define RAL_TIMECSR 0x00dc /* Timer control */ +#define RAL_MACCSR0 0x00e0 /* MAC configuration */ +#define RAL_MACCSR1 0x00e4 /* MAC configuration */ +#define RAL_RALINKCSR 0x00e8 /* Ralink RX auto-reset BBCR */ +#define RAL_BCNCSR 0x00ec /* Beacon interval control */ +#define RAL_BBPCSR 0x00f0 /* BBP serial control */ +#define RAL_RFCSR 0x00f4 /* RF serial control */ +#define RAL_LEDCSR 0x00f8 /* LED control */ +#define RAL_SECCSR3 0x00fc /* XXX not documented */ +#define RAL_DMACSR0 0x0100 /* Current RX ring address */ +#define RAL_DMACSR1 0x0104 /* Current Tx ring address */ +#define RAL_DMACSR2 0x0104 /* Current Priority ring address */ +#define RAL_DMACSR3 0x0104 /* Current ATIM ring address */ +#define RAL_TXACKCSR0 0x0110 /* XXX not documented */ +#define RAL_GPIOCSR 0x0120 /* */ +#define RAL_BBBPPCSR 0x0124 /* BBP Pin Control */ +#define RAL_FIFOCSR0 0x0128 /* TX FIFO pointer */ +#define RAL_FIFOCSR1 0x012c /* RX FIFO pointer */ +#define RAL_BCNOCSR 0x0130 /* Beacon time offset */ +#define RAL_RLPWCSR 0x0134 /* RX_PE Low Width */ +#define RAL_TESTCSR 0x0138 /* Test Mode Select */ +#define RAL_PLCP1MCSR 0x013c /* Signal/Service/Length of ACK/CTS @1M */ +#define RAL_PLCP2MCSR 0x0140 /* Signal/Service/Length of ACK/CTS @2M */ +#define RAL_PLCP5p5MCSR 0x0144 /* Signal/Service/Length of ACK/CTS @5.5M */ +#define RAL_PLCP11MCSR 0x0148 /* Signal/Service/Length of ACK/CTS @11M */ +#define RAL_ACKPCTCSR 0x014c /* ACK/CTS padload consume time */ +#define RAL_ARTCSR1 0x0150 /* ACK/CTS padload consume time */ +#define RAL_ARTCSR2 0x0154 /* ACK/CTS padload consume time */ +#define RAL_SECCSR1 0x0158 /* WEP control */ +#define RAL_BBPCSR1 0x015c /* BBP TX Configuration */ + + +/* possible flags for register RXCSR0 */ +#define RAL_DISABLE_RX (1 << 0) +#define RAL_DROP_CRC_ERROR (1 << 1) +#define RAL_DROP_PHY_ERROR (1 << 2) +#define RAL_DROP_CTL (1 << 3) +#define RAL_DROP_NOT_TO_ME (1 << 4) +#define RAL_DROP_TODS (1 << 5) +#define RAL_DROP_VERSION_ERROR (1 << 6) + +/* possible flags for register CSR1 */ +#define RAL_RESET_ASIC (1 << 0) +#define RAL_RESET_BBP (1 << 1) +#define RAL_HOST_READY (1 << 2) + +/* possible flags for register CSR14 */ +#define RAL_ENABLE_TSF (1 << 0) +#define RAL_ENABLE_TSF_SYNC(x) (((x) & 0x3) << 1) +#define RAL_ENABLE_TBCN (1 << 3) +#define RAL_ENABLE_BEACON_GENERATOR (1 << 6) + +/* possible flags for register CSR21 */ +#define RAL_EEPROM_C (1 << 1) +#define RAL_EEPROM_S (1 << 2) +#define RAL_EEPROM_D (1 << 3) +#define RAL_EEPROM_Q (1 << 4) +#define RAL_EEPROM_93C46 (1 << 5) + +#define RAL_EEPROM_SHIFT_D 3 +#define RAL_EEPROM_SHIFT_Q 4 + +/* possible flags for register TXCSR0 */ +#define RAL_KICK_TX (1 << 0) +#define RAL_KICK_ATIM (1 << 1) +#define RAL_KICK_PRIO (1 << 2) +#define RAL_ABORT_TX (1 << 3) + +/* possible flags for register SECCSR0 */ +#define RAL_KICK_DECRYPT (1 << 0) + +/* possible flags for register SECCSR1 */ +#define RAL_KICK_ENCRYPT (1 << 0) + +/* possible flags for register CSR7 */ +#define RAL_BEACON_EXPIRE 0x00000001 +#define RAL_WAKEUP_EXPIRE 0x00000002 +#define RAL_ATIM_EXPIRE 0x00000004 +#define RAL_TX_DONE 0x00000008 +#define RAL_ATIM_DONE 0x00000010 +#define RAL_PRIO_DONE 0x00000020 +#define RAL_RX_DONE 0x00000040 +#define RAL_DECRYPTION_DONE 0x00000080 +#define RAL_ENCRYPTION_DONE 0x00000100 + +#define RAL_INTR_MASK \ + (~(RAL_BEACON_EXPIRE | RAL_WAKEUP_EXPIRE | RAL_TX_DONE | \ + RAL_PRIO_DONE | RAL_RX_DONE | RAL_DECRYPTION_DONE | \ + RAL_ENCRYPTION_DONE)) + +/* Tx descriptor */ +struct ral_tx_desc { + uint32_t flags; +#define RAL_TX_BUSY (1 << 0) +#define RAL_TX_VALID (1 << 1) + +#define RAL_TX_RESULT_MASK 0x0000001c +#define RAL_TX_SUCCESS (0 << 2) +#define RAL_TX_SUCCESS_RETRY (1 << 2) +#define RAL_TX_FAIL_RETRY (2 << 2) +#define RAL_TX_FAIL_INVALID (3 << 2) +#define RAL_TX_FAIL_OTHER (4 << 2) + +#define RAL_TX_MORE_FRAG (1 << 8) +#define RAL_TX_ACK (1 << 9) +#define RAL_TX_TIMESTAMP (1 << 10) +#define RAL_TX_OFDM (1 << 11) +#define RAL_TX_CIPHER_BUSY (1 << 12) + +#define RAL_TX_IFS_MASK 0x00006000 +#define RAL_TX_IFS_BACKOFF (0 << 13) +#define RAL_TX_IFS_SIFS (1 << 13) +#define RAL_TX_IFS_NEWBACKOFF (2 << 13) +#define RAL_TX_IFS_NONE (3 << 13) + +#define RAL_TX_LONG_RETRY (1 << 15) + +#define RAL_TX_CIPHER_MASK 0xe0000000 +#define RAL_TX_CIPHER_NONE (0 << 29) +#define RAL_TX_CIPHER_WEP40 (1 << 29) +#define RAL_TX_CIPHER_WEP104 (2 << 29) +#define RAL_TX_CIPHER_TKIP (3 << 29) +#define RAL_TX_CIPHER_AES (4 << 29) + + uint32_t physaddr; + uint16_t wme; +#define RAL_LOGCWMAX(x) (((x) & 0xf) << 12) +#define RAL_LOGCWMIN(x) (((x) & 0xf) << 8) +#define RAL_AIFSN(x) (((x) & 0x3) << 6) +#define RAL_IVOFFSET(x) (((x) & 0x3f)) + + uint16_t reserved1; + uint8_t plcp_signal; + uint8_t plcp_service; +#define RAL_PLCP_LENGEXT 0x80 + + uint16_t plcp_length; + uint32_t iv; + uint32_t eiv; + uint8_t key[IEEE80211_KEYBUF_SIZE]; + uint32_t reserved2[2]; +} __packed; + +/* Rx descriptor */ +struct ral_rx_desc { + uint32_t flags; +#define RAL_RX_BUSY (1 << 0) +#define RAL_RX_CRC_ERROR (1 << 5) +#define RAL_RX_PHY_ERROR (1 << 7) +#define RAL_RX_CIPHER_BUSY (1 << 8) +#define RAL_RX_ICV_ERROR (1 << 9) + +#define RAL_RX_CIPHER_MASK 0xe0000000 +#define RAL_RX_CIPHER_NONE (0 << 29) +#define RAL_RX_CIPHER_WEP40 (1 << 29) +#define RAL_RX_CIPHER_WEP104 (2 << 29) +#define RAL_RX_CIPHER_TKIP (3 << 29) +#define RAL_RX_CIPHER_AES (4 << 29) + + uint32_t physaddr; + uint8_t rate; + uint8_t rssi; + uint8_t ta[IEEE80211_ADDR_LEN]; + uint32_t iv; + uint32_t eiv; + uint8_t key[IEEE80211_KEYBUF_SIZE]; + uint32_t reserved[2]; +} __packed; + +#define RAL_RF1 0 +#define RAL_RF2 2 +#define RAL_RF3 1 +#define RAL_RF4 3 + +#define RAL_RF1_AUTOTUNE 0x08000 +#define RAL_RF3_AUTOTUNE 0x00040 + +#define RAL_BBP_BUSY (1 << 15) +#define RAL_BBP_WRITE (1 << 16) +#define RAL_RF_20BIT (20 << 24) +#define RAL_RF_BUSY (1 << 31) + +#define RAL_RF_2522 0x00 +#define RAL_RF_2523 0x01 +#define RAL_RF_2524 0x02 +#define RAL_RF_2525 0x03 +#define RAL_RF_2525E 0x04 +#define RAL_RF_2526 0x05 +/* dual-band RF */ +#define RAL_RF_5222 0x10 + +#define RAL_BBP_VERSION 0 +#define RAL_BBP_TX 2 +#define RAL_BBP_RX 14 + +#define RAL_BBP_ANTA 0x00 +#define RAL_BBP_DIVERSITY 0x01 +#define RAL_BBP_ANTB 0x02 +#define RAL_BBP_ANTMASK 0x03 +#define RAL_BBP_FLIPIQ 0x04 + +#define RAL_LED_MODE_DEFAULT 0 +#define RAL_LED_MODE_TXRX_ACTIVITY 1 +#define RAL_LED_MODE_SINGLE 2 +#define RAL_LED_MODE_ASUS 3 + +#define RAL_JAPAN_FILTER 0x8 + +#define RAL_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ + +#define RAL_EEPROM_CONFIG0 16 +#define RAL_EEPROM_BBP_BASE 19 +#define RAL_EEPROM_TXPOWER 35 + +/* + * control and status registers access macros + */ +#define RAL_READ(sc, reg) \ + bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) + +#define RAL_WRITE(sc, reg, val) \ + bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) + +/* + * EEPROM access macro + */ +#define RAL_EEPROM_CTL(sc, val) do { \ + RAL_WRITE((sc), RAL_CSR21, (val)); \ + DELAY(RAL_EEPROM_DELAY); \ +} while (/* CONSTCOND */0) diff --git a/sys/dev/ral/if_ralvar.h b/sys/dev/ral/if_ralvar.h new file mode 100644 index 0000000..c05a8b4 --- /dev/null +++ b/sys/dev/ral/if_ralvar.h @@ -0,0 +1,175 @@ +/* $FreeBSD$ */ + +/*- + * Copyright (c) 2005 + * Damien Bergamini <damien.bergamini@free.fr> + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +struct ral_rx_radiotap_header { + struct ieee80211_radiotap_header wr_ihdr; + uint64_t wr_tsf; + uint8_t wr_flags; + uint16_t wr_chan_freq; + uint16_t wr_chan_flags; + uint8_t wr_antenna; + uint8_t wr_antsignal; +}; + +#define RAL_RX_RADIOTAP_PRESENT \ + ((1 << IEEE80211_RADIOTAP_TSFT) | \ + (1 << IEEE80211_RADIOTAP_FLAGS) | \ + (1 << IEEE80211_RADIOTAP_CHANNEL) | \ + (1 << IEEE80211_RADIOTAP_ANTENNA) | \ + (1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL)) + +struct ral_tx_radiotap_header { + struct ieee80211_radiotap_header wt_ihdr; + uint8_t wt_flags; + uint8_t wt_rate; + uint16_t wt_chan_freq; + uint16_t wt_chan_flags; + uint8_t wt_antenna; +}; + +#define RAL_TX_RADIOTAP_PRESENT \ + ((1 << IEEE80211_RADIOTAP_FLAGS) | \ + (1 << IEEE80211_RADIOTAP_RATE) | \ + (1 << IEEE80211_RADIOTAP_CHANNEL) | \ + (1 << IEEE80211_RADIOTAP_ANTENNA)) + +struct ral_tx_data { + bus_dmamap_t map; + struct mbuf *m; + struct ieee80211_node *ni; + struct ral_rssdesc id; +}; + +struct ral_tx_ring { + bus_dma_tag_t desc_dmat; + bus_dma_tag_t data_dmat; + bus_dmamap_t desc_map; + bus_addr_t physaddr; + struct ral_tx_desc *desc; + struct ral_tx_data *data; + int count; + int queued; + int cur; + int next; + int cur_encrypt; + int next_encrypt; +}; + +struct ral_rx_data { + bus_dmamap_t map; + struct mbuf *m; + int drop; +}; + +struct ral_rx_ring { + bus_dma_tag_t desc_dmat; + bus_dma_tag_t data_dmat; + bus_dmamap_t desc_map; + bus_addr_t physaddr; + struct ral_rx_desc *desc; + struct ral_rx_data *data; + int count; + int cur; + int next; + int cur_decrypt; +}; + +struct ral_node { + struct ieee80211_node ni; + struct ral_rssadapt rssadapt; +}; + +struct ral_softc { + struct arpcom sc_arp; + struct ieee80211com sc_ic; + int (*sc_newstate)(struct ieee80211com *, + enum ieee80211_state, int); + device_t sc_dev; + + struct mtx sc_mtx; + + struct callout scan_ch; + struct callout rssadapt_ch; + + int irq_rid; + int mem_rid; + struct resource *irq; + struct resource *mem; + bus_space_tag_t sc_st; + bus_space_handle_t sc_sh; + void *sc_ih; + + int sc_tx_timer; + + uint32_t asic_rev; + uint32_t eeprom_rev; + uint8_t rf_rev; + + struct ral_tx_ring txq; + struct ral_tx_ring prioq; + struct ral_tx_ring atimq; + struct ral_tx_ring bcnq; + struct ral_rx_ring rxq; + + struct ieee80211_beacon_offsets sc_bo; + + uint32_t rf_regs[4]; + uint8_t txpow[14]; + + struct { + uint8_t reg; + uint8_t val; + } bbp_prom[16]; + + int led_mode; + int hw_radio; + int rx_ant; + int tx_ant; + int nb_ant; + + int dwelltime; + + struct bpf_if *sc_drvbpf; + + union { + struct ral_rx_radiotap_header th; + uint8_t pad[64]; + } sc_rxtapu; +#define sc_rxtap sc_rxtapu.th + int sc_rxtap_len; + + union { + struct ral_tx_radiotap_header th; + uint8_t pad[64]; + } sc_txtapu; +#define sc_txtap sc_txtapu.th + int sc_txtap_len; +}; + +extern devclass_t ral_devclass; + +int ral_attach(device_t); +int ral_detach(device_t); +void ral_shutdown(device_t); +int ral_alloc(device_t, int); +void ral_free(device_t); +void ral_stop(void *); + +#define RAL_LOCK(sc) mtx_lock(&(sc)->sc_mtx) +#define RAL_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) diff --git a/sys/dev/usb/if_ural.c b/sys/dev/usb/if_ural.c new file mode 100644 index 0000000..31677cd0 --- /dev/null +++ b/sys/dev/usb/if_ural.c @@ -0,0 +1,2060 @@ +/* $FreeBSD$ */ + +/*- + * Copyright (c) 2005 + * Damien Bergamini <damien.bergamini@free.fr> + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +/*- + * Ralink Technology RT2500USB chipset driver + * http://www.ralinktech.com/ + */ + +#include <sys/param.h> +#include <sys/sysctl.h> +#include <sys/sockio.h> +#include <sys/mbuf.h> +#include <sys/kernel.h> +#include <sys/socket.h> +#include <sys/systm.h> +#include <sys/malloc.h> +#include <sys/module.h> +#include <sys/bus.h> +#include <sys/endian.h> + +#include <machine/bus.h> +#include <machine/resource.h> +#include <machine/clock.h> +#include <sys/rman.h> + +#include <net/bpf.h> +#include <net/if.h> +#include <net/if_arp.h> +#include <net/ethernet.h> +#include <net/if_dl.h> +#include <net/if_media.h> +#include <net/if_types.h> + +#include <net80211/ieee80211_var.h> +#include <net80211/ieee80211_radiotap.h> + +#include <netinet/in.h> +#include <netinet/in_systm.h> +#include <netinet/in_var.h> +#include <netinet/ip.h> +#include <netinet/if_ether.h> + +#include <dev/usb/usb.h> +#include <dev/usb/usbdi.h> +#include <dev/usb/usbdi_util.h> +#include "usbdevs.h" + +#include <dev/usb/if_uralreg.h> +#include <dev/usb/if_uralvar.h> + +#ifdef USB_DEBUG +#define DPRINTF(x) do { if (uraldebug > 0) logprintf x; } while (0) +#define DPRINTFN(n, x) do { if (uraldebug >= (n)) logprintf x; } while (0) +int uraldebug = 2; +SYSCTL_NODE(_hw_usb, OID_AUTO, ural, CTLFLAG_RW, 0, "USB ural"); +SYSCTL_INT(_hw_usb_ural, OID_AUTO, debug, CTLFLAG_RW, &uraldebug, 0, + "ural debug level"); +#else +#define DPRINTF(x) +#define DPRINTFN(n, x) +#endif + +/* various supported device vendors/products */ +static const struct usb_devno ural_devs[] = { + { USB_VENDOR_ASUS, USB_PRODUCT_ASUS_WL167G }, + { USB_VENDOR_ASUS, USB_PRODUCT_RALINK_RT2570 }, + { USB_VENDOR_CONCEPTRONIC, USB_PRODUCT_CONCEPTRONIC_C54U }, + { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DWLG122 }, + { USB_VENDOR_LINKSYS4, USB_PRODUCT_LINKSYS4_WUSB54G }, + { USB_VENDOR_LINKSYS4, USB_PRODUCT_LINKSYS4_WUSB54GP }, + { USB_VENDOR_MELCO, USB_PRODUCT_MELCO_KG54 }, + { USB_VENDOR_RALINK, USB_PRODUCT_RALINK_RT2570 }, + { USB_VENDOR_RALINK, USB_PRODUCT_RALINK_RT2570_2 }, + { USB_VENDOR_SMC, USB_PRODUCT_SMC_2862WG } +}; + +MODULE_DEPEND(ural, wlan, 1, 1, 1); + +Static int ural_alloc_tx_list(struct ural_softc *); +Static void ural_free_tx_list(struct ural_softc *); +Static int ural_alloc_rx_list(struct ural_softc *); +Static void ural_free_rx_list(struct ural_softc *); +Static int ural_media_change(struct ifnet *); +Static void ural_next_scan(void *); +Static void ural_task(void *); +Static int ural_newstate(struct ieee80211com *, + enum ieee80211_state, int); +Static void ural_txeof(usbd_xfer_handle, usbd_private_handle, + usbd_status); +Static void ural_rxeof(usbd_xfer_handle, usbd_private_handle, + usbd_status); +Static int ural_ack_rate(int); +Static uint16_t ural_txtime(int, int, uint32_t); +Static uint8_t ural_plcp_signal(int); +Static void ural_setup_tx_desc(struct ural_softc *, + struct ural_tx_desc *, uint32_t, int, int); +Static int ural_tx_bcn(struct ural_softc *, struct mbuf *, + struct ieee80211_node *); +Static int ural_tx_mgt(struct ural_softc *, struct mbuf *, + struct ieee80211_node *); +Static int ural_tx_data(struct ural_softc *, struct mbuf *, + struct ieee80211_node *); +Static void ural_start(struct ifnet *); +Static void ural_watchdog(struct ifnet *); +Static int ural_reset(struct ifnet *); +Static int ural_ioctl(struct ifnet *, u_long, caddr_t); +Static void ural_eeprom_read(struct ural_softc *, uint16_t, void *, + int); +Static uint16_t ural_read(struct ural_softc *, uint16_t); +Static void ural_read_multi(struct ural_softc *, uint16_t, void *, + int); +Static void ural_write(struct ural_softc *, uint16_t, uint16_t); +Static void ural_write_multi(struct ural_softc *, uint16_t, void *, + int); +Static void ural_bbp_write(struct ural_softc *, uint8_t, uint8_t); +Static uint8_t ural_bbp_read(struct ural_softc *, uint8_t); +Static void ural_rf_write(struct ural_softc *, uint8_t, uint32_t); +Static void ural_set_chan(struct ural_softc *, + struct ieee80211_channel *); +#if 0 +Static void ural_disable_rf_tune(struct ural_softc *); +#endif +Static void ural_enable_tsf_sync(struct ural_softc *); +Static void ural_set_bssid(struct ural_softc *, uint8_t *); +Static void ural_set_macaddr(struct ural_softc *, uint8_t *); +Static void ural_update_promisc(struct ural_softc *); +Static const char *ural_get_rf(int); +Static void ural_read_eeprom(struct ural_softc *); +Static int ural_bbp_init(struct ural_softc *); +Static void ural_set_txantenna(struct ural_softc *, int); +Static void ural_set_rxantenna(struct ural_softc *, int); +Static void ural_init(void *); +Static void ural_stop(void *); + +/* + * Supported rates for 802.11a/b/g modes (in 500Kbps unit). + */ +static const struct ieee80211_rateset ural_rateset_11a = + { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; + +static const struct ieee80211_rateset ural_rateset_11b = + { 4, { 2, 4, 11, 22 } }; + +static const struct ieee80211_rateset ural_rateset_11g = + { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; + +/* + * Default values for MAC registers; values taken from the reference driver. + */ +static const struct { + uint16_t reg; + uint16_t val; +} ural_def_mac[] = { + { RAL_TXRX_CSR5, 0x8c8d }, + { RAL_TXRX_CSR6, 0x8b8a }, + { RAL_TXRX_CSR7, 0x8687 }, + { RAL_TXRX_CSR8, 0x0085 }, + { RAL_MAC_CSR13, 0x1111 }, + { RAL_MAC_CSR14, 0x1e11 }, + { RAL_TXRX_CSR21, 0xe78f }, + { RAL_MAC_CSR9, 0xff1d }, + { RAL_MAC_CSR11, 0x0002 }, + { RAL_MAC_CSR22, 0x0053 }, + { RAL_MAC_CSR15, 0x0000 }, + { RAL_MAC_CSR8, 0x0780 }, + { RAL_TXRX_CSR19, 0x0000 }, + { RAL_TXRX_CSR18, 0x005a }, + { RAL_PHY_CSR2, 0x0000 }, + { RAL_TXRX_CSR0, 0x1ec0 }, + { RAL_PHY_CSR4, 0x000f } +}; + +/* + * Default values for BBP registers; values taken from the reference driver. + */ +static const struct { + uint8_t reg; + uint8_t val; +} ural_def_bbp[] = { + { 3, 0x02 }, + { 4, 0x19 }, + { 14, 0x1c }, + { 15, 0x30 }, + { 16, 0xac }, + { 17, 0x48 }, + { 18, 0x18 }, + { 19, 0xff }, + { 20, 0x1e }, + { 21, 0x08 }, + { 22, 0x08 }, + { 23, 0x08 }, + { 24, 0x80 }, + { 25, 0x50 }, + { 26, 0x08 }, + { 27, 0x23 }, + { 30, 0x10 }, + { 31, 0x2b }, + { 32, 0xb9 }, + { 34, 0x12 }, + { 35, 0x50 }, + { 39, 0xc4 }, + { 40, 0x02 }, + { 41, 0x60 }, + { 53, 0x10 }, + { 54, 0x18 }, + { 56, 0x08 }, + { 57, 0x10 }, + { 58, 0x08 }, + { 61, 0x60 }, + { 62, 0x10 }, + { 75, 0xff } +}; + +/* + * Default values for RF register R2 indexed by channel numbers. + */ +static const uint32_t ural_rf2522_r2[] = { + 0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814, + 0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e +}; + +static const uint32_t ural_rf2523_r2[] = { + 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, + 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 +}; + +static const uint32_t ural_rf2524_r2[] = { + 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, + 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 +}; + +static const uint32_t ural_rf2525_r2[] = { + 0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d, + 0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346 +}; + +static const uint32_t ural_rf2525_hi_r2[] = { + 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345, + 0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e +}; + +static const uint32_t ural_rf2525e_r2[] = { + 0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463, + 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b +}; + +static const uint32_t ural_rf2526_hi_r2[] = { + 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d, + 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241 +}; + +static const uint32_t ural_rf2526_r2[] = { + 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229, + 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d +}; + +/* + * For dual-band RF, RF registers R1 and R4 also depend on channel number; + * values taken from the reference driver. + */ +static const struct { + uint8_t chan; + uint32_t r1; + uint32_t r2; + uint32_t r4; +} ural_rf5222[] = { + /* channels in the 2.4GHz band */ + { 1, 0x08808, 0x0044d, 0x00282 }, + { 2, 0x08808, 0x0044e, 0x00282 }, + { 3, 0x08808, 0x0044f, 0x00282 }, + { 4, 0x08808, 0x00460, 0x00282 }, + { 5, 0x08808, 0x00461, 0x00282 }, + { 6, 0x08808, 0x00462, 0x00282 }, + { 7, 0x08808, 0x00463, 0x00282 }, + { 8, 0x08808, 0x00464, 0x00282 }, + { 9, 0x08808, 0x00465, 0x00282 }, + { 10, 0x08808, 0x00466, 0x00282 }, + { 11, 0x08808, 0x00467, 0x00282 }, + { 12, 0x08808, 0x00468, 0x00282 }, + { 13, 0x08808, 0x00469, 0x00282 }, + { 14, 0x08808, 0x0046b, 0x00286 }, + + /* channels in the 5.2GHz band */ + { 36, 0x08804, 0x06225, 0x00287 }, + { 40, 0x08804, 0x06226, 0x00287 }, + { 44, 0x08804, 0x06227, 0x00287 }, + { 48, 0x08804, 0x06228, 0x00287 }, + { 52, 0x08804, 0x06229, 0x00287 }, + { 56, 0x08804, 0x0622a, 0x00287 }, + { 60, 0x08804, 0x0622b, 0x00287 }, + { 64, 0x08804, 0x0622c, 0x00287 }, + + { 100, 0x08804, 0x02200, 0x00283 }, + { 104, 0x08804, 0x02201, 0x00283 }, + { 108, 0x08804, 0x02202, 0x00283 }, + { 112, 0x08804, 0x02203, 0x00283 }, + { 116, 0x08804, 0x02204, 0x00283 }, + { 120, 0x08804, 0x02205, 0x00283 }, + { 124, 0x08804, 0x02206, 0x00283 }, + { 128, 0x08804, 0x02207, 0x00283 }, + { 132, 0x08804, 0x02208, 0x00283 }, + { 136, 0x08804, 0x02209, 0x00283 }, + { 140, 0x08804, 0x0220a, 0x00283 }, + + { 149, 0x08808, 0x02429, 0x00281 }, + { 153, 0x08808, 0x0242b, 0x00281 }, + { 157, 0x08808, 0x0242d, 0x00281 }, + { 161, 0x08808, 0x0242f, 0x00281 } +}; + +USB_DECLARE_DRIVER(ural); + +USB_MATCH(ural) +{ + USB_MATCH_START(ural, uaa); + + if (uaa->iface != NULL) + return UMATCH_NONE; + + return (usb_lookup(ural_devs, uaa->vendor, uaa->product) != NULL) ? + UMATCH_VENDOR_PRODUCT : UMATCH_NONE; +} + +USB_ATTACH(ural) +{ + USB_ATTACH_START(ural, sc, uaa); + struct ifnet *ifp = &sc->sc_arp.ac_if; + struct ieee80211com *ic = &sc->sc_ic; + usb_interface_descriptor_t *id; + usb_endpoint_descriptor_t *ed; + usbd_status error; + char devinfo[1024]; + int i; + + sc->sc_udev = uaa->device; + + usbd_devinfo(sc->sc_udev, 0, devinfo); + USB_ATTACH_SETUP; + + if (usbd_set_config_no(sc->sc_udev, RAL_CONFIG_NO, 0) != 0) { + printf("%s: could not set configuration no\n", + USBDEVNAME(sc->sc_dev)); + USB_ATTACH_ERROR_RETURN; + } + + /* get the first interface handle */ + error = usbd_device2interface_handle(sc->sc_udev, RAL_IFACE_INDEX, + &sc->sc_iface); + if (error != 0) { + printf("%s: could not get interface handle\n", + USBDEVNAME(sc->sc_dev)); + USB_ATTACH_ERROR_RETURN; + } + + /* + * Find endpoints. + */ + id = usbd_get_interface_descriptor(sc->sc_iface); + + for (i = 0; i < id->bNumEndpoints; i++) { + ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); + if (ed == NULL) { + printf("%s: no endpoint descriptor for %d\n", + USBDEVNAME(sc->sc_dev), i); + USB_ATTACH_ERROR_RETURN; + } + + if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && + UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) + sc->sc_rx_no = ed->bEndpointAddress; + else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && + UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) + sc->sc_tx_no = ed->bEndpointAddress; + } + + mtx_init(&sc->sc_mtx, USBDEVNAME(sc->sc_dev), MTX_NETWORK_LOCK, + MTX_DEF | MTX_RECURSE); + + usb_init_task(&sc->sc_task, ural_task, sc); + callout_init(&sc->scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0); + + /* retrieve RT2570 rev. no */ + sc->asic_rev = ural_read(sc, RAL_MAC_CSR0); + + /* retrieve MAC address and various other things from EEPROM */ + ural_read_eeprom(sc); + + printf("%s: MAC/BBP RT2570 (rev 0x%02x), RF %s\n", + USBDEVNAME(sc->sc_dev), sc->asic_rev, ural_get_rf(sc->rf_rev)); + + ifp->if_softc = sc; + if_initname(ifp, "ural", USBDEVUNIT(sc->sc_dev)); + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | + IFF_NEEDSGIANT; /* USB stack is still under Giant lock */ + ifp->if_init = ural_init; + ifp->if_ioctl = ural_ioctl; + ifp->if_start = ural_start; + ifp->if_watchdog = ural_watchdog; + IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); + ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; + IFQ_SET_READY(&ifp->if_snd); + + ic->ic_ifp = ifp; + ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ + ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ + ic->ic_state = IEEE80211_S_INIT; + + /* set device capabilities */ + ic->ic_caps = IEEE80211_C_MONITOR | IEEE80211_C_IBSS | + IEEE80211_C_HOSTAP | IEEE80211_C_SHPREAMBLE | IEEE80211_C_SHSLOT | + IEEE80211_C_PMGT | IEEE80211_C_TXPMGT | IEEE80211_C_WPA; + + if (sc->rf_rev == RAL_RF_5222) { + /* set supported .11a rates */ + ic->ic_sup_rates[IEEE80211_MODE_11A] = ural_rateset_11a; + + /* set supported .11a channels */ + for (i = 36; i <= 64; i += 4) { + ic->ic_channels[i].ic_freq = + ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); + ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; + } + for (i = 100; i <= 140; i += 4) { + ic->ic_channels[i].ic_freq = + ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); + ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; + } + for (i = 149; i <= 161; i += 4) { + ic->ic_channels[i].ic_freq = + ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); + ic->ic_channels[i].ic_flags = IEEE80211_CHAN_A; + } + } + + /* set supported .11b and .11g rates */ + ic->ic_sup_rates[IEEE80211_MODE_11B] = ural_rateset_11b; + ic->ic_sup_rates[IEEE80211_MODE_11G] = ural_rateset_11g; + + /* set supported .11b and .11g channels (1 through 14) */ + for (i = 1; i <= 14; i++) { + ic->ic_channels[i].ic_freq = + ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); + ic->ic_channels[i].ic_flags = + IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | + IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; + } + + ieee80211_ifattach(ic); + ic->ic_reset = ural_reset; + + /* override state transition machine */ + sc->sc_newstate = ic->ic_newstate; + ic->ic_newstate = ural_newstate; + ieee80211_media_init(ic, ural_media_change, ieee80211_media_status); + + bpfattach2(ifp, DLT_IEEE802_11_RADIO, + sizeof (struct ieee80211_frame) + 64, &sc->sc_drvbpf); + + sc->sc_rxtap_len = sizeof sc->sc_rxtapu; + sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); + sc->sc_rxtap.wr_ihdr.it_present = htole32(RAL_RX_RADIOTAP_PRESENT); + + sc->sc_txtap_len = sizeof sc->sc_txtapu; + sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); + sc->sc_txtap.wt_ihdr.it_present = htole32(RAL_TX_RADIOTAP_PRESENT); + + if (bootverbose) + ieee80211_announce(ic); + + USB_ATTACH_SUCCESS_RETURN; +} + +USB_DETACH(ural) +{ + USB_DETACH_START(ural, sc); + struct ieee80211com *ic = &sc->sc_ic; + struct ifnet *ifp = ic->ic_ifp; + + usb_rem_task(sc->sc_udev, &sc->sc_task); + callout_stop(&sc->scan_ch); + + if (sc->sc_rx_pipeh != NULL) { + usbd_abort_pipe(sc->sc_rx_pipeh); + usbd_close_pipe(sc->sc_rx_pipeh); + } + + if (sc->sc_tx_pipeh != NULL) { + usbd_abort_pipe(sc->sc_tx_pipeh); + usbd_close_pipe(sc->sc_tx_pipeh); + } + + ural_free_rx_list(sc); + ural_free_tx_list(sc); + + bpfdetach(ifp); + ieee80211_ifdetach(ic); + + mtx_destroy(&sc->sc_mtx); + + return 0; +} + +Static int +ural_alloc_tx_list(struct ural_softc *sc) +{ + struct ural_tx_data *data; + int i, error; + + sc->tx_queued = 0; + + for (i = 0; i < RAL_TX_LIST_COUNT; i++) { + data = &sc->tx_data[i]; + + data->sc = sc; + + data->xfer = usbd_alloc_xfer(sc->sc_udev); + if (data->xfer == NULL) { + printf("%s: could not allocate tx xfer\n", + USBDEVNAME(sc->sc_dev)); + error = ENOMEM; + goto fail; + } + + data->buf = usbd_alloc_buffer(data->xfer, + RAL_TX_DESC_SIZE + MCLBYTES); + if (data->buf == NULL) { + printf("%s: could not allocate tx buffer\n", + USBDEVNAME(sc->sc_dev)); + error = ENOMEM; + goto fail; + } + } + + return 0; + +fail: ural_free_tx_list(sc); + return error; +} + +Static void +ural_free_tx_list(struct ural_softc *sc) +{ + struct ural_tx_data *data; + int i; + + for (i = 0; i < RAL_TX_LIST_COUNT; i++) { + data = &sc->tx_data[i]; + + if (data->xfer != NULL) { + usbd_free_xfer(data->xfer); + data->xfer = NULL; + } + + if (data->ni != NULL) { + ieee80211_free_node(data->ni); + data->ni = NULL; + } + } +} + +Static int +ural_alloc_rx_list(struct ural_softc *sc) +{ + struct ural_rx_data *data; + int i, error; + + for (i = 0; i < RAL_RX_LIST_COUNT; i++) { + data = &sc->rx_data[i]; + + data->sc = sc; + + data->xfer = usbd_alloc_xfer(sc->sc_udev); + if (data->xfer == NULL) { + printf("%s: could not allocate rx xfer\n", + USBDEVNAME(sc->sc_dev)); + error = ENOMEM; + goto fail; + } + + if (usbd_alloc_buffer(data->xfer, MCLBYTES) == NULL) { + printf("%s: could not allocate rx buffer\n", + USBDEVNAME(sc->sc_dev)); + error = ENOMEM; + goto fail; + } + + data->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + if (data->m == NULL) { + printf("%s: could not allocate rx mbuf\n", + USBDEVNAME(sc->sc_dev)); + error = ENOMEM; + goto fail; + } + + data->buf = mtod(data->m, uint8_t *); + } + + return 0; + +fail: ural_free_tx_list(sc); + return error; +} + +Static void +ural_free_rx_list(struct ural_softc *sc) +{ + struct ural_rx_data *data; + int i; + + for (i = 0; i < RAL_RX_LIST_COUNT; i++) { + data = &sc->rx_data[i]; + + if (data->xfer != NULL) { + usbd_free_xfer(data->xfer); + data->xfer = NULL; + } + + if (data->m != NULL) { + m_freem(data->m); + data->m = NULL; + } + } +} + +Static int +ural_media_change(struct ifnet *ifp) +{ + struct ural_softc *sc = ifp->if_softc; + int error; + + RAL_LOCK(sc); + + error = ieee80211_media_change(ifp); + if (error != ENETRESET) { + RAL_UNLOCK(sc); + return error; + } + + if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING)) + ural_init(ifp); + + RAL_UNLOCK(sc); + + return 0; +} + +/* + * This function is called periodically (every 200ms) during scanning to + * switch from one channel to another. + */ +Static void +ural_next_scan(void *arg) +{ + struct ural_softc *sc = arg; + struct ieee80211com *ic = &sc->sc_ic; + + if (ic->ic_state == IEEE80211_S_SCAN) + ieee80211_next_scan(ic); +} + +Static void +ural_task(void *arg) +{ + struct ural_softc *sc = arg; + struct ieee80211com *ic = &sc->sc_ic; + enum ieee80211_state ostate; + struct mbuf *m; + + ostate = ic->ic_state; + + switch (sc->sc_state) { + case IEEE80211_S_INIT: + if (ostate == IEEE80211_S_RUN) { + /* abort TSF synchronization */ + ural_write(sc, RAL_TXRX_CSR19, 0); + + /* force tx led to stop blinking */ + ural_write(sc, RAL_MAC_CSR20, 0); + } + break; + + case IEEE80211_S_SCAN: + ural_set_chan(sc, ic->ic_bss->ni_chan); + callout_reset(&sc->scan_ch, hz / 5, ural_next_scan, sc); + break; + + case IEEE80211_S_AUTH: + ural_set_chan(sc, ic->ic_bss->ni_chan); + break; + + case IEEE80211_S_ASSOC: + ural_set_chan(sc, ic->ic_bss->ni_chan); + break; + + case IEEE80211_S_RUN: + ural_set_chan(sc, ic->ic_bss->ni_chan); + + if (ic->ic_opmode != IEEE80211_M_MONITOR) + ural_set_bssid(sc, ic->ic_bss->ni_bssid); + + if (ic->ic_opmode == IEEE80211_M_HOSTAP || + ic->ic_opmode == IEEE80211_M_IBSS) { + m = ieee80211_beacon_alloc(ic, ic->ic_bss, &sc->sc_bo); + if (m == NULL) { + printf("%s: could not allocate beacon\n", + USBDEVNAME(sc->sc_dev)); + return; + } + + if (ural_tx_bcn(sc, m, ic->ic_bss) != 0) { + printf("%s: could not send beacon\n", + USBDEVNAME(sc->sc_dev)); + return; + } + } + + /* make tx led blink on tx (controlled by ASIC) */ + ural_write(sc, RAL_MAC_CSR20, 1); + + if (ic->ic_opmode != IEEE80211_M_MONITOR) + ural_enable_tsf_sync(sc); + break; + } + + sc->sc_newstate(ic, sc->sc_state, -1); +} + +Static int +ural_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) +{ + struct ural_softc *sc = ic->ic_ifp->if_softc; + + usb_rem_task(sc->sc_udev, &sc->sc_task); + callout_stop(&sc->scan_ch); + + /* do it in a process context */ + sc->sc_state = nstate; + usb_add_task(sc->sc_udev, &sc->sc_task); + + return 0; +} + +/* quickly determine if a given rate is CCK or OFDM */ +#define RAL_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22) + +#define RAL_ACK_SIZE 14 /* 10 + 4(FCS) */ +#define RAL_CTS_SIZE 14 /* 10 + 4(FCS) */ +#define RAL_SIFS 10 + +Static void +ural_txeof(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status) +{ + struct ural_tx_data *data = priv; + struct ural_softc *sc = data->sc; + struct ifnet *ifp = sc->sc_ic.ic_ifp; + + if (status != USBD_NORMAL_COMPLETION) { + if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) + return; + + printf("%s: could not transmit buffer: %s\n", + USBDEVNAME(sc->sc_dev), usbd_errstr(status)); + + if (status == USBD_STALLED) + usbd_clear_endpoint_stall(sc->sc_rx_pipeh); + + ifp->if_oerrors++; + return; + } + + m_freem(data->m); + data->m = NULL; + ieee80211_free_node(data->ni); + data->ni = NULL; + + sc->tx_queued--; + ifp->if_opackets++; + + DPRINTFN(10, ("tx done\n")); + + sc->sc_tx_timer = 0; + ifp->if_flags &= ~IFF_OACTIVE; + ural_start(ifp); +} + +Static void +ural_rxeof(usbd_xfer_handle xfer, usbd_private_handle priv, usbd_status status) +{ + struct ural_rx_data *data = priv; + struct ural_softc *sc = data->sc; + struct ieee80211com *ic = &sc->sc_ic; + struct ifnet *ifp = ic->ic_ifp; + struct ural_rx_desc *desc; + struct ieee80211_frame *wh; + struct ieee80211_node *ni; + struct mbuf *m; + int len; + + if (status != USBD_NORMAL_COMPLETION) { + if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) + return; + + if (status == USBD_STALLED) + usbd_clear_endpoint_stall(sc->sc_rx_pipeh); + goto skip; + } + + usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); + + if (len < RAL_RX_DESC_SIZE) { + printf("%s: xfer too short %d\n", USBDEVNAME(sc->sc_dev), len); + ifp->if_ierrors++; + goto skip; + } + + /* rx descriptor is located at the end */ + desc = (struct ural_rx_desc *)(data->buf + len - RAL_RX_DESC_SIZE); + + if ((le32toh(desc->flags) & RAL_RX_PHY_ERROR) || + (le32toh(desc->flags) & RAL_RX_CRC_ERROR)) { + /* + * This should not happen since we did not request to receive + * those frames when we filled RAL_TXRX_CSR2. + */ + DPRINTFN(5, ("PHY or CRC error\n")); + ifp->if_ierrors++; + goto skip; + } + + /* finalize mbuf */ + m = data->m; + m->m_pkthdr.rcvif = ifp; + m->m_pkthdr.len = m->m_len = (le32toh(desc->flags) >> 16) & 0xfff; + m->m_flags |= M_HASFCS; /* hardware appends FCS */ + + wh = mtod(m, struct ieee80211_frame *); + ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); + + /* send the frame to the 802.11 layer */ + ieee80211_input(ic, m, ni, desc->rssi, 0); + + /* node is no longer needed */ + ieee80211_free_node(ni); + + data->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + if (data->m == NULL) { + printf("%s: could not allocate rx mbuf\n", + USBDEVNAME(sc->sc_dev)); + return; + } + + data->buf = mtod(data->m, uint8_t *); + + DPRINTFN(15, ("rx done\n")); + +skip: /* setup a new transfer */ + usbd_setup_xfer(xfer, sc->sc_rx_pipeh, data, data->buf, MCLBYTES, + USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, ural_rxeof); + usbd_transfer(xfer); +} + +/* + * Return the expected ack rate for a frame transmitted at rate `rate'. + * XXX: this should depend on the destination node basic rate set. + */ +Static int +ural_ack_rate(int rate) +{ + switch (rate) { + /* CCK rates */ + case 2: + return 2; + case 4: + case 11: + case 22: + return 4; + + /* OFDM rates */ + case 12: + case 18: + return 12; + case 24: + case 36: + return 24; + case 48: + case 72: + case 96: + case 108: + return 48; + } + + /* default to 1Mbps */ + return 2; +} + +/* + * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'. + * The function automatically determines the operating mode depending on the + * given rate. `flags' indicates whether short preamble is in use or not. + */ +Static uint16_t +ural_txtime(int len, int rate, uint32_t flags) +{ + uint16_t txtime; + int ceil, dbps; + + if (RAL_RATE_IS_OFDM(rate)) { + /* + * OFDM TXTIME calculation. + * From IEEE Std 802.11a-1999, pp. 37. + */ + dbps = rate * 2; /* data bits per OFDM symbol */ + + ceil = (16 + 8 * len + 6) / dbps; + if ((16 + 8 * len + 6) % dbps != 0) + ceil++; + + txtime = 16 + 4 + 4 * ceil + 6; + } else { + /* + * High Rate TXTIME calculation. + * From IEEE Std 802.11b-1999, pp. 28. + */ + ceil = (8 * len * 2) / rate; + if ((8 * len * 2) % rate != 0) + ceil++; + + if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE)) + txtime = 72 + 24 + ceil; + else + txtime = 144 + 48 + ceil; + } + + return txtime; +} + +Static uint8_t +ural_plcp_signal(int rate) +{ + switch (rate) { + /* CCK rates (returned values are device-dependent) */ + case 2: return 0x0; + case 4: return 0x1; + case 11: return 0x2; + case 22: return 0x3; + + /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ + case 12: return 0xb; + case 18: return 0xf; + case 24: return 0xa; + case 36: return 0xe; + case 48: return 0x9; + case 72: return 0xd; + case 96: return 0x8; + case 108: return 0xc; + + /* unsupported rates (should not get there) */ + default: return 0xff; + } +} + +Static void +ural_setup_tx_desc(struct ural_softc *sc, struct ural_tx_desc *desc, + uint32_t flags, int len, int rate) +{ + struct ieee80211com *ic = &sc->sc_ic; + uint16_t plcp_length; + int remainder; + + desc->flags = htole32(flags); + desc->flags |= htole32(RAL_TX_NEWSEQ); + desc->flags |= htole32(len << 16); + + if (RAL_RATE_IS_OFDM(rate)) + desc->flags |= htole32(RAL_TX_OFDM); + + desc->wme = htole16(RAL_LOGCWMAX(5) | RAL_LOGCWMIN(3) | RAL_AIFSN(2)); + desc->wme |= htole16(RAL_IVOFFSET(sizeof (struct ieee80211_frame))); + + /* + * Fill PLCP fields. + */ + desc->plcp_service = 4; + + len += 4; /* account for FCS */ + if (RAL_RATE_IS_OFDM(rate)) { + /* + * PLCP length field (LENGTH). + * From IEEE Std 802.11a-1999, pp. 14. + */ + plcp_length = len & 0xfff; + desc->plcp_length = htole16((plcp_length >> 6) << 8 | + (plcp_length & 0x3f)); + } else { + /* + * Long PLCP LENGTH field. + * From IEEE Std 802.11b-1999, pp. 16. + */ + plcp_length = (8 * len * 2) / rate; + remainder = (8 * len * 2) % rate; + if (remainder != 0) { + if (rate == 22 && (rate - remainder) / 16 != 0) + desc->plcp_service |= RAL_PLCP_LENGEXT; + plcp_length++; + } + desc->plcp_length = htole16(plcp_length); + } + + desc->plcp_signal = ural_plcp_signal(rate); + if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) + desc->plcp_signal |= 0x08; + + desc->iv = 0; + desc->eiv = 0; +} + +#define RAL_TX_TIMEOUT 5000 + +Static int +ural_tx_bcn(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) +{ + struct ural_tx_desc *desc; + usbd_xfer_handle xfer; + uint8_t cmd = 0; + usbd_status error; + uint8_t *buf; + int xferlen, rate; + + rate = IEEE80211_IS_CHAN_5GHZ(ni->ni_chan) ? 12 : 4; + + xfer = usbd_alloc_xfer(sc->sc_udev); + if (xfer == NULL) + return ENOMEM; + + /* xfer length needs to be a multiple of two! */ + xferlen = (RAL_TX_DESC_SIZE + m0->m_pkthdr.len + 1) & ~1; + + buf = usbd_alloc_buffer(xfer, xferlen); + if (buf == NULL) { + usbd_free_xfer(xfer); + return ENOMEM; + } + + usbd_setup_xfer(xfer, sc->sc_tx_pipeh, NULL, &cmd, sizeof cmd, + USBD_FORCE_SHORT_XFER, RAL_TX_TIMEOUT, NULL); + + error = usbd_sync_transfer(xfer); + if (error != 0) { + usbd_free_xfer(xfer); + return error; + } + + desc = (struct ural_tx_desc *)buf; + + m_copydata(m0, 0, m0->m_pkthdr.len, buf + RAL_TX_DESC_SIZE); + ural_setup_tx_desc(sc, desc, RAL_TX_IFS_NEWBACKOFF | RAL_TX_TIMESTAMP, + m0->m_pkthdr.len, rate); + + DPRINTFN(10, ("sending beacon frame len=%u rate=%u xfer len=%u\n", + m0->m_pkthdr.len, rate, xferlen)); + + usbd_setup_xfer(xfer, sc->sc_tx_pipeh, NULL, buf, xferlen, + USBD_FORCE_SHORT_XFER | USBD_NO_COPY, RAL_TX_TIMEOUT, NULL); + + error = usbd_sync_transfer(xfer); + usbd_free_xfer(xfer); + + return error; +} + +Static int +ural_tx_mgt(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) +{ + struct ieee80211com *ic = &sc->sc_ic; + struct ural_tx_desc *desc; + struct ural_tx_data *data; + struct ieee80211_frame *wh; + uint32_t flags = 0; + uint16_t dur; + usbd_status error; + int xferlen, rate; + + data = &sc->tx_data[0]; + desc = (struct ural_tx_desc *)data->buf; + + rate = IEEE80211_IS_CHAN_5GHZ(ni->ni_chan) ? 12 : 4; + + if (sc->sc_drvbpf != NULL) { + struct ural_tx_radiotap_header *tap = &sc->sc_txtap; + + tap->wt_flags = 0; + tap->wt_rate = rate; + tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); + tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); + tap->wt_antenna = sc->tx_ant; + + bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); + } + + data->m = m0; + data->ni = ni; + + wh = mtod(m0, struct ieee80211_frame *); + + if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { + flags |= RAL_TX_ACK; + + dur = ural_txtime(RAL_ACK_SIZE, rate, ic->ic_flags) + RAL_SIFS; + *(uint16_t *)wh->i_dur = htole16(dur); + + /* tell hardware to add timestamp for probe responses */ + if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == + IEEE80211_FC0_TYPE_MGT && + (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == + IEEE80211_FC0_SUBTYPE_PROBE_RESP) + flags |= RAL_TX_TIMESTAMP; + } + + m_copydata(m0, 0, m0->m_pkthdr.len, data->buf + RAL_TX_DESC_SIZE); + ural_setup_tx_desc(sc, desc, flags, m0->m_pkthdr.len, rate); + + /* xfer length needs to be a multiple of two! */ + xferlen = (RAL_TX_DESC_SIZE + m0->m_pkthdr.len + 1) & ~1; + + DPRINTFN(10, ("sending mgt frame len=%u rate=%u xfer len=%u\n", + m0->m_pkthdr.len, rate, xferlen)); + + usbd_setup_xfer(data->xfer, sc->sc_tx_pipeh, data, data->buf, + xferlen, USBD_FORCE_SHORT_XFER | USBD_NO_COPY, RAL_TX_TIMEOUT, + ural_txeof); + + error = usbd_transfer(data->xfer); + if (error != USBD_NORMAL_COMPLETION && error != USBD_IN_PROGRESS) + return error; + + sc->tx_queued++; + + return 0; +} + +Static int +ural_tx_data(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) +{ + struct ieee80211com *ic = &sc->sc_ic; + struct ural_tx_desc *desc; + struct ural_tx_data *data; + struct ieee80211_frame *wh; + struct ieee80211_key *k; + uint32_t flags = 0; + uint16_t dur; + usbd_status error; + int xferlen, rate; + + wh = mtod(m0, struct ieee80211_frame *); + + /* XXX should do automatic rate adaptation */ + if (ic->ic_fixed_rate != -1) + rate = ic->ic_bss->ni_rates.rs_rates[ic->ic_fixed_rate]; + else + rate = ni->ni_rates.rs_rates[ni->ni_txrate]; + + rate &= IEEE80211_RATE_VAL; + + if (wh->i_fc[1] & IEEE80211_FC1_WEP) { + k = ieee80211_crypto_encap(ic, ni, m0); + if (k == NULL) + return ENOBUFS; + + /* packet header may have moved, reset our local pointer */ + wh = mtod(m0, struct ieee80211_frame *); + } + + if (sc->sc_drvbpf != NULL) { + struct ural_tx_radiotap_header *tap = &sc->sc_txtap; + + tap->wt_flags = 0; + tap->wt_rate = rate; + tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); + tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); + tap->wt_antenna = sc->tx_ant; + + bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0); + } + + data = &sc->tx_data[0]; + desc = (struct ural_tx_desc *)data->buf; + + data->m = m0; + data->ni = ni; + + if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { + flags |= RAL_TX_ACK; + flags |= RAL_TX_RETRY(7); + + dur = ural_txtime(RAL_ACK_SIZE, ural_ack_rate(rate), + ic->ic_flags) + RAL_SIFS; + *(uint16_t *)wh->i_dur = htole16(dur); + } + + m_copydata(m0, 0, m0->m_pkthdr.len, data->buf + RAL_TX_DESC_SIZE); + ural_setup_tx_desc(sc, desc, flags, m0->m_pkthdr.len, rate); + + /* xfer length needs to be a multiple of two! */ + xferlen = (RAL_TX_DESC_SIZE + m0->m_pkthdr.len + 1) & ~1; + + DPRINTFN(10, ("sending data frame len=%u rate=%u xfer len=%u\n", + m0->m_pkthdr.len, rate, xferlen)); + + usbd_setup_xfer(data->xfer, sc->sc_tx_pipeh, data, data->buf, + xferlen, USBD_FORCE_SHORT_XFER | USBD_NO_COPY, RAL_TX_TIMEOUT, + ural_txeof); + + error = usbd_transfer(data->xfer); + if (error != USBD_NORMAL_COMPLETION && error != USBD_IN_PROGRESS) + return error; + + sc->tx_queued++; + + return 0; +} + +Static void +ural_start(struct ifnet *ifp) +{ + struct ural_softc *sc = ifp->if_softc; + struct ieee80211com *ic = &sc->sc_ic; + struct mbuf *m0; + struct ether_header *eh; + struct ieee80211_node *ni; + + for (;;) { + IF_POLL(&ic->ic_mgtq, m0); + if (m0 != NULL) { + if (sc->tx_queued >= RAL_TX_LIST_COUNT) { + ifp->if_flags |= IFF_OACTIVE; + break; + } + IF_DEQUEUE(&ic->ic_mgtq, m0); + + ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif; + m0->m_pkthdr.rcvif = NULL; + + if (ic->ic_rawbpf != NULL) + bpf_mtap(ic->ic_rawbpf, m0); + + if (ural_tx_mgt(sc, m0, ni) != 0) + break; + + } else { + if (ic->ic_state != IEEE80211_S_RUN) + break; + IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); + if (m0 == NULL) + break; + if (sc->tx_queued >= RAL_TX_LIST_COUNT) { + IFQ_DRV_PREPEND(&ifp->if_snd, m0); + ifp->if_flags |= IFF_OACTIVE; + break; + } + + if (m0->m_len < sizeof (struct ether_header) && + !(m0 = m_pullup(m0, sizeof (struct ether_header)))) + continue; + + eh = mtod(m0, struct ether_header *); + ni = ieee80211_find_txnode(ic, eh->ether_dhost); + if (ni == NULL) { + m_freem(m0); + continue; + } + BPF_MTAP(ifp, m0); + + m0 = ieee80211_encap(ic, m0, ni); + if (m0 == NULL) + continue; + + if (ic->ic_rawbpf != NULL) + bpf_mtap(ic->ic_rawbpf, m0); + + if (ural_tx_data(sc, m0, ni) != 0) { + ieee80211_free_node(ni); + ifp->if_oerrors++; + break; + } + } + + sc->sc_tx_timer = 5; + ifp->if_timer = 1; + } +} + +Static void +ural_watchdog(struct ifnet *ifp) +{ + struct ural_softc *sc = ifp->if_softc; + struct ieee80211com *ic = &sc->sc_ic; + + RAL_LOCK(sc); + + ifp->if_timer = 0; + + if (sc->sc_tx_timer > 0) { + if (--sc->sc_tx_timer == 0) { + device_printf(sc->sc_dev, "device timeout\n"); + /*ural_init(sc); XXX needs a process context! */ + ifp->if_oerrors++; + RAL_UNLOCK(sc); + return; + } + ifp->if_timer = 1; + } + + ieee80211_watchdog(ic); + + RAL_UNLOCK(sc); +} + +/* + * This function allows for fast channel switching in monitor mode (used by + * net-mgmt/kismet). In IBSS mode, we must explicitly reset the interface to + * generate a new beacon frame. + */ +Static int +ural_reset(struct ifnet *ifp) +{ + struct ural_softc *sc = ifp->if_softc; + struct ieee80211com *ic = &sc->sc_ic; + + if (ic->ic_opmode != IEEE80211_M_MONITOR) + return ENETRESET; + + ural_set_chan(sc, ic->ic_ibss_chan); + + return 0; +} + +Static int +ural_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) +{ + struct ural_softc *sc = ifp->if_softc; + struct ieee80211com *ic = &sc->sc_ic; + int error = 0; + + RAL_LOCK(sc); + + switch (cmd) { + case SIOCSIFFLAGS: + if (ifp->if_flags & IFF_UP) { + if (ifp->if_flags & IFF_RUNNING) + ural_update_promisc(sc); + else + ural_init(sc); + } else { + if (ifp->if_flags & IFF_RUNNING) + ural_stop(sc); + } + break; + + default: + error = ieee80211_ioctl(ic, cmd, data); + } + + if (error == ENETRESET) { + if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == + (IFF_UP | IFF_RUNNING)) + ural_init(sc); + error = 0; + } + + RAL_UNLOCK(sc); + + return error; +} + +Static void +ural_eeprom_read(struct ural_softc *sc, uint16_t addr, void *buf, int len) +{ + usb_device_request_t req; + usbd_status error; + + req.bmRequestType = UT_READ_VENDOR_DEVICE; + req.bRequest = RAL_READ_EEPROM; + USETW(req.wValue, 0); + USETW(req.wIndex, addr); + USETW(req.wLength, len); + + error = usbd_do_request(sc->sc_udev, &req, buf); + if (error != 0) { + printf("%s: could not read EEPROM: %s\n", + USBDEVNAME(sc->sc_dev), usbd_errstr(error)); + } +} + +Static uint16_t +ural_read(struct ural_softc *sc, uint16_t reg) +{ + usb_device_request_t req; + usbd_status error; + uint16_t val; + + req.bmRequestType = UT_READ_VENDOR_DEVICE; + req.bRequest = RAL_READ_MAC; + USETW(req.wValue, 0); + USETW(req.wIndex, reg); + USETW(req.wLength, sizeof (uint16_t)); + + error = usbd_do_request(sc->sc_udev, &req, &val); + if (error != 0) { + printf("%s: could not read MAC register: %s\n", + USBDEVNAME(sc->sc_dev), usbd_errstr(error)); + return 0; + } + + return le16toh(val); +} + +Static void +ural_read_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) +{ + usb_device_request_t req; + usbd_status error; + + req.bmRequestType = UT_READ_VENDOR_DEVICE; + req.bRequest = RAL_READ_MULTI_MAC; + USETW(req.wValue, 0); + USETW(req.wIndex, reg); + USETW(req.wLength, len); + + error = usbd_do_request(sc->sc_udev, &req, buf); + if (error != 0) { + printf("%s: could not read MAC register: %s\n", + USBDEVNAME(sc->sc_dev), usbd_errstr(error)); + return; + } +} + +Static void +ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val) +{ + usb_device_request_t req; + usbd_status error; + + req.bmRequestType = UT_WRITE_VENDOR_DEVICE; + req.bRequest = RAL_WRITE_MAC; + USETW(req.wValue, val); + USETW(req.wIndex, reg); + USETW(req.wLength, 0); + + error = usbd_do_request(sc->sc_udev, &req, NULL); + if (error != 0) { + printf("%s: could not write MAC register: %s\n", + USBDEVNAME(sc->sc_dev), usbd_errstr(error)); + } +} + +Static void +ural_write_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) +{ + usb_device_request_t req; + usbd_status error; + + req.bmRequestType = UT_WRITE_VENDOR_DEVICE; + req.bRequest = RAL_WRITE_MULTI_MAC; + USETW(req.wValue, 0); + USETW(req.wIndex, reg); + USETW(req.wLength, len); + + error = usbd_do_request(sc->sc_udev, &req, buf); + if (error != 0) { + printf("%s: could not write MAC register: %s\n", + USBDEVNAME(sc->sc_dev), usbd_errstr(error)); + } +} + +Static void +ural_bbp_write(struct ural_softc *sc, uint8_t reg, uint8_t val) +{ + uint16_t tmp; + int ntries; + + for (ntries = 0; ntries < 5; ntries++) { + if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) + break; + } + if (ntries == 5) { + printf("%s: could not write to BBP\n", USBDEVNAME(sc->sc_dev)); + return; + } + + tmp = reg << 8 | val; + ural_write(sc, RAL_PHY_CSR7, tmp); +} + +Static uint8_t +ural_bbp_read(struct ural_softc *sc, uint8_t reg) +{ + uint16_t val; + int ntries; + + val = RAL_BBP_WRITE | reg << 8; + ural_write(sc, RAL_PHY_CSR7, val); + + for (ntries = 0; ntries < 5; ntries++) { + if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) + break; + } + if (ntries == 5) { + printf("%s: could not read BBP\n", USBDEVNAME(sc->sc_dev)); + return 0; + } + + return ural_read(sc, RAL_PHY_CSR7) & 0xff; +} + +Static void +ural_rf_write(struct ural_softc *sc, uint8_t reg, uint32_t val) +{ + uint32_t tmp; + int ntries; + + for (ntries = 0; ntries < 5; ntries++) { + if (!(ural_read(sc, RAL_PHY_CSR10) & RAL_RF_LOBUSY)) + break; + } + if (ntries == 5) { + printf("%s: could not write to RF\n", USBDEVNAME(sc->sc_dev)); + return; + } + + tmp = RAL_RF_BUSY | RAL_RF_20BIT | (val & 0xfffff) << 2 | (reg & 0x3); + ural_write(sc, RAL_PHY_CSR9, tmp & 0xffff); + ural_write(sc, RAL_PHY_CSR10, tmp >> 16); + + /* remember last written value in sc */ + sc->rf_regs[reg] = val; + + DPRINTFN(15, ("RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff)); +} + +Static void +ural_set_chan(struct ural_softc *sc, struct ieee80211_channel *c) +{ +#define N(a) (sizeof (a) / sizeof ((a)[0])) + struct ieee80211com *ic = &sc->sc_ic; + uint8_t power, tmp; + u_int i, chan; + + chan = ieee80211_chan2ieee(ic, c); + if (chan == 0 || chan == IEEE80211_CHAN_ANY) + return; + + if (IEEE80211_IS_CHAN_2GHZ(c)) + power = min(sc->txpow[chan - 1], 31); + else + power = 31; + + DPRINTFN(2, ("setting channel to %u, txpower to %u\n", chan, power)); + + switch (sc->rf_rev) { + case RAL_RF_2522: + ural_rf_write(sc, RAL_RF1, 0x00814); + ural_rf_write(sc, RAL_RF2, ural_rf2522_r2[chan - 1]); + ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); + break; + + case RAL_RF_2523: + ural_rf_write(sc, RAL_RF1, 0x08804); + ural_rf_write(sc, RAL_RF2, ural_rf2523_r2[chan - 1]); + ural_rf_write(sc, RAL_RF3, power << 7 | 0x38044); + ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); + break; + + case RAL_RF_2524: + ural_rf_write(sc, RAL_RF1, 0x0c808); + ural_rf_write(sc, RAL_RF2, ural_rf2524_r2[chan - 1]); + ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); + ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); + break; + + case RAL_RF_2525: + ural_rf_write(sc, RAL_RF1, 0x08808); + ural_rf_write(sc, RAL_RF2, ural_rf2525_hi_r2[chan - 1]); + ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); + ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); + + ural_rf_write(sc, RAL_RF1, 0x08808); + ural_rf_write(sc, RAL_RF2, ural_rf2525_r2[chan - 1]); + ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); + ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); + break; + + case RAL_RF_2525E: + ural_rf_write(sc, RAL_RF1, 0x08808); + ural_rf_write(sc, RAL_RF2, ural_rf2525e_r2[chan - 1]); + ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); + ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00286 : 0x00282); + break; + + case RAL_RF_2526: + ural_rf_write(sc, RAL_RF2, ural_rf2526_hi_r2[chan - 1]); + ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); + ural_rf_write(sc, RAL_RF1, 0x08804); + + ural_rf_write(sc, RAL_RF2, ural_rf2526_r2[chan - 1]); + ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); + ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); + break; + + /* dual-band RF */ + case RAL_RF_5222: + for (i = 0; i < N(ural_rf5222); i++) + if (ural_rf5222[i].chan == chan) + break; + + if (i < N(ural_rf5222)) { + ural_rf_write(sc, RAL_RF1, ural_rf5222[i].r1); + ural_rf_write(sc, RAL_RF2, ural_rf5222[i].r2); + ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); + ural_rf_write(sc, RAL_RF4, ural_rf5222[i].r4); + } + break; + } + + if (ic->ic_opmode != IEEE80211_M_MONITOR && + ic->ic_state != IEEE80211_S_SCAN) { + /* set Japan filter bit for channel 14 */ + tmp = ural_bbp_read(sc, 70); + + tmp &= ~RAL_JAPAN_FILTER; + if (chan == 14) + tmp |= RAL_JAPAN_FILTER; + + ural_bbp_write(sc, 70, tmp); + + /* clear CRC errors */ + ural_read(sc, RAL_STA_CSR0); + } +#undef N +} + +#if 0 +/* + * Disable RF auto-tuning. + */ +Static void +ural_disable_rf_tune(struct ural_softc *sc) +{ + uint32_t tmp; + + if (sc->rf_rev != RAL_RF_2523) { + tmp = sc->rf_regs[RAL_RF1] & ~RAL_RF1_AUTOTUNE; + ural_rf_write(sc, RAL_RF1, tmp); + } + + tmp = sc->rf_regs[RAL_RF3] & ~RAL_RF3_AUTOTUNE; + ural_rf_write(sc, RAL_RF3, tmp); + + DPRINTFN(2, ("disabling RF autotune\n")); +} +#endif + +/* + * Refer to IEEE Std 802.11-1999 pp. 123 for more information on TSF + * synchronization. + */ +Static void +ural_enable_tsf_sync(struct ural_softc *sc) +{ + struct ieee80211com *ic = &sc->sc_ic; + uint16_t logcwmin, preload, tmp; + + /* first, disable TSF synchronization */ + ural_write(sc, RAL_TXRX_CSR19, 0); + + tmp = (16 * ic->ic_bss->ni_intval) << 4; + ural_write(sc, RAL_TXRX_CSR18, tmp); + + logcwmin = (ic->ic_opmode == IEEE80211_M_IBSS) ? 2 : 0; + preload = (ic->ic_opmode == IEEE80211_M_IBSS) ? 320 : 6; + tmp = logcwmin << 12 | preload; + ural_write(sc, RAL_TXRX_CSR20, tmp); + + /* finally, enable TSF synchronization */ + tmp = RAL_ENABLE_TSF | RAL_ENABLE_TBCN; + if (ic->ic_opmode == IEEE80211_M_STA) + tmp |= RAL_ENABLE_TSF_SYNC(1); + else + tmp |= RAL_ENABLE_TSF_SYNC(2) | RAL_ENABLE_BEACON_GENERATOR; + ural_write(sc, RAL_TXRX_CSR19, tmp); + + DPRINTF(("enabling TSF synchronization\n")); +} + +Static void +ural_set_bssid(struct ural_softc *sc, uint8_t *bssid) +{ + uint16_t tmp; + + tmp = bssid[0] | bssid[1] << 8; + ural_write(sc, RAL_MAC_CSR5, tmp); + + tmp = bssid[2] | bssid[3] << 8; + ural_write(sc, RAL_MAC_CSR6, tmp); + + tmp = bssid[4] | bssid[5] << 8; + ural_write(sc, RAL_MAC_CSR7, tmp); + + DPRINTF(("setting BSSID to %6D\n", bssid, ":")); +} + +Static void +ural_set_macaddr(struct ural_softc *sc, uint8_t *addr) +{ + uint16_t tmp; + + tmp = addr[0] | addr[1] << 8; + ural_write(sc, RAL_MAC_CSR2, tmp); + + tmp = addr[2] | addr[3] << 8; + ural_write(sc, RAL_MAC_CSR3, tmp); + + tmp = addr[4] | addr[5] << 8; + ural_write(sc, RAL_MAC_CSR4, tmp); + + DPRINTF(("setting MAC address to %6D\n", addr, ":")); +} + +Static void +ural_update_promisc(struct ural_softc *sc) +{ + struct ifnet *ifp = sc->sc_ic.ic_ifp; + uint32_t tmp; + + tmp = ural_read(sc, RAL_TXRX_CSR2); + + tmp &= ~RAL_DROP_NOT_TO_ME; + if (!(ifp->if_flags & IFF_PROMISC)) + tmp |= RAL_DROP_NOT_TO_ME; + + ural_write(sc, RAL_TXRX_CSR2, tmp); + + DPRINTF(("%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? + "entering" : "leaving")); +} + +Static const char * +ural_get_rf(int rev) +{ + switch (rev) { + case RAL_RF_2522: return "RT2522"; + case RAL_RF_2523: return "RT2523"; + case RAL_RF_2524: return "RT2524"; + case RAL_RF_2525: return "RT2525"; + case RAL_RF_2525E: return "RT2525e"; + case RAL_RF_2526: return "RT2526"; + case RAL_RF_5222: return "RT5222"; + default: return "unknown"; + } +} + +Static void +ural_read_eeprom(struct ural_softc *sc) +{ + struct ieee80211com *ic = &sc->sc_ic; + uint16_t val; + + ural_eeprom_read(sc, RAL_EEPROM_CONFIG0, &val, 2); + val = le16toh(val); + sc->rf_rev = (val >> 11) & 0x7; + sc->hw_radio = (val >> 10) & 0x1; + sc->led_mode = (val >> 6) & 0x7; + sc->rx_ant = (val >> 4) & 0x3; + sc->tx_ant = (val >> 2) & 0x3; + sc->nb_ant = val & 0x3; + + /* read MAC address */ + ural_eeprom_read(sc, RAL_EEPROM_ADDRESS, ic->ic_myaddr, 6); + + /* read default values for BBP registers */ + ural_eeprom_read(sc, RAL_EEPROM_BBP_BASE, sc->bbp_prom, 2 * 16); + + /* read Tx power for all b/g channels */ + ural_eeprom_read(sc, RAL_EEPROM_TXPOWER, sc->txpow, 14); +} + +Static int +ural_bbp_init(struct ural_softc *sc) +{ +#define N(a) (sizeof (a) / sizeof ((a)[0])) + int i, ntries; + + /* wait for BBP to be ready */ + for (ntries = 0; ntries < 100; ntries++) { + if (ural_bbp_read(sc, RAL_BBP_VERSION) != 0) + break; + DELAY(1000); + } + if (ntries == 100) { + device_printf(sc->sc_dev, "timeout waiting for BBP\n"); + return EIO; + } + + /* initialize BBP registers to default values */ + for (i = 0; i < N(ural_def_bbp); i++) + ural_bbp_write(sc, ural_def_bbp[i].reg, ural_def_bbp[i].val); + +#if 0 + /* initialize BBP registers to values stored in EEPROM */ + for (i = 0; i < 16; i++) { + if (sc->bbp_prom[i].reg == 0xff) + continue; + ural_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); + } +#endif + + return 0; +#undef N +} + +Static void +ural_set_txantenna(struct ural_softc *sc, int antenna) +{ + uint16_t tmp; + uint8_t tx; + + tx = ural_bbp_read(sc, RAL_BBP_TX) & ~RAL_BBP_ANTMASK; + if (antenna == 1) + tx |= RAL_BBP_ANTA; + else if (antenna == 2) + tx |= RAL_BBP_ANTB; + else + tx |= RAL_BBP_DIVERSITY; + + /* need to force I/Q flip for RF 2525e, 2526 and 5222 */ + if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526 || + sc->rf_rev == RAL_RF_5222) + tx |= RAL_BBP_FLIPIQ; + + ural_bbp_write(sc, RAL_BBP_TX, tx); + + /* update values in PHY_CSR5 and PHY_CSR6 */ + tmp = ural_read(sc, RAL_PHY_CSR5) & ~0x7; + ural_write(sc, RAL_PHY_CSR5, tmp | (tx & 0x7)); + + tmp = ural_read(sc, RAL_PHY_CSR6) & ~0x7; + ural_write(sc, RAL_PHY_CSR6, tmp | (tx & 0x7)); +} + +Static void +ural_set_rxantenna(struct ural_softc *sc, int antenna) +{ + uint8_t rx; + + rx = ural_bbp_read(sc, RAL_BBP_RX) & ~RAL_BBP_ANTMASK; + if (antenna == 1) + rx |= RAL_BBP_ANTA; + else if (antenna == 2) + rx |= RAL_BBP_ANTB; + else + rx |= RAL_BBP_DIVERSITY; + + /* need to force no I/Q flip for RF 2525e and 2526 */ + if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526) + rx &= ~RAL_BBP_FLIPIQ; + + ural_bbp_write(sc, RAL_BBP_RX, rx); +} + +Static void +ural_init(void *priv) +{ +#define N(a) (sizeof (a) / sizeof ((a)[0])) + struct ural_softc *sc = priv; + struct ieee80211com *ic = &sc->sc_ic; + struct ifnet *ifp = ic->ic_ifp; + struct ieee80211_key *wk; + struct ural_rx_data *data; + uint16_t sta[11], tmp; + usbd_status error; + int i, ntries; + + ural_stop(sc); + + /* initialize MAC registers to default values */ + for (i = 0; i < N(ural_def_mac); i++) + ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val); + + /* wait for BBP and RF to wake up (this can take a long time!) */ + for (ntries = 0; ntries < 100; ntries++) { + tmp = ural_read(sc, RAL_MAC_CSR17); + if ((tmp & (RAL_BBP_AWAKE | RAL_RF_AWAKE)) == + (RAL_BBP_AWAKE | RAL_RF_AWAKE)) + break; + DELAY(1000); + } + if (ntries == 100) { + printf("%s: timeout waiting for BBP/RF to wakeup\n", + USBDEVNAME(sc->sc_dev)); + goto fail; + } + + /* we're ready! */ + ural_write(sc, RAL_MAC_CSR1, RAL_HOST_READY); + + /* set supported basic rates (1, 2, 6, 12, 24) */ + ural_write(sc, RAL_TXRX_CSR11, 0x153); + + if (ural_bbp_init(sc) != 0) + goto fail; + + /* set default BSS channel */ + ic->ic_bss->ni_chan = ic->ic_ibss_chan; + ural_set_chan(sc, ic->ic_bss->ni_chan); + + /* clear statistic registers (STA_CSR0 to STA_CSR10) */ + ural_read_multi(sc, RAL_STA_CSR0, sta, sizeof sta); + + ural_set_txantenna(sc, sc->tx_ant); + ural_set_rxantenna(sc, sc->rx_ant); + + IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); + ural_set_macaddr(sc, ic->ic_myaddr); + + /* + * Copy WEP keys into adapter's memory (SEC_CSR0 to SEC_CSR31). + */ + for (i = 0; i < IEEE80211_WEP_NKID; i++) { + wk = &ic->ic_crypto.cs_nw_keys[i]; + ural_write_multi(sc, wk->wk_keyix * IEEE80211_KEYBUF_SIZE + + RAL_SEC_CSR0, wk->wk_key, IEEE80211_KEYBUF_SIZE); + } + + /* + * Open Tx and Rx USB bulk pipes. + */ + error = usbd_open_pipe(sc->sc_iface, sc->sc_tx_no, USBD_EXCLUSIVE_USE, + &sc->sc_tx_pipeh); + if (error != 0) { + printf("%s: could not open Tx pipe: %s\n", + USBDEVNAME(sc->sc_dev), usbd_errstr(error)); + goto fail; + } + + error = usbd_open_pipe(sc->sc_iface, sc->sc_rx_no, USBD_EXCLUSIVE_USE, + &sc->sc_rx_pipeh); + if (error != 0) { + printf("%s: could not open Rx pipe: %s\n", + USBDEVNAME(sc->sc_dev), usbd_errstr(error)); + goto fail; + } + + /* + * Allocate Tx and Rx xfer queues. + */ + error = ural_alloc_tx_list(sc); + if (error != 0) { + printf("%s: could not allocate Tx list\n", + USBDEVNAME(sc->sc_dev)); + goto fail; + } + + error = ural_alloc_rx_list(sc); + if (error != 0) { + printf("%s: could not allocate Rx list\n", + USBDEVNAME(sc->sc_dev)); + goto fail; + } + + /* + * Start up the receive pipe. + */ + for (i = 0; i < RAL_RX_LIST_COUNT; i++) { + data = &sc->rx_data[i]; + + usbd_setup_xfer(data->xfer, sc->sc_rx_pipeh, data, data->buf, + MCLBYTES, USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, ural_rxeof); + usbd_transfer(data->xfer); + } + + /* kick Rx */ + tmp = RAL_DROP_PHY | RAL_DROP_CRC; + if (ic->ic_opmode != IEEE80211_M_MONITOR) { + tmp |= RAL_DROP_CTL | RAL_DROP_BAD_VERSION; + if (ic->ic_opmode != IEEE80211_M_HOSTAP) + tmp |= RAL_DROP_TODS; + if (!(ifp->if_flags & IFF_PROMISC)) + tmp |= RAL_DROP_NOT_TO_ME; + } + ural_write(sc, RAL_TXRX_CSR2, tmp); + + ifp->if_flags &= ~IFF_OACTIVE; + ifp->if_flags |= IFF_RUNNING; + + if (ic->ic_opmode == IEEE80211_M_MONITOR) + ieee80211_new_state(ic, IEEE80211_S_RUN, -1); + else + ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); + + return; + +fail: ural_stop(sc); +#undef N +} + +Static void +ural_stop(void *priv) +{ + struct ural_softc *sc = priv; + struct ieee80211com *ic = &sc->sc_ic; + struct ifnet *ifp = ic->ic_ifp; + + ieee80211_new_state(ic, IEEE80211_S_INIT, -1); + + sc->sc_tx_timer = 0; + ifp->if_timer = 0; + ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); + + /* disable Rx */ + ural_write(sc, RAL_TXRX_CSR2, RAL_DISABLE_RX); + + /* reset ASIC and BBP (but won't reset MAC registers!) */ + ural_write(sc, RAL_MAC_CSR1, RAL_RESET_ASIC | RAL_RESET_BBP); + ural_write(sc, RAL_MAC_CSR1, 0); + + if (sc->sc_rx_pipeh != NULL) { + usbd_abort_pipe(sc->sc_rx_pipeh); + usbd_close_pipe(sc->sc_rx_pipeh); + sc->sc_rx_pipeh = NULL; + } + + if (sc->sc_tx_pipeh != NULL) { + usbd_abort_pipe(sc->sc_tx_pipeh); + usbd_close_pipe(sc->sc_tx_pipeh); + sc->sc_tx_pipeh = NULL; + } + + ural_free_rx_list(sc); + ural_free_tx_list(sc); +} + +DRIVER_MODULE(ural, uhub, ural_driver, ural_devclass, usbd_driver_load, 0); diff --git a/sys/dev/usb/if_uralreg.h b/sys/dev/usb/if_uralreg.h new file mode 100644 index 0000000..8062fa5 --- /dev/null +++ b/sys/dev/usb/if_uralreg.h @@ -0,0 +1,200 @@ +/* $FreeBSD$ */ + +/*- + * Copyright (c) 2005 + * Damien Bergamini <damien.bergamini@free.fr> + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#define RAL_RX_DESC_SIZE (sizeof (struct ural_rx_desc)) +#define RAL_TX_DESC_SIZE (sizeof (struct ural_tx_desc)) + +#define RAL_CONFIG_NO 1 +#define RAL_IFACE_INDEX 0 + +#define RAL_WRITE_MAC 0x02 +#define RAL_READ_MAC 0x03 +#define RAL_WRITE_MULTI_MAC 0x06 +#define RAL_READ_MULTI_MAC 0x07 +#define RAL_READ_EEPROM 0x09 + +/* + * MAC registers. + */ +#define RAL_MAC_CSR0 0x0400 /* ASIC Version */ +#define RAL_MAC_CSR1 0x0402 /* System control */ +#define RAL_MAC_CSR2 0x0404 /* MAC addr0 */ +#define RAL_MAC_CSR3 0x0406 /* MAC addr1 */ +#define RAL_MAC_CSR4 0x0408 /* MAC addr2 */ +#define RAL_MAC_CSR5 0x040a /* BSSID0 */ +#define RAL_MAC_CSR6 0x040c /* BSSID1 */ +#define RAL_MAC_CSR7 0x040e /* BSSID2 */ +#define RAL_MAC_CSR8 0x0410 /* Max frame length */ +#define RAL_MAC_CSR9 0x0412 /* Timer control */ +#define RAL_MAC_CSR11 0x0416 /* IFS */ +#define RAL_MAC_CSR12 0x0418 /* EIFS */ +#define RAL_MAC_CSR13 0x041a /* Power mode0 */ +#define RAL_MAC_CSR14 0x041c /* Power mode1 */ +#define RAL_MAC_CSR15 0x041e /* Power saving transition0 */ +#define RAL_MAC_CSR16 0x0420 /* Power saving transition1 */ +#define RAL_MAC_CSR17 0x0422 /* Power state control */ +#define RAL_MAC_CSR18 0x0424 /* Auto wake-up control */ +#define RAL_MAC_CSR19 0x0426 /* GPIO control */ +#define RAL_MAC_CSR20 0x0428 /* LED control0 */ +#define RAL_MAC_CSR22 0x042c /* XXX not documented */ + +/* + * Tx/Rx Registers. + */ +#define RAL_TXRX_CSR0 0x0440 /* Security control */ +#define RAL_TXRX_CSR2 0x0444 /* Rx control */ +#define RAL_TXRX_CSR5 0x044a /* CCK Tx BBP ID0 */ +#define RAL_TXRX_CSR6 0x044c /* CCK Tx BBP ID1 */ +#define RAL_TXRX_CSR7 0x044e /* OFDM Tx BBP ID0 */ +#define RAL_TXRX_CSR8 0x0450 /* OFDM Tx BBP ID1 */ +#define RAL_TXRX_CSR11 0x0456 /* Auto responder basic rate */ +#define RAL_TXRX_CSR18 0x0464 /* Beacon interval */ +#define RAL_TXRX_CSR19 0x0466 /* Beacon/sync control */ +#define RAL_TXRX_CSR20 0x0468 /* Beacon alignment */ +#define RAL_TXRX_CSR21 0x046a /* XXX not documented */ + +/* + * Security registers. + */ +#define RAL_SEC_CSR0 0x0480 /* Shared key 0, word 0 */ + +/* + * PHY registers. + */ +#define RAL_PHY_CSR2 0x04c4 /* Tx MAC configuration */ +#define RAL_PHY_CSR4 0x04c8 /* Interface configuration */ +#define RAL_PHY_CSR5 0x04ca /* BBP Pre-Tx CCK */ +#define RAL_PHY_CSR6 0x04cc /* BBP Pre-Tx OFDM */ +#define RAL_PHY_CSR7 0x04ce /* BBP serial control */ +#define RAL_PHY_CSR8 0x04d0 /* BBP serial status */ +#define RAL_PHY_CSR9 0x04d2 /* RF serial control0 */ +#define RAL_PHY_CSR10 0x04d4 /* RF serial control1 */ + +/* + * Statistics registers. + */ +#define RAL_STA_CSR0 0x04e0 /* FCS error */ + + +#define RAL_DISABLE_RX (1 << 0) +#define RAL_DROP_CRC (1 << 1) +#define RAL_DROP_PHY (1 << 2) +#define RAL_DROP_CTL (1 << 3) +#define RAL_DROP_NOT_TO_ME (1 << 4) +#define RAL_DROP_TODS (1 << 5) +#define RAL_DROP_BAD_VERSION (1 << 6) +#define RAL_DROP_MULTICAST (1 << 9) +#define RAL_DROP_BROADCAST (1 << 10) + +#define RAL_RESET_ASIC (1 << 0) +#define RAL_RESET_BBP (1 << 1) +#define RAL_HOST_READY (1 << 2) + +#define RAL_ENABLE_TSF (1 << 0) +#define RAL_ENABLE_TSF_SYNC(x) (((x) & 0x3) << 1) +#define RAL_ENABLE_TBCN (1 << 3) +#define RAL_ENABLE_BEACON_GENERATOR (1 << 4) + +#define RAL_RF_AWAKE (3 << 7) +#define RAL_BBP_AWAKE (3 << 5) + +#define RAL_BBP_WRITE (1 << 15) +#define RAL_BBP_BUSY (1 << 0) + +#define RAL_RF1_AUTOTUNE 0x08000 +#define RAL_RF3_AUTOTUNE 0x00040 + +#define RAL_RF_2522 0x00 +#define RAL_RF_2523 0x01 +#define RAL_RF_2524 0x02 +#define RAL_RF_2525 0x03 +#define RAL_RF_2525E 0x04 +#define RAL_RF_2526 0x05 +/* dual-band RF */ +#define RAL_RF_5222 0x10 + +#define RAL_BBP_VERSION 0 +#define RAL_BBP_TX 2 +#define RAL_BBP_RX 14 + +#define RAL_BBP_ANTA 0x00 +#define RAL_BBP_DIVERSITY 0x01 +#define RAL_BBP_ANTB 0x02 +#define RAL_BBP_ANTMASK 0x03 +#define RAL_BBP_FLIPIQ 0x04 + +#define RAL_JAPAN_FILTER 0x08 + +struct ural_tx_desc { + uint32_t flags; +#define RAL_TX_RETRY(x) ((x) << 4) +#define RAL_TX_MORE_FRAG (1 << 8) +#define RAL_TX_ACK (1 << 9) +#define RAL_TX_TIMESTAMP (1 << 10) +#define RAL_TX_OFDM (1 << 11) +#define RAL_TX_NEWSEQ (1 << 12) + +#define RAL_TX_IFS_MASK 0x00006000 +#define RAL_TX_IFS_BACKOFF (0 << 13) +#define RAL_TX_IFS_SIFS (1 << 13) +#define RAL_TX_IFS_NEWBACKOFF (2 << 13) +#define RAL_TX_IFS_NONE (3 << 13) + + uint16_t wme; +#define RAL_LOGCWMAX(x) (((x) & 0xf) << 12) +#define RAL_LOGCWMIN(x) (((x) & 0xf) << 8) +#define RAL_AIFSN(x) (((x) & 0x3) << 6) +#define RAL_IVOFFSET(x) (((x) & 0x3f)) + + uint16_t reserved1; + uint8_t plcp_signal; + uint8_t plcp_service; +#define RAL_PLCP_LENGEXT 0x80 + + uint16_t plcp_length; + uint32_t iv; + uint32_t eiv; +} __packed; + +struct ural_rx_desc { + uint32_t flags; +#define RAL_RX_CRC_ERROR (1 << 5) +#define RAL_RX_PHY_ERROR (1 << 7) + + uint8_t rate; + uint8_t rssi; + uint16_t reserved; + + uint32_t iv; + uint32_t eiv; +} __packed; + +#define RAL_RF_LOBUSY (1 << 15) +#define RAL_RF_BUSY (1 << 31) +#define RAL_RF_20BIT (20 << 24) + +#define RAL_RF1 0 +#define RAL_RF2 2 +#define RAL_RF3 1 +#define RAL_RF4 3 + +#define RAL_EEPROM_ADDRESS 0x0004 +#define RAL_EEPROM_TXPOWER 0x003c +#define RAL_EEPROM_CONFIG0 0x0016 +#define RAL_EEPROM_BBP_BASE 0x001c diff --git a/sys/dev/usb/if_uralvar.h b/sys/dev/usb/if_uralvar.h new file mode 100644 index 0000000..225a43a --- /dev/null +++ b/sys/dev/usb/if_uralvar.h @@ -0,0 +1,140 @@ +/* $FreeBSD$ */ + +/*- + * Copyright (c) 2005 + * Damien Bergamini <damien.bergamini@free.fr> + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#define RAL_RX_LIST_COUNT 1 +#define RAL_TX_LIST_COUNT 1 + +struct ural_rx_radiotap_header { + struct ieee80211_radiotap_header wr_ihdr; + uint8_t wr_flags; + uint16_t wr_chan_freq; + uint16_t wr_chan_flags; + uint8_t wr_antenna; + uint8_t wr_antsignal; +}; + +#define RAL_RX_RADIOTAP_PRESENT \ + ((1 << IEEE80211_RADIOTAP_FLAGS) | \ + (1 << IEEE80211_RADIOTAP_CHANNEL) | \ + (1 << IEEE80211_RADIOTAP_ANTENNA) | \ + (1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL)) + +struct ural_tx_radiotap_header { + struct ieee80211_radiotap_header wt_ihdr; + uint8_t wt_flags; + uint8_t wt_rate; + uint16_t wt_chan_freq; + uint16_t wt_chan_flags; + uint8_t wt_antenna; +}; + +#define RAL_TX_RADIOTAP_PRESENT \ + ((1 << IEEE80211_RADIOTAP_FLAGS) | \ + (1 << IEEE80211_RADIOTAP_RATE) | \ + (1 << IEEE80211_RADIOTAP_CHANNEL) | \ + (1 << IEEE80211_RADIOTAP_ANTENNA)) + +struct ural_softc; + +struct ural_tx_data { + struct ural_softc *sc; + usbd_xfer_handle xfer; + uint8_t *buf; + struct mbuf *m; + struct ieee80211_node *ni; +}; + +struct ural_rx_data { + struct ural_softc *sc; + usbd_xfer_handle xfer; + uint8_t *buf; + struct mbuf *m; +}; + +struct ural_softc { + struct arpcom sc_arp; + struct ieee80211com sc_ic; + int (*sc_newstate)(struct ieee80211com *, + enum ieee80211_state, int); + USBBASEDEVICE sc_dev; + usbd_device_handle sc_udev; + usbd_interface_handle sc_iface; + + uint8_t sc_rx_no; + uint8_t sc_tx_no; + + uint32_t asic_rev; + uint8_t rf_rev; + + usbd_pipe_handle sc_rx_pipeh; + usbd_pipe_handle sc_tx_pipeh; + + enum ieee80211_state sc_state; + struct usb_task sc_task; + + struct ural_rx_data rx_data[RAL_RX_LIST_COUNT]; + struct ural_tx_data tx_data[RAL_TX_LIST_COUNT]; + int tx_queued; + + struct ieee80211_beacon_offsets sc_bo; + + struct mtx sc_mtx; + + struct callout scan_ch; + + int sc_tx_timer; + + uint32_t rf_regs[4]; + uint8_t txpow[14]; + + struct { + uint8_t val; + uint8_t reg; + } __packed bbp_prom[16]; + + int led_mode; + int hw_radio; + int rx_ant; + int tx_ant; + int nb_ant; + + struct bpf_if *sc_drvbpf; + + union { + struct ural_rx_radiotap_header th; + uint8_t pad[64]; + } sc_rxtapu; +#define sc_rxtap sc_rxtapu.th + int sc_rxtap_len; + + union { + struct ural_tx_radiotap_header th; + uint8_t pad[64]; + } sc_txtapu; +#define sc_txtap sc_txtapu.th + int sc_txtap_len; +}; + +#if 0 +#define RAL_LOCK(sc) mtx_lock(&(sc)->sc_mtx) +#define RAL_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) +#else +#define RAL_LOCK(sc) do { ((sc) = (sc)); mtx_lock(&Giant); } while (0) +#define RAL_UNLOCK(sc) mtx_unlock(&Giant) +#endif diff --git a/sys/dev/usb/usbdevs b/sys/dev/usb/usbdevs index 30f0bda..722ddd4 100644 --- a/sys/dev/usb/usbdevs +++ b/sys/dev/usb/usbdevs @@ -452,6 +452,7 @@ vendor GREENHOUSE 0x0a6b GREENHOUSE vendor GEOCAST 0x0a79 Geocast vendor NEODIO 0x0aec Neodio vendor VODAFONE 0x0af0 Vodafone +vendor ASUS 0x0b05 ASUS vendor TODOS 0x0b0c Todos Data System vendor SIIG2 0x0b39 SIIG vendor TEKRAM 0x0b3b Tekram @@ -499,8 +500,11 @@ vendor CREATIVE2 0x1292 Creative Labs vendor BELKIN2 0x1293 Belkin vendor AINCOMM 0x12fd Aincomm vendor MOBILITY 0x1342 Mobility +vendor LINKSYS4 0x13b1 Linksys vendor SHARK 0x13d2 Shark vendor SILICOM 0x1485 Silicom +vendor RALINK 0x148f Ralink Technology +vendor CONCEPTRONIC 0x14b2 Conceptronic vendor SILICONPORTALS 0x1527 Silicon Portals vendor SOHOWARE 0x15e8 SOHOware vendor UMAX 0x1606 UMAX @@ -643,6 +647,9 @@ product ASAHIOPTICAL OPTIO330 0x0006 Digital camera /* ASIX Electronics products */ product ASIX AX88172 0x1720 10/100 ethernet +/* ASUS products */ +product ASUS WL167G 0x1707 WL-167g wireless adapter + /* ATen products */ product ATEN UC1284 0x2001 Parallel printer product ATEN UC10T 0x2002 10Mbps ethernet @@ -742,6 +749,9 @@ product FTDI SEMC_DSS20 0xfc82 SEMC DSS-20 SyncStation product CSR BT_DONGLE 0x0001 Bluetooth USB dongle product CSR CSRDFU 0xffff USB Bluetooth Device in DFU State +/* Conceptronic products */ +product CONCEPTRONIC C54U 0x3c02 C54U wireless adapter + /* CTX products */ product CTX EX1300 0x9999 Ex1300 hub @@ -776,6 +786,7 @@ product DIGI ACCELEPORT8 0x0008 AccelePort USB 8 /*product DLINK DSBS25 0x0100 DSB-S25 serial*/ product DLINK DUBE100 0x1a00 10/100 ethernet product DLINK DSB650TX4 0x200c 10/100 ethernet +product DLINK DWLG122 0x3c00 DWL-G122 b1 wireless adapter product DLINK DSB650C 0x4000 10Mbps ethernet product DLINK DSB650TX1 0x4001 10/100 ethernet product DLINK DSB650TX 0x4002 10/100 ethernet @@ -1061,6 +1072,8 @@ product LINKSYS USB10TX2 0x400b USB10TX product LINKSYS2 WUSB11 0x2219 WUSB11 Wireless adapter product LINKSYS2 USB200M 0x2226 USB 2.0 10/100 ethernet product LINKSYS3 WUSB11v28 0x2233 WUSB11 v2.8 wireless adapter +product LINKSYS4 WUSB54G 0x000d WUSB54G wireless adapter +product LINKSYS4 WUSB54GP 0x0011 WUSB54GP wireless adapter /* Logitech products */ product LOGITECH M2452 0x0203 M2452 keyboard @@ -1118,6 +1131,7 @@ product MELCO LUA2TX5 0x0009 LUA2-TX Ethernet product MELCO LUAKTX 0x0012 LUA-KTX Ethernet product MELCO DUBPXXG 0x001c USB-IDE Bridge: DUB-PxxG product MELCO LUAU2KTX 0x003d LUA-U2-KTX Ethernet +product MELCO KG54 0x0066 KG54 wireless adapter /* Metricom products */ product METRICOM RICOCHET_GS 0x0001 Ricochet GS @@ -1317,6 +1331,10 @@ product QUICKSHOT STRIKEPAD 0x6238 USB StrikePad /* Rainbow Technologies products */ product RAINBOW IKEY2000 0x1200 i-Key 2000 +/* Ralink Technology products */ +product RALINK RT2570 0x1706 RT2500USB wireless adapter +product RALINK RT2570_2 0x2570 RT2500USB wireless adapter + /* ReakTek products */ product REALTEK USBKR100 0x8150 USBKR100 USB Ethernet (GREEN HOUSE) @@ -1400,6 +1418,7 @@ product SMARTBRIDGES SMARTNIC 0x0003 smartNIC 2 PnP ethernet product SMC 2102USB 0x0100 10Mbps ethernet product SMC 2202USB 0x0200 10/100 ethernet product SMC 2206USB 0x0201 EZ Connect USB Ethernet +product SMC 2862WG 0xee13 EZ Connect wireless adapter product SMC2 2020HUB 0x2020 USB Hub product SMC3 2662WUSB 0xa002 2662W-AR Wireless diff --git a/sys/modules/Makefile b/sys/modules/Makefile index 06ac18c..b99c6aa 100644 --- a/sys/modules/Makefile +++ b/sys/modules/Makefile @@ -116,8 +116,10 @@ SUBDIR= ${_3dfx} \ ipfw \ ip_mroute_mod \ ${_ips} \ + ipw \ isp \ ispfw \ + iwi \ joy \ kue \ lge \ @@ -181,6 +183,7 @@ SUBDIR= ${_3dfx} \ procfs \ pseudofs \ ${_pst} \ + ral \ ${_random} \ ${_ray} \ rc \ @@ -243,6 +246,7 @@ SUBDIR= ${_3dfx} \ ums \ unionfs \ uplcom \ + ural \ urio \ usb \ uscanner \ diff --git a/sys/modules/ipw/Makefile b/sys/modules/ipw/Makefile new file mode 100644 index 0000000..8ef8135 --- /dev/null +++ b/sys/modules/ipw/Makefile @@ -0,0 +1,8 @@ +# $FreeBSD$ + +.PATH: ${.CURDIR}/../../dev/ipw + +KMOD = if_ipw +SRCS = if_ipw.c opt_bdg.h device_if.h bus_if.h pci_if.h + +.include <bsd.kmod.mk> diff --git a/sys/modules/iwi/Makefile b/sys/modules/iwi/Makefile new file mode 100644 index 0000000..a5a9605 --- /dev/null +++ b/sys/modules/iwi/Makefile @@ -0,0 +1,8 @@ +# $FreeBSD$ + +.PATH: ${.CURDIR}/../../dev/iwi + +KMOD = if_iwi +SRCS = if_iwi.c opt_bdg.h device_if.h bus_if.h pci_if.h + +.include <bsd.kmod.mk> diff --git a/sys/modules/ral/Makefile b/sys/modules/ral/Makefile new file mode 100644 index 0000000..002d1e8 --- /dev/null +++ b/sys/modules/ral/Makefile @@ -0,0 +1,9 @@ +# $FreeBSD$ + +.PATH: ${.CURDIR}/../../dev/ral + +KMOD = if_ral +SRCS = if_ral.c if_ralrate.c if_ral_pccard.c if_ral_pci.c \ + opt_bdg.h device_if.h bus_if.h pci_if.h card_if.h pccarddevs.h + +.include <bsd.kmod.mk> diff --git a/sys/modules/ural/Makefile b/sys/modules/ural/Makefile new file mode 100644 index 0000000..e347e05 --- /dev/null +++ b/sys/modules/ural/Makefile @@ -0,0 +1,8 @@ +# $FreeBSD$ + +.PATH: ${.CURDIR}/../../dev/usb + +KMOD = if_ural +SRCS = if_ural.c opt_bdg.h opt_usb.h device_if.h bus_if.h usbdevs.h + +.include <bsd.kmod.mk> |
