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-rw-r--r--release/texts/HARDWARE.TXT12
-rw-r--r--release/texts/alpha/RELNOTES.TXT12
-rw-r--r--release/texts/i386/RELNOTES.TXT12
-rw-r--r--share/man/man4/Makefile1
-rw-r--r--share/man/man4/nge.4205
-rw-r--r--sys/conf/NOTES5
-rw-r--r--sys/conf/files2
-rw-r--r--sys/dev/mii/miidevs2
-rw-r--r--sys/dev/mii/nsgphy.c475
-rw-r--r--sys/dev/mii/nsgphyreg.h168
-rw-r--r--sys/dev/nge/if_nge.c2006
-rw-r--r--sys/dev/nge/if_ngereg.h706
-rw-r--r--sys/i386/conf/NOTES5
-rw-r--r--sys/modules/Makefile4
-rw-r--r--sys/modules/mii/Makefile2
-rw-r--r--sys/modules/nge/Makefile12
-rw-r--r--usr.sbin/sade/devices.c1
-rw-r--r--usr.sbin/sysinstall/devices.c1
18 files changed, 3627 insertions, 4 deletions
diff --git a/release/texts/HARDWARE.TXT b/release/texts/HARDWARE.TXT
index a83c3c5..322f097 100644
--- a/release/texts/HARDWARE.TXT
+++ b/release/texts/HARDWARE.TXT
@@ -119,6 +119,7 @@ ie0 300 10 dyn d0000 AT&T StarLAN 10 and EN100;
lnc0 280 10 n/a dyn Lance/PCnet cards
(Isolan, Novell NE2100, NE32-VL,
some PCnet-PCI cards)
+nge0 dyn dyn n/a dyn NatSemi DP83820 gigabit ethernet
pcn0 dyn dyn n/a dyn AMD PCnet/FAST, PCnet/FAST+,
PCnet/FAST III, PCnet/PRO, PCnet/Home,
and HomePNA cards
@@ -126,7 +127,9 @@ rl0 dyn dyn n/a dyn RealTek 8129/8139 Fast Ethernet
sf0 dyn dyn n/a dyn Adaptec AIC-6915 Fast Ethernet
sis0 dyn dyn n/a dyn SiS 900/SiS 7016 Fast Ethernet
sn0 0x300 10 n/a n/a SMC 91xx Ethernet
+sk0 dyn dyn n/a dyn SysKonnect gigabit ethernet
ste0 dyn dyn n/a dyn Sundance ST201 Fast Ethernet
+ti0 dyn dyn n/a dyn Alteon Tigon 1 & 2 gigabit ethernet
tl0 dyn dyn n/a dyn TI TNET100 'ThunderLAN' cards.
tx0 dyn dyn n/a dyn SMC 9432 'Epic' Fast Ethernet
wb0 dyn dyn n/a dyn Winbond W89C840F PCI based cards.
@@ -541,7 +544,7 @@ The following CD-ROM type systems are supported at this time:
(acd) ATAPI IDE interface
Unmaintained drivers, they might or might not work for your hardware:
-
+NatSemi DP83820 gigabit ethernet
(mcd) Mitsumi proprietary CD-ROM interface (all models)
4.2. Network cards
@@ -623,6 +626,13 @@ National Semiconductor DP83815 Fast Ethernet NICs including the following:
NetGear FA311-TX
NetGear FA312-TX
+National Semiconductor DP83820 and DP83821 Gigabit Ethernet NICs including
+the following:
+ D-Link DGE-500T
+ SMC EZ Card 1000 (SMC9462TX)
+ Asante FriendlyNet GigaNIC 1000TA and 1000TPC
+ Addtron AEG320T
+
Sundance Technologies ST201 PCI Fast Ethernet NICs including
the following:
D-Link DFE-550TX
diff --git a/release/texts/alpha/RELNOTES.TXT b/release/texts/alpha/RELNOTES.TXT
index 31b22698..c59edac 100644
--- a/release/texts/alpha/RELNOTES.TXT
+++ b/release/texts/alpha/RELNOTES.TXT
@@ -356,6 +356,10 @@ The wx(4) driver now supports the Intel PRO1000-F and PRO1000-T
The labpc(4) driver has been removed due to bitrot.
+Added support for PCI Gigabit Ethernet adapters based on the National
+Semiconductor DP83820 and DP83821 gigabit ethernet controller chips,
+including the D-Link DGE-500T, SMC EZ Card 1000 (SMC9462TX),
+Asante FriendlyNet GigaNIC 1000TA and 1000TPC and Addtron AEG320T.
1.2. SECURITY FIXES
-------------------
@@ -1285,8 +1289,16 @@ NICs including the following:
Silicon Integrated Systems SiS 900 and SiS 7016 PCI Fast Ethernet NICs
National Semiconductor DP83815 Fast Ethernet NICs including the following:
+ NetGear FA311-TX
NetGear FA312-TX
+National Semiconductor DP83820 and DP83821 Gigabit Ethernet NICs including
+the following:
+ D-Link DGE-500T
+ SMC EZ Card 1000 (SMC9462TX)
+ Asante FriendlyNet GigaNIC 1000TA and 1000TPC
+ Addtron AEG320T
+
Sundance Technologies ST201 PCI Fast Ethernet NICs including
the following:
D-Link DFE-550TX
diff --git a/release/texts/i386/RELNOTES.TXT b/release/texts/i386/RELNOTES.TXT
index 6b02e35..0b247a9 100644
--- a/release/texts/i386/RELNOTES.TXT
+++ b/release/texts/i386/RELNOTES.TXT
@@ -437,6 +437,10 @@ testing.
smbfs (CIFS) support in kernel has been added.
+Added support for PCI Gigabit Ethernet adapters based on the National
+Semiconductor DP83820 and DP83821 gigabit ethernet controller chips,
+including the D-Link DGE-500T, SMC EZ Card 1000 (SMC9462TX),
+Asante FriendlyNet GigaNIC 1000TA and 1000TPC and Addtron AEG320T.
1.2. SECURITY FIXES
-------------------
@@ -1470,8 +1474,16 @@ NICs including the following:
Silicon Integrated Systems SiS 900 and SiS 7016 PCI Fast Ethernet NICs
National Semiconductor DP83815 Fast Ethernet NICs including the following:
+ NetGear FA311-TX
NetGear FA312-TX
+National Semiconductor DP83820 and DP83821 Gigabit Ethernet NICs including
+the following:
+ D-Link DGE-500T
+ SMC EZ Card 1000 (SMC9462TX)
+ Asante FriendlyNet GigaNIC 1000TA and 1000TPC
+ Addtron AEG320T
+
Sundance Technologies ST201 PCI Fast Ethernet NICs including
the following:
D-Link DFE-550TX
diff --git a/share/man/man4/Makefile b/share/man/man4/Makefile
index ec9bfab..c0731e6 100644
--- a/share/man/man4/Makefile
+++ b/share/man/man4/Makefile
@@ -100,6 +100,7 @@ MAN= aac.4 \
ng_tee.4 \
ng_tty.4 \
ng_vjc.4 \
+ nge.4 \
null.4 \
ohci.4 \
pass.4 \
diff --git a/share/man/man4/nge.4 b/share/man/man4/nge.4
new file mode 100644
index 0000000..cc5fa34
--- /dev/null
+++ b/share/man/man4/nge.4
@@ -0,0 +1,205 @@
+.\" Copyright (c) 2001 Wind River Syste,s
+.\" Copyright (c) 1997, 1998, 1999, 2000, 2001
+.\" Bill Paul <wpaul@bsdi.com>. All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\" notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\" notice, this list of conditions and the following disclaimer in the
+.\" documentation and/or other materials provided with the distribution.
+.\" 3. All advertising materials mentioning features or use of this software
+.\" must display the following acknowledgement:
+.\" This product includes software developed by Bill Paul.
+.\" 4. Neither the name of the author nor the names of any co-contributors
+.\" may be used to endorse or promote products derived from this software
+.\" without specific prior written permission.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+.\" ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+.\" THE POSSIBILITY OF SUCH DAMAGE.
+.\"
+.\" $FreeBSD$
+.\"
+.Dd July 11, 2001
+.Dt NGE 4
+.Os FreeBSD
+.Sh NAME
+.Nm nge
+.Nd "National Semiconductor PCI gigabit ethernet adapter driver"
+.Sh SYNOPSIS
+.Cd "device miibus"
+.Cd "device nge"
+.Sh DESCRIPTION
+The
+.Nm
+driver provides support for various NICs based on the National Semiconductor
+DP83820 and DP83821 gigabit ethernet controller chips, including the
+following:
+.Pp
+.Bl -bullet -offset indent -compact
+.It
+SMC EZ Card 1000 (SMC9462TX)
+.It
+D-Link DGE-500T
+.It
+Asante FriendlyNet GigaNIX 1000TA and 1000TPC
+.It
+Addrton AEG320T
+.El
+.Pp
+All of these NICs are capable of 10, 100 and 1000mbps speeds over CAT5
+copper cable. The DP83820 supports TBI (ten bit interface) and GMII
+transceivers, which means it can be used with either copper of 1000baseX
+fiber applications. The DP83820 supports TCP/IP checksum offload and
+VLAN tagging/insertion as well as a 2048-bit multicast hash filter
+and up to 4 pattern match buffers.
+.Pp
+Most cards also use the DP83861 10/100/1000 copper gigabit tranceiver
+chip, which supports autonegotiation of 10, 100 and 1000mbps modes in
+full or half duplex.
+.Pp
+The DP83820 also supports jumbo frames, which can be configured
+via the interface MTY setting.
+Selecting an MTU larger than 1500 bytes with the
+.Xr ifconfig 8
+utility configures the adapter to receive and transmit jumbo frames.
+Using jumbo frames can greatly improve performance for certain tanges,
+such as file transfers and data streaming.
+.Pp
+The
+.Nm
+driver supports the following media types:
+.Pp
+.Bl -tag -width 10baseTXUTP
+.It autoselect
+Enable autoselection of the media type and options.
+The user can manually override
+the autoselected mode by adding media options to
+.Xr rc.conf 5 .
+.It 10baseT/UTP
+Set 10Mbps operation.
+The
+.Xr ifconfig 8
+.Cm mediaopt
+option can also be used to select either
+.Sq full-duplex
+or
+.Sq half-duplex
+modes.
+.It 100baseTX
+Set 100Mbps (fast ethernet) operation.
+The
+.Xr ifconfig 8
+.Cm mediaopt
+option can also be used to select either
+.Sq full-duplex
+or
+.Sq half-duplex
+modes.
+.It 1000baseTX
+Set 1000baseTX operation over twisted pair.
+.Ar full-duplex
+and
+.Ar half-duplex
+modes are supported.
+.It 1000baseSX
+Set 1000Mbps (gigabit ethernet) operation.
+Both
+.Ar full-duplex
+and
+.Ar half-duplex
+modes are supported.
+.El
+.Pp
+The
+.Nm
+driver supports the following media options:
+.Pp
+.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
+.It full-duplex
+Force full duplex operation
+.It half-duplex
+Force half duplex operation.
+.El
+.Pp
+The
+.Nm
+driver also supports one special link option for 1000baseTX cards:
+.Pp
+.Bl -tag -width xxxxxxxxx
+.It link0
+With 1000baseTX cards, establishing a link between two ports requires
+that one port be configured as a master and the other a slave.
+With autonegotiation,
+the master/slave settings will be chosen automatically.
+However when manually selecting the link state, it is necessary to
+force one side of the link to be a master and the other a slave.
+The
+.Nm
+driver configures the ports as slaves by default.
+Setting the
+.Ar link0
+flag with
+.Xr ifconfig 8
+will set a port as a master instead.
+.El
+.Pp
+For more information on configuring this device, see
+.Xr ifconfig 8 .
+.Sh DIAGNOSTICS
+.Bl -diag
+.It "nge%d: couldn't map memory"
+A fatal initialization error has occurred.
+.It "nge%d: couldn't map ports"
+A fatal initialization error has occurred.
+.It "nge%d: couldn't map interrupt"
+A fatal initialization error has occurred.
+.It "nge%d: no memory for softc struct!"
+The driver failed to allocate memory for per-device instance information
+during initialization.
+.It "nge%d: failed to enable memory mapping!"
+The driver failed to initialize PCI shared memory mapping.
+This might
+happen if the card is not in a bus-master slot.
+.It "nge%d: no memory for jumbo buffers!"
+The driver failed to allocate memory for jumbo frames during
+initialization.
+.It "nge%d: watchdog timeout"
+The device has stopped responding to the network, or there is a problem with
+the network connection (cable).
+.El
+.Sh SEE ALSO
+.Xr arp 4 ,
+.Xr netintro 4 ,
+.Xr vlan 4 ,
+.Xr ng_ether 4 ,
+.Xr ifconfig 8
+.Rs
+.%T National Semiconductor DP83820 datasheet
+.%O http://www.national.com
+.Re
+.Rs
+.%T National Semiconductor DP83861 datasheet
+.%O http://www.national.com
+.Re
+.Sh HISTORY
+The
+.Nm
+device driver first appeared in
+.Fx 5.0 .
+.Sh AUTHORS
+The
+.Nm
+driver was written by
+.An Bill Paul Aq wpaul@bsdi.com .
diff --git a/sys/conf/NOTES b/sys/conf/NOTES
index bd884f2..810420a 100644
--- a/sys/conf/NOTES
+++ b/sys/conf/NOTES
@@ -1634,6 +1634,10 @@ device miibus
# DE101, DE200, DE201, DE202, DE203, DE204, DE205, DE422)
# lnc: Lance/PCnet cards (Isolan, Novell NE2100, NE32-VL, AMD Am7990 and
# Am79C960)
+# nge: Support for PCI gigabit ethernet adapters based on the National
+# Semiconductor DP83820 and DP83821 chipset. This includes the
+# SMC EZ Card 1000 (SMC9462TX), D-Link DGE-500T, Asante FriendlyNet
+# GigaNIX 1000TA and 1000TPC, and the Addtron AEG320T.
# oltr: Olicom ISA token-ring adapters OC-3115, OC-3117, OC-3118 and OC-3133
# (no hints needed).
# Olicom PCI token-ring adapters OC-3136, OC-3137, OC-3139, OC-3140,
@@ -1803,6 +1807,7 @@ device de # DEC/Intel DC21x4x (``Tulip'')
device vx # 3Com 3c590, 3c595 (``Vortex'')
# PCI Gigabit & FDDI NICs.
+device nge
device sk
device ti
device wx
diff --git a/sys/conf/files b/sys/conf/files
index 8688d30..0b53c9eda 100644
--- a/sys/conf/files
+++ b/sys/conf/files
@@ -385,6 +385,7 @@ dev/mii/mii.c optional miibus
dev/mii/mii_physubr.c optional miibus
dev/mii/mlphy.c optional miibus
dev/mii/nsphy.c optional miibus
+dev/mii/nsgphy.c optional miibus
dev/mii/pnphy.c optional miibus
dev/mii/pnaphy.c optional miibus
dev/mii/rlphy.c optional miibus
@@ -404,6 +405,7 @@ dev/mly/mly.c optional mly
dev/mly/mly_cam.c optional mly
dev/mly/mly_pci.c optional mly
dev/musycc/musycc.c optional musycc
+dev/nge/if_nge.c optional nge
dev/null/null.c standard
dev/nmdm/nmdm.c optional nmdm
dev/pccard/card_if.m optional card
diff --git a/sys/dev/mii/miidevs b/sys/dev/mii/miidevs
index 91d604a..27221c8 100644
--- a/sys/dev/mii/miidevs
+++ b/sys/dev/mii/miidevs
@@ -122,6 +122,8 @@ model xxLEVEL1 LXT970 0x0000 LXT970 10/100 media interface
/* National Semiconductor PHYs */
model NATSEMI DP83840 0x0000 DP83840 10/100 media interface
model NATSEMI DP83843 0x0001 DP83843 10/100 media interface
+model NATSEMI DP83891 0x0005 DP83891 10/100/1000 media interface
+model NATSEMI DP83861 0x0006 DP83861 10/100/1000 media interface
/* Quality Semiconductor PHYs */
model QUALSEMI QS6612 0x0000 QS6612 10/100 media interface
diff --git a/sys/dev/mii/nsgphy.c b/sys/dev/mii/nsgphy.c
new file mode 100644
index 0000000..19a585a
--- /dev/null
+++ b/sys/dev/mii/nsgphy.c
@@ -0,0 +1,475 @@
+/*
+ * Copyright (c) 2001 Wind River Systems
+ * Copyright (c) 2001
+ * Bill Paul <wpaul@bsdi.com>. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Bill Paul.
+ * 4. Neither the name of the author nor the names of any co-contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ * Driver for the National Semiconductor DP83891 and DP83861
+ * 10/100/1000 PHYs.
+ * Datasheet available at: http://www.national.com/ds/DP/DP83861.pdf
+ *
+ * The DP83891 is the older NatSemi gigE PHY which isn't being sold
+ * anymore. The DP83861 is its replacement, which is an 'enhanced'
+ * firmware driven component. The major difference between the
+ * two is that the 83891 can't generate interrupts, while the
+ * 83861 can. (I think it wasn't originally designed to do this, but
+ * it can now thanks to firmware updates.) The 83861 also allows
+ * access to its internal RAM via indirect register access.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/socket.h>
+#include <sys/bus.h>
+
+#include <machine/clock.h>
+
+#include <net/if.h>
+#include <net/if_media.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+#include <dev/mii/miidevs.h>
+
+#include <dev/mii/nsgphyreg.h>
+
+#include "miibus_if.h"
+
+#if !defined(lint)
+static const char rcsid[] =
+ "$FreeBSD$";
+#endif
+
+static int nsgphy_probe __P((device_t));
+static int nsgphy_attach __P((device_t));
+static int nsgphy_detach __P((device_t));
+
+static device_method_t nsgphy_methods[] = {
+ /* device interface */
+ DEVMETHOD(device_probe, nsgphy_probe),
+ DEVMETHOD(device_attach, nsgphy_attach),
+ DEVMETHOD(device_detach, nsgphy_detach),
+ DEVMETHOD(device_shutdown, bus_generic_shutdown),
+ { 0, 0 }
+};
+
+static devclass_t nsgphy_devclass;
+
+static driver_t nsgphy_driver = {
+ "nsgphy",
+ nsgphy_methods,
+ sizeof(struct mii_softc)
+};
+
+DRIVER_MODULE(nsgphy, miibus, nsgphy_driver, nsgphy_devclass, 0, 0);
+
+int nsgphy_service __P((struct mii_softc *, struct mii_data *, int));
+void nsgphy_status __P((struct mii_softc *));
+
+static int nsgphy_mii_phy_auto __P((struct mii_softc *, int));
+extern void mii_phy_auto_timeout __P((void *));
+
+static int nsgphy_probe(dev)
+ device_t dev;
+{
+ struct mii_attach_args *ma;
+
+ ma = device_get_ivars(dev);
+
+ if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_NATSEMI) {
+ if (MII_MODEL(ma->mii_id2) == MII_MODEL_NATSEMI_DP83891) {
+ device_set_desc(dev, MII_STR_NATSEMI_DP83891);
+ return(0);
+ }
+ if (MII_MODEL(ma->mii_id2) == MII_MODEL_NATSEMI_DP83861) {
+ device_set_desc(dev, MII_STR_NATSEMI_DP83861);
+ return(0);
+ }
+ }
+
+ return(ENXIO);
+}
+
+static int nsgphy_attach(dev)
+ device_t dev;
+{
+ struct mii_softc *sc;
+ struct mii_attach_args *ma;
+ struct mii_data *mii;
+ const char *sep = "";
+
+ sc = device_get_softc(dev);
+ ma = device_get_ivars(dev);
+ sc->mii_dev = device_get_parent(dev);
+ mii = device_get_softc(sc->mii_dev);
+ LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
+
+ sc->mii_inst = mii->mii_instance;
+ sc->mii_phy = ma->mii_phyno;
+ sc->mii_service = nsgphy_service;
+ sc->mii_pdata = mii;
+
+ sc->mii_flags |= MIIF_NOISOLATE;
+ mii->mii_instance++;
+
+#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
+#define PRINT(s) printf("%s%s", sep, s); sep = ", "
+
+ ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
+ BMCR_ISO);
+#if 0
+ ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
+ BMCR_LOOP|BMCR_S100);
+#endif
+
+ mii_phy_reset(sc);
+
+ device_printf(dev, " ");
+ ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_TX, IFM_FDX, sc->mii_inst),
+ NSGPHY_S1000|NSGPHY_BMCR_FDX);
+ PRINT("1000baseTX-FDX");
+ ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_TX, 0, sc->mii_inst),
+ NSGPHY_S1000);
+ PRINT("1000baseTX");
+ sc->mii_capabilities =
+ (PHY_READ(sc, MII_BMSR) |
+ (BMSR_10TFDX|BMSR_10THDX)) & ma->mii_capmask;
+ ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_FDX, sc->mii_inst),
+ NSGPHY_S100|NSGPHY_BMCR_FDX);
+ PRINT("100baseTX-FDX");
+ ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, sc->mii_inst), NSGPHY_S100);
+ PRINT("100baseTX");
+ ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, IFM_FDX, sc->mii_inst),
+ NSGPHY_S10|NSGPHY_BMCR_FDX);
+ PRINT("10baseT-FDX");
+ ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, sc->mii_inst), NSGPHY_S10);
+ PRINT("10baseT");
+ ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
+ PRINT("auto");
+ printf("\n");
+#undef ADD
+#undef PRINT
+
+ MIIBUS_MEDIAINIT(sc->mii_dev);
+ return(0);
+}
+
+static int nsgphy_detach(dev)
+ device_t dev;
+{
+ struct mii_softc *sc;
+ struct mii_data *mii;
+
+ sc = device_get_softc(dev);
+ mii = device_get_softc(device_get_parent(dev));
+ if (sc->mii_flags & MIIF_DOINGAUTO)
+ untimeout(mii_phy_auto_timeout, sc, sc->mii_auto_ch);
+ sc->mii_dev = NULL;
+ LIST_REMOVE(sc, mii_list);
+
+ return(0);
+}
+int
+nsgphy_service(sc, mii, cmd)
+ struct mii_softc *sc;
+ struct mii_data *mii;
+ int cmd;
+{
+ struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
+ int reg;
+
+ switch (cmd) {
+ case MII_POLLSTAT:
+ /*
+ * If we're not polling our PHY instance, just return.
+ */
+ if (IFM_INST(ife->ifm_media) != sc->mii_inst)
+ return (0);
+ break;
+
+ case MII_MEDIACHG:
+ /*
+ * If the media indicates a different PHY instance,
+ * isolate ourselves.
+ */
+ if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
+ reg = PHY_READ(sc, MII_BMCR);
+ PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
+ return (0);
+ }
+
+ /*
+ * If the interface is not up, don't do anything.
+ */
+ if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
+ break;
+
+
+ switch (IFM_SUBTYPE(ife->ifm_media)) {
+ case IFM_AUTO:
+#ifdef foo
+ /*
+ * If we're already in auto mode, just return.
+ */
+ if (PHY_READ(sc, NSGPHY_MII_BMCR) & NSGPHY_BMCR_AUTOEN)
+ return (0);
+#endif
+ (void) nsgphy_mii_phy_auto(sc, 0);
+ break;
+ case IFM_1000_TX:
+ if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
+ PHY_WRITE(sc, NSGPHY_MII_BMCR,
+ NSGPHY_BMCR_FDX|NSGPHY_BMCR_SPD1);
+ } else {
+ PHY_WRITE(sc, NSGPHY_MII_BMCR,
+ NSGPHY_BMCR_SPD1);
+ }
+ PHY_WRITE(sc, NSGPHY_MII_ANAR, NSGPHY_SEL_TYPE);
+
+ /*
+ * When setting the link manually, one side must
+ * be the master and the other the slave. However
+ * ifmedia doesn't give us a good way to specify
+ * this, so we fake it by using one of the LINK
+ * flags. If LINK0 is set, we program the PHY to
+ * be a master, otherwise it's a slave.
+ */
+ if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
+ PHY_WRITE(sc, NSGPHY_MII_1000CTL,
+ NSGPHY_1000CTL_MSE|NSGPHY_1000CTL_MSC);
+ } else {
+ PHY_WRITE(sc, NSGPHY_MII_1000CTL,
+ NSGPHY_1000CTL_MSE);
+ }
+ break;
+ case IFM_100_T4:
+ /*
+ * XXX Not supported as a manual setting right now.
+ */
+ return (EINVAL);
+ case IFM_NONE:
+ PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
+ break;
+ default:
+ /*
+ * BMCR data is stored in the ifmedia entry.
+ */
+ PHY_WRITE(sc, MII_ANAR,
+ mii_anar(ife->ifm_media));
+ PHY_WRITE(sc, MII_BMCR, ife->ifm_data);
+ break;
+ }
+ break;
+
+ case MII_TICK:
+ /*
+ * If we're not currently selected, just return.
+ */
+ if (IFM_INST(ife->ifm_media) != sc->mii_inst)
+ return (0);
+
+ /*
+ * Only used for autonegotiation.
+ */
+ if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
+ return (0);
+
+ /*
+ * Is the interface even up?
+ */
+ if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
+ return (0);
+
+ /*
+ * Only retry autonegotiation every 5 seconds.
+ * Actually, for gigE PHYs, we should wait longer, since
+ * 5 seconds is the mimimum time the documentation
+ * says to wait for a 1000mbps link to be established.
+ */
+ if (++sc->mii_ticks != 10)
+ return (0);
+
+ sc->mii_ticks = 0;
+
+ /*
+ * Check to see if we have link.
+ */
+ reg = PHY_READ(sc, NSGPHY_MII_PHYSUP);
+ if (reg & NSGPHY_PHYSUP_LNKSTS)
+ break;
+
+ mii_phy_reset(sc);
+ if (nsgphy_mii_phy_auto(sc, 0) == EJUSTRETURN)
+ return(0);
+ break;
+ }
+
+ /* Update the media status. */
+ nsgphy_status(sc);
+
+ /* Callback if something changed. */
+ if (sc->mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) {
+ MIIBUS_STATCHG(sc->mii_dev);
+ sc->mii_active = mii->mii_media_active;
+ }
+ return (0);
+}
+
+void
+nsgphy_status(sc)
+ struct mii_softc *sc;
+{
+ struct mii_data *mii = sc->mii_pdata;
+ int bmsr, bmcr, physup, anlpar, gstat;
+
+ mii->mii_media_status = IFM_AVALID;
+ mii->mii_media_active = IFM_ETHER;
+
+ bmsr = PHY_READ(sc, NSGPHY_MII_BMSR);
+ physup = PHY_READ(sc, NSGPHY_MII_PHYSUP);
+ if (physup & NSGPHY_PHYSUP_LNKSTS)
+ mii->mii_media_status |= IFM_ACTIVE;
+
+ bmcr = PHY_READ(sc, NSGPHY_MII_BMCR);
+
+ if (bmcr & NSGPHY_BMCR_LOOP)
+ mii->mii_media_active |= IFM_LOOP;
+
+ if (bmcr & NSGPHY_BMCR_AUTOEN) {
+ if ((bmsr & NSGPHY_BMSR_ACOMP) == 0) {
+ /* Erg, still trying, I guess... */
+ mii->mii_media_active |= IFM_NONE;
+ return;
+ }
+ anlpar = PHY_READ(sc, NSGPHY_MII_ANLPAR);
+ gstat = PHY_READ(sc, NSGPHY_MII_1000STS);
+ if (gstat & NSGPHY_1000STS_LPFD)
+ mii->mii_media_active |= IFM_1000_TX|IFM_FDX;
+ else if (gstat & NSGPHY_1000STS_LPHD)
+ mii->mii_media_active |= IFM_1000_TX|IFM_HDX;
+ else if (anlpar & NSGPHY_ANLPAR_100T4)
+ mii->mii_media_active |= IFM_100_T4;
+ else if (anlpar & NSGPHY_ANLPAR_100FDX)
+ mii->mii_media_active |= IFM_100_TX|IFM_FDX;
+ else if (anlpar & NSGPHY_ANLPAR_100HDX)
+ mii->mii_media_active |= IFM_100_TX;
+ else if (anlpar & NSGPHY_ANLPAR_10FDX)
+ mii->mii_media_active |= IFM_10_T|IFM_FDX;
+ else if (anlpar & NSGPHY_ANLPAR_10HDX)
+ mii->mii_media_active |= IFM_10_T|IFM_HDX;
+ else
+ mii->mii_media_active |= IFM_NONE;
+ return;
+ }
+
+ switch(bmcr & (NSGPHY_BMCR_SPD1|NSGPHY_BMCR_SPD0)) {
+ case NSGPHY_S1000:
+ mii->mii_media_active |= IFM_1000_TX;
+ break;
+ case NSGPHY_S100:
+ mii->mii_media_active |= IFM_100_TX;
+ break;
+ case NSGPHY_S10:
+ mii->mii_media_active |= IFM_10_T;
+ break;
+ default:
+ break;
+ }
+
+ if (bmcr & NSGPHY_BMCR_FDX)
+ mii->mii_media_active |= IFM_FDX;
+ else
+ mii->mii_media_active |= IFM_HDX;
+
+ return;
+}
+
+
+static int
+nsgphy_mii_phy_auto(mii, waitfor)
+ struct mii_softc *mii;
+ int waitfor;
+{
+ int bmsr, ktcr = 0, i;
+
+ if ((mii->mii_flags & MIIF_DOINGAUTO) == 0) {
+ mii_phy_reset(mii);
+ PHY_WRITE(mii, NSGPHY_MII_BMCR, 0);
+ DELAY(1000);
+ ktcr = PHY_READ(mii, NSGPHY_MII_1000CTL);
+ PHY_WRITE(mii, NSGPHY_MII_1000CTL, ktcr |
+ (NSGPHY_1000CTL_AFD|NSGPHY_1000CTL_AHD));
+ ktcr = PHY_READ(mii, NSGPHY_MII_1000CTL);
+ DELAY(1000);
+ PHY_WRITE(mii, NSGPHY_MII_ANAR,
+ BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA);
+ DELAY(1000);
+ PHY_WRITE(mii, NSGPHY_MII_BMCR,
+ NSGPHY_BMCR_AUTOEN | NSGPHY_BMCR_STARTNEG);
+ }
+
+ if (waitfor) {
+ /* Wait 500ms for it to complete. */
+ for (i = 0; i < 500; i++) {
+ if ((bmsr = PHY_READ(mii, NSGPHY_MII_BMSR)) &
+ NSGPHY_BMSR_ACOMP)
+ return (0);
+ DELAY(1000);
+#if 0
+ if ((bmsr & BMSR_ACOMP) == 0)
+ printf("%s: autonegotiation failed to complete\n",
+ mii->mii_dev.dv_xname);
+#endif
+ }
+
+ /*
+ * Don't need to worry about clearing MIIF_DOINGAUTO.
+ * If that's set, a timeout is pending, and it will
+ * clear the flag.
+ */
+ return (EIO);
+ }
+
+ /*
+ * Just let it finish asynchronously. This is for the benefit of
+ * the tick handler driving autonegotiation. Don't want 500ms
+ * delays all the time while the system is running!
+ */
+ if ((mii->mii_flags & MIIF_DOINGAUTO) == 0) {
+ mii->mii_flags |= MIIF_DOINGAUTO;
+ mii->mii_auto_ch = timeout(mii_phy_auto_timeout, mii, hz >> 1);
+ }
+ return (EJUSTRETURN);
+}
diff --git a/sys/dev/mii/nsgphyreg.h b/sys/dev/mii/nsgphyreg.h
new file mode 100644
index 0000000..c63cf35
--- /dev/null
+++ b/sys/dev/mii/nsgphyreg.h
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2001 Wind River Systems
+ * Copyright (c) 2001
+ * Bill Paul <wpaul@bsdi.com>. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Bill Paul.
+ * 4. Neither the name of the author nor the names of any co-contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _DEV_MII_NSGPHYREG_H_
+#define _DEV_MII_NSGPHYREG_H_
+
+/*
+ * NatSemi DP83891 registers
+ */
+
+#define NSGPHY_MII_BMCR 0x00
+#define NSGPHY_BMCR_RESET 0x8000
+#define NSGPHY_BMCR_LOOP 0x4000
+#define NSGPHY_BMCR_SPD0 0x2000 /* speed select, lower bit */
+#define NSGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
+#define NSGPHY_BMCR_PDOWN 0x0800 /* Power down */
+#define NSGPHY_BMCR_ISO 0x0400 /* Isolate */
+#define NSGPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
+#define NSGPHY_BMCR_FDX 0x0100 /* Duplex mode */
+#define NSGPHY_BMCR_CTEST 0x0080 /* Collision test enable */
+#define NSGPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */
+
+#define NSGPHY_S1000 NSGPHY_BMCR_SPD1 /* 1000mbps */
+#define NSGPHY_S100 NSGPHY_BMCR_SPD0 /* 100mpbs */
+#define NSGPHY_S10 0 /* 10mbps */
+
+#define NSGPHY_MII_BMSR 0x01
+#define NSGPHY_BMSR_100BT4 0x8000 /* 100baseT4 support */
+#define NSGPHY_BMSR_100FDX 0x4000 /* 100baseTX full duplex */
+#define NSGPHY_BMSR_100HDX 0x2000 /* 100baseTX half duplex */
+#define NSGPHY_BMSR_10FDX 0x1000 /* 10baseT full duplex */
+#define NSGPHY_BMSR_10HDX 0x0800 /* 10baseT half duplex */
+#define NSGPHY_BMSR_100T2FDX 0x0400 /* 100baseT2 full duplex */
+#define NSGPHY_BMSR_100T2HDX 0x0200 /* 100baseT2 full duplex */
+#define NSGPHY_BMSR_EXTSTS 0x0100 /* 1000baseT Extended status present */
+#define NSGPHY_BMSR_PRESUB 0x0040 /* Preamble surpression */
+#define NSGPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */
+#define NSGPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occured */
+#define NSGPHY_BMSR_ANEG 0x0008 /* Autoneg capable */
+#define NSGPHY_BMSR_LINK 0x0004 /* Link status */
+#define NSGPHY_BMSR_JABBER 0x0002 /* Jabber detected */
+#define NSGPHY_BMSR_EXT 0x0001 /* Extended capability */
+
+#define NSGPHY_MII_ANAR 0x04
+#define NSGPHY_ANAR_NP 0x8000 /* Next page */
+#define NSGPHY_ANAR_RF 0x2000 /* Remote fault */
+#define NSGPHY_ANAR_ASP 0x0800 /* Asymetric Pause */
+#define NSGPHY_ANAR_PC 0x0400 /* Pause capable */
+#define NSGPHY_ANAR_100T4 0x0200 /* 100baseT4 support */
+#define NSGPHY_ANAR_100FDX 0x0100 /* 100baseTX full duplex support */
+#define NSGPHY_ANAR_100HDX 0x0080 /* 100baseTX half duplex support */
+#define NSGPHY_ANAR_10FDX 0x0040 /* 10baseT full duplex support */
+#define NSGPHY_ANAR_10HDX 0x0020 /* 10baseT half duplex support */
+#define NSGPHY_ANAR_SEL 0x001F /* selector field, 00001=Ethernet */
+
+#define NSGPHY_MII_ANLPAR 0x05
+#define NSGPHY_ANLPAR_NP 0x8000 /* Next page */
+#define NSGPHY_ANLPAR_RF 0x2000 /* Remote fault */
+#define NSGPHY_ANLPAR_ASP 0x0800 /* Asymetric Pause */
+#define NSGPHY_ANLPAR_PC 0x0400 /* Pause capable */
+#define NSGPHY_ANLPAR_100T4 0x0200 /* 100baseT4 support */
+#define NSGPHY_ANLPAR_100FDX 0x0100 /* 100baseTX full duplex support */
+#define NSGPHY_ANLPAR_100HDX 0x0080 /* 100baseTX half duplex support */
+#define NSGPHY_ANLPAR_10FDX 0x0040 /* 10baseT full duplex support */
+#define NSGPHY_ANLPAR_10HDX 0x0020 /* 10baseT half duplex support */
+#define NSGPHY_ANLPAR_SEL 0x001F /* selector field, 00001=Ethernet */
+
+#define NSGPHY_SEL_TYPE 0x0001 /* ethernet */
+
+#define NSGPHY_MII_ANER 0x06
+#define NSGPHY_ANER_PDF 0x0010 /* Parallel detection fault */
+#define NSGPHY_ANER_LPNP 0x0008 /* Link partner can next page */
+#define NSGPHY_ANER_NP 0x0004 /* Local PHY can next page */
+#define NSGPHY_ANER_RX 0x0002 /* Next page received */
+#define NSGPHY_ANER_LPAN 0x0001 /* Link partner autoneg capable */
+
+#define NSGPHY_MII_NEXTP 0x07 /* Next page */
+#define NSGPHY_NEXTP_NP 0x8000 /* Next page indication */
+#define NSGPHY_NEXTP_MP 0x2000 /* Message page */
+#define NSGPHY_NEXTP_ACK2 0x1000 /* Acknowledge 2 */
+#define NSGPHY_NEXTP_TOGGLE 0x0800 /* Toggle */
+#define NSGPHY_NEXTP_CODE 0x07FF /* Code field */
+
+#define NSGPHY_MII_NEXTP_LP 0x08 /* Next page of link partner */
+#define NSGPHY_NEXTPLP_NP 0x8000 /* Next page indication */
+#define NSGPHY_NEXTPLP_MP 0x2000 /* Message page */
+#define NSGPHY_NEXTPLP_ACK2 0x1000 /* Acknowledge 2 */
+#define NSGPHY_NEXTPLP_TOGGLE 0x0800 /* Toggle */
+#define NSGPHY_NEXTPLP_CODE 0x07FF /* Code field */
+
+#define NSGPHY_MII_1000CTL 0x09 /* 1000baseT control */
+#define NSGPHY_1000CTL_TST 0xE000 /* test modes */
+#define NSGPHY_1000CTL_MSE 0x1000 /* Master/Slave config enable */
+#define NSGPHY_1000CTL_MSC 0x0800 /* Master/Slave setting */
+#define NSGPHY_1000CTL_RD 0x0400 /* Port type: Repeater/DTE */
+#define NSGPHY_1000CTL_AFD 0x0200 /* Advertise full duplex */
+#define NSGPHY_1000CTL_AHD 0x0100 /* Advertise half duplex */
+
+#define NSGPHY_MII_1000STS 0x0A /* 1000baseT status */
+#define NSGPHY_1000STS_MSF 0x8000 /* Master/slave fault */
+#define NSGPHY_1000STS_MSR 0x4000 /* Master/slave result */
+#define NSGPHY_1000STS_LRS 0x2000 /* Local receiver status */
+#define NSGPHY_1000STS_RRS 0x1000 /* Remote receiver status */
+#define NSGPHY_1000STS_LPFD 0x0800 /* Link partner can FD */
+#define NSGPHY_1000STS_LPHD 0x0400 /* Link partner can HD */
+#define NSGPHY_1000STS_ASM_DIR 0x0200 /* Asymetric pause capable */
+#define NSGPHY_1000STS_IEC 0x00FF /* Idle error count */
+
+#define NSGPHY_MII_EXTSTS 0x0F /* Extended status */
+#define NSGPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */
+#define NSGPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */
+#define NSGPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */
+#define NSGPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */
+
+#define NSGPHY_MII_STRAPOPT 0x10 /* Strap options */
+#define NSGPHY_STRAPOPT_PHYADDR 0xF800 /* PHY address */
+#define NSGPHY_STRAPOPT_COMPAT 0x0400 /* Broadcom compat mode */
+#define NSGPHY_STRAPOPT_MMSE 0x0200 /* Manual master/slave enable */
+#define NSGPHY_STRAPOPT_ANEG 0x0100 /* Autoneg enable */
+#define NSGPHY_STRAPOPT_MMSV 0x0080 /* Manual master/slave setting */
+#define NSGPHY_STRAPOPT_1000HDX 0x0010 /* Advertise 1000 half-duplex */
+#define NSGPHY_STRAPOPT_1000FDX 0x0008 /* Advertise 1000 full-duplex */
+#define NSGPHY_STRAPOPT_100_ADV 0x0004 /* Advertise 100 full/half-duplex */
+#define NSGPHY_STRAPOPT_SPDSEL 0x0003 /* speed selection */
+
+#define NSGPHY_MII_PHYSUP 0x11 /* PHY support/current status */
+#define NSGPHY_PHYSUP_SPDSTS 0x0018 /* speed status */
+#define NSGPHY_PHYSUP_LNKSTS 0x0004 /* link status */
+#define NSGPHY_PHYSUP_DUPSTS 0x0002 /* duplex status 1 == full */
+#define NSGPHY_PHYSUP_10BT 0x0001 /* 10baseT resolved */
+
+#define NSGPHY_SPDSTS_1000 0x0010
+#define NSGPHY_SPDSTS_100 0x0008
+#define NSGPHY_SPDSTS_10 0x0000
+
+#endif /* _DEV_NSGPHY_MIIREG_H_ */
diff --git a/sys/dev/nge/if_nge.c b/sys/dev/nge/if_nge.c
new file mode 100644
index 0000000..30c287c
--- /dev/null
+++ b/sys/dev/nge/if_nge.c
@@ -0,0 +1,2006 @@
+/*
+ * Copyright (c) 2001 Wind River Systems
+ * Copyright (c) 1997, 1998, 1999, 2000, 2001
+ * Bill Paul <wpaul@bsdi.com>. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Bill Paul.
+ * 4. Neither the name of the author nor the names of any co-contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ * National Semiconductor DP83820/DP83821 gigabit ethernet driver
+ * for FreeBSD. Datasheets are available from:
+ *
+ * http://www.national.com/ds/DP/DP83820.pdf
+ * http://www.national.com/ds/DP/DP83821.pdf
+ *
+ * These chips are used on several low cost gigabit ethernet NICs
+ * sold by D-Link, Addtron, SMC and Asante. Both parts are
+ * virtually the same, except the 83820 is a 64-bit/32-bit part,
+ * while the 83821 is 32-bit only.
+ *
+ * Many cards also use National gigE transceivers, such as the
+ * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet
+ * contains a full register description that applies to all of these
+ * components:
+ *
+ * http://www.national.com/ds/DP/DP83861.pdf
+ *
+ * Written by Bill Paul <wpaul@bsdi.com>
+ * BSDi Open Source Solutions
+ */
+
+/*
+ * The NatSemi DP83820 and 83821 controllers are enhanced versions
+ * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100
+ * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII
+ * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP
+ * hardware checksum offload (IPv4 only), VLAN tagging and filtering,
+ * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern
+ * matching buffers, one perfect address filter buffer and interrupt
+ * moderation. The 83820 supports both 64-bit and 32-bit addressing
+ * and data transfers: the 64-bit support can be toggled on or off
+ * via software. This affects the size of certain fields in the DMA
+ * descriptors.
+ *
+ * As far as I can tell, the 83820 and 83821 are decent chips, marred by
+ * only one flaw: the RX buffers must be aligned on 64-bit boundaries.
+ * So far this is the only gigE MAC that I've encountered with this
+ * requirement.
+ */
+
+#include "opt_vlan.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/ethernet.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+
+#if NVLAN > 0
+#include <net/if_types.h>
+#include <net/if_vlan_var.h>
+#endif
+
+#include <net/bpf.h>
+
+#include <vm/vm.h> /* for vtophys */
+#include <vm/pmap.h> /* for vtophys */
+#include <machine/clock.h> /* for DELAY */
+#include <machine/bus_pio.h>
+#include <machine/bus_memio.h>
+#include <machine/bus.h>
+#include <machine/resource.h>
+#include <sys/bus.h>
+#include <sys/rman.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+
+#include <pci/pcireg.h>
+#include <pci/pcivar.h>
+
+#define NGE_USEIOSPACE
+
+#include <pci/if_ngereg.h>
+
+MODULE_DEPEND(nge, miibus, 1, 1, 1);
+
+/* "controller miibus0" required. See GENERIC if you get errors here. */
+#include "miibus_if.h"
+
+#ifndef lint
+static const char rcsid[] =
+ "$FreeBSD$";
+#endif
+
+#define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
+
+/*
+ * Various supported device vendors/types and their names.
+ */
+static struct nge_type nge_devs[] = {
+ { NGE_VENDORID, NGE_DEVICEID,
+ "National Semiconductor Gigabit Ethernet" },
+ { 0, 0, NULL }
+};
+
+static int nge_probe __P((device_t));
+static int nge_attach __P((device_t));
+static int nge_detach __P((device_t));
+
+static int nge_alloc_jumbo_mem __P((struct nge_softc *));
+static void nge_free_jumbo_mem __P((struct nge_softc *));
+static void *nge_jalloc __P((struct nge_softc *));
+static void nge_jfree __P((caddr_t, void *));
+
+static int nge_newbuf __P((struct nge_softc *,
+ struct nge_desc *,
+ struct mbuf *));
+static int nge_encap __P((struct nge_softc *,
+ struct mbuf *, u_int32_t *));
+static void nge_rxeof __P((struct nge_softc *));
+static void nge_rxeoc __P((struct nge_softc *));
+static void nge_txeof __P((struct nge_softc *));
+static void nge_intr __P((void *));
+static void nge_tick __P((void *));
+static void nge_start __P((struct ifnet *));
+static int nge_ioctl __P((struct ifnet *, u_long, caddr_t));
+static void nge_init __P((void *));
+static void nge_stop __P((struct nge_softc *));
+static void nge_watchdog __P((struct ifnet *));
+static void nge_shutdown __P((device_t));
+static int nge_ifmedia_upd __P((struct ifnet *));
+static void nge_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
+
+static void nge_delay __P((struct nge_softc *));
+static void nge_eeprom_idle __P((struct nge_softc *));
+static void nge_eeprom_putbyte __P((struct nge_softc *, int));
+static void nge_eeprom_getword __P((struct nge_softc *, int, u_int16_t *));
+static void nge_read_eeprom __P((struct nge_softc *, caddr_t, int,
+ int, int));
+
+static void nge_mii_sync __P((struct nge_softc *));
+static void nge_mii_send __P((struct nge_softc *, u_int32_t, int));
+static int nge_mii_readreg __P((struct nge_softc *,
+ struct nge_mii_frame *));
+static int nge_mii_writereg __P((struct nge_softc *,
+ struct nge_mii_frame *));
+
+static int nge_miibus_readreg __P((device_t, int, int));
+static int nge_miibus_writereg __P((device_t, int, int, int));
+static void nge_miibus_statchg __P((device_t));
+
+static void nge_setmulti __P((struct nge_softc *));
+static u_int32_t nge_crc __P((struct nge_softc *, caddr_t));
+static void nge_reset __P((struct nge_softc *));
+static int nge_list_rx_init __P((struct nge_softc *));
+static int nge_list_tx_init __P((struct nge_softc *));
+
+#ifdef NGE_USEIOSPACE
+#define NGE_RES SYS_RES_IOPORT
+#define NGE_RID NGE_PCI_LOIO
+#else
+#define NGE_RES SYS_RES_MEMORY
+#define NGE_RID NGE_PCI_LOMEM
+#endif
+
+static device_method_t nge_methods[] = {
+ /* Device interface */
+ DEVMETHOD(device_probe, nge_probe),
+ DEVMETHOD(device_attach, nge_attach),
+ DEVMETHOD(device_detach, nge_detach),
+ DEVMETHOD(device_shutdown, nge_shutdown),
+
+ /* bus interface */
+ DEVMETHOD(bus_print_child, bus_generic_print_child),
+ DEVMETHOD(bus_driver_added, bus_generic_driver_added),
+
+ /* MII interface */
+ DEVMETHOD(miibus_readreg, nge_miibus_readreg),
+ DEVMETHOD(miibus_writereg, nge_miibus_writereg),
+ DEVMETHOD(miibus_statchg, nge_miibus_statchg),
+
+ { 0, 0 }
+};
+
+static driver_t nge_driver = {
+ "nge",
+ nge_methods,
+ sizeof(struct nge_softc)
+};
+
+static devclass_t nge_devclass;
+
+DRIVER_MODULE(if_nge, pci, nge_driver, nge_devclass, 0, 0);
+DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0);
+
+#define NGE_SETBIT(sc, reg, x) \
+ CSR_WRITE_4(sc, reg, \
+ CSR_READ_4(sc, reg) | (x))
+
+#define NGE_CLRBIT(sc, reg, x) \
+ CSR_WRITE_4(sc, reg, \
+ CSR_READ_4(sc, reg) & ~(x))
+
+#define SIO_SET(x) \
+ CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | x)
+
+#define SIO_CLR(x) \
+ CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~x)
+
+static void nge_delay(sc)
+ struct nge_softc *sc;
+{
+ int idx;
+
+ for (idx = (300 / 33) + 1; idx > 0; idx--)
+ CSR_READ_4(sc, NGE_CSR);
+
+ return;
+}
+
+static void nge_eeprom_idle(sc)
+ struct nge_softc *sc;
+{
+ register int i;
+
+ SIO_SET(NGE_MEAR_EE_CSEL);
+ nge_delay(sc);
+ SIO_SET(NGE_MEAR_EE_CLK);
+ nge_delay(sc);
+
+ for (i = 0; i < 25; i++) {
+ SIO_CLR(NGE_MEAR_EE_CLK);
+ nge_delay(sc);
+ SIO_SET(NGE_MEAR_EE_CLK);
+ nge_delay(sc);
+ }
+
+ SIO_CLR(NGE_MEAR_EE_CLK);
+ nge_delay(sc);
+ SIO_CLR(NGE_MEAR_EE_CSEL);
+ nge_delay(sc);
+ CSR_WRITE_4(sc, NGE_MEAR, 0x00000000);
+
+ return;
+}
+
+/*
+ * Send a read command and address to the EEPROM, check for ACK.
+ */
+static void nge_eeprom_putbyte(sc, addr)
+ struct nge_softc *sc;
+ int addr;
+{
+ register int d, i;
+
+ d = addr | NGE_EECMD_READ;
+
+ /*
+ * Feed in each bit and stobe the clock.
+ */
+ for (i = 0x400; i; i >>= 1) {
+ if (d & i) {
+ SIO_SET(NGE_MEAR_EE_DIN);
+ } else {
+ SIO_CLR(NGE_MEAR_EE_DIN);
+ }
+ nge_delay(sc);
+ SIO_SET(NGE_MEAR_EE_CLK);
+ nge_delay(sc);
+ SIO_CLR(NGE_MEAR_EE_CLK);
+ nge_delay(sc);
+ }
+
+ return;
+}
+
+/*
+ * Read a word of data stored in the EEPROM at address 'addr.'
+ */
+static void nge_eeprom_getword(sc, addr, dest)
+ struct nge_softc *sc;
+ int addr;
+ u_int16_t *dest;
+{
+ register int i;
+ u_int16_t word = 0;
+
+ /* Force EEPROM to idle state. */
+ nge_eeprom_idle(sc);
+
+ /* Enter EEPROM access mode. */
+ nge_delay(sc);
+ SIO_CLR(NGE_MEAR_EE_CLK);
+ nge_delay(sc);
+ SIO_SET(NGE_MEAR_EE_CSEL);
+ nge_delay(sc);
+
+ /*
+ * Send address of word we want to read.
+ */
+ nge_eeprom_putbyte(sc, addr);
+
+ /*
+ * Start reading bits from EEPROM.
+ */
+ for (i = 0x8000; i; i >>= 1) {
+ SIO_SET(NGE_MEAR_EE_CLK);
+ nge_delay(sc);
+ if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT)
+ word |= i;
+ nge_delay(sc);
+ SIO_CLR(NGE_MEAR_EE_CLK);
+ nge_delay(sc);
+ }
+
+ /* Turn off EEPROM access mode. */
+ nge_eeprom_idle(sc);
+
+ *dest = word;
+
+ return;
+}
+
+/*
+ * Read a sequence of words from the EEPROM.
+ */
+static void nge_read_eeprom(sc, dest, off, cnt, swap)
+ struct nge_softc *sc;
+ caddr_t dest;
+ int off;
+ int cnt;
+ int swap;
+{
+ int i;
+ u_int16_t word = 0, *ptr;
+
+ for (i = 0; i < cnt; i++) {
+ nge_eeprom_getword(sc, off + i, &word);
+ ptr = (u_int16_t *)(dest + (i * 2));
+ if (swap)
+ *ptr = ntohs(word);
+ else
+ *ptr = word;
+ }
+
+ return;
+}
+
+/*
+ * Sync the PHYs by setting data bit and strobing the clock 32 times.
+ */
+static void nge_mii_sync(sc)
+ struct nge_softc *sc;
+{
+ register int i;
+
+ SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA);
+
+ for (i = 0; i < 32; i++) {
+ SIO_SET(NGE_MEAR_MII_CLK);
+ DELAY(1);
+ SIO_CLR(NGE_MEAR_MII_CLK);
+ DELAY(1);
+ }
+
+ return;
+}
+
+/*
+ * Clock a series of bits through the MII.
+ */
+static void nge_mii_send(sc, bits, cnt)
+ struct nge_softc *sc;
+ u_int32_t bits;
+ int cnt;
+{
+ int i;
+
+ SIO_CLR(NGE_MEAR_MII_CLK);
+
+ for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
+ if (bits & i) {
+ SIO_SET(NGE_MEAR_MII_DATA);
+ } else {
+ SIO_CLR(NGE_MEAR_MII_DATA);
+ }
+ DELAY(1);
+ SIO_CLR(NGE_MEAR_MII_CLK);
+ DELAY(1);
+ SIO_SET(NGE_MEAR_MII_CLK);
+ }
+}
+
+/*
+ * Read an PHY register through the MII.
+ */
+static int nge_mii_readreg(sc, frame)
+ struct nge_softc *sc;
+ struct nge_mii_frame *frame;
+
+{
+ int i, ack, s;
+
+ s = splimp();
+
+ /*
+ * Set up frame for RX.
+ */
+ frame->mii_stdelim = NGE_MII_STARTDELIM;
+ frame->mii_opcode = NGE_MII_READOP;
+ frame->mii_turnaround = 0;
+ frame->mii_data = 0;
+
+ CSR_WRITE_4(sc, NGE_MEAR, 0);
+
+ /*
+ * Turn on data xmit.
+ */
+ SIO_SET(NGE_MEAR_MII_DIR);
+
+ nge_mii_sync(sc);
+
+ /*
+ * Send command/address info.
+ */
+ nge_mii_send(sc, frame->mii_stdelim, 2);
+ nge_mii_send(sc, frame->mii_opcode, 2);
+ nge_mii_send(sc, frame->mii_phyaddr, 5);
+ nge_mii_send(sc, frame->mii_regaddr, 5);
+
+ /* Idle bit */
+ SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA));
+ DELAY(1);
+ SIO_SET(NGE_MEAR_MII_CLK);
+ DELAY(1);
+
+ /* Turn off xmit. */
+ SIO_CLR(NGE_MEAR_MII_DIR);
+ /* Check for ack */
+ SIO_CLR(NGE_MEAR_MII_CLK);
+ DELAY(1);
+ SIO_SET(NGE_MEAR_MII_CLK);
+ DELAY(1);
+ ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA;
+
+ /*
+ * Now try reading data bits. If the ack failed, we still
+ * need to clock through 16 cycles to keep the PHY(s) in sync.
+ */
+ if (ack) {
+ for(i = 0; i < 16; i++) {
+ SIO_CLR(NGE_MEAR_MII_CLK);
+ DELAY(1);
+ SIO_SET(NGE_MEAR_MII_CLK);
+ DELAY(1);
+ }
+ goto fail;
+ }
+
+ for (i = 0x8000; i; i >>= 1) {
+ SIO_CLR(NGE_MEAR_MII_CLK);
+ DELAY(1);
+ if (!ack) {
+ if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA)
+ frame->mii_data |= i;
+ DELAY(1);
+ }
+ SIO_SET(NGE_MEAR_MII_CLK);
+ DELAY(1);
+ }
+
+fail:
+
+ SIO_CLR(NGE_MEAR_MII_CLK);
+ DELAY(1);
+ SIO_SET(NGE_MEAR_MII_CLK);
+ DELAY(1);
+
+ splx(s);
+
+ if (ack)
+ return(1);
+ return(0);
+}
+
+/*
+ * Write to a PHY register through the MII.
+ */
+static int nge_mii_writereg(sc, frame)
+ struct nge_softc *sc;
+ struct nge_mii_frame *frame;
+
+{
+ int s;
+
+ s = splimp();
+ /*
+ * Set up frame for TX.
+ */
+
+ frame->mii_stdelim = NGE_MII_STARTDELIM;
+ frame->mii_opcode = NGE_MII_WRITEOP;
+ frame->mii_turnaround = NGE_MII_TURNAROUND;
+
+ /*
+ * Turn on data output.
+ */
+ SIO_SET(NGE_MEAR_MII_DIR);
+
+ nge_mii_sync(sc);
+
+ nge_mii_send(sc, frame->mii_stdelim, 2);
+ nge_mii_send(sc, frame->mii_opcode, 2);
+ nge_mii_send(sc, frame->mii_phyaddr, 5);
+ nge_mii_send(sc, frame->mii_regaddr, 5);
+ nge_mii_send(sc, frame->mii_turnaround, 2);
+ nge_mii_send(sc, frame->mii_data, 16);
+
+ /* Idle bit. */
+ SIO_SET(NGE_MEAR_MII_CLK);
+ DELAY(1);
+ SIO_CLR(NGE_MEAR_MII_CLK);
+ DELAY(1);
+
+ /*
+ * Turn off xmit.
+ */
+ SIO_CLR(NGE_MEAR_MII_DIR);
+
+ splx(s);
+
+ return(0);
+}
+
+static int nge_miibus_readreg(dev, phy, reg)
+ device_t dev;
+ int phy, reg;
+{
+ struct nge_softc *sc;
+ struct nge_mii_frame frame;
+
+ sc = device_get_softc(dev);
+
+ bzero((char *)&frame, sizeof(frame));
+
+ frame.mii_phyaddr = phy;
+ frame.mii_regaddr = reg;
+ nge_mii_readreg(sc, &frame);
+
+ return(frame.mii_data);
+}
+
+static int nge_miibus_writereg(dev, phy, reg, data)
+ device_t dev;
+ int phy, reg, data;
+{
+ struct nge_softc *sc;
+ struct nge_mii_frame frame;
+
+ sc = device_get_softc(dev);
+
+ bzero((char *)&frame, sizeof(frame));
+
+ frame.mii_phyaddr = phy;
+ frame.mii_regaddr = reg;
+ frame.mii_data = data;
+ nge_mii_writereg(sc, &frame);
+
+ return(0);
+}
+
+static void nge_miibus_statchg(dev)
+ device_t dev;
+{
+ struct nge_softc *sc;
+ struct mii_data *mii;
+
+ sc = device_get_softc(dev);
+ mii = device_get_softc(sc->nge_miibus);
+
+ if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
+ NGE_SETBIT(sc, NGE_TX_CFG,
+ (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
+ NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
+ } else {
+ NGE_CLRBIT(sc, NGE_TX_CFG,
+ (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
+ NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
+ }
+
+ return;
+}
+
+static u_int32_t nge_crc(sc, addr)
+ struct nge_softc *sc;
+ caddr_t addr;
+{
+ u_int32_t crc, carry;
+ int i, j;
+ u_int8_t c;
+
+ /* Compute CRC for the address value. */
+ crc = 0xFFFFFFFF; /* initial value */
+
+ for (i = 0; i < 6; i++) {
+ c = *(addr + i);
+ for (j = 0; j < 8; j++) {
+ carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
+ crc <<= 1;
+ c >>= 1;
+ if (carry)
+ crc = (crc ^ 0x04c11db6) | carry;
+ }
+ }
+
+ /*
+ * return the filter bit position
+ */
+
+ return((crc >> 21) & 0x00000FFF);
+}
+
+static void nge_setmulti(sc)
+ struct nge_softc *sc;
+{
+ struct ifnet *ifp;
+ struct ifmultiaddr *ifma;
+ u_int32_t h = 0, i, filtsave;
+ int bit, index;
+
+ ifp = &sc->arpcom.ac_if;
+
+ if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
+ NGE_CLRBIT(sc, NGE_RXFILT_CTL,
+ NGE_RXFILTCTL_MCHASH|NGE_RXFILTCTL_UCHASH);
+ NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI);
+ return;
+ }
+
+ /*
+ * We have to explicitly enable the multicast hash table
+ * on the NatSemi chip if we want to use it, which we do.
+ * We also have to tell it that we don't want to use the
+ * hash table for matching unicast addresses.
+ */
+ NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH);
+ NGE_CLRBIT(sc, NGE_RXFILT_CTL,
+ NGE_RXFILTCTL_ALLMULTI|NGE_RXFILTCTL_UCHASH);
+
+ filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL);
+
+ /* first, zot all the existing hash bits */
+ for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) {
+ CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i);
+ CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0);
+ }
+
+ /*
+ * From the 11 bits returned by the crc routine, the top 7
+ * bits represent the 16-bit word in the mcast hash table
+ * that needs to be updated, and the lower 4 bits represent
+ * which bit within that byte needs to be set.
+ */
+ TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
+ if (ifma->ifma_addr->sa_family != AF_LINK)
+ continue;
+ h = nge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
+ index = (h >> 4) & 0x7F;
+ bit = h & 0xF;
+ CSR_WRITE_4(sc, NGE_RXFILT_CTL,
+ NGE_FILTADDR_MCAST_LO + (index * 2));
+ NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit));
+ }
+
+ CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave);
+
+ return;
+}
+
+static void nge_reset(sc)
+ struct nge_softc *sc;
+{
+ register int i;
+
+ NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET);
+
+ for (i = 0; i < NGE_TIMEOUT; i++) {
+ if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET))
+ break;
+ }
+
+ if (i == NGE_TIMEOUT)
+ printf("nge%d: reset never completed\n", sc->nge_unit);
+
+ /* Wait a little while for the chip to get its brains in order. */
+ DELAY(1000);
+
+ /*
+ * If this is a NetSemi chip, make sure to clear
+ * PME mode.
+ */
+ CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS);
+ CSR_WRITE_4(sc, NGE_CLKRUN, 0);
+
+ return;
+}
+
+/*
+ * Probe for an NatSemi chip. Check the PCI vendor and device
+ * IDs against our list and return a device name if we find a match.
+ */
+static int nge_probe(dev)
+ device_t dev;
+{
+ struct nge_type *t;
+
+ t = nge_devs;
+
+ while(t->nge_name != NULL) {
+ if ((pci_get_vendor(dev) == t->nge_vid) &&
+ (pci_get_device(dev) == t->nge_did)) {
+ device_set_desc(dev, t->nge_name);
+ return(0);
+ }
+ t++;
+ }
+
+ return(ENXIO);
+}
+
+/*
+ * Attach the interface. Allocate softc structures, do ifmedia
+ * setup and ethernet/BPF attach.
+ */
+static int nge_attach(dev)
+ device_t dev;
+{
+ int s;
+ u_char eaddr[ETHER_ADDR_LEN];
+ u_int32_t command;
+ struct nge_softc *sc;
+ struct ifnet *ifp;
+ int unit, error = 0, rid;
+
+ s = splimp();
+
+ sc = device_get_softc(dev);
+ unit = device_get_unit(dev);
+ bzero(sc, sizeof(struct nge_softc));
+
+ mtx_init(&sc->nge_mtx, device_get_nameunit(dev), MTX_DEF|MTX_RECURSE);
+
+ /*
+ * Handle power management nonsense.
+ */
+ if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
+ u_int32_t iobase, membase, irq;
+
+ /* Save important PCI config data. */
+ iobase = pci_read_config(dev, NGE_PCI_LOIO, 4);
+ membase = pci_read_config(dev, NGE_PCI_LOMEM, 4);
+ irq = pci_read_config(dev, NGE_PCI_INTLINE, 4);
+
+ /* Reset the power state. */
+ printf("nge%d: chip is in D%d power mode "
+ "-- setting to D0\n", unit,
+ pci_get_powerstate(dev));
+ pci_set_powerstate(dev, PCI_POWERSTATE_D0);
+
+ /* Restore PCI config data. */
+ pci_write_config(dev, NGE_PCI_LOIO, iobase, 4);
+ pci_write_config(dev, NGE_PCI_LOMEM, membase, 4);
+ pci_write_config(dev, NGE_PCI_INTLINE, irq, 4);
+ }
+
+ /*
+ * Map control/status registers.
+ */
+ pci_enable_busmaster(dev);
+ pci_enable_io(dev, PCIM_CMD_PORTEN);
+ pci_enable_io(dev, PCIM_CMD_MEMEN);
+ command = pci_read_config(dev, PCIR_COMMAND, 4);
+
+#ifdef NGE_USEIOSPACE
+ if (!(command & PCIM_CMD_PORTEN)) {
+ printf("nge%d: failed to enable I/O ports!\n", unit);
+ error = ENXIO;;
+ goto fail;
+ }
+#else
+ if (!(command & PCIM_CMD_MEMEN)) {
+ printf("nge%d: failed to enable memory mapping!\n", unit);
+ error = ENXIO;;
+ goto fail;
+ }
+#endif
+
+ rid = NGE_RID;
+ sc->nge_res = bus_alloc_resource(dev, NGE_RES, &rid,
+ 0, ~0, 1, RF_ACTIVE);
+
+ if (sc->nge_res == NULL) {
+ printf("nge%d: couldn't map ports/memory\n", unit);
+ error = ENXIO;
+ goto fail;
+ }
+
+ sc->nge_btag = rman_get_bustag(sc->nge_res);
+ sc->nge_bhandle = rman_get_bushandle(sc->nge_res);
+
+ /* Allocate interrupt */
+ rid = 0;
+ sc->nge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
+ RF_SHAREABLE | RF_ACTIVE);
+
+ if (sc->nge_irq == NULL) {
+ printf("nge%d: couldn't map interrupt\n", unit);
+ bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
+ error = ENXIO;
+ goto fail;
+ }
+
+ error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET,
+ nge_intr, sc, &sc->nge_intrhand);
+
+ if (error) {
+ bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
+ bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
+ printf("nge%d: couldn't set up irq\n", unit);
+ goto fail;
+ }
+
+ /* Reset the adapter. */
+ nge_reset(sc);
+
+ /*
+ * Get station address from the EEPROM.
+ */
+ nge_read_eeprom(sc, (caddr_t)&eaddr[4], NGE_EE_NODEADDR, 1, 0);
+ nge_read_eeprom(sc, (caddr_t)&eaddr[2], NGE_EE_NODEADDR + 1, 1, 0);
+ nge_read_eeprom(sc, (caddr_t)&eaddr[0], NGE_EE_NODEADDR + 2, 1, 0);
+
+ /*
+ * A NatSemi chip was detected. Inform the world.
+ */
+ printf("nge%d: Ethernet address: %6D\n", unit, eaddr, ":");
+
+ sc->nge_unit = unit;
+ bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
+
+ sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF,
+ M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
+
+ if (sc->nge_ldata == NULL) {
+ printf("nge%d: no memory for list buffers!\n", unit);
+ bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
+ bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
+ bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
+ error = ENXIO;
+ goto fail;
+ }
+ bzero(sc->nge_ldata, sizeof(struct nge_list_data));
+
+ /* Try to allocate memory for jumbo buffers. */
+ if (nge_alloc_jumbo_mem(sc)) {
+ printf("nge%d: jumbo buffer allocation failed\n",
+ sc->nge_unit);
+ contigfree(sc->nge_ldata,
+ sizeof(struct nge_list_data), M_DEVBUF);
+ bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
+ bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
+ bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
+ error = ENXIO;
+ goto fail;
+ }
+
+ ifp = &sc->arpcom.ac_if;
+ ifp->if_softc = sc;
+ ifp->if_unit = unit;
+ ifp->if_name = "nge";
+ ifp->if_mtu = ETHERMTU;
+ ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+ ifp->if_ioctl = nge_ioctl;
+ ifp->if_output = ether_output;
+ ifp->if_start = nge_start;
+ ifp->if_watchdog = nge_watchdog;
+ ifp->if_init = nge_init;
+ ifp->if_baudrate = 1000000000;
+ ifp->if_snd.ifq_maxlen = NGE_TX_LIST_CNT - 1;
+ ifp->if_hwassist = NGE_CSUM_FEATURES;
+
+ /*
+ * Do MII setup.
+ */
+ if (mii_phy_probe(dev, &sc->nge_miibus,
+ nge_ifmedia_upd, nge_ifmedia_sts)) {
+ printf("nge%d: MII without any PHY!\n", sc->nge_unit);
+ nge_free_jumbo_mem(sc);
+ bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
+ bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
+ bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
+ error = ENXIO;
+ goto fail;
+ }
+
+ /*
+ * Call MI attach routine.
+ */
+ ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
+ callout_handle_init(&sc->nge_stat_ch);
+
+fail:
+ splx(s);
+ mtx_destroy(&sc->nge_mtx);
+ return(error);
+}
+
+static int nge_detach(dev)
+ device_t dev;
+{
+ struct nge_softc *sc;
+ struct ifnet *ifp;
+ int s;
+
+ s = splimp();
+
+ sc = device_get_softc(dev);
+ ifp = &sc->arpcom.ac_if;
+
+ nge_reset(sc);
+ nge_stop(sc);
+ ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
+
+ bus_generic_detach(dev);
+ device_delete_child(dev, sc->nge_miibus);
+
+ bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
+ bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
+ bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
+
+ contigfree(sc->nge_ldata, sizeof(struct nge_list_data), M_DEVBUF);
+ nge_free_jumbo_mem(sc);
+
+ splx(s);
+ mtx_destroy(&sc->nge_mtx);
+
+ return(0);
+}
+
+/*
+ * Initialize the transmit descriptors.
+ */
+static int nge_list_tx_init(sc)
+ struct nge_softc *sc;
+{
+ struct nge_list_data *ld;
+ struct nge_ring_data *cd;
+ int i;
+
+ cd = &sc->nge_cdata;
+ ld = sc->nge_ldata;
+
+ for (i = 0; i < NGE_TX_LIST_CNT; i++) {
+ if (i == (NGE_TX_LIST_CNT - 1)) {
+ ld->nge_tx_list[i].nge_nextdesc =
+ &ld->nge_tx_list[0];
+ ld->nge_tx_list[i].nge_next =
+ vtophys(&ld->nge_tx_list[0]);
+ } else {
+ ld->nge_tx_list[i].nge_nextdesc =
+ &ld->nge_tx_list[i + 1];
+ ld->nge_tx_list[i].nge_next =
+ vtophys(&ld->nge_tx_list[i + 1]);
+ }
+ ld->nge_tx_list[i].nge_mbuf = NULL;
+ ld->nge_tx_list[i].nge_ptr = 0;
+ ld->nge_tx_list[i].nge_ctl = 0;
+ }
+
+ cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0;
+
+ return(0);
+}
+
+
+/*
+ * Initialize the RX descriptors and allocate mbufs for them. Note that
+ * we arrange the descriptors in a closed ring, so that the last descriptor
+ * points back to the first.
+ */
+static int nge_list_rx_init(sc)
+ struct nge_softc *sc;
+{
+ struct nge_list_data *ld;
+ struct nge_ring_data *cd;
+ int i;
+
+ ld = sc->nge_ldata;
+ cd = &sc->nge_cdata;
+
+ for (i = 0; i < NGE_RX_LIST_CNT; i++) {
+ if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS)
+ return(ENOBUFS);
+ if (i == (NGE_RX_LIST_CNT - 1)) {
+ ld->nge_rx_list[i].nge_nextdesc =
+ &ld->nge_rx_list[0];
+ ld->nge_rx_list[i].nge_next =
+ vtophys(&ld->nge_rx_list[0]);
+ } else {
+ ld->nge_rx_list[i].nge_nextdesc =
+ &ld->nge_rx_list[i + 1];
+ ld->nge_rx_list[i].nge_next =
+ vtophys(&ld->nge_rx_list[i + 1]);
+ }
+ }
+
+ cd->nge_rx_prod = 0;
+
+ return(0);
+}
+
+/*
+ * Initialize an RX descriptor and attach an MBUF cluster.
+ */
+static int nge_newbuf(sc, c, m)
+ struct nge_softc *sc;
+ struct nge_desc *c;
+ struct mbuf *m;
+{
+ struct mbuf *m_new = NULL;
+ caddr_t *buf = NULL;
+
+ if (m == NULL) {
+ MGETHDR(m_new, M_DONTWAIT, MT_DATA);
+ if (m_new == NULL) {
+ printf("nge%d: no memory for rx list "
+ "-- packet dropped!\n", sc->nge_unit);
+ return(ENOBUFS);
+ }
+
+ /* Allocate the jumbo buffer */
+ buf = nge_jalloc(sc);
+ if (buf == NULL) {
+#ifdef NGE_VERBOSE
+ printf("nge%d: jumbo allocation failed "
+ "-- packet dropped!\n", sc->nge_unit);
+#endif
+ m_freem(m_new);
+ return(ENOBUFS);
+ }
+ /* Attach the buffer to the mbuf */
+ m_new->m_data = (void *)buf;
+ m_new->m_len = m_new->m_pkthdr.len = NGE_MCLBYTES;
+ MEXTADD(m_new, buf, NGE_MCLBYTES, nge_jfree,
+ (struct ti_softc *)sc, 0, EXT_NET_DRV);
+ } else {
+ m_new = m;
+ m_new->m_len = m_new->m_pkthdr.len = NGE_MCLBYTES;
+ m_new->m_data = m_new->m_ext.ext_buf;
+ }
+
+ m_adj(m_new, sizeof(u_int64_t));
+
+ c->nge_mbuf = m_new;
+ c->nge_ptr = vtophys(mtod(m_new, caddr_t));
+ c->nge_ctl = m_new->m_len;
+ c->nge_extsts = 0;
+
+ return(0);
+}
+
+static int nge_alloc_jumbo_mem(sc)
+ struct nge_softc *sc;
+{
+ caddr_t ptr;
+ register int i;
+ struct nge_jpool_entry *entry;
+
+ /* Grab a big chunk o' storage. */
+ sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF,
+ M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
+
+ if (sc->nge_cdata.nge_jumbo_buf == NULL) {
+ printf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit);
+ return(ENOBUFS);
+ }
+
+ SLIST_INIT(&sc->nge_jfree_listhead);
+ SLIST_INIT(&sc->nge_jinuse_listhead);
+
+ /*
+ * Now divide it up into 9K pieces and save the addresses
+ * in an array.
+ */
+ ptr = sc->nge_cdata.nge_jumbo_buf;
+ for (i = 0; i < NGE_JSLOTS; i++) {
+ sc->nge_cdata.nge_jslots[i] = ptr;
+ ptr += NGE_MCLBYTES;
+ entry = malloc(sizeof(struct nge_jpool_entry),
+ M_DEVBUF, M_NOWAIT);
+ if (entry == NULL) {
+ free(sc->nge_cdata.nge_jumbo_buf, M_DEVBUF);
+ sc->nge_cdata.nge_jumbo_buf = NULL;
+ printf("nge%d: no memory for jumbo "
+ "buffer queue!\n", sc->nge_unit);
+ return(ENOBUFS);
+ }
+ entry->slot = i;
+ SLIST_INSERT_HEAD(&sc->nge_jfree_listhead,
+ entry, jpool_entries);
+ }
+
+ return(0);
+}
+
+static void nge_free_jumbo_mem(sc)
+ struct nge_softc *sc;
+{
+ register int i;
+ struct nge_jpool_entry *entry;
+
+ for (i = 0; i < NGE_JSLOTS; i++) {
+ entry = SLIST_FIRST(&sc->nge_jfree_listhead);
+ free(entry, M_DEVBUF);
+ SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries);
+ }
+
+ contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF);
+
+ return;
+}
+
+/*
+ * Allocate a jumbo buffer.
+ */
+static void *nge_jalloc(sc)
+ struct nge_softc *sc;
+{
+ struct nge_jpool_entry *entry;
+
+ entry = SLIST_FIRST(&sc->nge_jfree_listhead);
+
+ if (entry == NULL) {
+#ifdef NGE_VERBOSE
+ printf("nge%d: no free jumbo buffers\n", sc->nge_unit);
+#endif
+ return(NULL);
+ }
+
+ SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries);
+ SLIST_INSERT_HEAD(&sc->nge_jinuse_listhead, entry, jpool_entries);
+ return(sc->nge_cdata.nge_jslots[entry->slot]);
+}
+
+/*
+ * Release a jumbo buffer.
+ */
+static void nge_jfree(buf, args)
+ caddr_t buf;
+ void *args;
+{
+ struct nge_softc *sc;
+ int i;
+ struct nge_jpool_entry *entry;
+
+ /* Extract the softc struct pointer. */
+ sc = args;
+
+ if (sc == NULL)
+ panic("nge_jfree: can't find softc pointer!");
+
+ /* calculate the slot this buffer belongs to */
+ i = ((vm_offset_t)buf
+ - (vm_offset_t)sc->nge_cdata.nge_jumbo_buf) / NGE_JLEN;
+
+ if ((i < 0) || (i >= NGE_JSLOTS))
+ panic("nge_jfree: asked to free buffer that we don't manage!");
+
+ entry = SLIST_FIRST(&sc->nge_jinuse_listhead);
+ if (entry == NULL)
+ panic("nge_jfree: buffer not in use!");
+ entry->slot = i;
+ SLIST_REMOVE_HEAD(&sc->nge_jinuse_listhead, jpool_entries);
+ SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jpool_entries);
+
+ return;
+}
+/*
+ * A frame has been uploaded: pass the resulting mbuf chain up to
+ * the higher level protocols.
+ */
+static void nge_rxeof(sc)
+ struct nge_softc *sc;
+{
+ struct ether_header *eh;
+ struct mbuf *m;
+ struct ifnet *ifp;
+ struct nge_desc *cur_rx;
+ int i, total_len = 0;
+ u_int32_t rxstat;
+
+ ifp = &sc->arpcom.ac_if;
+ i = sc->nge_cdata.nge_rx_prod;
+
+ while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) {
+ struct mbuf *m0 = NULL;
+ u_int32_t extsts;
+
+ cur_rx = &sc->nge_ldata->nge_rx_list[i];
+ rxstat = cur_rx->nge_rxstat;
+ extsts = cur_rx->nge_extsts;
+ m = cur_rx->nge_mbuf;
+ cur_rx->nge_mbuf = NULL;
+ total_len = NGE_RXBYTES(cur_rx);
+ NGE_INC(i, NGE_RX_LIST_CNT);
+
+ /*
+ * If an error occurs, update stats, clear the
+ * status word and leave the mbuf cluster in place:
+ * it should simply get re-used next time this descriptor
+ * comes up in the ring.
+ */
+ if (!(rxstat & NGE_CMDSTS_PKT_OK)) {
+ ifp->if_ierrors++;
+ nge_newbuf(sc, cur_rx, m);
+ continue;
+ }
+
+
+ /*
+ * Ok. NatSemi really screwed up here. This is the
+ * only gigE chip I know of with alignment constraints
+ * on receive buffers. RX buffers must be 64-bit aligned.
+ */
+ m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
+ total_len + ETHER_ALIGN, 0, ifp, NULL);
+ nge_newbuf(sc, cur_rx, m);
+ if (m0 == NULL) {
+ printf("nge%d: no receive buffers "
+ "available -- packet dropped!\n",
+ sc->nge_unit);
+ ifp->if_ierrors++;
+ continue;
+ }
+ m_adj(m0, ETHER_ALIGN);
+ m = m0;
+
+ ifp->if_ipackets++;
+ eh = mtod(m, struct ether_header *);
+
+ /* Remove header from mbuf and pass it on. */
+ m_adj(m, sizeof(struct ether_header));
+
+ /* Do IP checksum checking. */
+ if (ifp->if_hwassist) {
+ if (extsts & NGE_RXEXTSTS_IPPKT)
+ m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
+ if (!(extsts & NGE_RXEXTSTS_IPCSUMERR))
+ m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
+ }
+
+#if NVLAN > 0
+ /*
+ * If we received a packet with a vlan tag, pass it
+ * to vlan_input() instead of ether_input().
+ */
+ if (extsts & NGE_RXEXTSTS_VLANPKT) {
+ vlan_input_tag(eh, m, extsts & NGE_RXEXTSTS_VTCI);
+ continue;
+ }
+#endif
+
+ ether_input(ifp, eh, m);
+ }
+
+ sc->nge_cdata.nge_rx_prod = i;
+
+ return;
+}
+
+void nge_rxeoc(sc)
+ struct nge_softc *sc;
+{
+ struct ifnet *ifp;
+
+ ifp = &sc->arpcom.ac_if;
+ nge_rxeof(sc);
+ ifp->if_flags &= ~IFF_RUNNING;
+ nge_init(sc);
+ return;
+}
+
+/*
+ * A frame was downloaded to the chip. It's safe for us to clean up
+ * the list buffers.
+ */
+
+static void nge_txeof(sc)
+ struct nge_softc *sc;
+{
+ struct nge_desc *cur_tx = NULL;
+ struct ifnet *ifp;
+ u_int32_t idx;
+
+ ifp = &sc->arpcom.ac_if;
+
+ /* Clear the timeout timer. */
+ ifp->if_timer = 0;
+
+ /*
+ * Go through our tx list and free mbufs for those
+ * frames that have been transmitted.
+ */
+ idx = sc->nge_cdata.nge_tx_cons;
+ while (idx != sc->nge_cdata.nge_tx_prod) {
+ cur_tx = &sc->nge_ldata->nge_tx_list[idx];
+
+ if (NGE_OWNDESC(cur_tx))
+ break;
+
+ if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) {
+ sc->nge_cdata.nge_tx_cnt--;
+ NGE_INC(idx, NGE_TX_LIST_CNT);
+ continue;
+ }
+
+ if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) {
+ ifp->if_oerrors++;
+ if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS)
+ ifp->if_collisions++;
+ if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL)
+ ifp->if_collisions++;
+ }
+
+ ifp->if_collisions +=
+ (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16;
+
+ ifp->if_opackets++;
+ if (cur_tx->nge_mbuf != NULL) {
+ m_freem(cur_tx->nge_mbuf);
+ cur_tx->nge_mbuf = NULL;
+ }
+
+ sc->nge_cdata.nge_tx_cnt--;
+ NGE_INC(idx, NGE_TX_LIST_CNT);
+ ifp->if_timer = 0;
+ }
+
+ sc->nge_cdata.nge_tx_cons = idx;
+
+ if (cur_tx != NULL)
+ ifp->if_flags &= ~IFF_OACTIVE;
+
+ return;
+}
+
+static void nge_tick(xsc)
+ void *xsc;
+{
+ struct nge_softc *sc;
+ struct mii_data *mii;
+ struct ifnet *ifp;
+ int s;
+
+ s = splimp();
+
+ sc = xsc;
+ ifp = &sc->arpcom.ac_if;
+
+ mii = device_get_softc(sc->nge_miibus);
+ mii_tick(mii);
+
+ if (!sc->nge_link) {
+ mii_pollstat(mii);
+ if (mii->mii_media_status & IFM_ACTIVE &&
+ IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
+ sc->nge_link++;
+ if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX)
+ printf("nge%d: gigabit link up\n",
+ sc->nge_unit);
+ if (ifp->if_snd.ifq_head != NULL)
+ nge_start(ifp);
+ } else
+ sc->nge_stat_ch = timeout(nge_tick, sc, hz);
+ }
+
+
+ splx(s);
+
+ return;
+}
+
+static void nge_intr(arg)
+ void *arg;
+{
+ struct nge_softc *sc;
+ struct ifnet *ifp;
+ u_int32_t status;
+
+ sc = arg;
+ ifp = &sc->arpcom.ac_if;
+
+ /* Supress unwanted interrupts */
+ if (!(ifp->if_flags & IFF_UP)) {
+ nge_stop(sc);
+ return;
+ }
+
+ /* Disable interrupts. */
+ CSR_WRITE_4(sc, NGE_IER, 0);
+
+ for (;;) {
+ /* Reading the ISR register clears all interrupts. */
+ status = CSR_READ_4(sc, NGE_ISR);
+
+ if ((status & NGE_INTRS) == 0)
+ break;
+
+ if ((status & NGE_ISR_TX_DESC_OK) ||
+ (status & NGE_ISR_TX_ERR) ||
+ (status & NGE_ISR_TX_OK) ||
+ (status & NGE_ISR_TX_IDLE))
+ nge_txeof(sc);
+
+ if ((status & NGE_ISR_RX_DESC_OK) ||
+ (status & NGE_ISR_RX_OK))
+ nge_rxeof(sc);
+
+ if ((status & NGE_ISR_RX_ERR) ||
+ (status & NGE_ISR_RX_OFLOW)) {
+ nge_rxeoc(sc);
+ }
+
+ if (status & NGE_ISR_SYSERR) {
+ nge_reset(sc);
+ ifp->if_flags &= ~IFF_RUNNING;
+ nge_init(sc);
+ }
+
+ if (status & NGE_IMR_PHY_INTR) {
+ sc->nge_link = 0;
+ nge_tick(sc);
+ }
+ }
+
+ /* Re-enable interrupts. */
+ CSR_WRITE_4(sc, NGE_IER, 1);
+
+ if (ifp->if_snd.ifq_head != NULL)
+ nge_start(ifp);
+
+ return;
+}
+
+/*
+ * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
+ * pointers to the fragment pointers.
+ */
+static int nge_encap(sc, m_head, txidx)
+ struct nge_softc *sc;
+ struct mbuf *m_head;
+ u_int32_t *txidx;
+{
+ struct nge_desc *f = NULL;
+ struct mbuf *m;
+ int frag, cur, cnt = 0;
+#if NVLAN > 0
+ struct ifvlan *ifv = NULL;
+
+ if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
+ m_head->m_pkthdr.rcvif != NULL &&
+ m_head->m_pkthdr.rcvif->if_type == IFT_8021_VLAN)
+ ifv = m_head->m_pkthdr.rcvif->if_softc;
+#endif
+
+ /*
+ * Start packing the mbufs in this chain into
+ * the fragment pointers. Stop when we run out
+ * of fragments or hit the end of the mbuf chain.
+ */
+ m = m_head;
+ cur = frag = *txidx;
+
+ for (m = m_head; m != NULL; m = m->m_next) {
+ if (m->m_len != 0) {
+ if ((NGE_TX_LIST_CNT -
+ (sc->nge_cdata.nge_tx_cnt + cnt)) < 2)
+ return(ENOBUFS);
+ f = &sc->nge_ldata->nge_tx_list[frag];
+ f->nge_ctl = NGE_CMDSTS_MORE | m->m_len;
+ f->nge_ptr = vtophys(mtod(m, vm_offset_t));
+ if (cnt != 0)
+ f->nge_ctl |= NGE_CMDSTS_OWN;
+ cur = frag;
+ NGE_INC(frag, NGE_TX_LIST_CNT);
+ cnt++;
+ }
+ }
+
+ if (m != NULL)
+ return(ENOBUFS);
+
+ sc->nge_ldata->nge_tx_list[cur].nge_extsts = 0;
+ if (m_head->m_pkthdr.csum_flags) {
+ if (m_head->m_pkthdr.csum_flags & CSUM_IP)
+ sc->nge_ldata->nge_tx_list[cur].nge_extsts |=
+ NGE_TXEXTSTS_IPCSUM;
+ if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
+ sc->nge_ldata->nge_tx_list[cur].nge_extsts |=
+ NGE_TXEXTSTS_TCPCSUM;
+ if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
+ sc->nge_ldata->nge_tx_list[cur].nge_extsts |=
+ NGE_TXEXTSTS_UDPCSUM;
+ }
+
+#if NVLAN > 0
+ if (ifv != NULL) {
+ sc->nge_ldata->nge_tx_list[cur].nge_extsts |=
+ (NGE_TXEXTSTS_VLANPKT|ifv->ifv_tag);
+ }
+#endif
+
+ sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head;
+ sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE;
+ sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN;
+ sc->nge_cdata.nge_tx_cnt += cnt;
+ *txidx = frag;
+
+ return(0);
+}
+
+/*
+ * Main transmit routine. To avoid having to do mbuf copies, we put pointers
+ * to the mbuf data regions directly in the transmit lists. We also save a
+ * copy of the pointers since the transmit list fragment pointers are
+ * physical addresses.
+ */
+
+static void nge_start(ifp)
+ struct ifnet *ifp;
+{
+ struct nge_softc *sc;
+ struct mbuf *m_head = NULL;
+ u_int32_t idx;
+
+ sc = ifp->if_softc;
+
+ if (!sc->nge_link)
+ return;
+
+ idx = sc->nge_cdata.nge_tx_prod;
+
+ if (ifp->if_flags & IFF_OACTIVE)
+ return;
+
+ while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) {
+ IF_DEQUEUE(&ifp->if_snd, m_head);
+ if (m_head == NULL)
+ break;
+
+ if (nge_encap(sc, m_head, &idx)) {
+ IF_PREPEND(&ifp->if_snd, m_head);
+ ifp->if_flags |= IFF_OACTIVE;
+ break;
+ }
+
+ /*
+ * If there's a BPF listener, bounce a copy of this frame
+ * to him.
+ */
+ if (ifp->if_bpf)
+ bpf_mtap(ifp, m_head);
+
+ }
+
+ /* Transmit */
+ sc->nge_cdata.nge_tx_prod = idx;
+ NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE);
+
+ /*
+ * Set a timeout in case the chip goes out to lunch.
+ */
+ ifp->if_timer = 5;
+
+ return;
+}
+
+static void nge_init(xsc)
+ void *xsc;
+{
+ struct nge_softc *sc = xsc;
+ struct ifnet *ifp = &sc->arpcom.ac_if;
+ struct mii_data *mii;
+ int s;
+
+ if (ifp->if_flags & IFF_RUNNING)
+ return;
+
+ s = splimp();
+
+ /*
+ * Cancel pending I/O and free all RX/TX buffers.
+ */
+ nge_stop(sc);
+
+ mii = device_get_softc(sc->nge_miibus);
+
+ /* Set MAC address */
+ CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0);
+ CSR_WRITE_4(sc, NGE_RXFILT_DATA,
+ ((u_int16_t *)sc->arpcom.ac_enaddr)[0]);
+ CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1);
+ CSR_WRITE_4(sc, NGE_RXFILT_DATA,
+ ((u_int16_t *)sc->arpcom.ac_enaddr)[1]);
+ CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2);
+ CSR_WRITE_4(sc, NGE_RXFILT_DATA,
+ ((u_int16_t *)sc->arpcom.ac_enaddr)[2]);
+
+ /* Init circular RX list. */
+ if (nge_list_rx_init(sc) == ENOBUFS) {
+ printf("nge%d: initialization failed: no "
+ "memory for rx buffers\n", sc->nge_unit);
+ nge_stop(sc);
+ (void)splx(s);
+ return;
+ }
+
+ /*
+ * Init tx descriptors.
+ */
+ nge_list_tx_init(sc);
+
+ /*
+ * For the NatSemi chip, we have to explicitly enable the
+ * reception of ARP frames, as well as turn on the 'perfect
+ * match' filter where we store the station address, otherwise
+ * we won't receive unicasts meant for this host.
+ */
+ NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP);
+ NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT);
+
+ /* If we want promiscuous mode, set the allframes bit. */
+ if (ifp->if_flags & IFF_PROMISC) {
+ NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
+ } else {
+ NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
+ }
+
+ /*
+ * Set the capture broadcast bit to capture broadcast frames.
+ */
+ if (ifp->if_flags & IFF_BROADCAST) {
+ NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
+ } else {
+ NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
+ }
+
+ /*
+ * Load the multicast filter.
+ */
+ nge_setmulti(sc);
+
+ /* Turn the receive filter on */
+ NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE);
+
+ /*
+ * Load the address of the RX and TX lists.
+ */
+ CSR_WRITE_4(sc, NGE_RX_LISTPTR,
+ vtophys(&sc->nge_ldata->nge_rx_list[0]));
+ CSR_WRITE_4(sc, NGE_TX_LISTPTR,
+ vtophys(&sc->nge_ldata->nge_tx_list[0]));
+
+ /* Set RX configuration */
+ CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG);
+ /*
+ * Enable hardware checksum validation for all IPv4
+ * packets, do not reject packets with bad checksums.
+ */
+ if (ifp->if_hwassist)
+ CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB);
+
+#if NVLAN > 0
+ /*
+ * If VLAN support is enabled, tell the chip to detect
+ * and strip VLAN tag info from received frames. The tag
+ * will be provided in the extsts field in the RX descriptors.
+ */
+ NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL,
+ NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB);
+#endif
+
+ /* Set TX configuration */
+ CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG);
+
+ /*
+ * Enable TX IPv4 checksumming on a per-packet basis.
+ */
+ if (ifp->if_hwassist)
+ CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT);
+
+#if NVLAN > 0
+ /*
+ * If VLAN support is enabled, tell the chip to insert
+ * VLAN tags on a per-packet basis as dictated by the
+ * code in the frame encapsulation routine.
+ */
+ NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT);
+#endif
+
+ /* Set full/half duplex mode. */
+ if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
+ NGE_SETBIT(sc, NGE_TX_CFG,
+ (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
+ NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
+ } else {
+ NGE_CLRBIT(sc, NGE_TX_CFG,
+ (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
+ NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
+ }
+
+ /*
+ * Enable the delivery of PHY interrupts based on
+ * link/speed/duplex status changes.
+ */
+ NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD|NGE_CFG_MODE_1000|
+ NGE_CFG_PHYINTR_LNK|NGE_CFG_PHYINTR_DUP);
+
+ /*
+ * Enable interrupts.
+ */
+ CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS);
+ CSR_WRITE_4(sc, NGE_IER, 1);
+
+ /* Enable receiver and transmitter. */
+ NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE);
+ NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
+
+ nge_ifmedia_upd(ifp);
+
+ ifp->if_flags |= IFF_RUNNING;
+ ifp->if_flags &= ~IFF_OACTIVE;
+
+ (void)splx(s);
+
+ return;
+}
+
+/*
+ * Set media options.
+ */
+static int nge_ifmedia_upd(ifp)
+ struct ifnet *ifp;
+{
+ struct nge_softc *sc;
+ struct mii_data *mii;
+
+ sc = ifp->if_softc;
+
+ mii = device_get_softc(sc->nge_miibus);
+ sc->nge_link = 0;
+ if (mii->mii_instance) {
+ struct mii_softc *miisc;
+ for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
+ miisc = LIST_NEXT(miisc, mii_list))
+ mii_phy_reset(miisc);
+ }
+ mii_mediachg(mii);
+
+ return(0);
+}
+
+/*
+ * Report current media status.
+ */
+static void nge_ifmedia_sts(ifp, ifmr)
+ struct ifnet *ifp;
+ struct ifmediareq *ifmr;
+{
+ struct nge_softc *sc;
+ struct mii_data *mii;
+
+ sc = ifp->if_softc;
+
+ mii = device_get_softc(sc->nge_miibus);
+ mii_pollstat(mii);
+ ifmr->ifm_active = mii->mii_media_active;
+ ifmr->ifm_status = mii->mii_media_status;
+
+ return;
+}
+
+static int nge_ioctl(ifp, command, data)
+ struct ifnet *ifp;
+ u_long command;
+ caddr_t data;
+{
+ struct nge_softc *sc = ifp->if_softc;
+ struct ifreq *ifr = (struct ifreq *) data;
+ struct mii_data *mii;
+ int s, error = 0;
+
+ s = splimp();
+
+ switch(command) {
+ case SIOCSIFADDR:
+ case SIOCGIFADDR:
+ error = ether_ioctl(ifp, command, data);
+ break;
+ case SIOCSIFMTU:
+ if (ifr->ifr_mtu > NGE_JUMBO_MTU)
+ error = EINVAL;
+ else
+ ifp->if_mtu = ifr->ifr_mtu;
+ break;
+ case SIOCSIFFLAGS:
+ if (ifp->if_flags & IFF_UP) {
+ if (ifp->if_flags & IFF_RUNNING &&
+ ifp->if_flags & IFF_PROMISC &&
+ !(sc->nge_if_flags & IFF_PROMISC)) {
+ NGE_SETBIT(sc, NGE_RXFILT_CTL,
+ NGE_RXFILTCTL_ALLPHYS|
+ NGE_RXFILTCTL_ALLMULTI);
+ } else if (ifp->if_flags & IFF_RUNNING &&
+ !(ifp->if_flags & IFF_PROMISC) &&
+ sc->nge_if_flags & IFF_PROMISC) {
+ NGE_CLRBIT(sc, NGE_RXFILT_CTL,
+ NGE_RXFILTCTL_ALLPHYS);
+ if (!(ifp->if_flags & IFF_ALLMULTI))
+ NGE_CLRBIT(sc, NGE_RXFILT_CTL,
+ NGE_RXFILTCTL_ALLMULTI);
+ } else {
+ ifp->if_flags &= ~IFF_RUNNING;
+ nge_init(sc);
+ }
+ } else {
+ if (ifp->if_flags & IFF_RUNNING)
+ nge_stop(sc);
+ }
+ sc->nge_if_flags = ifp->if_flags;
+ error = 0;
+ break;
+ case SIOCADDMULTI:
+ case SIOCDELMULTI:
+ nge_setmulti(sc);
+ error = 0;
+ break;
+ case SIOCGIFMEDIA:
+ case SIOCSIFMEDIA:
+ mii = device_get_softc(sc->nge_miibus);
+ error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
+ break;
+ default:
+ error = EINVAL;
+ break;
+ }
+
+ (void)splx(s);
+
+ return(error);
+}
+
+static void nge_watchdog(ifp)
+ struct ifnet *ifp;
+{
+ struct nge_softc *sc;
+
+ sc = ifp->if_softc;
+
+ ifp->if_oerrors++;
+ printf("nge%d: watchdog timeout\n", sc->nge_unit);
+
+ nge_stop(sc);
+ nge_reset(sc);
+ ifp->if_flags &= ~IFF_RUNNING;
+ nge_init(sc);
+
+ if (ifp->if_snd.ifq_head != NULL)
+ nge_start(ifp);
+
+ return;
+}
+
+/*
+ * Stop the adapter and free any mbufs allocated to the
+ * RX and TX lists.
+ */
+static void nge_stop(sc)
+ struct nge_softc *sc;
+{
+ register int i;
+ struct ifnet *ifp;
+ struct ifmedia_entry *ifm;
+ struct mii_data *mii;
+ int mtmp, itmp;
+
+ ifp = &sc->arpcom.ac_if;
+ ifp->if_timer = 0;
+ mii = device_get_softc(sc->nge_miibus);
+
+ untimeout(nge_tick, sc, sc->nge_stat_ch);
+ CSR_WRITE_4(sc, NGE_IER, 0);
+ CSR_WRITE_4(sc, NGE_IMR, 0);
+ NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE);
+ DELAY(1000);
+ CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0);
+ CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0);
+
+ /*
+ * Isolate/power down the PHY, but leave the media selection
+ * unchanged so that things will be put back to normal when
+ * we bring the interface back up.
+ */
+ itmp = ifp->if_flags;
+ ifp->if_flags |= IFF_UP;
+ ifm = mii->mii_media.ifm_cur;
+ mtmp = ifm->ifm_media;
+ ifm->ifm_media = IFM_ETHER|IFM_NONE;
+ mii_mediachg(mii);
+ ifm->ifm_media = mtmp;
+ ifp->if_flags = itmp;
+
+ sc->nge_link = 0;
+
+ /*
+ * Free data in the RX lists.
+ */
+ for (i = 0; i < NGE_RX_LIST_CNT; i++) {
+ if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) {
+ m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf);
+ sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL;
+ }
+ }
+ bzero((char *)&sc->nge_ldata->nge_rx_list,
+ sizeof(sc->nge_ldata->nge_rx_list));
+
+ /*
+ * Free the TX list buffers.
+ */
+ for (i = 0; i < NGE_TX_LIST_CNT; i++) {
+ if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) {
+ m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf);
+ sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL;
+ }
+ }
+
+ bzero((char *)&sc->nge_ldata->nge_tx_list,
+ sizeof(sc->nge_ldata->nge_tx_list));
+
+ ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
+
+ return;
+}
+
+/*
+ * Stop all chip I/O so that the kernel's probe routines don't
+ * get confused by errant DMAs when rebooting.
+ */
+static void nge_shutdown(dev)
+ device_t dev;
+{
+ struct nge_softc *sc;
+
+ sc = device_get_softc(dev);
+
+ nge_reset(sc);
+ nge_stop(sc);
+
+ return;
+}
diff --git a/sys/dev/nge/if_ngereg.h b/sys/dev/nge/if_ngereg.h
new file mode 100644
index 0000000..e53bcdb
--- /dev/null
+++ b/sys/dev/nge/if_ngereg.h
@@ -0,0 +1,706 @@
+/*
+ * Copyright (c) 2001 Wind River Systems
+ * Copyright (c) 1997, 1998, 1999, 2000, 2001
+ * Bill Paul <wpaul@bsdi.com>. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Bill Paul.
+ * 4. Neither the name of the author nor the names of any co-contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#define NGE_CSR 0x00
+#define NGE_CFG 0x04
+#define NGE_MEAR 0x08
+#define NGE_PCITST 0x0C
+#define NGE_ISR 0x10
+#define NGE_IMR 0x14
+#define NGE_IER 0x18
+#define NGE_IHR 0x1C
+#define NGE_TX_LISTPTR_LO 0x20
+#define NGE_TX_LISTPTR_HI 0x24
+#define NGE_TX_LISTPTR NGE_TX_LISTPTR_LO
+#define NGE_TX_CFG 0x28
+#define NGE_GPIO 0x2C
+#define NGE_RX_LISTPTR_LO 0x30
+#define NGE_RX_LISTPTR_HI 0x34
+#define NGE_RX_LISTPTR NGE_RX_LISTPTR_LO
+#define NGE_RX_CFG 0x38
+#define NGE_PRIOQCTL 0x3C
+#define NGE_WOLCSR 0x40
+#define NGE_PAUSECSR 0x44
+#define NGE_RXFILT_CTL 0x48
+#define NGE_RXFILT_DATA 0x4C
+#define NGE_BOOTROM_ADDR 0x50
+#define NGE_BOOTROM_DATA 0x54
+#define NGE_SILICONREV 0x58
+#define NGE_MIBCTL 0x5C
+#define NGE_MIB_RXERRPKT 0x60
+#define NGE_MIB_RXERRFCS 0x64
+#define NGE_MIB_RXERRMISSEDPKT 0x68
+#define NGE_MIB_RXERRALIGN 0x6C
+#define NGE_MIB_RXERRSYM 0x70
+#define NGE_MIB_RXERRGIANT 0x74
+#define NGE_MIB_RXERRRANGLEN 0x78
+#define NGE_MIB_RXBADOPCODE 0x7C
+#define NGE_MIB_RXPAUSEPKTS 0x80
+#define NGE_MIB_TXPAUSEPKTS 0x84
+#define NGE_MIB_TXERRSQE 0x88
+#define NGE_TXPRIOQ_PTR1 0xA0
+#define NGE_TXPRIOQ_PTR2 0xA4
+#define NGE_TXPRIOQ_PTR3 0xA8
+#define NGE_RXPRIOQ_PTR1 0xB0
+#define NGE_RXPRIOQ_PTR2 0xB4
+#define NGE_RXPRIOQ_PTR3 0xB8
+#define NGE_VLAN_IP_RXCTL 0xBC
+#define NGE_VLAN_IP_TXCTL 0xC0
+#define NGE_VLAN_DATA 0xC4
+#define NGE_CLKRUN 0xCC
+#define NGE_TBI_BMCR 0xE0
+#define NGE_TBI_BMSR 0xE4
+#define NGE_TBI_ANAR 0xE8
+#define NGE_TBI_ANLPAR 0xEC
+#define NGE_TBI_ANER 0xF0
+#define NGE_TBI_ESR 0xF4
+
+/* Control/status register */
+#define NGE_CSR_TX_ENABLE 0x00000001
+#define NGE_CSR_TX_DISABLE 0x00000002
+#define NGE_CSR_RX_ENABLE 0x00000004
+#define NGE_CSR_RX_DISABLE 0x00000008
+#define NGE_CSR_TX_RESET 0x00000010
+#define NGE_CSR_RX_RESET 0x00000020
+#define NGE_CSR_SOFTINTR 0x00000080
+#define NGE_CSR_RESET 0x00000100
+#define NGE_CSR_TX_PRIOQ_ENB0 0x00000200
+#define NGE_CSR_TX_PRIOQ_ENB1 0x00000400
+#define NGE_CSR_TX_PRIOQ_ENB2 0x00000800
+#define NGE_CSR_TX_PRIOQ_ENB3 0x00001000
+#define NGE_CSR_RX_PRIOQ_ENB0 0x00002000
+#define NGE_CSR_RX_PRIOQ_ENB1 0x00004000
+#define NGE_CSR_RX_PRIOQ_ENB2 0x00008000
+#define NGE_CSR_RX_PRIOQ_ENB3 0x00010000
+
+/* Configuration register */
+#define NGE_CFG_BIGENDIAN 0x00000001
+#define NGE_CFG_EXT_125MHZ 0x00000002
+#define NGE_CFG_BOOTROM_DIS 0x00000004
+#define NGE_CFG_PERR_DETECT 0x00000008
+#define NGE_CFG_DEFER_DISABLE 0x00000010
+#define NGE_CFG_OUTOFWIN_TIMER 0x00000020
+#define NGE_CFG_SINGLE_BACKOFF 0x00000040
+#define NGE_CFG_PCIREQ_ALG 0x00000080
+#define NGE_CFG_EXTSTS_ENB 0x00000100
+#define NGE_CFG_PHY_DIS 0x00000200
+#define NGE_CFG_PHY_RST 0x00000400
+#define NGE_CFG_64BIT_ADDR_ENB 0x00000800
+#define NGE_CFG_64BIT_DATA_ENB 0x00001000
+#define NGE_CFG_64BIT_PCI_DET 0x00002000
+#define NGE_CFG_64BIT_TARG 0x00004000
+#define NGE_CFG_MWI_DIS 0x00008000
+#define NGE_CFG_MRM_DIS 0x00010000
+#define NGE_CFG_TMRTST 0x00020000
+#define NGE_CFG_PHYINTR_SPD 0x00040000
+#define NGE_CFG_PHYINTR_LNK 0x00080000
+#define NGE_CFG_PHYINTR_DUP 0x00100000
+#define NGE_CFG_MODE_1000 0x00400000
+#define NGE_CFG_DUPLEX_STS 0x10000000
+#define NGE_CFG_SPEED_STS 0x60000000
+#define NGE_CFG_LINK_STS 0x80000000
+
+/* MII/EEPROM control register */
+#define NGE_MEAR_EE_DIN 0x00000001
+#define NGE_MEAR_EE_DOUT 0x00000002
+#define NGE_MEAR_EE_CLK 0x00000004
+#define NGE_MEAR_EE_CSEL 0x00000008
+#define NGE_MEAR_MII_DATA 0x00000010
+#define NGE_MEAR_MII_DIR 0x00000020
+#define NGE_MEAR_MII_CLK 0x00000040
+
+#define NGE_EECMD_WRITE 0x140
+#define NGE_EECMD_READ 0x180
+#define NGE_EECMD_ERASE 0x1c0
+
+#define NGE_EE_NODEADDR 0xA
+
+/* PCI control register */
+#define NGE_PCICTL_SRAMADDR 0x0000001F
+#define NGE_PCICTL_RAMTSTENB 0x00000020
+#define NGE_PCICTL_TXTSTENB 0x00000040
+#define NGE_PCICTL_RXTSTENB 0x00000080
+#define NGE_PCICTL_BMTSTENB 0x00000200
+#define NGE_PCICTL_RAMADDR 0x001F0000
+#define NGE_PCICTL_ROMTIME 0x0F000000
+#define NGE_PCICTL_DISCTEST 0x40000000
+
+/* Interrupt/status register */
+#define NGE_ISR_RX_OK 0x00000001
+#define NGE_ISR_RX_DESC_OK 0x00000002
+#define NGE_ISR_RX_ERR 0x00000004
+#define NGE_ISR_RX_EARLY 0x00000008
+#define NGE_ISR_RX_IDLE 0x00000010
+#define NGE_ISR_RX_OFLOW 0x00000020
+#define NGE_ISR_TX_OK 0x00000040
+#define NGE_ISR_TX_DESC_OK 0x00000080
+#define NGE_ISR_TX_ERR 0x00000100
+#define NGE_ISR_TX_IDLE 0x00000200
+#define NGE_ISR_TX_UFLOW 0x00000400
+#define NGE_ISR_MIB_SERVICE 0x00000800
+#define NGE_ISR_SOFTINTR 0x00001000
+#define NGE_ISR_PME_EVENT 0x00002000
+#define NGE_ISR_PHY_INTR 0x00004000
+#define NGE_ISR_HIBITS 0x00008000
+#define NGE_ISR_RX_FIFO_OFLOW 0x00010000
+#define NGE_ISR_TGT_ABRT 0x00020000
+#define NGE_ISR_BM_ABRT 0x00040000
+#define NGE_ISR_SYSERR 0x00080000
+#define NGE_ISR_PARITY_ERR 0x00100000
+#define NGE_ISR_RX_RESET_DONE 0x00200000
+#define NGE_ISR_TX_RESET_DONE 0x00400000
+#define NGE_ISR_RX_PRIOQ_DESC0 0x00800000
+#define NGE_ISR_RX_PRIOQ_DESC1 0x01000000
+#define NGE_ISR_RX_PRIOQ_DESC2 0x02000000
+#define NGE_ISR_RX_PRIOQ_DESC3 0x04000000
+#define NGE_ISR_TX_PRIOQ_DESC0 0x08000000
+#define NGE_ISR_TX_PRIOQ_DESC1 0x10000000
+#define NGE_ISR_TX_PRIOQ_DESC2 0x20000000
+#define NGE_ISR_TX_PRIOQ_DESC3 0x40000000
+
+/* Interrupt mask register */
+#define NGE_IMR_RX_OK 0x00000001
+#define NGE_IMR_RX_DESC_OK 0x00000002
+#define NGE_IMR_RX_ERR 0x00000004
+#define NGE_IMR_RX_EARLY 0x00000008
+#define NGE_IMR_RX_IDLE 0x00000010
+#define NGE_IMR_RX_OFLOW 0x00000020
+#define NGE_IMR_TX_OK 0x00000040
+#define NGE_IMR_TX_DESC_OK 0x00000080
+#define NGE_IMR_TX_ERR 0x00000100
+#define NGE_IMR_TX_IDLE 0x00000200
+#define NGE_IMR_TX_UFLOW 0x00000400
+#define NGE_IMR_MIB_SERVICE 0x00000800
+#define NGE_IMR_SOFTINTR 0x00001000
+#define NGE_IMR_PME_EVENT 0x00002000
+#define NGE_IMR_PHY_INTR 0x00004000
+#define NGE_IMR_HIBITS 0x00008000
+#define NGE_IMR_RX_FIFO_OFLOW 0x00010000
+#define NGE_IMR_TGT_ABRT 0x00020000
+#define NGE_IMR_BM_ABRT 0x00040000
+#define NGE_IMR_SYSERR 0x00080000
+#define NGE_IMR_PARITY_ERR 0x00100000
+#define NGE_IMR_RX_RESET_DONE 0x00200000
+#define NGE_IMR_TX_RESET_DONE 0x00400000
+#define NGE_IMR_RX_PRIOQ_DESC0 0x00800000
+#define NGE_IMR_RX_PRIOQ_DESC1 0x01000000
+#define NGE_IMR_RX_PRIOQ_DESC2 0x02000000
+#define NGE_IMR_RX_PRIOQ_DESC3 0x04000000
+#define NGE_IMR_TX_PRIOQ_DESC0 0x08000000
+#define NGE_IMR_TX_PRIOQ_DESC1 0x10000000
+#define NGE_IMR_TX_PRIOQ_DESC2 0x20000000
+#define NGE_IMR_TX_PRIOQ_DESC3 0x40000000
+
+#define NGE_INTRS \
+ (NGE_IMR_RX_OFLOW|NGE_IMR_TX_UFLOW|NGE_IMR_TX_OK|\
+ NGE_IMR_TX_IDLE|NGE_IMR_RX_OK|NGE_IMR_RX_ERR|\
+ NGE_IMR_SYSERR|NGE_IMR_PHY_INTR)
+
+/* Interrupt enable register */
+#define NGE_IER_INTRENB 0x00000001
+
+/* Interrupt moderation timer register */
+#define NGE_IHR_HOLDOFF 0x000000FF
+#define NGE_IHR_HOLDCTL 0x00000100
+
+/* Transmit configuration register */
+#define NGE_TXCFG_DRAIN_THRESH 0x000000FF /* 32-byte units */
+#define NGE_TXCFG_FILL_THRESH 0x0000FF00 /* 32-byte units */
+#define NGE_1000MB_BURST_DIS 0x00080000
+#define NGE_TXCFG_DMABURST 0x00700000
+#define NGE_TXCFG_ECRETRY 0x00800000
+#define NGE_TXCFG_AUTOPAD 0x10000000
+#define NGE_TXCFG_LOOPBK 0x20000000
+#define NGE_TXCFG_IGN_HBEAT 0x40000000
+#define NGE_TXCFG_IGN_CARR 0x80000000
+
+#define NGE_TXCFG_DRAIN(x) (((x) >> 5) & NGE_TXCFG_DRAIN_THRESH)
+#define NGE_TXCFG_FILL(x) ((((x) >> 5) << 8) & NGE_TXCFG_FILL_THRESH)
+
+#define NGE_TXDMA_1024BYTES 0x00000000
+#define NGE_TXDMA_8BYTES 0x00100000
+#define NGE_TXDMA_16BYTES 0x00200000
+#define NGE_TXDMA_32BYTES 0x00300000
+#define NGE_TXDMA_64BYTES 0x00400000
+#define NGE_TXDMA_128BYTES 0x00500000
+#define NGE_TXDMA_256BYTES 0x00600000
+#define NGE_TXDMA_512BYTES 0x00700000
+
+#define NGE_TXCFG_100 \
+ (NGE_TXDMA_64BYTES|NGE_TXCFG_AUTOPAD|\
+ NGE_TXCFG_FILL(64)|NGE_TXCFG_DRAIN(1536))
+
+#define NGE_TXCFG_10 \
+ (NGE_TXDMA_32BYTES|NGE_TXCFG_AUTOPAD|\
+ NGE_TXCFG_FILL(64)|NGE_TXCFG_DRAIN(1536))
+
+#define NGE_TXCFG \
+ (NGE_TXDMA_512BYTES|NGE_TXCFG_AUTOPAD|\
+ NGE_TXCFG_FILL(64)|NGE_TXCFG_DRAIN(6400))
+
+/* GPIO register */
+#define NGE_GPIO_GP1_OUT 0x00000001
+#define NGE_GPIO_GP2_OUT 0x00000002
+#define NGE_GPIO_GP3_OUT 0x00000004
+#define NGE_GPIO_GP4_OUT 0x00000008
+#define NGE_GPIO_GP5_OUT 0x00000010
+#define NGE_GPIO_GP1_OUTENB 0x00000020
+#define NGE_GPIO_GP2_OUTENB 0x00000040
+#define NGE_GPIO_GP3_OUTENB 0x00000080
+#define NGE_GPIO_GP4_OUTENB 0x00000100
+#define NGE_GPIO_GP5_OUTENB 0x00000200
+#define NGE_GPIO_GP1_IN 0x00000400
+#define NGE_GPIO_GP2_IN 0x00000800
+#define NGE_GPIO_GP3_IN 0x00001000
+#define NGE_GPIO_GP4_IN 0x00002000
+#define NGE_GPIO_GP5_IN 0x00004000
+
+/* Receive configuration register */
+#define NGE_RXCFG_DRAIN_THRESH 0x0000003E /* 8-byte units */
+#define NGE_RXCFG_DMABURST 0x00700000
+#define NGE_RXCFG_RX_RANGEERR 0x04000000 /* accept in-range err frames */
+#define NGE_RXCFG_RX_GIANTS 0x08000000 /* accept packets > 1518 bytes */
+#define NGE_RXCFG_RX_FDX 0x10000000 /* full duplex receive */
+#define NGE_RXCFG_RX_NOCRC 0x20000000 /* strip CRC */
+#define NGE_RXCFG_RX_RUNT 0x40000000 /* accept short frames */
+#define NGE_RXCFG_RX_BADPKTS 0x80000000 /* accept error frames */
+
+#define NGE_RXCFG_DRAIN(x) ((((x) >> 3) << 1) & NGE_RXCFG_DRAIN_THRESH)
+
+#define NGE_RXDMA_1024BYTES 0x00000000
+#define NGE_RXDMA_8BYTES 0x00100000
+#define NGE_RXDMA_16BYTES 0x00200000
+#define NGE_RXDMA_32YTES 0x00300000
+#define NGE_RXDMA_64BYTES 0x00400000
+#define NGE_RXDMA_128BYTES 0x00500000
+#define NGE_RXDMA_256BYTES 0x00600000
+#define NGE_RXDMA_512BYTES 0x00700000
+
+#define NGE_RXCFG \
+ (NGE_RXCFG_DRAIN(64)|NGE_RXDMA_256BYTES|\
+ NGE_RXCFG_RX_GIANTS|NGE_RXCFG_RX_NOCRC)
+
+/* Priority queue control */
+#define NGE_PRIOQCTL_TXPRIO_ENB 0x00000001
+#define NGE_PRIOQCTL_TXFAIR_ENB 0x00000002
+#define NGE_PRIOQCTL_RXPRIO 0x0000000C
+
+#define NGE_RXPRIOQ_DISABLED 0x00000000
+#define NGE_RXPRIOQ_TWOQS 0x00000004
+#define NGE_RXPRIOQ_THREEQS 0x00000008
+#define NGE_RXPRIOQ_FOURQS 0x0000000C
+
+/* Wake On LAN command/status register */
+#define NGE_WOLCSR_WAKE_ON_PHYINTR 0x00000001
+#define NGE_WOLCSR_WAKE_ON_UNICAST 0x00000002
+#define NGE_WOLCSR_WAKE_ON_MULTICAST 0x00000004
+#define NGR_WOLCSR_WAKE_ON_BROADCAST 0x00000008
+#define NGE_WOLCSR_WAKE_ON_ARP 0x00000010
+#define NGE_WOLCSR_WAKE_ON_PAT0_MATCH 0x00000020
+#define NGE_WOLCSR_WAKE_ON_PAT1_MATCH 0x00000040
+#define NGE_WOLCSR_WAKE_ON_PAT2_MATCH 0x00000080
+#define NGE_WOLCSR_WAKE_ON_PAT3_MATCH 0x00000100
+#define NGE_WOLCSR_SECUREON_ENB 0x00000200
+#define NGE_WOLCSR_SECUREON_HACK 0x00200000
+#define NGE_WOLCSR_PHYINTR 0x00400000
+#define NGE_WOLCSR_UNICAST 0x00800000
+#define NGE_WOLCSR_MULTICAST 0x01000000
+#define NGE_WOLCSR_BROADCAST 0x02000000
+#define NGE_WOLCSR_ARP_RCVD 0x04000000
+#define NGE_WOLCSR_PAT0_MATCH 0x08000000
+#define NGE_WOLCSR_PAT1_MATCH 0x10000000
+#define NGE_WOLCSR_PAT2_MATCH 0x20000000
+#define NGE_WOLCSR_PAT3_MATCH 0x40000000
+#define NGE_WOLCSR_MAGICPKT 0x80000000
+
+/* Pause control/status register */
+#define NGE_PAUSECSR_CNT 0x0000FFFF
+#define NGE_PAUSECSR_PFRAME_SENT 0x00020000
+#define NGE_PAUSECSR_RX_DATAFIFO_THR_LO 0x000C0000
+#define NGE_PAUSECSR_RX_DATAFIFO_THR_HI 0x00300000
+#define NGE_PAUSECSR_RX_STATFIFO_THR_LO 0x00C00000
+#define NGE_PAUSECSR_RX_STATFIFO_THR_HI 0x03000000
+#define NGE_PAUSECSR_PFRAME_RCVD 0x08000000
+#define NGE_PAUSECSR_PAUSE_ACTIVE 0x10000000
+#define NGE_PAUSECSR_PAUSE_ON_DA 0x20000000 /* pause on direct addr */
+#define NGE_PAUSECSR_PAUSE_ON_MCAST 0x40000000 /* pause on mcast */
+#define NGE_PAUSECSR_PAUSE_ENB 0x80000000
+
+/* Receive filter/match control message */
+#define MGE_RXFILTCTL_ADDR 0x000003FF
+#define NGE_RXFILTCTL_ULMASK 0x00080000
+#define NGE_RXFILTCTL_UCHASH 0x00100000
+#define NGE_RXFILTCTL_MCHASH 0x00200000
+#define NGE_RXFILTCTL_ARP 0x00400000
+#define NGE_RXFILTCTL_PMATCH0 0x00800000
+#define NGE_RXFILTCTL_PMATCH1 0x01000000
+#define NGE_RXFILTCTL_PMATCH2 0x02000000
+#define NGE_RXFILTCTL_PMATCH3 0x04000000
+#define NGE_RXFILTCTL_PERFECT 0x08000000
+#define NGE_RXFILTCTL_ALLPHYS 0x10000000
+#define NGE_RXFILTCTL_ALLMULTI 0x20000000
+#define NGE_RXFILTCTL_BROAD 0x40000000
+#define NGE_RXFILTCTL_ENABLE 0x80000000
+
+
+#define NGE_FILTADDR_PAR0 0x00000000
+#define NGE_FILTADDR_PAR1 0x00000002
+#define NGE_FILTADDR_PAR2 0x00000004
+#define NGE_FILTADDR_PMATCH0 0x00000006
+#define NGE_FILTADDR_PMATCH1 0x00000008
+#define NGE_FILTADDR_SOPASS0 0x0000000A
+#define NGE_FILTADDR_SOPASS1 0x0000000C
+#define NGE_FILTADDR_SOPASS2 0x0000000E
+#define NGE_FILTADDR_FMEM_LO 0x00000100
+#define NGE_FILTADDR_FMEM_HI 0x000003FE
+#define NGE_FILTADDR_MCAST_LO 0x00000100 /* start of multicast filter */
+#define NGE_FILTADDR_MCAST_HI 0x000001FE /* end of multicast filter */
+#define NGE_MCAST_FILTER_LEN 256 /* bytes */
+#define NGE_FILTADDR_PBUF0 0x00000200 /* pattern buffer 0 */
+#define NGE_FILTADDR_PBUF1 0x00000280 /* pattern buffer 1 */
+#define NGE_FILTADDR_PBUF2 0x00000300 /* pattern buffer 2 */
+#define NGE_FILTADDR_PBUF3 0x00000380 /* pattern buffer 3 */
+
+/* MIB control register */
+#define NGE_MIBCTL_WARNTEST 0x00000001
+#define NGE_MIBCTL_FREEZE_CNT 0x00000002
+#define NGE_MIBCTL_CLEAR_CNT 0x00000004
+#define NGE_MIBCTL_STROBE_CNT 0x00000008
+
+/* VLAN/IP RX control register */
+#define NGE_VIPRXCTL_TAG_DETECT_ENB 0x00000001
+#define NGE_VIPRXCTL_TAG_STRIP_ENB 0x00000002
+#define NGE_VIPRXCTL_DROP_TAGGEDPKTS 0x00000004
+#define NGE_VIPRXCTL_DROP_UNTAGGEDPKTS 0x00000008
+#define NGE_VIPRXCTL_IPCSUM_ENB 0x00000010
+#define NGE_VIPRXCTL_REJECT_BADIPCSUM 0x00000020
+#define NGE_VIPRXCTL_REJECT_BADTCPCSUM 0x00000040
+#define NGE_VIPRXCTL_REJECT_BADUDPCSUM 0x00000080
+
+/* VLAN/IP TX control register */
+#define NGE_VIPTXCTL_TAG_ALL 0x00000001
+#define NGE_VIPTXCTL_TAG_PER_PKT 0x00000002
+#define NGE_VIPTXCTL_CSUM_ALL 0x00000004
+#define NGE_VIPTXCTL_CSUM_PER_PKT 0x00000008
+
+/* VLAN data register */
+#define NGE_VLANDATA_VTYPE 0x0000FFFF
+#define NGE_VLANDATA_VTCI 0xFFFF0000
+
+/* Clockrun register */
+#define NGE_CLKRUN_PMESTS 0x00008000
+#define NGE_CLKRUN_PMEENB 0x00000100
+#define NGE_CLNRUN_CLKRUN_ENB 0x00000001
+
+
+/* TBI BMCR */
+#define NGE_TBIBMCR_RESTART_ANEG 0x00000200
+#define NGE_TBIBMCR_ENABLE_ANEG 0x00001000
+#define NGE_TBIBMCR_LOOPBACK 0x00004000
+
+/* TBI BMSR */
+#define NGE_TBIBMSR_ANEG_DONE 0x00000004
+#define NGE_TBIBMSR_LINKSTAT 0x00000020
+
+/* TBI ANAR */
+#define NGE_TBIANAR_HDX 0x00000020
+#define NGE_TBIANAR_FDX 0x00000040
+#define NGE_TBIANAR_PCAP 0x00000180
+#define NGE_TBIANAR_REMFAULT 0x00003000
+#define NGE_TBIANAR_NEXTPAGE 0x00008000
+
+/* TBI ANLPAR */
+#define NGE_TBIANLPAR_HDX 0x00000020
+#define NGE_TBIANLPAR_FDX 0x00000040
+#define NGE_TBIANLPAR_PCAP 0x00000180
+#define NGE_TBIANLPAR_REMFAULT 0x00003000
+#define NGE_TBIANLPAR_NEXTPAGE 0x00008000
+
+/* TBI ANER */
+#define NGE_TBIANER_PAGERCVD 0x00000002
+#define NGE_TBIANER_NEXTPGABLE 0x00000004
+
+/* TBI EXTSTS */
+#define NGE_TBIEXTSTS_HXD 0x00004000
+#define NGE_TBIEXTSTS_FXD 0x00008000
+
+/*
+ * DMA descriptor structures. The RX and TX descriptor formats are
+ * deliberately designed to be similar to facilitate passing them between
+ * RX and TX queues on multiple controllers, in the case where you have
+ * multiple MACs in a switching configuration. With the 83820, the pointer
+ * values can be either 64 bits or 32 bits depending on how the chip is
+ * configured. For the 83821, the fields are always 32-bits. There is
+ * also an optional extended status field for VLAN and TCP/IP checksum
+ * functions. We use the checksum feature so we enable the use of this
+ * field. Descriptors must be 64-bit aligned.
+ * After this, we include some additional structure members for
+ * use by the driver. Note that for this structure will be a different
+ * size on the alpha, but that's okay as long as it's a multiple of 4
+ * bytes in size.
+ *
+ */
+struct nge_desc_64 {
+ /* Hardware descriptor section */
+ u_int32_t nge_next_lo;
+ u_int32_t nge_next_hi;
+ u_int32_t nge_ptr_lo;
+ u_int32_t nge_ptr_hi;
+ u_int32_t nge_cmdsts;
+#define nge_rxstat nge_cmdsts
+#define nge_txstat nge_cmdsts
+#define nge_ctl nge_cmdsts
+ u_int32_t nge_extsts;
+ /* Driver software section */
+ struct mbuf *nge_mbuf;
+ struct nge_desc_64 *nge_nextdesc;
+};
+
+struct nge_desc_32 {
+ /* Hardware descriptor section */
+ u_int32_t nge_next;
+ u_int32_t nge_ptr;
+ u_int32_t nge_cmdsts;
+#define nge_rxstat nge_cmdsts
+#define nge_txstat nge_cmdsts
+#define nge_ctl nge_cmdsts
+ u_int32_t nge_extsts;
+ /* Driver software section */
+ struct mbuf *nge_mbuf;
+ struct nge_desc_32 *nge_nextdesc;
+};
+
+#define nge_desc nge_desc_32
+
+#define NGE_CMDSTS_BUFLEN 0x0000FFFF
+#define NGE_CMDSTS_PKT_OK 0x08000000
+#define NGE_CMDSTS_CRC 0x10000000
+#define NGE_CMDSTS_INTR 0x20000000
+#define NGE_CMDSTS_MORE 0x40000000
+#define NGE_CMDSTS_OWN 0x80000000
+
+#define NGE_LASTDESC(x) (!((x)->nge_ctl & NGE_CMDSTS_MORE)))
+#define NGE_OWNDESC(x) ((x)->nge_ctl & NGE_CMDSTS_OWN)
+#define NGE_INC(x, y) (x) = (x + 1) % y
+#define NGE_RXBYTES(x) ((x)->nge_ctl & NGE_CMDSTS_BUFLEN)
+
+#define NGE_RXSTAT_RANGELENERR 0x00010000
+#define NGE_RXSTAT_LOOPBK 0x00020000
+#define NGE_RXSTAT_ALIGNERR 0x00040000
+#define NGE_RXSTAT_CRCERR 0x00080000
+#define NGE_RXSTAT_SYMBOLERR 0x00100000
+#define NGE_RXSTAT_RUNT 0x00200000
+#define NGE_RXSTAT_GIANT 0x00400000
+#define NGE_RXSTAT_DSTCLASS 0x01800000
+#define NGE_RXSTAT_OVERRUN 0x02000000
+#define NGE_RXSTAT_RX_ABORT 0x04000000
+
+#define NGE_DSTCLASS_REJECT 0x00000000
+#define NGE_DSTCLASS_UNICAST 0x00800000
+#define NGE_DSTCLASS_MULTICAST 0x01000000
+#define NGE_DSTCLASS_BROADCAST 0x02000000
+
+#define NGE_TXSTAT_COLLCNT 0x000F0000
+#define NGE_TXSTAT_EXCESSCOLLS 0x00100000
+#define NGE_TXSTAT_OUTOFWINCOLL 0x00200000
+#define NGE_TXSTAT_EXCESS_DEFER 0x00400000
+#define NGE_TXSTAT_DEFERED 0x00800000
+#define NGE_TXSTAT_CARR_LOST 0x01000000
+#define NGE_TXSTAT_UNDERRUN 0x02000000
+#define NGE_TXSTAT_TX_ABORT 0x04000000
+
+#define NGE_TXEXTSTS_VLAN_TCI 0x0000FFFF
+#define NGE_TXEXTSTS_VLANPKT 0x00010000
+#define NGE_TXEXTSTS_IPCSUM 0x00020000
+#define NGE_TXEXTSTS_TCPCSUM 0x00080000
+#define NGE_TXEXTSTS_UDPCSUM 0x00200000
+
+#define NGE_RXEXTSTS_VTCI 0x0000FFFF
+#define NGE_RXEXTSTS_VLANPKT 0x00010000
+#define NGE_RXEXTSTS_IPPKT 0x00020000
+#define NGE_RXEXTSTS_IPCSUMERR 0x00040000
+#define NGE_RXEXTSTS_TCPPKT 0x00080000
+#define NGE_RXEXTSTS_TCPCSUMERR 0x00100000
+#define NGE_RXEXTSTS_UDPPKT 0x00200000
+#define NGE_RXEXTSTS_UDPCSUMERR 0x00400000
+
+#define NGE_RX_LIST_CNT 64
+#define NGE_TX_LIST_CNT 128
+
+struct nge_list_data {
+ struct nge_desc nge_rx_list[NGE_RX_LIST_CNT];
+ struct nge_desc nge_tx_list[NGE_TX_LIST_CNT];
+};
+
+
+/*
+ * NatSemi PCI vendor ID.
+ */
+#define NGE_VENDORID 0x100B
+
+/*
+ * 83820/83821 PCI device IDs
+ */
+#define NGE_DEVICEID 0x0022
+
+struct nge_type {
+ u_int16_t nge_vid;
+ u_int16_t nge_did;
+ char *nge_name;
+};
+
+struct nge_mii_frame {
+ u_int8_t mii_stdelim;
+ u_int8_t mii_opcode;
+ u_int8_t mii_phyaddr;
+ u_int8_t mii_regaddr;
+ u_int8_t mii_turnaround;
+ u_int16_t mii_data;
+};
+
+/*
+ * MII constants
+ */
+#define NGE_MII_STARTDELIM 0x01
+#define NGE_MII_READOP 0x02
+#define NGE_MII_WRITEOP 0x01
+#define NGE_MII_TURNAROUND 0x02
+
+#define NGE_JUMBO_FRAMELEN 9018
+#define NGE_JUMBO_MTU (NGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
+#define NGE_JSLOTS 384
+
+#define NGE_JRAWLEN (NGE_JUMBO_FRAMELEN + ETHER_ALIGN)
+#define NGE_JLEN (NGE_JRAWLEN + (sizeof(u_int64_t) - \
+ (NGE_JRAWLEN % sizeof(u_int64_t))))
+#define NGE_MCLBYTES (NGE_JLEN - sizeof(u_int64_t))
+#define NGE_JPAGESZ PAGE_SIZE
+#define NGE_RESID (NGE_JPAGESZ - (NGE_JLEN * NGE_JSLOTS) % NGE_JPAGESZ)
+#define NGE_JMEM ((NGE_JLEN * NGE_JSLOTS) + NGE_RESID)
+
+struct nge_jpool_entry {
+ int slot;
+ SLIST_ENTRY(nge_jpool_entry) jpool_entries;
+};
+
+struct nge_ring_data {
+ int nge_rx_prod;
+ int nge_tx_prod;
+ int nge_tx_cons;
+ int nge_tx_cnt;
+ /* Stick the jumbo mem management stuff here too. */
+ caddr_t nge_jslots[NGE_JSLOTS];
+ void *nge_jumbo_buf;
+};
+
+struct nge_softc {
+ struct arpcom arpcom; /* interface info */
+ bus_space_handle_t nge_bhandle;
+ bus_space_tag_t nge_btag;
+ struct resource *nge_res;
+ struct resource *nge_irq;
+ void *nge_intrhand;
+ device_t nge_miibus;
+ int nge_if_flags;
+ u_int8_t nge_unit;
+ u_int8_t nge_type;
+ u_int8_t nge_link;
+ u_int8_t nge_width;
+#define NGE_WIDTH_32BITS 0
+#define NGE_WIDTH_64BITS 1
+ struct nge_list_data *nge_ldata;
+ struct nge_ring_data nge_cdata;
+ struct callout_handle nge_stat_ch;
+ SLIST_HEAD(__nge_jfreehead, nge_jpool_entry) nge_jfree_listhead;
+ SLIST_HEAD(__nge_jinusehead, nge_jpool_entry) nge_jinuse_listhead;
+ struct mtx nge_mtx;
+};
+
+/*
+ * register space access macros
+ */
+#define CSR_WRITE_4(sc, reg, val) \
+ bus_space_write_4(sc->nge_btag, sc->nge_bhandle, reg, val)
+
+#define CSR_READ_4(sc, reg) \
+ bus_space_read_4(sc->nge_btag, sc->nge_bhandle, reg)
+
+#define NGE_TIMEOUT 1000
+#define ETHER_ALIGN 2
+#define NGE_RXLEN 1536
+#define NGE_MIN_FRAMELEN 60
+
+/*
+ * PCI low memory base and low I/O base register, and
+ * other PCI registers.
+ */
+
+#define NGE_PCI_VENDOR_ID 0x00
+#define NGE_PCI_DEVICE_ID 0x02
+#define NGE_PCI_COMMAND 0x04
+#define NGE_PCI_STATUS 0x06
+#define NGE_PCI_REVID 0x08
+#define NGE_PCI_CLASSCODE 0x09
+#define NGE_PCI_CACHELEN 0x0C
+#define NGE_PCI_LATENCY_TIMER 0x0D
+#define NGE_PCI_HEADER_TYPE 0x0E
+#define NGE_PCI_LOIO 0x10
+#define NGE_PCI_LOMEM 0x14
+#define NGE_PCI_BIOSROM 0x30
+#define NGE_PCI_INTLINE 0x3C
+#define NGE_PCI_INTPIN 0x3D
+#define NGE_PCI_MINGNT 0x3E
+#define NGE_PCI_MINLAT 0x0F
+#define NGE_PCI_RESETOPT 0x48
+#define NGE_PCI_EEPROM_DATA 0x4C
+
+/* power management registers */
+#define NGE_PCI_CAPID 0x50 /* 8 bits */
+#define NGE_PCI_NEXTPTR 0x51 /* 8 bits */
+#define NGE_PCI_PWRMGMTCAP 0x52 /* 16 bits */
+#define NGE_PCI_PWRMGMTCTRL 0x54 /* 16 bits */
+
+#define NGE_PSTATE_MASK 0x0003
+#define NGE_PSTATE_D0 0x0000
+#define NGE_PSTATE_D1 0x0001
+#define NGE_PSTATE_D2 0x0002
+#define NGE_PSTATE_D3 0x0003
+#define NGE_PME_EN 0x0010
+#define NGE_PME_STATUS 0x8000
+
+#ifdef __alpha__
+#undef vtophys
+#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
+#endif
diff --git a/sys/i386/conf/NOTES b/sys/i386/conf/NOTES
index bd884f2..810420a 100644
--- a/sys/i386/conf/NOTES
+++ b/sys/i386/conf/NOTES
@@ -1634,6 +1634,10 @@ device miibus
# DE101, DE200, DE201, DE202, DE203, DE204, DE205, DE422)
# lnc: Lance/PCnet cards (Isolan, Novell NE2100, NE32-VL, AMD Am7990 and
# Am79C960)
+# nge: Support for PCI gigabit ethernet adapters based on the National
+# Semiconductor DP83820 and DP83821 chipset. This includes the
+# SMC EZ Card 1000 (SMC9462TX), D-Link DGE-500T, Asante FriendlyNet
+# GigaNIX 1000TA and 1000TPC, and the Addtron AEG320T.
# oltr: Olicom ISA token-ring adapters OC-3115, OC-3117, OC-3118 and OC-3133
# (no hints needed).
# Olicom PCI token-ring adapters OC-3136, OC-3137, OC-3139, OC-3140,
@@ -1803,6 +1807,7 @@ device de # DEC/Intel DC21x4x (``Tulip'')
device vx # 3Com 3c590, 3c595 (``Vortex'')
# PCI Gigabit & FDDI NICs.
+device nge
device sk
device ti
device wx
diff --git a/sys/modules/Makefile b/sys/modules/Makefile
index 770abc9..eac6ea8 100644
--- a/sys/modules/Makefile
+++ b/sys/modules/Makefile
@@ -9,8 +9,8 @@ _random= random
SUBDIR= 3dfx accf_data accf_http agp aha amr an aue \
cam ccd cd9660 coda cue dc de dgm digi ed fdesc fxp if_disc if_ef \
if_ppp if_sl if_tap if_tun ip6fw ipfilter ipfw ispfw joy kue \
- libmchain linux lnc md mfs mii mlx msdos ncp netgraph nfs ntfs nullfs \
- nwfs pcn portal procfs ${_random} \
+ libmchain linux lnc md mfs mii mlx msdos ncp netgraph nfs nge ntfs \
+ nullfs nwfs pcn portal procfs ${_random} \
rl rp sf sis sk sn sound sppp ste sym syscons sysvipc ti tl twe tx \
udbp ugen uhid ukbd ulpt umapfs umass umodem ums union urio usb \
uscanner \
diff --git a/sys/modules/mii/Makefile b/sys/modules/mii/Makefile
index c8ab470..45e9f40 100644
--- a/sys/modules/mii/Makefile
+++ b/sys/modules/mii/Makefile
@@ -6,6 +6,6 @@ KMOD= miibus
SRCS= mii.c mii_physubr.c ukphy.c ukphy_subr.c bus_if.h pci_if.h
SRCS+= miibus_if.h device_if.h miibus_if.c e1000phy.c exphy.c nsphy.c
SRCS+= mlphy.c tlphy.c rlphy.c amphy.c dcphy.c pnphy.c inphy.c
-SRCS+= brgphy.c xmphy.c pnaphy.c lxtphy.c qsphy.c acphy.c
+SRCS+= brgphy.c xmphy.c pnaphy.c lxtphy.c qsphy.c acphy.c nsgphy.c
.include <bsd.kmod.mk>
diff --git a/sys/modules/nge/Makefile b/sys/modules/nge/Makefile
new file mode 100644
index 0000000..e5e4b8f
--- /dev/null
+++ b/sys/modules/nge/Makefile
@@ -0,0 +1,12 @@
+# $FreeBSD$
+
+.PATH: ${.CURDIR}/../../dev/nge
+
+KMOD= if_nge
+SRCS= if_nge.c opt_bdg.h vlan.h device_if.h bus_if.h pci_if.h
+CLEANFILES= vlan.h
+
+vlan.h:
+ touch vlan.h
+
+.include <bsd.kmod.mk>
diff --git a/usr.sbin/sade/devices.c b/usr.sbin/sade/devices.c
index f8397f5..484a3d6 100644
--- a/usr.sbin/sade/devices.c
+++ b/usr.sbin/sade/devices.c
@@ -100,6 +100,7 @@ static struct _devname {
{ DEVICE_TYPE_NETWORK, "kue", "Kawasaki LSI USB ethernet adapter" },
{ DEVICE_TYPE_NETWORK, "le", "DEC EtherWorks 2 or 3 ethernet card" },
{ DEVICE_TYPE_NETWORK, "lnc", "Lance/PCnet (Isolan/Novell NE2100/NE32-VL) ethernet" },
+ { DEVICE_TYPE_NETWORK, "nge", "NatSemi PCI gigabit ethernet card" },
{ DEVICE_TYPE_NETWORK, "pcn", "AMD Am79c79x PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "rl", "RealTek 8129/8139 PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "sf", "Adaptec AIC-6915 PCI ethernet card" },
diff --git a/usr.sbin/sysinstall/devices.c b/usr.sbin/sysinstall/devices.c
index f8397f5..484a3d6 100644
--- a/usr.sbin/sysinstall/devices.c
+++ b/usr.sbin/sysinstall/devices.c
@@ -100,6 +100,7 @@ static struct _devname {
{ DEVICE_TYPE_NETWORK, "kue", "Kawasaki LSI USB ethernet adapter" },
{ DEVICE_TYPE_NETWORK, "le", "DEC EtherWorks 2 or 3 ethernet card" },
{ DEVICE_TYPE_NETWORK, "lnc", "Lance/PCnet (Isolan/Novell NE2100/NE32-VL) ethernet" },
+ { DEVICE_TYPE_NETWORK, "nge", "NatSemi PCI gigabit ethernet card" },
{ DEVICE_TYPE_NETWORK, "pcn", "AMD Am79c79x PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "rl", "RealTek 8129/8139 PCI ethernet card" },
{ DEVICE_TYPE_NETWORK, "sf", "Adaptec AIC-6915 PCI ethernet card" },
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