diff options
| -rw-r--r-- | release/sysinstall/devices.c | 3 | ||||
| -rw-r--r-- | release/texts/RELNOTES.TXT | 11 | ||||
| -rw-r--r-- | release/texts/i386/RELNOTES.TXT | 11 | ||||
| -rw-r--r-- | share/man/man4/ax.4 | 152 | ||||
| -rw-r--r-- | share/man/man4/man4.i386/Makefile | 7 | ||||
| -rw-r--r-- | share/man/man4/man4.i386/ax.4 | 152 | ||||
| -rw-r--r-- | sys/amd64/conf/GENERIC | 3 | ||||
| -rw-r--r-- | sys/conf/NOTES | 7 | ||||
| -rw-r--r-- | sys/conf/files | 1 | ||||
| -rw-r--r-- | sys/i386/conf/GENERIC | 3 | ||||
| -rw-r--r-- | sys/i386/conf/LINT | 7 | ||||
| -rw-r--r-- | sys/i386/conf/NOTES | 7 | ||||
| -rw-r--r-- | sys/i386/i386/userconfig.c | 5 | ||||
| -rw-r--r-- | sys/pci/if_ax.c | 2171 | ||||
| -rw-r--r-- | sys/pci/if_axreg.h | 560 | ||||
| -rw-r--r-- | usr.sbin/sade/devices.c | 3 | ||||
| -rw-r--r-- | usr.sbin/sysinstall/devices.c | 3 |
17 files changed, 3091 insertions, 15 deletions
diff --git a/release/sysinstall/devices.c b/release/sysinstall/devices.c index d7ac76b..7b7261d 100644 --- a/release/sysinstall/devices.c +++ b/release/sysinstall/devices.c @@ -4,7 +4,7 @@ * This is probably the last program in the `sysinstall' line - the next * generation being essentially a complete rewrite. * - * $Id: devices.c,v 1.86 1998/10/19 14:58:38 jkh Exp $ + * $Id: devices.c,v 1.87 1998/12/04 18:01:10 wpaul Exp $ * * Copyright (c) 1995 * Jordan Hubbard. All rights reserved. @@ -80,6 +80,7 @@ static struct _devname { { DEVICE_TYPE_FLOPPY, "fd%d", "floppy drive unit A", 2, 0, 64, 4, 'b' }, { DEVICE_TYPE_FLOPPY, "wfd%d", "ATAPI floppy drive unit A", 1, 0, 8, 4, 'b' }, { DEVICE_TYPE_FLOPPY, "worm%d", "SCSI optical disk / CDR", 23, 0, 1, 4, 'b' }, + { DEVICE_TYPE_NETWORK, "ax", "ASIX AX88140A PCI ethernet card" }, { DEVICE_TYPE_NETWORK, "fpa", "DEC DEFPA PCI FDDI card" }, { DEVICE_TYPE_NETWORK, "sr", "SDL T1/E1 sync serial PCI card" }, { DEVICE_TYPE_NETWORK, "cc3i", "SDL HSSI sync serial PCI card" }, diff --git a/release/texts/RELNOTES.TXT b/release/texts/RELNOTES.TXT index e56ec93..43dc3b7 100644 --- a/release/texts/RELNOTES.TXT +++ b/release/texts/RELNOTES.TXT @@ -57,7 +57,7 @@ SMC EZ Card 10/100 PCI 1211-TX. Added driver support for Lite-On PNIC-based fast ethernet cards including the LinkSys LNE100TX, NetGear FA310TX Rev. D1 and -Matrox FastNIC 10.100. +Matrox FastNIC 10/100. Added driver support for fast ethernet adapters based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips. @@ -71,6 +71,9 @@ VIA Technologies VT3043 "Rhine I" and VT86C100A "Rhine II" chips. Added driver support for pocket ethernet adapters based on the RealTek RTL 8002 chip. +Added driver support for fast ethernet adapters based on the +ASIX Electronics AX88140A chip. + 1.2. SECURITY FIXES ------------------- @@ -226,6 +229,7 @@ Macronix 98713, 98713A, 98715, 98715A and 98725 fast ethernet NICs NDC Communications SFA100A (98713A) CNet Pro120A (98713 or 98713A) CNet Pro120B (98715) + SVEC PN102TX (98713) Winbond W89C840F fast ethernet NICs including the following: Trendware TE100-PCIE @@ -241,6 +245,9 @@ Texas Instruments ThunderLAN PCI NICs, including the following: Compaq NetFlex 3P, 3P Integrated, 3P w/ BNC Olicom OC-2135/2138, OC-2325, OC-2326 10/100 TX UTP +ASIX Electronics AX88140A PCI NICs, including the following: + Alfa Inc. GFC2204 + DEC EtherWORKS III NICs (DE203, DE204, and DE205) DEC EtherWORKS II NICs (DE200, DE201, DE202, and DE422) DEC DC21040, DC21041, or DC21140 based NICs (SMC Etherpower 8432T, DE245, etc) @@ -270,6 +277,8 @@ Novell NE1000, NE2000, and NE2100 ethernet interface. 3Com 3C509, 3C579, 3C589 (PCMCIA), 3C590/592/595/900/905/905B PCI and EISA (Fast) Etherlink III / (Fast) Etherlink XL +3Com 3c980 Fast Etherlink XL server adapter + Toshiba ethernet cards Crystal Semiconductor CS89x0-based NICs, including: diff --git a/release/texts/i386/RELNOTES.TXT b/release/texts/i386/RELNOTES.TXT index e56ec93..43dc3b7 100644 --- a/release/texts/i386/RELNOTES.TXT +++ b/release/texts/i386/RELNOTES.TXT @@ -57,7 +57,7 @@ SMC EZ Card 10/100 PCI 1211-TX. Added driver support for Lite-On PNIC-based fast ethernet cards including the LinkSys LNE100TX, NetGear FA310TX Rev. D1 and -Matrox FastNIC 10.100. +Matrox FastNIC 10/100. Added driver support for fast ethernet adapters based on the Macronix 98713, 98713A, 98715, 98715A and 98725 chips. @@ -71,6 +71,9 @@ VIA Technologies VT3043 "Rhine I" and VT86C100A "Rhine II" chips. Added driver support for pocket ethernet adapters based on the RealTek RTL 8002 chip. +Added driver support for fast ethernet adapters based on the +ASIX Electronics AX88140A chip. + 1.2. SECURITY FIXES ------------------- @@ -226,6 +229,7 @@ Macronix 98713, 98713A, 98715, 98715A and 98725 fast ethernet NICs NDC Communications SFA100A (98713A) CNet Pro120A (98713 or 98713A) CNet Pro120B (98715) + SVEC PN102TX (98713) Winbond W89C840F fast ethernet NICs including the following: Trendware TE100-PCIE @@ -241,6 +245,9 @@ Texas Instruments ThunderLAN PCI NICs, including the following: Compaq NetFlex 3P, 3P Integrated, 3P w/ BNC Olicom OC-2135/2138, OC-2325, OC-2326 10/100 TX UTP +ASIX Electronics AX88140A PCI NICs, including the following: + Alfa Inc. GFC2204 + DEC EtherWORKS III NICs (DE203, DE204, and DE205) DEC EtherWORKS II NICs (DE200, DE201, DE202, and DE422) DEC DC21040, DC21041, or DC21140 based NICs (SMC Etherpower 8432T, DE245, etc) @@ -270,6 +277,8 @@ Novell NE1000, NE2000, and NE2100 ethernet interface. 3Com 3C509, 3C579, 3C589 (PCMCIA), 3C590/592/595/900/905/905B PCI and EISA (Fast) Etherlink III / (Fast) Etherlink XL +3Com 3c980 Fast Etherlink XL server adapter + Toshiba ethernet cards Crystal Semiconductor CS89x0-based NICs, including: diff --git a/share/man/man4/ax.4 b/share/man/man4/ax.4 new file mode 100644 index 0000000..05d4100 --- /dev/null +++ b/share/man/man4/ax.4 @@ -0,0 +1,152 @@ +.\" Copyright (c) 1997, 1998, 1999 +.\" Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. +.\" +.\" Redistribution and use in source and binary forms, with or without +.\" modification, are permitted provided that the following conditions +.\" are met: +.\" 1. Redistributions of source code must retain the above copyright +.\" notice, this list of conditions and the following disclaimer. +.\" 2. Redistributions in binary form must reproduce the above copyright +.\" notice, this list of conditions and the following disclaimer in the +.\" documentation and/or other materials provided with the distribution. +.\" 3. All advertising materials mentioning features or use of this software +.\" must display the following acknowledgement: +.\" This product includes software developed by Bill Paul. +.\" 4. Neither the name of the author nor the names of any co-contributors +.\" may be used to endorse or promote products derived from this software +.\" without specific prior written permission. +.\" +.\" THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND +.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +.\" ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD +.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +.\" THE POSSIBILITY OF SUCH DAMAGE. +.\" +.\" $Id: ax.4,v 1.2 1999/01/09 17:19:41 wpaul Exp $ +.\" +.Dd January 2, 1999 +.Dt AX 4 i386 +.Os FreeBSD +.Sh NAME +.Nm ax +.Nd +ASIX Electronics AX88140A fast ethernet device driver +.Sh SYNOPSIS +.Cd "device ax0" +.Sh DESCRIPTION +The +.Nm +driver provides support for PCI ethernet adapters and embedded +controllers based on the ASIX AX88140A fast ethernet controller chip, +including the Alfa Inc. GFC2204. +.Pp +The ASIX chip uses bus master DMA and is designed to be a +DEC 21x4x workalike. The only major difference between the DEC +and ASIX parts is that the ASIX receiver filter is programmed +using two special registers where as the DEC chip is programmed +by uploading a special setup frame via the transmit DMA engine. +The ASIX receive filter can only be programmed with a single +perfect filter entry for the local station address and a 64-bit +multicast hash table; the DEC filter has supports several other +options. The ASIX fast ethernet controller supports both +10 and 100Mbps speeds in either full or half duplex using +an external MII transceiver. +.Pp +The +.Nm +driver supports the following media types: +.Pp +.Bl -tag -width xxxxxxxxxxxxxxxxxxxx +.It autoselect +Enable autoselection of the media type and options. +The user can manually override +the autoselected mode by adding media options to the +.Pa /etc/rc.conf +fine. +.It 10baseT/UTP +Set 10Mbps operation. The +.Ar mediaopt +option can also be used to select either +.Ar full-duplex +or +.Ar half-duplex modes. +.It 100baseTX +Set 100Mbps (fast ethernet) operation. The +.Ar mediaopt +option can also be used to select either +.Ar full-duplex +or +.Ar half-duplex +modes. +.El +.Pp +The +.Nm +driver supports the following media options: +.Pp +.Bl -tag -width xxxxxxxxxxxxxxxxxxxx +.It full-duplex +Force full duplex operation +.It half-duplex +Force half duplex operation. +.El +.Pp +For more information on configuring this device, see +.Xr ifconfig 8 . +.Sh DIAGNOSTICS +.Bl -diag +.It "ax%d: couldn't map memory" +A fatal initialization error has occurred. +.It "ax%d: couldn't map interrupt" +A fatal initialization error has occurred. +.It "ax%d: watchdog timeout" +The device has stopped responding to the network, or there is a problem with +the network connection (cable). +.It "ax%d: no memory for rx list" +The driver failed to allocate an mbuf for the receiver ring. +.It "ax%d: no memory for tx list" +The driver failed to allocate an mbuf for the transmitter ring when +allocating a pad buffer or collapsing an mbuf chain into a cluster. +.It "ax%d: chip is in D3 power state -- setting to D0" +This message applies only to adapters which support power +management. Some operating systems place the controller in low power +mode when shutting down, and some PCI BIOSes fail to bring the chip +out of this state before configuring it. The controller loses all of +its PCI configuration in the D3 state, so if the BIOS does not set +it back to full power mode in time, it won't be able to configure it +correctly. The driver tries to detect this condition and bring +the adapter back to the D0 (full power) state, but this may not be +enough to return the driver to a fully operational condition. If +you see this message at boot time and the driver fails to attach +the device as a network interface, you will have to perform second +warm boot to have the device properly configured. +.Pp +Note that this condition only occurs when warm booting from another +operating system. If you power down your system prior to booting +.Fx , +the card should be configured correctly. +.El +.Sh SEE ALSO +.Xr arp 4 , +.Xr netintro 4 , +.Xr ifconfig 8 +.Rs +.%T ASIX AX81140A data sheet +.%O http://www.asix.com.tw +.Re +.Sh HISTORY +The +.Nm +device driver first appeared in +.Fx 3.0 . +.Sh AUTHOR +The +.Nm +driver was written by +.An Bill Paul Aq wpaul@ctr.columbia.edu . diff --git a/share/man/man4/man4.i386/Makefile b/share/man/man4/man4.i386/Makefile index 79bf029..81da7ae 100644 --- a/share/man/man4/man4.i386/Makefile +++ b/share/man/man4/man4.i386/Makefile @@ -1,7 +1,7 @@ -# $Id: Makefile,v 1.92 1998/12/27 13:06:36 phk Exp $ +# $Id: Makefile,v 1.93 1999/01/01 08:48:30 peter Exp $ -MAN4= adv.4 adw.4 aha.4 ahb.4 ahc.4 aic.4 alog.4 apm.4 ar.4 asc.4 bktr.4 \ - bt.4 cs.4 cx.4 cy.4 de.4 \ +MAN4= adv.4 adw.4 aha.4 ahb.4 ahc.4 aic.4 alog.4 apm.4 ar.4 asc.4 ax.4 \ + bktr.4 bt.4 cs.4 cx.4 cy.4 de.4 \ dgb.4 dpt.4 ed.4 el.4 en.4 ep.4 ex.4 fdc.4 fe.4 fxp.4 gsc.4 ie.4 \ io.4 joy.4 keyboard.4 labpc.4 le.4 lnc.4 lp.4 lpt.4 matcd.4 mcd.4 \ mem.4 meteor.4 mouse.4 mse.4 mtio.4 mx.4 ncr.4 npx.4 \ @@ -20,6 +20,7 @@ MLINKS+= alog.4 ../alog.4 MLINKS+= apm.4 ../apm.4 MLINKS+= ar.4 ../ar.4 MLINKS+= asc.4 ../asc.4 +MLINKS+= ax.4 ../ax.4 MLINKS+= bktr.4 ../bktr.4 MLINKS+= bt.4 ../bt.4 MLINKS+= cs.4 ../cs.4 diff --git a/share/man/man4/man4.i386/ax.4 b/share/man/man4/man4.i386/ax.4 new file mode 100644 index 0000000..05d4100 --- /dev/null +++ b/share/man/man4/man4.i386/ax.4 @@ -0,0 +1,152 @@ +.\" Copyright (c) 1997, 1998, 1999 +.\" Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. +.\" +.\" Redistribution and use in source and binary forms, with or without +.\" modification, are permitted provided that the following conditions +.\" are met: +.\" 1. Redistributions of source code must retain the above copyright +.\" notice, this list of conditions and the following disclaimer. +.\" 2. Redistributions in binary form must reproduce the above copyright +.\" notice, this list of conditions and the following disclaimer in the +.\" documentation and/or other materials provided with the distribution. +.\" 3. All advertising materials mentioning features or use of this software +.\" must display the following acknowledgement: +.\" This product includes software developed by Bill Paul. +.\" 4. Neither the name of the author nor the names of any co-contributors +.\" may be used to endorse or promote products derived from this software +.\" without specific prior written permission. +.\" +.\" THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND +.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +.\" ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD +.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +.\" THE POSSIBILITY OF SUCH DAMAGE. +.\" +.\" $Id: ax.4,v 1.2 1999/01/09 17:19:41 wpaul Exp $ +.\" +.Dd January 2, 1999 +.Dt AX 4 i386 +.Os FreeBSD +.Sh NAME +.Nm ax +.Nd +ASIX Electronics AX88140A fast ethernet device driver +.Sh SYNOPSIS +.Cd "device ax0" +.Sh DESCRIPTION +The +.Nm +driver provides support for PCI ethernet adapters and embedded +controllers based on the ASIX AX88140A fast ethernet controller chip, +including the Alfa Inc. GFC2204. +.Pp +The ASIX chip uses bus master DMA and is designed to be a +DEC 21x4x workalike. The only major difference between the DEC +and ASIX parts is that the ASIX receiver filter is programmed +using two special registers where as the DEC chip is programmed +by uploading a special setup frame via the transmit DMA engine. +The ASIX receive filter can only be programmed with a single +perfect filter entry for the local station address and a 64-bit +multicast hash table; the DEC filter has supports several other +options. The ASIX fast ethernet controller supports both +10 and 100Mbps speeds in either full or half duplex using +an external MII transceiver. +.Pp +The +.Nm +driver supports the following media types: +.Pp +.Bl -tag -width xxxxxxxxxxxxxxxxxxxx +.It autoselect +Enable autoselection of the media type and options. +The user can manually override +the autoselected mode by adding media options to the +.Pa /etc/rc.conf +fine. +.It 10baseT/UTP +Set 10Mbps operation. The +.Ar mediaopt +option can also be used to select either +.Ar full-duplex +or +.Ar half-duplex modes. +.It 100baseTX +Set 100Mbps (fast ethernet) operation. The +.Ar mediaopt +option can also be used to select either +.Ar full-duplex +or +.Ar half-duplex +modes. +.El +.Pp +The +.Nm +driver supports the following media options: +.Pp +.Bl -tag -width xxxxxxxxxxxxxxxxxxxx +.It full-duplex +Force full duplex operation +.It half-duplex +Force half duplex operation. +.El +.Pp +For more information on configuring this device, see +.Xr ifconfig 8 . +.Sh DIAGNOSTICS +.Bl -diag +.It "ax%d: couldn't map memory" +A fatal initialization error has occurred. +.It "ax%d: couldn't map interrupt" +A fatal initialization error has occurred. +.It "ax%d: watchdog timeout" +The device has stopped responding to the network, or there is a problem with +the network connection (cable). +.It "ax%d: no memory for rx list" +The driver failed to allocate an mbuf for the receiver ring. +.It "ax%d: no memory for tx list" +The driver failed to allocate an mbuf for the transmitter ring when +allocating a pad buffer or collapsing an mbuf chain into a cluster. +.It "ax%d: chip is in D3 power state -- setting to D0" +This message applies only to adapters which support power +management. Some operating systems place the controller in low power +mode when shutting down, and some PCI BIOSes fail to bring the chip +out of this state before configuring it. The controller loses all of +its PCI configuration in the D3 state, so if the BIOS does not set +it back to full power mode in time, it won't be able to configure it +correctly. The driver tries to detect this condition and bring +the adapter back to the D0 (full power) state, but this may not be +enough to return the driver to a fully operational condition. If +you see this message at boot time and the driver fails to attach +the device as a network interface, you will have to perform second +warm boot to have the device properly configured. +.Pp +Note that this condition only occurs when warm booting from another +operating system. If you power down your system prior to booting +.Fx , +the card should be configured correctly. +.El +.Sh SEE ALSO +.Xr arp 4 , +.Xr netintro 4 , +.Xr ifconfig 8 +.Rs +.%T ASIX AX81140A data sheet +.%O http://www.asix.com.tw +.Re +.Sh HISTORY +The +.Nm +device driver first appeared in +.Fx 3.0 . +.Sh AUTHOR +The +.Nm +driver was written by +.An Bill Paul Aq wpaul@ctr.columbia.edu . diff --git a/sys/amd64/conf/GENERIC b/sys/amd64/conf/GENERIC index ef57d0a..88943bb 100644 --- a/sys/amd64/conf/GENERIC +++ b/sys/amd64/conf/GENERIC @@ -11,7 +11,7 @@ # device lines is present in the ./LINT configuration file. If you are # in doubt as to the purpose or necessity of a line, check first in LINT. # -# $Id: GENERIC,v 1.140 1998/12/27 13:55:47 sos Exp $ +# $Id: GENERIC,v 1.141 1999/01/01 08:09:57 peter Exp $ machine "i386" cpu "I386_CPU" @@ -142,6 +142,7 @@ device psm0 at isa? port IO_KBD conflicts tty irq 12 # this list of network interfaces until the probes have been fixed. # Right now it appears that the ie0 must be probed before ep0. See # revision 1.20 of this file. +device ax0 device de0 device fxp0 device mx0 diff --git a/sys/conf/NOTES b/sys/conf/NOTES index 27f1cea..fbeb207 100644 --- a/sys/conf/NOTES +++ b/sys/conf/NOTES @@ -2,7 +2,7 @@ # LINT -- config file for checking all the sources, tries to pull in # as much of the source tree as it can. # -# $Id: LINT,v 1.527 1999/01/08 16:04:18 eivind Exp $ +# $Id: LINT,v 1.528 1999/01/08 17:31:07 eivind Exp $ # # NB: You probably don't want to try running a kernel built from this # file. Instead, you should start from GENERIC, and add options from @@ -1448,6 +1448,10 @@ options "EISA_SLOTS=12" # nd 1040B PCI SCSI host adapters, as well as the Qlogic ISP 2100 # FC/AL Host Adapter. # +# The `ax' device provides support for PCI fast ethernet adapters +# based on the ASIX Electronics AX88140A chip, including the Alfa +# Inc. GFC2204. +# # The `de' device provides support for the Digital Equipment DC21040 # self-contained Ethernet adapter. # @@ -1535,6 +1539,7 @@ controller pci0 controller ahc1 controller ncr0 controller isp0 +device ax0 device de0 device fxp0 device mx0 diff --git a/sys/conf/files b/sys/conf/files index 3bfcb39..9ecf05b 100644 --- a/sys/conf/files +++ b/sys/conf/files @@ -578,6 +578,7 @@ pci/bt848_i2c.c optional bktr device-driver pci/bt_pci.c optional bt device-driver pci/dpt_pci.c optional pci dpt device-driver pci/cy_pci.c optional cy device-driver +pci/if_ax.c optional ax device-driver pci/if_de.c optional de device-driver pci/if_ed_p.c optional ed device-driver pci/if_en_pci.c optional en device-driver diff --git a/sys/i386/conf/GENERIC b/sys/i386/conf/GENERIC index ef57d0a..88943bb 100644 --- a/sys/i386/conf/GENERIC +++ b/sys/i386/conf/GENERIC @@ -11,7 +11,7 @@ # device lines is present in the ./LINT configuration file. If you are # in doubt as to the purpose or necessity of a line, check first in LINT. # -# $Id: GENERIC,v 1.140 1998/12/27 13:55:47 sos Exp $ +# $Id: GENERIC,v 1.141 1999/01/01 08:09:57 peter Exp $ machine "i386" cpu "I386_CPU" @@ -142,6 +142,7 @@ device psm0 at isa? port IO_KBD conflicts tty irq 12 # this list of network interfaces until the probes have been fixed. # Right now it appears that the ie0 must be probed before ep0. See # revision 1.20 of this file. +device ax0 device de0 device fxp0 device mx0 diff --git a/sys/i386/conf/LINT b/sys/i386/conf/LINT index 27f1cea..fbeb207 100644 --- a/sys/i386/conf/LINT +++ b/sys/i386/conf/LINT @@ -2,7 +2,7 @@ # LINT -- config file for checking all the sources, tries to pull in # as much of the source tree as it can. # -# $Id: LINT,v 1.527 1999/01/08 16:04:18 eivind Exp $ +# $Id: LINT,v 1.528 1999/01/08 17:31:07 eivind Exp $ # # NB: You probably don't want to try running a kernel built from this # file. Instead, you should start from GENERIC, and add options from @@ -1448,6 +1448,10 @@ options "EISA_SLOTS=12" # nd 1040B PCI SCSI host adapters, as well as the Qlogic ISP 2100 # FC/AL Host Adapter. # +# The `ax' device provides support for PCI fast ethernet adapters +# based on the ASIX Electronics AX88140A chip, including the Alfa +# Inc. GFC2204. +# # The `de' device provides support for the Digital Equipment DC21040 # self-contained Ethernet adapter. # @@ -1535,6 +1539,7 @@ controller pci0 controller ahc1 controller ncr0 controller isp0 +device ax0 device de0 device fxp0 device mx0 diff --git a/sys/i386/conf/NOTES b/sys/i386/conf/NOTES index 27f1cea..fbeb207 100644 --- a/sys/i386/conf/NOTES +++ b/sys/i386/conf/NOTES @@ -2,7 +2,7 @@ # LINT -- config file for checking all the sources, tries to pull in # as much of the source tree as it can. # -# $Id: LINT,v 1.527 1999/01/08 16:04:18 eivind Exp $ +# $Id: LINT,v 1.528 1999/01/08 17:31:07 eivind Exp $ # # NB: You probably don't want to try running a kernel built from this # file. Instead, you should start from GENERIC, and add options from @@ -1448,6 +1448,10 @@ options "EISA_SLOTS=12" # nd 1040B PCI SCSI host adapters, as well as the Qlogic ISP 2100 # FC/AL Host Adapter. # +# The `ax' device provides support for PCI fast ethernet adapters +# based on the ASIX Electronics AX88140A chip, including the Alfa +# Inc. GFC2204. +# # The `de' device provides support for the Digital Equipment DC21040 # self-contained Ethernet adapter. # @@ -1535,6 +1539,7 @@ controller pci0 controller ahc1 controller ncr0 controller isp0 +device ax0 device de0 device fxp0 device mx0 diff --git a/sys/i386/i386/userconfig.c b/sys/i386/i386/userconfig.c index a822f86..884b1cb 100644 --- a/sys/i386/i386/userconfig.c +++ b/sys/i386/i386/userconfig.c @@ -46,7 +46,7 @@ ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** - ** $Id: userconfig.c,v 1.120 1999/01/07 09:49:28 abial Exp $ + ** $Id: userconfig.c,v 1.121 1999/01/08 21:00:26 abial Exp $ **/ /** @@ -392,6 +392,7 @@ static DEV_INFO device_info[] = { {"vx", "3COM 3C590/3C595 Ethernet adapters", 0, CLS_NETWORK}, {"ze", "IBM/National Semiconductor PCMCIA Ethernet adapter",0, CLS_NETWORK}, {"zp", "3COM PCMCIA Etherlink III Ethernet adapter", 0, CLS_NETWORK}, +{"ax", "ASIC AX88140A ethernet adapter", FLG_FIXED, CLS_NETWORK}, {"de", "DEC DC21040 Ethernet adapter", FLG_FIXED, CLS_NETWORK}, {"fpa", "DEC DEFPA PCI FDDI adapter", FLG_FIXED, CLS_NETWORK}, {"rl", "RealTek 8129/8139 ethernet adapter", FLG_FIXED, CLS_NETWORK}, @@ -2515,7 +2516,7 @@ visuserconfig(void) * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $Id: userconfig.c,v 1.120 1999/01/07 09:49:28 abial Exp $ + * $Id: userconfig.c,v 1.121 1999/01/08 21:00:26 abial Exp $ */ #include "scbus.h" diff --git a/sys/pci/if_ax.c b/sys/pci/if_ax.c new file mode 100644 index 0000000..42463bb --- /dev/null +++ b/sys/pci/if_ax.c @@ -0,0 +1,2171 @@ +/* + * Copyright (c) 1997, 1998, 1999 + * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * $Id: if_ax.c,v 1.6 1999/01/08 19:40:59 wpaul Exp $ + */ + +/* + * ASIX AX88140A fast ethernet PCI NIC driver. + * + * Written by Bill Paul <wpaul@ctr.columbia.edu> + * Electrical Engineering Department + * Columbia University, New York City + */ + +/* + * The ASIX Electronics AX88140A is still another DEC 21x4x clone. It's + * a reasonably close copy of the tulip, except for the receiver filter + * programming. Where the DEC chip has a special setup frame that + * needs to be downloaded into the transmit DMA engine, the ASIX chip + * has a less complicated setup frame which is written into one of + * the registers. + */ + +#include "bpfilter.h" + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/sockio.h> +#include <sys/mbuf.h> +#include <sys/malloc.h> +#include <sys/kernel.h> +#include <sys/socket.h> + +#include <net/if.h> +#include <net/if_arp.h> +#include <net/ethernet.h> +#include <net/if_dl.h> +#include <net/if_media.h> + +#if NBPFILTER > 0 +#include <net/bpf.h> +#endif + +#include <vm/vm.h> /* for vtophys */ +#include <vm/pmap.h> /* for vtophys */ +#include <machine/clock.h> /* for DELAY */ +#include <machine/bus_pio.h> +#include <machine/bus_memio.h> +#include <machine/bus.h> + +#include <pci/pcireg.h> +#include <pci/pcivar.h> + +#define AX_USEIOSPACE + +/* #define AX_BACKGROUND_AUTONEG */ + +#include <pci/if_axreg.h> + +#ifndef lint +static const char rcsid[] = + "$Id: if_ax.c,v 1.6 1999/01/08 19:40:59 wpaul Exp $"; +#endif + +/* + * Various supported device vendors/types and their names. + */ +static struct ax_type ax_devs[] = { + { AX_VENDORID, AX_DEVICEID_AX88140A, + "ASIX AX88140A 10/100BaseTX" }, + { 0, 0, NULL } +}; + +/* + * Various supported PHY vendors/types and their names. Note that + * this driver will work with pretty much any MII-compliant PHY, + * so failure to positively identify the chip is not a fatal error. + */ + +static struct ax_type ax_phys[] = { + { TI_PHY_VENDORID, TI_PHY_10BT, "<TI ThunderLAN 10BT (internal)>" }, + { TI_PHY_VENDORID, TI_PHY_100VGPMI, "<TI TNETE211 100VG Any-LAN>" }, + { NS_PHY_VENDORID, NS_PHY_83840A, "<National Semiconductor DP83840A>"}, + { LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "<Level 1 LXT970>" }, + { INTEL_PHY_VENDORID, INTEL_PHY_82555, "<Intel 82555>" }, + { SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "<SEEQ 80220>" }, + { 0, 0, "<MII-compliant physical interface>" } +}; + +static unsigned long ax_count = 0; +static const char *ax_probe __P((pcici_t, pcidi_t)); +static void ax_attach __P((pcici_t, int)); + +static int ax_newbuf __P((struct ax_softc *, + struct ax_chain_onefrag *)); +static int ax_encap __P((struct ax_softc *, struct ax_chain *, + struct mbuf *)); + +static void ax_rxeof __P((struct ax_softc *)); +static void ax_rxeoc __P((struct ax_softc *)); +static void ax_txeof __P((struct ax_softc *)); +static void ax_txeoc __P((struct ax_softc *)); +static void ax_intr __P((void *)); +static void ax_start __P((struct ifnet *)); +static int ax_ioctl __P((struct ifnet *, u_long, caddr_t)); +static void ax_init __P((void *)); +static void ax_stop __P((struct ax_softc *)); +static void ax_watchdog __P((struct ifnet *)); +static void ax_shutdown __P((int, void *)); +static int ax_ifmedia_upd __P((struct ifnet *)); +static void ax_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); + +static void ax_delay __P((struct ax_softc *)); +static void ax_eeprom_idle __P((struct ax_softc *)); +static void ax_eeprom_putbyte __P((struct ax_softc *, int)); +static void ax_eeprom_getword __P((struct ax_softc *, int, u_int16_t *)); +static void ax_read_eeprom __P((struct ax_softc *, caddr_t, int, + int, int)); + +static void ax_mii_writebit __P((struct ax_softc *, int)); +static int ax_mii_readbit __P((struct ax_softc *)); +static void ax_mii_sync __P((struct ax_softc *)); +static void ax_mii_send __P((struct ax_softc *, u_int32_t, int)); +static int ax_mii_readreg __P((struct ax_softc *, struct ax_mii_frame *)); +static int ax_mii_writereg __P((struct ax_softc *, struct ax_mii_frame *)); +static u_int16_t ax_phy_readreg __P((struct ax_softc *, int)); +static void ax_phy_writereg __P((struct ax_softc *, int, int)); + +static void ax_autoneg_xmit __P((struct ax_softc *)); +static void ax_autoneg_mii __P((struct ax_softc *, int, int)); +static void ax_setmode_mii __P((struct ax_softc *, int)); +static void ax_setmode __P((struct ax_softc *, int, int)); +static void ax_getmode_mii __P((struct ax_softc *)); +static void ax_setcfg __P((struct ax_softc *, int)); +static u_int32_t ax_calchash __P((caddr_t)); +static void ax_setmulti __P((struct ax_softc *)); +static void ax_reset __P((struct ax_softc *)); +static int ax_list_rx_init __P((struct ax_softc *)); +static int ax_list_tx_init __P((struct ax_softc *)); + +#define AX_SETBIT(sc, reg, x) \ + CSR_WRITE_4(sc, reg, \ + CSR_READ_4(sc, reg) | x) + +#define AX_CLRBIT(sc, reg, x) \ + CSR_WRITE_4(sc, reg, \ + CSR_READ_4(sc, reg) & ~x) + +#define SIO_SET(x) \ + CSR_WRITE_4(sc, AX_SIO, \ + CSR_READ_4(sc, AX_SIO) | x) + +#define SIO_CLR(x) \ + CSR_WRITE_4(sc, AX_SIO, \ + CSR_READ_4(sc, AX_SIO) & ~x) + +static void ax_delay(sc) + struct ax_softc *sc; +{ + int idx; + + for (idx = (300 / 33) + 1; idx > 0; idx--) + CSR_READ_4(sc, AX_BUSCTL); +} + +static void ax_eeprom_idle(sc) + struct ax_softc *sc; +{ + register int i; + + CSR_WRITE_4(sc, AX_SIO, AX_SIO_EESEL); + ax_delay(sc); + AX_SETBIT(sc, AX_SIO, AX_SIO_ROMCTL_READ); + ax_delay(sc); + AX_SETBIT(sc, AX_SIO, AX_SIO_EE_CS); + ax_delay(sc); + AX_SETBIT(sc, AX_SIO, AX_SIO_EE_CLK); + ax_delay(sc); + + for (i = 0; i < 25; i++) { + AX_CLRBIT(sc, AX_SIO, AX_SIO_EE_CLK); + ax_delay(sc); + AX_SETBIT(sc, AX_SIO, AX_SIO_EE_CLK); + ax_delay(sc); + } + + AX_CLRBIT(sc, AX_SIO, AX_SIO_EE_CLK); + ax_delay(sc); + AX_CLRBIT(sc, AX_SIO, AX_SIO_EE_CS); + ax_delay(sc); + CSR_WRITE_4(sc, AX_SIO, 0x00000000); + + return; +} + +/* + * Send a read command and address to the EEPROM, check for ACK. + */ +static void ax_eeprom_putbyte(sc, addr) + struct ax_softc *sc; + int addr; +{ + register int d, i; + + d = addr | AX_EECMD_READ; + + /* + * Feed in each bit and stobe the clock. + */ + for (i = 0x400; i; i >>= 1) { + if (d & i) { + SIO_SET(AX_SIO_EE_DATAIN); + } else { + SIO_CLR(AX_SIO_EE_DATAIN); + } + ax_delay(sc); + SIO_SET(AX_SIO_EE_CLK); + ax_delay(sc); + SIO_CLR(AX_SIO_EE_CLK); + ax_delay(sc); + } + + return; +} + +/* + * Read a word of data stored in the EEPROM at address 'addr.' + */ +static void ax_eeprom_getword(sc, addr, dest) + struct ax_softc *sc; + int addr; + u_int16_t *dest; +{ + register int i; + u_int16_t word = 0; + + /* Force EEPROM to idle state. */ + ax_eeprom_idle(sc); + + /* Enter EEPROM access mode. */ + CSR_WRITE_4(sc, AX_SIO, AX_SIO_EESEL); + ax_delay(sc); + AX_SETBIT(sc, AX_SIO, AX_SIO_ROMCTL_READ); + ax_delay(sc); + AX_SETBIT(sc, AX_SIO, AX_SIO_EE_CS); + ax_delay(sc); + AX_SETBIT(sc, AX_SIO, AX_SIO_EE_CLK); + ax_delay(sc); + + /* + * Send address of word we want to read. + */ + ax_eeprom_putbyte(sc, addr); + + /* + * Start reading bits from EEPROM. + */ + for (i = 0x8000; i; i >>= 1) { + SIO_SET(AX_SIO_EE_CLK); + ax_delay(sc); + if (CSR_READ_4(sc, AX_SIO) & AX_SIO_EE_DATAOUT) + word |= i; + ax_delay(sc); + SIO_CLR(AX_SIO_EE_CLK); + ax_delay(sc); + } + + /* Turn off EEPROM access mode. */ + ax_eeprom_idle(sc); + + *dest = word; + + return; +} + +/* + * Read a sequence of words from the EEPROM. + */ +static void ax_read_eeprom(sc, dest, off, cnt, swap) + struct ax_softc *sc; + caddr_t dest; + int off; + int cnt; + int swap; +{ + int i; + u_int16_t word = 0, *ptr; + + for (i = 0; i < cnt; i++) { + ax_eeprom_getword(sc, off + i, &word); + ptr = (u_int16_t *)(dest + (i * 2)); + if (swap) + *ptr = ntohs(word); + else + *ptr = word; + } + + return; +} + +/* + * Write a bit to the MII bus. + */ +static void ax_mii_writebit(sc, bit) + struct ax_softc *sc; + int bit; +{ + if (bit) + CSR_WRITE_4(sc, AX_SIO, AX_SIO_ROMCTL_WRITE|AX_SIO_MII_DATAOUT); + else + CSR_WRITE_4(sc, AX_SIO, AX_SIO_ROMCTL_WRITE); + + AX_SETBIT(sc, AX_SIO, AX_SIO_MII_CLK); + AX_CLRBIT(sc, AX_SIO, AX_SIO_MII_CLK); + + return; +} + +/* + * Read a bit from the MII bus. + */ +static int ax_mii_readbit(sc) + struct ax_softc *sc; +{ + CSR_WRITE_4(sc, AX_SIO, AX_SIO_ROMCTL_READ|AX_SIO_MII_DIR); + CSR_READ_4(sc, AX_SIO); + AX_SETBIT(sc, AX_SIO, AX_SIO_MII_CLK); + AX_CLRBIT(sc, AX_SIO, AX_SIO_MII_CLK); + if (CSR_READ_4(sc, AX_SIO) & AX_SIO_MII_DATAIN) + return(1); + + return(0); +} + +/* + * Sync the PHYs by setting data bit and strobing the clock 32 times. + */ +static void ax_mii_sync(sc) + struct ax_softc *sc; +{ + register int i; + + CSR_WRITE_4(sc, AX_SIO, AX_SIO_ROMCTL_WRITE); + + for (i = 0; i < 32; i++) + ax_mii_writebit(sc, 1); + + return; +} + +/* + * Clock a series of bits through the MII. + */ +static void ax_mii_send(sc, bits, cnt) + struct ax_softc *sc; + u_int32_t bits; + int cnt; +{ + int i; + + for (i = (0x1 << (cnt - 1)); i; i >>= 1) + ax_mii_writebit(sc, bits & i); +} + +/* + * Read an PHY register through the MII. + */ +static int ax_mii_readreg(sc, frame) + struct ax_softc *sc; + struct ax_mii_frame *frame; + +{ + int i, ack, s; + + s = splimp(); + + /* + * Set up frame for RX. + */ + frame->mii_stdelim = AX_MII_STARTDELIM; + frame->mii_opcode = AX_MII_READOP; + frame->mii_turnaround = 0; + frame->mii_data = 0; + + /* + * Sync the PHYs. + */ + ax_mii_sync(sc); + + /* + * Send command/address info. + */ + ax_mii_send(sc, frame->mii_stdelim, 2); + ax_mii_send(sc, frame->mii_opcode, 2); + ax_mii_send(sc, frame->mii_phyaddr, 5); + ax_mii_send(sc, frame->mii_regaddr, 5); + +#ifdef notdef + /* Idle bit */ + ax_mii_writebit(sc, 1); + ax_mii_writebit(sc, 0); +#endif + + /* Check for ack */ + ack = ax_mii_readbit(sc); + + /* + * Now try reading data bits. If the ack failed, we still + * need to clock through 16 cycles to keep the PHY(s) in sync. + */ + if (ack) { + for(i = 0; i < 16; i++) { + ax_mii_readbit(sc); + } + goto fail; + } + + for (i = 0x8000; i; i >>= 1) { + if (!ack) { + if (ax_mii_readbit(sc)) + frame->mii_data |= i; + } + } + +fail: + + ax_mii_writebit(sc, 0); + ax_mii_writebit(sc, 0); + + splx(s); + + if (ack) + return(1); + return(0); +} + +/* + * Write to a PHY register through the MII. + */ +static int ax_mii_writereg(sc, frame) + struct ax_softc *sc; + struct ax_mii_frame *frame; + +{ + int s; + + s = splimp(); + /* + * Set up frame for TX. + */ + + frame->mii_stdelim = AX_MII_STARTDELIM; + frame->mii_opcode = AX_MII_WRITEOP; + frame->mii_turnaround = AX_MII_TURNAROUND; + + /* + * Sync the PHYs. + */ + ax_mii_sync(sc); + + ax_mii_send(sc, frame->mii_stdelim, 2); + ax_mii_send(sc, frame->mii_opcode, 2); + ax_mii_send(sc, frame->mii_phyaddr, 5); + ax_mii_send(sc, frame->mii_regaddr, 5); + ax_mii_send(sc, frame->mii_turnaround, 2); + ax_mii_send(sc, frame->mii_data, 16); + + /* Idle bit. */ + ax_mii_writebit(sc, 0); + ax_mii_writebit(sc, 0); + + splx(s); + + return(0); +} + +static u_int16_t ax_phy_readreg(sc, reg) + struct ax_softc *sc; + int reg; +{ + struct ax_mii_frame frame; + + bzero((char *)&frame, sizeof(frame)); + + frame.mii_phyaddr = sc->ax_phy_addr; + frame.mii_regaddr = reg; + ax_mii_readreg(sc, &frame); + + return(frame.mii_data); +} + +static void ax_phy_writereg(sc, reg, data) + struct ax_softc *sc; + int reg; + int data; +{ + struct ax_mii_frame frame; + + bzero((char *)&frame, sizeof(frame)); + + frame.mii_phyaddr = sc->ax_phy_addr; + frame.mii_regaddr = reg; + frame.mii_data = data; + + ax_mii_writereg(sc, &frame); + + return; +} + +/* + * Calculate CRC of a multicast group address, return the lower 6 bits. + */ +static u_int32_t ax_calchash(addr) + caddr_t addr; +{ + u_int32_t crc, carry; + int i, j; + u_int8_t c; + + /* Compute CRC for the address value. */ + crc = 0xFFFFFFFF; /* initial value */ + + for (i = 0; i < 6; i++) { + c = *(addr + i); + for (j = 0; j < 8; j++) { + carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); + crc <<= 1; + c >>= 1; + if (carry) + crc = (crc ^ 0x04c11db6) | carry; + } + } + + /* return the filter bit position */ + return((crc >> 26) & 0x0000003F); +} + +static void ax_setmulti(sc) + struct ax_softc *sc; +{ + struct ifnet *ifp; + int h = 0; + u_int32_t hashes[2] = { 0, 0 }; + struct ifmultiaddr *ifma; + u_int32_t rxfilt; + + ifp = &sc->arpcom.ac_if; + + rxfilt = CSR_READ_4(sc, AX_NETCFG); + + if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { + rxfilt |= AX_NETCFG_RX_ALLMULTI; + CSR_WRITE_4(sc, AX_NETCFG, rxfilt); + return; + } else + rxfilt &= ~AX_NETCFG_RX_ALLMULTI; + + /* first, zot all the existing hash bits */ + CSR_WRITE_4(sc, AX_FILTIDX, AX_FILTIDX_MAR0); + CSR_WRITE_4(sc, AX_FILTDATA, 0); + CSR_WRITE_4(sc, AX_FILTIDX, AX_FILTIDX_MAR1); + CSR_WRITE_4(sc, AX_FILTDATA, 0); + + /* now program new ones */ + for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; + ifma = ifma->ifma_link.le_next) { + if (ifma->ifma_addr->sa_family != AF_LINK) + continue; + h = ax_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); + if (h < 32) + hashes[0] |= (1 << h); + else + hashes[1] |= (1 << (h - 32)); + } + + CSR_WRITE_4(sc, AX_FILTIDX, AX_FILTIDX_MAR0); + CSR_WRITE_4(sc, AX_FILTDATA, hashes[0]); + CSR_WRITE_4(sc, AX_FILTIDX, AX_FILTIDX_MAR1); + CSR_WRITE_4(sc, AX_FILTDATA, hashes[1]); + CSR_WRITE_4(sc, AX_NETCFG, rxfilt); + + return; +} + +/* + * Initiate an autonegotiation session. + */ +static void ax_autoneg_xmit(sc) + struct ax_softc *sc; +{ + u_int16_t phy_sts; + + ax_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); + DELAY(500); + while(ax_phy_readreg(sc, PHY_BMCR) + & PHY_BMCR_RESET); + + phy_sts = ax_phy_readreg(sc, PHY_BMCR); + phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR; + ax_phy_writereg(sc, PHY_BMCR, phy_sts); + + return; +} + +/* + * Invoke autonegotiation on a PHY. + */ +static void ax_autoneg_mii(sc, flag, verbose) + struct ax_softc *sc; + int flag; + int verbose; +{ + u_int16_t phy_sts = 0, media, advert, ability; + struct ifnet *ifp; + struct ifmedia *ifm; + + ifm = &sc->ifmedia; + ifp = &sc->arpcom.ac_if; + + ifm->ifm_media = IFM_ETHER | IFM_AUTO; + + /* + * The 100baseT4 PHY on the 3c905-T4 has the 'autoneg supported' + * bit cleared in the status register, but has the 'autoneg enabled' + * bit set in the control register. This is a contradiction, and + * I'm not sure how to handle it. If you want to force an attempt + * to autoneg for 100baseT4 PHYs, #define FORCE_AUTONEG_TFOUR + * and see what happens. + */ +#ifndef FORCE_AUTONEG_TFOUR + /* + * First, see if autoneg is supported. If not, there's + * no point in continuing. + */ + phy_sts = ax_phy_readreg(sc, PHY_BMSR); + if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { + if (verbose) + printf("ax%d: autonegotiation not supported\n", + sc->ax_unit); + ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; + return; + } +#endif + + switch (flag) { + case AX_FLAG_FORCEDELAY: + /* + * XXX Never use this option anywhere but in the probe + * routine: making the kernel stop dead in its tracks + * for three whole seconds after we've gone multi-user + * is really bad manners. + */ + ax_autoneg_xmit(sc); + DELAY(5000000); + break; + case AX_FLAG_SCHEDDELAY: + /* + * Wait for the transmitter to go idle before starting + * an autoneg session, otherwise ax_start() may clobber + * our timeout, and we don't want to allow transmission + * during an autoneg session since that can screw it up. + */ + if (sc->ax_cdata.ax_tx_head != NULL) { + sc->ax_want_auto = 1; + return; + } + ax_autoneg_xmit(sc); + ifp->if_timer = 5; + sc->ax_autoneg = 1; + sc->ax_want_auto = 0; + return; + break; + case AX_FLAG_DELAYTIMEO: + ifp->if_timer = 0; + sc->ax_autoneg = 0; + break; + default: + printf("ax%d: invalid autoneg flag: %d\n", sc->ax_unit, flag); + return; + } + + if (ax_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { + if (verbose) + printf("ax%d: autoneg complete, ", sc->ax_unit); + phy_sts = ax_phy_readreg(sc, PHY_BMSR); + } else { + if (verbose) + printf("ax%d: autoneg not complete, ", sc->ax_unit); + } + + media = ax_phy_readreg(sc, PHY_BMCR); + + /* Link is good. Report modes and set duplex mode. */ + if (ax_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { + if (verbose) + printf("link status good "); + advert = ax_phy_readreg(sc, PHY_ANAR); + ability = ax_phy_readreg(sc, PHY_LPAR); + + if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { + ifm->ifm_media = IFM_ETHER|IFM_100_T4; + media |= PHY_BMCR_SPEEDSEL; + media &= ~PHY_BMCR_DUPLEX; + printf("(100baseT4)\n"); + } else if (advert & PHY_ANAR_100BTXFULL && + ability & PHY_ANAR_100BTXFULL) { + ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX; + media |= PHY_BMCR_SPEEDSEL; + media |= PHY_BMCR_DUPLEX; + printf("(full-duplex, 100Mbps)\n"); + } else if (advert & PHY_ANAR_100BTXHALF && + ability & PHY_ANAR_100BTXHALF) { + ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX; + media |= PHY_BMCR_SPEEDSEL; + media &= ~PHY_BMCR_DUPLEX; + printf("(half-duplex, 100Mbps)\n"); + } else if (advert & PHY_ANAR_10BTFULL && + ability & PHY_ANAR_10BTFULL) { + ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX; + media &= ~PHY_BMCR_SPEEDSEL; + media |= PHY_BMCR_DUPLEX; + printf("(full-duplex, 10Mbps)\n"); + } else if (advert & PHY_ANAR_10BTHALF && + ability & PHY_ANAR_10BTHALF) { + ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; + media &= ~PHY_BMCR_SPEEDSEL; + media &= ~PHY_BMCR_DUPLEX; + printf("(half-duplex, 10Mbps)\n"); + } + + media &= ~PHY_BMCR_AUTONEGENBL; + + /* Set ASIC's duplex mode to match the PHY. */ + ax_setcfg(sc, media); + ax_phy_writereg(sc, PHY_BMCR, media); + } else { + if (verbose) + printf("no carrier\n"); + } + + ax_init(sc); + + if (sc->ax_tx_pend) { + sc->ax_autoneg = 0; + sc->ax_tx_pend = 0; + ax_start(ifp); + } + + return; +} + +static void ax_getmode_mii(sc) + struct ax_softc *sc; +{ + u_int16_t bmsr; + struct ifnet *ifp; + + ifp = &sc->arpcom.ac_if; + + bmsr = ax_phy_readreg(sc, PHY_BMSR); + if (bootverbose) + printf("ax%d: PHY status word: %x\n", sc->ax_unit, bmsr); + + /* fallback */ + sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; + + if (bmsr & PHY_BMSR_10BTHALF) { + if (bootverbose) + printf("ax%d: 10Mbps half-duplex mode supported\n", + sc->ax_unit); + ifmedia_add(&sc->ifmedia, + IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); + ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); + } + + if (bmsr & PHY_BMSR_10BTFULL) { + if (bootverbose) + printf("ax%d: 10Mbps full-duplex mode supported\n", + sc->ax_unit); + ifmedia_add(&sc->ifmedia, + IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); + sc->ifmedia.ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX; + } + + if (bmsr & PHY_BMSR_100BTXHALF) { + if (bootverbose) + printf("ax%d: 100Mbps half-duplex mode supported\n", + sc->ax_unit); + ifp->if_baudrate = 100000000; + ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); + ifmedia_add(&sc->ifmedia, + IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); + sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX; + } + + if (bmsr & PHY_BMSR_100BTXFULL) { + if (bootverbose) + printf("ax%d: 100Mbps full-duplex mode supported\n", + sc->ax_unit); + ifp->if_baudrate = 100000000; + ifmedia_add(&sc->ifmedia, + IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); + sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX; + } + + /* Some also support 100BaseT4. */ + if (bmsr & PHY_BMSR_100BT4) { + if (bootverbose) + printf("ax%d: 100baseT4 mode supported\n", sc->ax_unit); + ifp->if_baudrate = 100000000; + ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL); + sc->ifmedia.ifm_media = IFM_ETHER|IFM_100_T4; +#ifdef FORCE_AUTONEG_TFOUR + if (bootverbose) + printf("ax%d: forcing on autoneg support for BT4\n", + sc->ax_unit); + ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0 NULL): + sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO; +#endif + } + + if (bmsr & PHY_BMSR_CANAUTONEG) { + if (bootverbose) + printf("ax%d: autoneg supported\n", sc->ax_unit); + ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); + sc->ifmedia.ifm_media = IFM_ETHER|IFM_AUTO; + } + + return; +} + +/* + * Set speed and duplex mode. + */ +static void ax_setmode_mii(sc, media) + struct ax_softc *sc; + int media; +{ + u_int16_t bmcr; + struct ifnet *ifp; + + ifp = &sc->arpcom.ac_if; + + /* + * If an autoneg session is in progress, stop it. + */ + if (sc->ax_autoneg) { + printf("ax%d: canceling autoneg session\n", sc->ax_unit); + ifp->if_timer = sc->ax_autoneg = sc->ax_want_auto = 0; + bmcr = ax_phy_readreg(sc, PHY_BMCR); + bmcr &= ~PHY_BMCR_AUTONEGENBL; + ax_phy_writereg(sc, PHY_BMCR, bmcr); + } + + printf("ax%d: selecting MII, ", sc->ax_unit); + + bmcr = ax_phy_readreg(sc, PHY_BMCR); + + bmcr &= ~(PHY_BMCR_AUTONEGENBL|PHY_BMCR_SPEEDSEL| + PHY_BMCR_DUPLEX|PHY_BMCR_LOOPBK); + + if (IFM_SUBTYPE(media) == IFM_100_T4) { + printf("100Mbps/T4, half-duplex\n"); + bmcr |= PHY_BMCR_SPEEDSEL; + bmcr &= ~PHY_BMCR_DUPLEX; + } + + if (IFM_SUBTYPE(media) == IFM_100_TX) { + printf("100Mbps, "); + bmcr |= PHY_BMCR_SPEEDSEL; + } + + if (IFM_SUBTYPE(media) == IFM_10_T) { + printf("10Mbps, "); + bmcr &= ~PHY_BMCR_SPEEDSEL; + } + + if ((media & IFM_GMASK) == IFM_FDX) { + printf("full duplex\n"); + bmcr |= PHY_BMCR_DUPLEX; + } else { + printf("half duplex\n"); + bmcr &= ~PHY_BMCR_DUPLEX; + } + + ax_setcfg(sc, bmcr); + ax_phy_writereg(sc, PHY_BMCR, bmcr); + + return; +} + +/* + * Set speed and duplex mode on internal transceiver. + */ +static void ax_setmode(sc, media, verbose) + struct ax_softc *sc; + int media; + int verbose; +{ + struct ifnet *ifp; + u_int32_t mode; + + ifp = &sc->arpcom.ac_if; + + if (verbose) + printf("ax%d: selecting internal xcvr, ", sc->ax_unit); + + mode = CSR_READ_4(sc, AX_NETCFG); + + mode &= ~(AX_NETCFG_FULLDUPLEX|AX_NETCFG_PORTSEL| + AX_NETCFG_PCS|AX_NETCFG_SCRAMBLER|AX_NETCFG_SPEEDSEL); + + if (IFM_SUBTYPE(media) == IFM_100_T4) { + if (verbose) + printf("100Mbps/T4, half-duplex\n"); + mode |= AX_NETCFG_PORTSEL|AX_NETCFG_PCS|AX_NETCFG_SCRAMBLER; + } + + if (IFM_SUBTYPE(media) == IFM_100_TX) { + if (verbose) + printf("100Mbps, "); + mode |= AX_NETCFG_PORTSEL|AX_NETCFG_PCS|AX_NETCFG_SCRAMBLER; + } + + if (IFM_SUBTYPE(media) == IFM_10_T) { + if (verbose) + printf("10Mbps, "); + mode &= ~AX_NETCFG_PORTSEL; + mode |= AX_NETCFG_SPEEDSEL; + } + + if ((media & IFM_GMASK) == IFM_FDX) { + if (verbose) + printf("full duplex\n"); + mode |= AX_NETCFG_FULLDUPLEX; + } else { + if (verbose) + printf("half duplex\n"); + mode &= ~AX_NETCFG_FULLDUPLEX; + } + + CSR_WRITE_4(sc, AX_NETCFG, mode); + + return; +} + +/* + * In order to fiddle with the + * 'full-duplex' and '100Mbps' bits in the netconfig register, we + * first have to put the transmit and/or receive logic in the idle state. + */ +static void ax_setcfg(sc, bmcr) + struct ax_softc *sc; + int bmcr; +{ + int i, restart = 0; + + if (CSR_READ_4(sc, AX_NETCFG) & (AX_NETCFG_TX_ON|AX_NETCFG_RX_ON)) { + restart = 1; + AX_CLRBIT(sc, AX_NETCFG, (AX_NETCFG_TX_ON|AX_NETCFG_RX_ON)); + + for (i = 0; i < AX_TIMEOUT; i++) { + DELAY(10); + if (CSR_READ_4(sc, AX_ISR) & AX_ISR_TX_IDLE) + break; + } + + if (i == AX_TIMEOUT) + printf("ax%d: failed to force tx and " + "rx to idle state\n", sc->ax_unit); + + } + + if (bmcr & PHY_BMCR_SPEEDSEL) + AX_CLRBIT(sc, AX_NETCFG, AX_NETCFG_SPEEDSEL); + else + AX_SETBIT(sc, AX_NETCFG, AX_NETCFG_SPEEDSEL); + + if (bmcr & PHY_BMCR_DUPLEX) + AX_SETBIT(sc, AX_NETCFG, AX_NETCFG_FULLDUPLEX); + else + AX_CLRBIT(sc, AX_NETCFG, AX_NETCFG_FULLDUPLEX); + + if (restart) + AX_SETBIT(sc, AX_NETCFG, AX_NETCFG_TX_ON|AX_NETCFG_RX_ON); + + return; +} + +static void ax_reset(sc) + struct ax_softc *sc; +{ + register int i; + + AX_SETBIT(sc, AX_BUSCTL, AX_BUSCTL_RESET); + + for (i = 0; i < AX_TIMEOUT; i++) { + DELAY(10); + if (!(CSR_READ_4(sc, AX_BUSCTL) & AX_BUSCTL_RESET)) + break; + } +#ifdef notdef + if (i == AX_TIMEOUT) + printf("ax%d: reset never completed!\n", sc->ax_unit); +#endif + CSR_WRITE_4(sc, AX_BUSCTL, AX_BUSCTL_CONFIG); + + /* Wait a little while for the chip to get its brains in order. */ + DELAY(1000); + return; +} + +/* + * Probe for an ASIX chip. Check the PCI vendor and device + * IDs against our list and return a device name if we find a match. + */ +static const char * +ax_probe(config_id, device_id) + pcici_t config_id; + pcidi_t device_id; +{ + struct ax_type *t; + + t = ax_devs; + + while(t->ax_name != NULL) { + if ((device_id & 0xFFFF) == t->ax_vid && + ((device_id >> 16) & 0xFFFF) == t->ax_did) { + return(t->ax_name); + } + t++; + } + + return(NULL); +} + +/* + * Attach the interface. Allocate softc structures, do ifmedia + * setup and ethernet/BPF attach. + */ +static void +ax_attach(config_id, unit) + pcici_t config_id; + int unit; +{ + int s, i; +#ifndef AX_USEIOSPACE + vm_offset_t pbase, vbase; +#endif + u_char eaddr[ETHER_ADDR_LEN]; + u_int32_t command; + struct ax_softc *sc; + struct ifnet *ifp; + int media = IFM_ETHER|IFM_100_TX|IFM_FDX; + unsigned int round; + caddr_t roundptr; + struct ax_type *p; + u_int16_t phy_vid, phy_did, phy_sts; + + s = splimp(); + + sc = malloc(sizeof(struct ax_softc), M_DEVBUF, M_NOWAIT); + if (sc == NULL) { + printf("ax%d: no memory for softc struct!\n", unit); + goto fail; + } + bzero(sc, sizeof(struct ax_softc)); + + /* + * Handle power management nonsense. + */ + + command = pci_conf_read(config_id, AX_PCI_CAPID) & 0x000000FF; + if (command == 0x01) { + + command = pci_conf_read(config_id, AX_PCI_PWRMGMTCTRL); + if (command & AX_PSTATE_MASK) { + u_int32_t iobase, membase, irq; + + /* Save important PCI config data. */ + iobase = pci_conf_read(config_id, AX_PCI_LOIO); + membase = pci_conf_read(config_id, AX_PCI_LOMEM); + irq = pci_conf_read(config_id, AX_PCI_INTLINE); + + /* Reset the power state. */ + printf("ax%d: chip is in D%d power mode " + "-- setting to D0\n", unit, command & AX_PSTATE_MASK); + command &= 0xFFFFFFFC; + pci_conf_write(config_id, AX_PCI_PWRMGMTCTRL, command); + + /* Restore PCI config data. */ + pci_conf_write(config_id, AX_PCI_LOIO, iobase); + pci_conf_write(config_id, AX_PCI_LOMEM, membase); + pci_conf_write(config_id, AX_PCI_INTLINE, irq); + } + } + + /* + * Map control/status registers. + */ + command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); + command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); + pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command); + command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); + +#ifdef AX_USEIOSPACE + if (!(command & PCIM_CMD_PORTEN)) { + printf("ax%d: failed to enable I/O ports!\n", unit); + free(sc, M_DEVBUF); + goto fail; + } + + if (!pci_map_port(config_id, AX_PCI_LOIO, + (u_short *)&(sc->ax_bhandle))) { + printf ("ax%d: couldn't map ports\n", unit); + goto fail; + } + sc->ax_btag = I386_BUS_SPACE_IO; +#else + if (!(command & PCIM_CMD_MEMEN)) { + printf("ax%d: failed to enable memory mapping!\n", unit); + goto fail; + } + + if (!pci_map_mem(config_id, AX_PCI_LOMEM, &vbase, &pbase)) { + printf ("ax%d: couldn't map memory\n", unit); + goto fail; + } + sc->ax_btag = I386_BUS_SPACE_MEM; + sc->ax_bhandle = vbase; +#endif + + /* Allocate interrupt */ + if (!pci_map_int(config_id, ax_intr, sc, &net_imask)) { + printf("ax%d: couldn't map interrupt\n", unit); + goto fail; + } + + /* Reset the adapter. */ + ax_reset(sc); + + /* + * Get station address from the EEPROM. + */ + ax_read_eeprom(sc, (caddr_t)&eaddr, AX_EE_NODEADDR, 3, 0); + + /* + * An ASIX chip was detected. Inform the world. + */ + printf("ax%d: Ethernet address: %6D\n", unit, eaddr, ":"); + + sc->ax_unit = unit; + bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); + + sc->ax_ldata_ptr = malloc(sizeof(struct ax_list_data) + 8, + M_DEVBUF, M_NOWAIT); + if (sc->ax_ldata_ptr == NULL) { + free(sc, M_DEVBUF); + printf("ax%d: no memory for list buffers!\n", unit); + goto fail; + } + + sc->ax_ldata = (struct ax_list_data *)sc->ax_ldata_ptr; + round = (unsigned int)sc->ax_ldata_ptr & 0xF; + roundptr = sc->ax_ldata_ptr; + for (i = 0; i < 8; i++) { + if (round % 8) { + round++; + roundptr++; + } else + break; + } + sc->ax_ldata = (struct ax_list_data *)roundptr; + bzero(sc->ax_ldata, sizeof(struct ax_list_data)); + + ifp = &sc->arpcom.ac_if; + ifp->if_softc = sc; + ifp->if_unit = unit; + ifp->if_name = "ax"; + ifp->if_mtu = ETHERMTU; + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; + ifp->if_ioctl = ax_ioctl; + ifp->if_output = ether_output; + ifp->if_start = ax_start; + ifp->if_watchdog = ax_watchdog; + ifp->if_init = ax_init; + ifp->if_baudrate = 10000000; + + + if (bootverbose) + printf("ax%d: probing for a PHY\n", sc->ax_unit); + for (i = AX_PHYADDR_MIN; i < AX_PHYADDR_MAX + 1; i++) { + if (bootverbose) + printf("ax%d: checking address: %d\n", + sc->ax_unit, i); + sc->ax_phy_addr = i; + ax_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); + DELAY(500); + while(ax_phy_readreg(sc, PHY_BMCR) + & PHY_BMCR_RESET); + if ((phy_sts = ax_phy_readreg(sc, PHY_BMSR))) + break; + } + if (phy_sts) { + phy_vid = ax_phy_readreg(sc, PHY_VENID); + phy_did = ax_phy_readreg(sc, PHY_DEVID); + if (bootverbose) + printf("ax%d: found PHY at address %d, ", + sc->ax_unit, sc->ax_phy_addr); + if (bootverbose) + printf("vendor id: %x device id: %x\n", + phy_vid, phy_did); + p = ax_phys; + while(p->ax_vid) { + if (phy_vid == p->ax_vid && + (phy_did | 0x000F) == p->ax_did) { + sc->ax_pinfo = p; + break; + } + p++; + } + if (sc->ax_pinfo == NULL) + sc->ax_pinfo = &ax_phys[PHY_UNKNOWN]; + if (bootverbose) + printf("ax%d: PHY type: %s\n", + sc->ax_unit, sc->ax_pinfo->ax_name); + } else { +#ifdef DIAGNOSTIC + printf("ax%d: MII without any phy!\n", sc->ax_unit); +#endif + } + + /* + * Do ifmedia setup. + */ + ifmedia_init(&sc->ifmedia, 0, ax_ifmedia_upd, ax_ifmedia_sts); + + if (sc->ax_pinfo != NULL) { + ax_getmode_mii(sc); + ax_autoneg_mii(sc, AX_FLAG_FORCEDELAY, 1); + } else { + ifmedia_add(&sc->ifmedia, + IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); + ifmedia_add(&sc->ifmedia, + IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); + ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); + ifmedia_add(&sc->ifmedia, + IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); + ifmedia_add(&sc->ifmedia, + IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); + ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); + ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); + } + + media = sc->ifmedia.ifm_media; + ax_stop(sc); + + ifmedia_set(&sc->ifmedia, media); + + /* + * Call MI attach routines. + */ + if_attach(ifp); + ether_ifattach(ifp); + +#if NBPFILTER > 0 + bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); +#endif + at_shutdown(ax_shutdown, sc, SHUTDOWN_POST_SYNC); + +fail: + splx(s); + return; +} + +/* + * Initialize the transmit descriptors. + */ +static int ax_list_tx_init(sc) + struct ax_softc *sc; +{ + struct ax_chain_data *cd; + struct ax_list_data *ld; + int i; + + cd = &sc->ax_cdata; + ld = sc->ax_ldata; + for (i = 0; i < AX_TX_LIST_CNT; i++) { + cd->ax_tx_chain[i].ax_ptr = &ld->ax_tx_list[i]; + if (i == (AX_TX_LIST_CNT - 1)) + cd->ax_tx_chain[i].ax_nextdesc = + &cd->ax_tx_chain[0]; + else + cd->ax_tx_chain[i].ax_nextdesc = + &cd->ax_tx_chain[i + 1]; + } + + cd->ax_tx_free = &cd->ax_tx_chain[0]; + cd->ax_tx_tail = cd->ax_tx_head = NULL; + + return(0); +} + + +/* + * Initialize the RX descriptors and allocate mbufs for them. Note that + * we arrange the descriptors in a closed ring, so that the last descriptor + * points back to the first. + */ +static int ax_list_rx_init(sc) + struct ax_softc *sc; +{ + struct ax_chain_data *cd; + struct ax_list_data *ld; + int i; + + cd = &sc->ax_cdata; + ld = sc->ax_ldata; + + for (i = 0; i < AX_RX_LIST_CNT; i++) { + cd->ax_rx_chain[i].ax_ptr = + (struct ax_desc *)&ld->ax_rx_list[i]; + if (ax_newbuf(sc, &cd->ax_rx_chain[i]) == ENOBUFS) + return(ENOBUFS); + if (i == (AX_RX_LIST_CNT - 1)) { + cd->ax_rx_chain[i].ax_nextdesc = + &cd->ax_rx_chain[0]; + ld->ax_rx_list[i].ax_next = + vtophys(&ld->ax_rx_list[0]); + } else { + cd->ax_rx_chain[i].ax_nextdesc = + &cd->ax_rx_chain[i + 1]; + ld->ax_rx_list[i].ax_next = + vtophys(&ld->ax_rx_list[i + 1]); + } + } + + cd->ax_rx_head = &cd->ax_rx_chain[0]; + + return(0); +} + +/* + * Initialize an RX descriptor and attach an MBUF cluster. + * Note: the length fields are only 11 bits wide, which means the + * largest size we can specify is 2047. This is important because + * MCLBYTES is 2048, so we have to subtract one otherwise we'll + * overflow the field and make a mess. + */ +static int ax_newbuf(sc, c) + struct ax_softc *sc; + struct ax_chain_onefrag *c; +{ + struct mbuf *m_new = NULL; + + MGETHDR(m_new, M_DONTWAIT, MT_DATA); + if (m_new == NULL) { + printf("ax%d: no memory for rx list -- packet dropped!\n", + sc->ax_unit); + return(ENOBUFS); + } + + MCLGET(m_new, M_DONTWAIT); + if (!(m_new->m_flags & M_EXT)) { + printf("ax%d: no memory for rx list -- packet dropped!\n", + sc->ax_unit); + m_freem(m_new); + return(ENOBUFS); + } + + c->ax_mbuf = m_new; + c->ax_ptr->ax_status = AX_RXSTAT; + c->ax_ptr->ax_data = vtophys(mtod(m_new, caddr_t)); + c->ax_ptr->ax_ctl = MCLBYTES - 1; + + return(0); +} + +/* + * A frame has been uploaded: pass the resulting mbuf chain up to + * the higher level protocols. + */ +static void ax_rxeof(sc) + struct ax_softc *sc; +{ + struct ether_header *eh; + struct mbuf *m; + struct ifnet *ifp; + struct ax_chain_onefrag *cur_rx; + int total_len = 0; + u_int32_t rxstat; + + ifp = &sc->arpcom.ac_if; + + while(!((rxstat = sc->ax_cdata.ax_rx_head->ax_ptr->ax_status) & + AX_RXSTAT_OWN)) { + cur_rx = sc->ax_cdata.ax_rx_head; + sc->ax_cdata.ax_rx_head = cur_rx->ax_nextdesc; + + /* + * If an error occurs, update stats, clear the + * status word and leave the mbuf cluster in place: + * it should simply get re-used next time this descriptor + * comes up in the ring. + */ + if (rxstat & AX_RXSTAT_RXERR) { + ifp->if_ierrors++; + if (rxstat & AX_RXSTAT_COLLSEEN) + ifp->if_collisions++; + cur_rx->ax_ptr->ax_status = AX_RXSTAT; + cur_rx->ax_ptr->ax_ctl = (MCLBYTES - 1); + continue; + } + + /* No errors; receive the packet. */ + m = cur_rx->ax_mbuf; + total_len = AX_RXBYTES(cur_rx->ax_ptr->ax_status); + + total_len -= ETHER_CRC_LEN; + + /* + * Try to conjure up a new mbuf cluster. If that + * fails, it means we have an out of memory condition and + * should leave the buffer in place and continue. This will + * result in a lost packet, but there's little else we + * can do in this situation. + */ + if (ax_newbuf(sc, cur_rx) == ENOBUFS) { + ifp->if_ierrors++; + cur_rx->ax_ptr->ax_status = AX_RXSTAT; + cur_rx->ax_ptr->ax_ctl = (MCLBYTES - 1); + continue; + } + + ifp->if_ipackets++; + eh = mtod(m, struct ether_header *); + m->m_pkthdr.rcvif = ifp; + m->m_pkthdr.len = m->m_len = total_len; +#if NBPFILTER > 0 + /* + * Handle BPF listeners. Let the BPF user see the packet, but + * don't pass it up to the ether_input() layer unless it's + * a broadcast packet, multicast packet, matches our ethernet + * address or the interface is in promiscuous mode. + */ + if (ifp->if_bpf) { + bpf_mtap(ifp, m); + if (ifp->if_flags & IFF_PROMISC && + (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, + ETHER_ADDR_LEN) && + (eh->ether_dhost[0] & 1) == 0)) { + m_freem(m); + continue; + } + } +#endif + /* Remove header from mbuf and pass it on. */ + m_adj(m, sizeof(struct ether_header)); + ether_input(ifp, eh, m); + } + + return; +} + +void ax_rxeoc(sc) + struct ax_softc *sc; +{ + + ax_rxeof(sc); + AX_CLRBIT(sc, AX_NETCFG, AX_NETCFG_RX_ON); + CSR_WRITE_4(sc, AX_RXADDR, vtophys(sc->ax_cdata.ax_rx_head->ax_ptr)); + AX_SETBIT(sc, AX_NETCFG, AX_NETCFG_RX_ON); + CSR_WRITE_4(sc, AX_RXSTART, 0xFFFFFFFF); + + return; +} + +/* + * A frame was downloaded to the chip. It's safe for us to clean up + * the list buffers. + */ + +static void ax_txeof(sc) + struct ax_softc *sc; +{ + struct ax_chain *cur_tx; + struct ifnet *ifp; + + ifp = &sc->arpcom.ac_if; + + /* Clear the timeout timer. */ + ifp->if_timer = 0; + + if (sc->ax_cdata.ax_tx_head == NULL) + return; + + /* + * Go through our tx list and free mbufs for those + * frames that have been transmitted. + */ + while(sc->ax_cdata.ax_tx_head->ax_mbuf != NULL) { + u_int32_t txstat; + + cur_tx = sc->ax_cdata.ax_tx_head; + txstat = AX_TXSTATUS(cur_tx); + + if (txstat & AX_TXSTAT_OWN) + break; + + if (txstat & AX_TXSTAT_ERRSUM) { + ifp->if_oerrors++; + if (txstat & AX_TXSTAT_EXCESSCOLL) + ifp->if_collisions++; + if (txstat & AX_TXSTAT_LATECOLL) + ifp->if_collisions++; + } + + ifp->if_collisions += (txstat & AX_TXSTAT_COLLCNT) >> 3; + + ifp->if_opackets++; + m_freem(cur_tx->ax_mbuf); + cur_tx->ax_mbuf = NULL; + + if (sc->ax_cdata.ax_tx_head == sc->ax_cdata.ax_tx_tail) { + sc->ax_cdata.ax_tx_head = NULL; + sc->ax_cdata.ax_tx_tail = NULL; + break; + } + + sc->ax_cdata.ax_tx_head = cur_tx->ax_nextdesc; + } + + return; +} + +/* + * TX 'end of channel' interrupt handler. + */ +static void ax_txeoc(sc) + struct ax_softc *sc; +{ + struct ifnet *ifp; + + ifp = &sc->arpcom.ac_if; + + ifp->if_timer = 0; + + if (sc->ax_cdata.ax_tx_head == NULL) { + ifp->if_flags &= ~IFF_OACTIVE; + sc->ax_cdata.ax_tx_tail = NULL; + if (sc->ax_want_auto) + ax_autoneg_mii(sc, AX_FLAG_DELAYTIMEO, 1); + } + + return; +} + +static void ax_intr(arg) + void *arg; +{ + struct ax_softc *sc; + struct ifnet *ifp; + u_int32_t status; + + sc = arg; + ifp = &sc->arpcom.ac_if; + + /* Supress unwanted interrupts */ + if (!(ifp->if_flags & IFF_UP)) { + ax_stop(sc); + return; + } + + /* Disable interrupts. */ + CSR_WRITE_4(sc, AX_IMR, 0x00000000); + + for (;;) { + status = CSR_READ_4(sc, AX_ISR); + if (status) + CSR_WRITE_4(sc, AX_ISR, status); + + if ((status & AX_INTRS) == 0) + break; + + if ((status & AX_ISR_TX_OK) || (status & AX_ISR_TX_EARLY)) + ax_txeof(sc); + + if (status & AX_ISR_TX_NOBUF) + ax_txeoc(sc); + + if (status & AX_ISR_TX_IDLE) { + ax_txeof(sc); + if (sc->ax_cdata.ax_tx_head != NULL) { + AX_SETBIT(sc, AX_NETCFG, AX_NETCFG_TX_ON); + CSR_WRITE_4(sc, AX_TXSTART, 0xFFFFFFFF); + } + } + + if (status & AX_ISR_TX_UNDERRUN) { + u_int32_t cfg; + cfg = CSR_READ_4(sc, AX_NETCFG); + if ((cfg & AX_NETCFG_TX_THRESH) == AX_TXTHRESH_160BYTES) + AX_SETBIT(sc, AX_NETCFG, AX_NETCFG_STORENFWD); + else + CSR_WRITE_4(sc, AX_NETCFG, cfg + 0x4000); + } + + if (status & AX_ISR_RX_OK) + ax_rxeof(sc); + + if ((status & AX_ISR_RX_WATDOGTIMEO) + || (status & AX_ISR_RX_NOBUF)) + ax_rxeoc(sc); + + if (status & AX_ISR_BUS_ERR) { + ax_reset(sc); + ax_init(sc); + } + } + + /* Re-enable interrupts. */ + CSR_WRITE_4(sc, AX_IMR, AX_INTRS); + + if (ifp->if_snd.ifq_head != NULL) { + ax_start(ifp); + } + + return; +} + +/* + * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data + * pointers to the fragment pointers. + */ +static int ax_encap(sc, c, m_head) + struct ax_softc *sc; + struct ax_chain *c; + struct mbuf *m_head; +{ + int frag = 0; + volatile struct ax_desc *f = NULL; + int total_len; + struct mbuf *m; + + /* + * Start packing the mbufs in this chain into + * the fragment pointers. Stop when we run out + * of fragments or hit the end of the mbuf chain. + */ + m = m_head; + total_len = 0; + + for (m = m_head, frag = 0; m != NULL; m = m->m_next) { + if (m->m_len != 0) { + if (frag == AX_MAXFRAGS) + break; + total_len += m->m_len; + f = &c->ax_ptr->ax_frag[frag]; + f->ax_ctl = m->m_len; + if (frag == 0) { + f->ax_status = 0; + f->ax_ctl |= AX_TXCTL_FIRSTFRAG; + } else + f->ax_status = AX_TXSTAT_OWN; + f->ax_next = vtophys(&c->ax_ptr->ax_frag[frag + 1]); + f->ax_data = vtophys(mtod(m, vm_offset_t)); + frag++; + } + } + + /* + * Handle special case: we ran out of fragments, + * but we have more mbufs left in the chain. Copy the + * data into an mbuf cluster. Note that we don't + * bother clearing the values in the other fragment + * pointers/counters; it wouldn't gain us anything, + * and would waste cycles. + */ + if (m != NULL) { + struct mbuf *m_new = NULL; + + MGETHDR(m_new, M_DONTWAIT, MT_DATA); + if (m_new == NULL) { + printf("ax%d: no memory for tx list", sc->ax_unit); + return(1); + } + if (m_head->m_pkthdr.len > MHLEN) { + MCLGET(m_new, M_DONTWAIT); + if (!(m_new->m_flags & M_EXT)) { + m_freem(m_new); + printf("ax%d: no memory for tx list", + sc->ax_unit); + return(1); + } + } + m_copydata(m_head, 0, m_head->m_pkthdr.len, + mtod(m_new, caddr_t)); + m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; + m_freem(m_head); + m_head = m_new; + f = &c->ax_ptr->ax_frag[0]; + f->ax_status = 0; + f->ax_data = vtophys(mtod(m_new, caddr_t)); + f->ax_ctl = total_len = m_new->m_len; + f->ax_ctl |= AX_TXCTL_FIRSTFRAG; + frag = 1; + } + + + if (total_len < AX_MIN_FRAMELEN) { + f = &c->ax_ptr->ax_frag[frag]; + f->ax_ctl = AX_MIN_FRAMELEN - total_len; + f->ax_data = vtophys(&sc->ax_cdata.ax_pad); + f->ax_status = AX_TXSTAT_OWN; + frag++; + } + + c->ax_mbuf = m_head; + c->ax_lastdesc = frag - 1; + AX_TXCTL(c) |= AX_TXCTL_LASTFRAG|AX_TXCTL_FINT; + AX_TXNEXT(c) = vtophys(&c->ax_nextdesc->ax_ptr->ax_frag[0]); + return(0); +} + +/* + * Main transmit routine. To avoid having to do mbuf copies, we put pointers + * to the mbuf data regions directly in the transmit lists. We also save a + * copy of the pointers since the transmit list fragment pointers are + * physical addresses. + */ + +static void ax_start(ifp) + struct ifnet *ifp; +{ + struct ax_softc *sc; + struct mbuf *m_head = NULL; + struct ax_chain *cur_tx = NULL, *start_tx; + + sc = ifp->if_softc; + + if (sc->ax_autoneg) { + sc->ax_tx_pend = 1; + return; + } + + /* + * Check for an available queue slot. If there are none, + * punt. + */ + if (sc->ax_cdata.ax_tx_free->ax_mbuf != NULL) { + ifp->if_flags |= IFF_OACTIVE; + return; + } + + start_tx = sc->ax_cdata.ax_tx_free; + + while(sc->ax_cdata.ax_tx_free->ax_mbuf == NULL) { + IF_DEQUEUE(&ifp->if_snd, m_head); + if (m_head == NULL) + break; + + /* Pick a descriptor off the free list. */ + cur_tx = sc->ax_cdata.ax_tx_free; + sc->ax_cdata.ax_tx_free = cur_tx->ax_nextdesc; + + /* Pack the data into the descriptor. */ + ax_encap(sc, cur_tx, m_head); + if (cur_tx != start_tx) + AX_TXOWN(cur_tx) = AX_TXSTAT_OWN; + +#if NBPFILTER > 0 + /* + * If there's a BPF listener, bounce a copy of this frame + * to him. + */ + if (ifp->if_bpf) + bpf_mtap(ifp, cur_tx->ax_mbuf); +#endif + AX_TXOWN(cur_tx) = AX_TXSTAT_OWN; + CSR_WRITE_4(sc, AX_TXSTART, 0xFFFFFFFF); + } + + sc->ax_cdata.ax_tx_tail = cur_tx; + if (sc->ax_cdata.ax_tx_head == NULL) + sc->ax_cdata.ax_tx_head = start_tx; + + /* + * Set a timeout in case the chip goes out to lunch. + */ + ifp->if_timer = 5; + + return; +} + +static void ax_init(xsc) + void *xsc; +{ + struct ax_softc *sc = xsc; + struct ifnet *ifp = &sc->arpcom.ac_if; + u_int16_t phy_bmcr = 0; + int s; + + if (sc->ax_autoneg) + return; + + s = splimp(); + + if (sc->ax_pinfo != NULL) + phy_bmcr = ax_phy_readreg(sc, PHY_BMCR); + + /* + * Cancel pending I/O and free all RX/TX buffers. + */ + ax_stop(sc); + ax_reset(sc); + + /* + * Set cache alignment and burst length. + */ + CSR_WRITE_4(sc, AX_BUSCTL, AX_BUSCTL_CONFIG); + + AX_CLRBIT(sc, AX_NETCFG, AX_NETCFG_HEARTBEAT); + AX_CLRBIT(sc, AX_NETCFG, AX_NETCFG_STORENFWD); + + if (sc->ax_pinfo != NULL) { + AX_SETBIT(sc, AX_NETCFG, AX_NETCFG_PORTSEL); + ax_setcfg(sc, ax_phy_readreg(sc, PHY_BMCR)); + } else + ax_setmode(sc, sc->ifmedia.ifm_media, 0); + + AX_CLRBIT(sc, AX_NETCFG, AX_NETCFG_TX_THRESH); + AX_CLRBIT(sc, AX_NETCFG, AX_NETCFG_SPEEDSEL); + + if (IFM_SUBTYPE(sc->ifmedia.ifm_media) == IFM_10_T) + AX_SETBIT(sc, AX_NETCFG, AX_TXTHRESH_160BYTES); + else + AX_SETBIT(sc, AX_NETCFG, AX_TXTHRESH_72BYTES); + + /* Init our MAC address */ + CSR_WRITE_4(sc, AX_FILTIDX, AX_FILTIDX_PAR0); + CSR_WRITE_4(sc, AX_FILTDATA, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); + CSR_WRITE_4(sc, AX_FILTIDX, AX_FILTIDX_PAR1); + CSR_WRITE_4(sc, AX_FILTDATA, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); + + /* Init circular RX list. */ + if (ax_list_rx_init(sc) == ENOBUFS) { + printf("ax%d: initialization failed: no " + "memory for rx buffers\n", sc->ax_unit); + ax_stop(sc); + (void)splx(s); + return; + } + + /* + * Init tx descriptors. + */ + ax_list_tx_init(sc); + + /* If we want promiscuous mode, set the allframes bit. */ + if (ifp->if_flags & IFF_PROMISC) { + AX_SETBIT(sc, AX_NETCFG, AX_NETCFG_RX_PROMISC); + } else { + AX_CLRBIT(sc, AX_NETCFG, AX_NETCFG_RX_PROMISC); + } + + /* + * Set the capture broadcast bit to capture broadcast frames. + */ + if (ifp->if_flags & IFF_BROADCAST) { + AX_SETBIT(sc, AX_NETCFG, AX_NETCFG_RX_BROAD); + } else { + AX_CLRBIT(sc, AX_NETCFG, AX_NETCFG_RX_BROAD); + } + + /* + * Load the multicast filter. + */ + ax_setmulti(sc); + + /* + * Load the address of the RX list. + */ + CSR_WRITE_4(sc, AX_RXADDR, vtophys(sc->ax_cdata.ax_rx_head->ax_ptr)); + CSR_WRITE_4(sc, AX_TXADDR, vtophys(&sc->ax_ldata->ax_tx_list[0])); + + /* + * Enable interrupts. + */ + CSR_WRITE_4(sc, AX_IMR, AX_INTRS); + CSR_WRITE_4(sc, AX_ISR, 0xFFFFFFFF); + + /* Enable receiver and transmitter. */ + AX_SETBIT(sc, AX_NETCFG, AX_NETCFG_TX_ON|AX_NETCFG_RX_ON); + CSR_WRITE_4(sc, AX_RXSTART, 0xFFFFFFFF); + + /* Restore state of BMCR */ + if (sc->ax_pinfo != NULL) + ax_phy_writereg(sc, PHY_BMCR, phy_bmcr); + + ifp->if_flags |= IFF_RUNNING; + ifp->if_flags &= ~IFF_OACTIVE; + + (void)splx(s); + + return; +} + +/* + * Set media options. + */ +static int ax_ifmedia_upd(ifp) + struct ifnet *ifp; +{ + struct ax_softc *sc; + struct ifmedia *ifm; + + sc = ifp->if_softc; + ifm = &sc->ifmedia; + + if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) + return(EINVAL); + + if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) + ax_autoneg_mii(sc, AX_FLAG_SCHEDDELAY, 1); + else { + if (sc->ax_pinfo == NULL) + ax_setmode(sc, ifm->ifm_media, 1); + else + ax_setmode_mii(sc, ifm->ifm_media); + } + + return(0); +} + +/* + * Report current media status. + */ +static void ax_ifmedia_sts(ifp, ifmr) + struct ifnet *ifp; + struct ifmediareq *ifmr; +{ + struct ax_softc *sc; + u_int16_t advert = 0, ability = 0; + u_int32_t media = 0; + + sc = ifp->if_softc; + + ifmr->ifm_active = IFM_ETHER; + + if (sc->ax_pinfo == NULL) { + media = CSR_READ_4(sc, AX_NETCFG); + if (media & AX_NETCFG_PORTSEL) + ifmr->ifm_active = IFM_ETHER|IFM_100_TX; + else + ifmr->ifm_active = IFM_ETHER|IFM_10_T; + if (media & AX_NETCFG_FULLDUPLEX) + ifmr->ifm_active |= IFM_FDX; + else + ifmr->ifm_active |= IFM_HDX; + return; + } + + if (!(ax_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { + if (ax_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) + ifmr->ifm_active = IFM_ETHER|IFM_100_TX; + else + ifmr->ifm_active = IFM_ETHER|IFM_10_T; + if (ax_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) + ifmr->ifm_active |= IFM_FDX; + else + ifmr->ifm_active |= IFM_HDX; + return; + } + + ability = ax_phy_readreg(sc, PHY_LPAR); + advert = ax_phy_readreg(sc, PHY_ANAR); + if (advert & PHY_ANAR_100BT4 && + ability & PHY_ANAR_100BT4) { + ifmr->ifm_active = IFM_ETHER|IFM_100_T4; + } else if (advert & PHY_ANAR_100BTXFULL && + ability & PHY_ANAR_100BTXFULL) { + ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_FDX; + } else if (advert & PHY_ANAR_100BTXHALF && + ability & PHY_ANAR_100BTXHALF) { + ifmr->ifm_active = IFM_ETHER|IFM_100_TX|IFM_HDX; + } else if (advert & PHY_ANAR_10BTFULL && + ability & PHY_ANAR_10BTFULL) { + ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_FDX; + } else if (advert & PHY_ANAR_10BTHALF && + ability & PHY_ANAR_10BTHALF) { + ifmr->ifm_active = IFM_ETHER|IFM_10_T|IFM_HDX; + } + + return; +} + +static int ax_ioctl(ifp, command, data) + struct ifnet *ifp; + u_long command; + caddr_t data; +{ + struct ax_softc *sc = ifp->if_softc; + struct ifreq *ifr = (struct ifreq *) data; + int s, error = 0; + + s = splimp(); + + switch(command) { + case SIOCSIFADDR: + case SIOCGIFADDR: + case SIOCSIFMTU: + error = ether_ioctl(ifp, command, data); + break; + case SIOCSIFFLAGS: + if (ifp->if_flags & IFF_UP) { + ax_init(sc); + } else { + if (ifp->if_flags & IFF_RUNNING) + ax_stop(sc); + } + error = 0; + break; + case SIOCADDMULTI: + case SIOCDELMULTI: + ax_setmulti(sc); + error = 0; + break; + case SIOCGIFMEDIA: + case SIOCSIFMEDIA: + error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); + break; + default: + error = EINVAL; + break; + } + + (void)splx(s); + + return(error); +} + +static void ax_watchdog(ifp) + struct ifnet *ifp; +{ + struct ax_softc *sc; + + sc = ifp->if_softc; + + if (sc->ax_autoneg) { + ax_autoneg_mii(sc, AX_FLAG_DELAYTIMEO, 1); + return; + } + + ifp->if_oerrors++; + printf("ax%d: watchdog timeout\n", sc->ax_unit); + + if (sc->ax_pinfo != NULL) { + if (!(ax_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) + printf("ax%d: no carrier - transceiver " + "cable problem?\n", sc->ax_unit); + } + + ax_stop(sc); + ax_reset(sc); + ax_init(sc); + + if (ifp->if_snd.ifq_head != NULL) + ax_start(ifp); + + return; +} + +/* + * Stop the adapter and free any mbufs allocated to the + * RX and TX lists. + */ +static void ax_stop(sc) + struct ax_softc *sc; +{ + register int i; + struct ifnet *ifp; + + ifp = &sc->arpcom.ac_if; + ifp->if_timer = 0; + + AX_CLRBIT(sc, AX_NETCFG, (AX_NETCFG_RX_ON|AX_NETCFG_TX_ON)); + CSR_WRITE_4(sc, AX_IMR, 0x00000000); + CSR_WRITE_4(sc, AX_TXADDR, 0x00000000); + CSR_WRITE_4(sc, AX_RXADDR, 0x00000000); + + /* + * Free data in the RX lists. + */ + for (i = 0; i < AX_RX_LIST_CNT; i++) { + if (sc->ax_cdata.ax_rx_chain[i].ax_mbuf != NULL) { + m_freem(sc->ax_cdata.ax_rx_chain[i].ax_mbuf); + sc->ax_cdata.ax_rx_chain[i].ax_mbuf = NULL; + } + } + bzero((char *)&sc->ax_ldata->ax_rx_list, + sizeof(sc->ax_ldata->ax_rx_list)); + + /* + * Free the TX list buffers. + */ + for (i = 0; i < AX_TX_LIST_CNT; i++) { + if (sc->ax_cdata.ax_tx_chain[i].ax_mbuf != NULL) { + m_freem(sc->ax_cdata.ax_tx_chain[i].ax_mbuf); + sc->ax_cdata.ax_tx_chain[i].ax_mbuf = NULL; + } + } + + bzero((char *)&sc->ax_ldata->ax_tx_list, + sizeof(sc->ax_ldata->ax_tx_list)); + + ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); + + return; +} + +/* + * Stop all chip I/O so that the kernel's probe routines don't + * get confused by errant DMAs when rebooting. + */ +static void ax_shutdown(howto, arg) + int howto; + void *arg; +{ + struct ax_softc *sc = (struct ax_softc *)arg; + + ax_stop(sc); + + return; +} + +static struct pci_device ax_device = { + "ax", + ax_probe, + ax_attach, + &ax_count, + NULL +}; +DATA_SET(pcidevice_set, ax_device); diff --git a/sys/pci/if_axreg.h b/sys/pci/if_axreg.h new file mode 100644 index 0000000..bb4a874 --- /dev/null +++ b/sys/pci/if_axreg.h @@ -0,0 +1,560 @@ +/* + * Copyright (c) 1997, 1998, 1999 + * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * $Id: if_axreg.h,v 1.3 1999/01/07 02:59:08 wpaul Exp $ + */ + +/* + * ASIX register definitions. + */ + +#define AX_BUSCTL 0x00 /* bus control */ +#define AX_TXSTART 0x08 /* tx start demand */ +#define AX_RXSTART 0x10 /* rx start demand */ +#define AX_RXADDR 0x18 /* rx descriptor list start addr */ +#define AX_TXADDR 0x20 /* tx descriptor list start addr */ +#define AX_ISR 0x28 /* interrupt status register */ +#define AX_NETCFG 0x30 /* network config register */ +#define AX_IMR 0x38 /* interrupt mask */ +#define AX_FRAMESDISCARDED 0x40 /* # of discarded frames */ +#define AX_SIO 0x48 /* MII and ROM/EEPROM access */ +#define AX_RESERVED 0x50 +#define AX_GENTIMER 0x58 /* general timer */ +#define AX_GENPORT 0x60 /* general purpose port */ +#define AX_FILTIDX 0x68 /* RX filter index */ +#define AX_FILTDATA 0x70 /* RX filter data */ + +/* + * Bus control bits. + */ +#define AX_BUSCTL_RESET 0x00000001 +#define AX_BUSCTL_ARBITRATION 0x00000002 +#define AX_BUSCTL_BIGENDIAN 0x00000080 +#define AX_BUSCTL_BURSTLEN 0x00003F00 +#define AX_BUSCTL_BUF_BIGENDIAN 0x00100000 +#define AX_BISCTL_READMULTI 0x00200000 + +#define AX_BURSTLEN_UNLIMIT 0x00000000 +#define AX_BURSTLEN_1LONG 0x00000100 +#define AX_BURSTLEN_2LONG 0x00000200 +#define AX_BURSTLEN_4LONG 0x00000400 +#define AX_BURSTLEN_8LONG 0x00000800 +#define AX_BURSTLEN_16LONG 0x00001000 +#define AX_BURSTLEN_32LONG 0x00002000 + +#define AX_BUSCTL_CONFIG (AX_BUSCTL_ARBITRATION|AX_BURSTLEN_8LONG|AX_BURSTLEN_8LONG) + +/* + * Interrupt status bits. + */ +#define AX_ISR_TX_OK 0x00000001 +#define AX_ISR_TX_IDLE 0x00000002 +#define AX_ISR_TX_NOBUF 0x00000004 +#define AX_ISR_TX_JABBERTIMEO 0x00000008 +#define AX_ISR_TX_UNDERRUN 0x00000020 +#define AX_ISR_RX_OK 0x00000040 +#define AX_ISR_RX_NOBUF 0x00000080 +#define AX_ISR_RX_IDLE 0x00000100 +#define AX_ISR_RX_WATDOGTIMEO 0x00000200 +#define AX_ISR_TX_EARLY 0x00000400 +#define AX_ISR_TIMER_EXPIRED 0x00000800 +#define AX_ISR_BUS_ERR 0x00002000 +#define AX_ISR_ABNORMAL 0x00008000 +#define AX_ISR_NORMAL 0x00010000 +#define AX_ISR_RX_STATE 0x000E0000 +#define AX_ISR_TX_STATE 0x00700000 +#define AX_ISR_BUSERRTYPE 0x03800000 + +#define AX_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */ +#define AX_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */ +#define AX_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */ +#define AX_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */ +#define AX_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */ +#define AX_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */ +#define AX_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */ +#define AX_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */ + +#define AX_TXSTATE_RESET 0x00000000 /* 000 - reset */ +#define AX_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */ +#define AX_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */ +#define AX_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */ +#define AX_TXSTATE_RSVD 0x00400000 /* 100 - reserved */ +#define AX_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */ +#define AX_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */ +#define AX_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */ + +/* + * Network config bits. + */ +#define AX_NETCFG_LINKSTAT_PCS 0x00000001 +#define AX_NETCFG_RX_ON 0x00000002 +#define AX_NETCFG_RX_BADFRAMES 0x00000008 +#define AX_NETCFG_RX_PROMISC 0x00000040 +#define AX_NETCFG_RX_ALLMULTI 0x00000080 +#define AX_NETCFG_RX_BROAD 0x00000100 +#define AX_NETCFG_FULLDUPLEX 0x00000200 +#define AX_NETCFG_LOOPBACK 0x00000C00 +#define AX_NETCFG_FORCECOLL 0x00001000 +#define AX_NETCFG_TX_ON 0x00002000 +#define AX_NETCFG_TX_THRESH 0x0000C000 +#define AX_NETCFG_PORTSEL 0x00040000 /* 0 == SRL, 1 == MII/SYM */ +#define AX_NETCFG_HEARTBEAT 0x00080000 /* 0 == ON, 1 == OFF */ +#define AX_NETCFG_STORENFWD 0x00200000 +#define AX_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */ +#define AX_NETCFG_PCS 0x00800000 +#define AX_NETCFG_SCRAMBLER 0x01000000 +#define AX_NETCFG_RX_ALL 0x40000000 + +#define AX_OPMODE_NORM 0x00000000 +#define AX_OPMODE_INTLOOP 0x00000400 +#define AX_OPMODE_EXTLOOP 0x00000800 + +#define AX_TXTHRESH_72BYTES 0x00000000 +#define AX_TXTHRESH_96BYTES 0x00004000 +#define AX_TXTHRESH_128BYTES 0x00008000 +#define AX_TXTHRESH_160BYTES 0x0000C000 + +/* + * Interrupt mask bits. + */ +#define AX_IMR_TX_OK 0x00000001 +#define AX_IMR_TX_IDLE 0x00000002 +#define AX_IMR_TX_NOBUF 0x00000004 +#define AX_IMR_TX_JABBERTIMEO 0x00000008 +#define AX_IMR_TX_UNDERRUN 0x00000020 +#define AX_IMR_RX_OK 0x00000040 +#define AX_IMR_RX_NOBUF 0x00000080 +#define AX_IMR_RX_IDLE 0x00000100 +#define AX_IMR_RX_WATDOGTIMEO 0x00000200 +#define AX_IMR_TX_EARLY 0x00000400 +#define AX_IMR_TIMER_EXPIRED 0x00000800 +#define AX_IMR_BUS_ERR 0x00002000 +#define AX_IMR_RX_EARLY 0x00004000 +#define AX_IMR_ABNORMAL 0x00008000 +#define AX_IMR_NORMAL 0x00010000 + +#define AX_INTRS \ + (AX_IMR_RX_OK|AX_IMR_TX_OK|AX_IMR_RX_NOBUF|AX_IMR_RX_WATDOGTIMEO|\ + AX_IMR_TX_NOBUF|AX_IMR_TX_UNDERRUN|AX_IMR_BUS_ERR| \ + AX_IMR_ABNORMAL|AX_IMR_NORMAL|/*AX_IMR_TX_EARLY*/ \ + AX_IMR_TX_IDLE|AX_IMR_RX_IDLE) + +/* + * Serial I/O (EEPROM/ROM) bits. + */ +#define AX_SIO_EE_CS 0x00000001 /* EEPROM chip select */ +#define AX_SIO_EE_CLK 0x00000002 /* EEPROM clock */ +#define AX_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */ +#define AX_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */ +#define AX_SIO_EESEL 0x00000800 +#define AX_SIO_ROMSEL 0x00001000 +#define AX_SIO_ROMCTL_WRITE 0x00002000 +#define AX_SIO_ROMCTL_READ 0x00004000 +#define AX_SIO_MII_CLK 0x00010000 /* MDIO clock */ +#define AX_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */ +#define AX_SIO_MII_DIR 0x00040000 /* MDIO dir */ +#define AX_SIO_MII_DATAIN 0x00080000 /* MDIO data in */ + +#define AX_EECMD_WRITE 0x140 +#define AX_EECMD_READ 0x180 +#define AX_EECMD_ERASE 0x1c0 + +#define AX_EE_NODEADDR_OFFSET 0x70 +#define AX_EE_NODEADDR 10 + +/* + * General purpose timer register + */ +#define AX_TIMER_VALUE 0x0000FFFF +#define AX_TIMER_CONTINUOUS 0x00010000 + +/* + * RX Filter Index Register values + */ +#define AX_FILTIDX_PAR0 0x00000000 +#define AX_FILTIDX_PAR1 0x00000001 +#define AX_FILTIDX_MAR0 0x00000002 +#define AX_FILTIDX_MAR1 0x00000003 + +/* + * ASIX TX/RX list structure. + */ + +struct ax_desc { + volatile u_int32_t ax_status; + volatile u_int32_t ax_ctl; + volatile u_int32_t ax_ptr1; + volatile u_int32_t ax_ptr2; +}; + +#define ax_data ax_ptr1 +#define ax_next ax_ptr2 + +#define AX_RXSTAT_FIFOOFLOW 0x00000001 +#define AX_RXSTAT_CRCERR 0x00000002 +#define AX_RXSTAT_DRIBBLE 0x00000004 +#define AX_RXSTAT_WATCHDOG 0x00000010 +#define AX_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */ +#define AX_RXSTAT_COLLSEEN 0x00000040 +#define AX_RXSTAT_GIANT 0x00000080 +#define AX_RXSTAT_LASTFRAG 0x00000100 +#define AX_RXSTAT_FIRSTFRAG 0x00000200 +#define AX_RXSTAT_MULTICAST 0x00000400 +#define AX_RXSTAT_RUNT 0x00000800 +#define AX_RXSTAT_RXTYPE 0x00003000 +#define AX_RXSTAT_RXERR 0x00008000 +#define AX_RXSTAT_RXLEN 0x3FFF0000 +#define AX_RXSTAT_OWN 0x80000000 + +#define AX_RXBYTES(x) ((x & AX_RXSTAT_RXLEN) >> 16) +#define AX_RXSTAT (AX_RXSTAT_FIRSTFRAG|AX_RXSTAT_LASTFRAG|AX_RXSTAT_OWN) + +#define AX_RXCTL_BUFLEN1 0x00000FFF +#define AX_RXCTL_BUFLEN2 0x00FFF000 +#define AX_RXCTL_RLAST 0x02000000 + +#define AX_TXSTAT_DEFER 0x00000001 +#define AX_TXSTAT_UNDERRUN 0x00000002 +#define AX_TXSTAT_LINKFAIL 0x00000003 +#define AX_TXSTAT_COLLCNT 0x00000078 +#define AX_TXSTAT_SQE 0x00000080 +#define AX_TXSTAT_EXCESSCOLL 0x00000100 +#define AX_TXSTAT_LATECOLL 0x00000200 +#define AX_TXSTAT_NOCARRIER 0x00000400 +#define AX_TXSTAT_CARRLOST 0x00000800 +#define AX_TXSTAT_JABTIMEO 0x00004000 +#define AX_TXSTAT_ERRSUM 0x00008000 +#define AX_TXSTAT_OWN 0x80000000 + +#define AX_TXCTL_BUFLEN1 0x000007FF +#define AX_TXCTL_BUFLEN2 0x003FF800 +#define AX_TXCTL_PAD 0x00800000 +#define AX_TXCTL_TLAST 0x02000000 +#define AX_TXCTL_NOCRC 0x04000000 +#define AX_TXCTL_FIRSTFRAG 0x20000000 +#define AX_TXCTL_LASTFRAG 0x40000000 +#define AX_TXCTL_FINT 0x80000000 + +#define AX_MAXFRAGS 16 +#define AX_RX_LIST_CNT 64 +#define AX_TX_LIST_CNT 64 +#define AX_MIN_FRAMELEN 60 + +/* + * A tx 'super descriptor' is actually 16 regular descriptors + * back to back. + */ +struct ax_txdesc { + volatile struct ax_desc ax_frag[AX_MAXFRAGS]; +}; + +#define AX_TXNEXT(x) x->ax_ptr->ax_frag[x->ax_lastdesc].ax_next +#define AX_TXSTATUS(x) x->ax_ptr->ax_frag[x->ax_lastdesc].ax_status +#define AX_TXCTL(x) x->ax_ptr->ax_frag[x->ax_lastdesc].ax_ctl +#define AX_TXDATA(x) x->ax_ptr->ax_frag[x->ax_lastdesc].ax_data + +#define AX_TXOWN(x) x->ax_ptr->ax_frag[0].ax_status + +#define AX_UNSENT 0x12341234 + +struct ax_list_data { + volatile struct ax_desc ax_rx_list[AX_RX_LIST_CNT]; + volatile struct ax_txdesc ax_tx_list[AX_TX_LIST_CNT]; +}; + +struct ax_chain { + volatile struct ax_txdesc *ax_ptr; + struct mbuf *ax_mbuf; + struct ax_chain *ax_nextdesc; + u_int8_t ax_lastdesc; +}; + +struct ax_chain_onefrag { + volatile struct ax_desc *ax_ptr; + struct mbuf *ax_mbuf; + struct ax_chain_onefrag *ax_nextdesc; +}; + +struct ax_chain_data { + u_int8_t ax_pad[AX_MIN_FRAMELEN]; + struct ax_chain_onefrag ax_rx_chain[AX_RX_LIST_CNT]; + struct ax_chain ax_tx_chain[AX_TX_LIST_CNT]; + + struct ax_chain_onefrag *ax_rx_head; + + struct ax_chain *ax_tx_head; + struct ax_chain *ax_tx_tail; + struct ax_chain *ax_tx_free; +}; + +struct ax_type { + u_int16_t ax_vid; + u_int16_t ax_did; + char *ax_name; +}; + +struct ax_mii_frame { + u_int8_t mii_stdelim; + u_int8_t mii_opcode; + u_int8_t mii_phyaddr; + u_int8_t mii_regaddr; + u_int8_t mii_turnaround; + u_int16_t mii_data; +}; + +/* + * MII constants + */ +#define AX_MII_STARTDELIM 0x01 +#define AX_MII_READOP 0x02 +#define AX_MII_WRITEOP 0x01 +#define AX_MII_TURNAROUND 0x02 + +#define AX_FLAG_FORCEDELAY 1 +#define AX_FLAG_SCHEDDELAY 2 +#define AX_FLAG_DELAYTIMEO 3 + +struct ax_softc { + struct arpcom arpcom; /* interface info */ + struct ifmedia ifmedia; /* media info */ + bus_space_handle_t ax_bhandle; /* bus space handle */ + bus_space_tag_t ax_btag; /* bus space tag */ + struct ax_type *ax_info; /* ASIX adapter info */ + struct ax_type *ax_pinfo; /* phy info */ + u_int8_t ax_unit; /* interface number */ + u_int8_t ax_type; + u_int8_t ax_phy_addr; /* PHY address */ + u_int8_t ax_tx_pend; /* TX pending */ + u_int8_t ax_want_auto; + u_int8_t ax_autoneg; + caddr_t ax_ldata_ptr; + struct ax_list_data *ax_ldata; + struct ax_chain_data ax_cdata; +}; + +/* + * register space access macros + */ +#define CSR_WRITE_4(sc, reg, val) \ + bus_space_write_4(sc->ax_btag, sc->ax_bhandle, reg, val) +#define CSR_WRITE_2(sc, reg, val) \ + bus_space_write_2(sc->ax_btag, sc->ax_bbhandle, reg, val) +#define CSR_WRITE_1(sc, reg, val) \ + bus_space_write_1(sc->ax_btag, sc->ax_bhandle, reg, val) + +#define CSR_READ_4(sc, reg) \ + bus_space_read_4(sc->ax_btag, sc->ax_bhandle, reg) +#define CSR_READ_2(sc, reg) \ + bus_space_read_2(sc->ax_btag, sc->ax_bhandle, reg) +#define CSR_READ_1(sc, reg) \ + bus_space_read_1(sc->ax_btag, sc->ax_bhandle, reg) + +#define AX_TIMEOUT 1000 + +/* + * General constants that are fun to know. + * + * ASIX PCI vendor ID + */ +#define AX_VENDORID 0x125B + +/* + * ASIX device IDs. + */ +#define AX_DEVICEID_AX88140A 0x1400 + +/* + * Texas Instruments PHY identifiers + */ +#define TI_PHY_VENDORID 0x4000 +#define TI_PHY_10BT 0x501F +#define TI_PHY_100VGPMI 0x502F + +/* + * These ID values are for the NS DP83840A 10/100 PHY + */ +#define NS_PHY_VENDORID 0x2000 +#define NS_PHY_83840A 0x5C0F + +/* + * Level 1 10/100 PHY + */ +#define LEVEL1_PHY_VENDORID 0x7810 +#define LEVEL1_PHY_LXT970 0x000F + +/* + * Intel 82555 10/100 PHY + */ +#define INTEL_PHY_VENDORID 0x0A28 +#define INTEL_PHY_82555 0x015F + +/* + * SEEQ 80220 10/100 PHY + */ +#define SEEQ_PHY_VENDORID 0x0016 +#define SEEQ_PHY_80220 0xF83F + + +/* + * PCI low memory base and low I/O base register, and + * other PCI registers. + */ + +#define AX_PCI_VENDOR_ID 0x00 +#define AX_PCI_DEVICE_ID 0x02 +#define AX_PCI_COMMAND 0x04 +#define AX_PCI_STATUS 0x06 +#define AX_PCI_REVID 0x08 +#define AX_PCI_CLASSCODE 0x09 +#define AX_PCI_LATENCY_TIMER 0x0D +#define AX_PCI_HEADER_TYPE 0x0E +#define AX_PCI_LOIO 0x10 +#define AX_PCI_LOMEM 0x14 +#define AX_PCI_BIOSROM 0x30 +#define AX_PCI_INTLINE 0x3C +#define AX_PCI_INTPIN 0x3D +#define AX_PCI_MINGNT 0x3E +#define AX_PCI_MINLAT 0x0F +#define AX_PCI_RESETOPT 0x48 +#define AX_PCI_EEPROM_DATA 0x4C + +/* power management registers */ +#define AX_PCI_CAPID 0xDC /* 8 bits */ +#define AX_PCI_NEXTPTR 0xDD /* 8 bits */ +#define AX_PCI_PWRMGMTCAP 0xDE /* 16 bits */ +#define AX_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */ + +#define AX_PSTATE_MASK 0x0003 +#define AX_PSTATE_D0 0x0000 +#define AX_PSTATE_D1 0x0001 +#define AX_PSTATE_D2 0x0002 +#define AX_PSTATE_D3 0x0003 +#define AX_PME_EN 0x0010 +#define AX_PME_STATUS 0x8000 + +#define PHY_UNKNOWN 6 + +#define AX_PHYADDR_MIN 0x00 +#define AX_PHYADDR_MAX 0x1F + +#define PHY_BMCR 0x00 +#define PHY_BMSR 0x01 +#define PHY_VENID 0x02 +#define PHY_DEVID 0x03 +#define PHY_ANAR 0x04 +#define PHY_LPAR 0x05 +#define PHY_ANEXP 0x06 + +#define PHY_ANAR_NEXTPAGE 0x8000 +#define PHY_ANAR_RSVD0 0x4000 +#define PHY_ANAR_TLRFLT 0x2000 +#define PHY_ANAR_RSVD1 0x1000 +#define PHY_ANAR_RSVD2 0x0800 +#define PHY_ANAR_RSVD3 0x0400 +#define PHY_ANAR_100BT4 0x0200 +#define PHY_ANAR_100BTXFULL 0x0100 +#define PHY_ANAR_100BTXHALF 0x0080 +#define PHY_ANAR_10BTFULL 0x0040 +#define PHY_ANAR_10BTHALF 0x0020 +#define PHY_ANAR_PROTO4 0x0010 +#define PHY_ANAR_PROTO3 0x0008 +#define PHY_ANAR_PROTO2 0x0004 +#define PHY_ANAR_PROTO1 0x0002 +#define PHY_ANAR_PROTO0 0x0001 + +/* + * These are the register definitions for the PHY (physical layer + * interface chip). + */ +/* + * PHY BMCR Basic Mode Control Register + */ +#define PHY_BMCR_RESET 0x8000 +#define PHY_BMCR_LOOPBK 0x4000 +#define PHY_BMCR_SPEEDSEL 0x2000 +#define PHY_BMCR_AUTONEGENBL 0x1000 +#define PHY_BMCR_RSVD0 0x0800 /* write as zero */ +#define PHY_BMCR_ISOLATE 0x0400 +#define PHY_BMCR_AUTONEGRSTR 0x0200 +#define PHY_BMCR_DUPLEX 0x0100 +#define PHY_BMCR_COLLTEST 0x0080 +#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */ +#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */ +#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */ +#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */ +#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */ +#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */ +#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */ +/* + * RESET: 1 == software reset, 0 == normal operation + * Resets status and control registers to default values. + * Relatches all hardware config values. + * + * LOOPBK: 1 == loopback operation enabled, 0 == normal operation + * + * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s + * Link speed is selected byt his bit or if auto-negotiation if bit + * 12 (AUTONEGENBL) is set (in which case the value of this register + * is ignored). + * + * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled + * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13 + * determine speed and mode. Should be cleared and then set if PHY configured + * for no autoneg on startup. + * + * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation + * + * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation + * + * DUPLEX: 1 == full duplex mode, 0 == half duplex mode + * + * COLLTEST: 1 == collision test enabled, 0 == normal operation + */ + +/* + * PHY, BMSR Basic Mode Status Register + */ +#define PHY_BMSR_100BT4 0x8000 +#define PHY_BMSR_100BTXFULL 0x4000 +#define PHY_BMSR_100BTXHALF 0x2000 +#define PHY_BMSR_10BTFULL 0x1000 +#define PHY_BMSR_10BTHALF 0x0800 +#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */ +#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */ +#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */ +#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */ +#define PHY_BMSR_MFPRESUP 0x0040 +#define PHY_BMSR_AUTONEGCOMP 0x0020 +#define PHY_BMSR_REMFAULT 0x0010 +#define PHY_BMSR_CANAUTONEG 0x0008 +#define PHY_BMSR_LINKSTAT 0x0004 +#define PHY_BMSR_JABBER 0x0002 +#define PHY_BMSR_EXTENDED 0x0001 diff --git a/usr.sbin/sade/devices.c b/usr.sbin/sade/devices.c index d7ac76b..7b7261d 100644 --- a/usr.sbin/sade/devices.c +++ b/usr.sbin/sade/devices.c @@ -4,7 +4,7 @@ * This is probably the last program in the `sysinstall' line - the next * generation being essentially a complete rewrite. * - * $Id: devices.c,v 1.86 1998/10/19 14:58:38 jkh Exp $ + * $Id: devices.c,v 1.87 1998/12/04 18:01:10 wpaul Exp $ * * Copyright (c) 1995 * Jordan Hubbard. All rights reserved. @@ -80,6 +80,7 @@ static struct _devname { { DEVICE_TYPE_FLOPPY, "fd%d", "floppy drive unit A", 2, 0, 64, 4, 'b' }, { DEVICE_TYPE_FLOPPY, "wfd%d", "ATAPI floppy drive unit A", 1, 0, 8, 4, 'b' }, { DEVICE_TYPE_FLOPPY, "worm%d", "SCSI optical disk / CDR", 23, 0, 1, 4, 'b' }, + { DEVICE_TYPE_NETWORK, "ax", "ASIX AX88140A PCI ethernet card" }, { DEVICE_TYPE_NETWORK, "fpa", "DEC DEFPA PCI FDDI card" }, { DEVICE_TYPE_NETWORK, "sr", "SDL T1/E1 sync serial PCI card" }, { DEVICE_TYPE_NETWORK, "cc3i", "SDL HSSI sync serial PCI card" }, diff --git a/usr.sbin/sysinstall/devices.c b/usr.sbin/sysinstall/devices.c index d7ac76b..7b7261d 100644 --- a/usr.sbin/sysinstall/devices.c +++ b/usr.sbin/sysinstall/devices.c @@ -4,7 +4,7 @@ * This is probably the last program in the `sysinstall' line - the next * generation being essentially a complete rewrite. * - * $Id: devices.c,v 1.86 1998/10/19 14:58:38 jkh Exp $ + * $Id: devices.c,v 1.87 1998/12/04 18:01:10 wpaul Exp $ * * Copyright (c) 1995 * Jordan Hubbard. All rights reserved. @@ -80,6 +80,7 @@ static struct _devname { { DEVICE_TYPE_FLOPPY, "fd%d", "floppy drive unit A", 2, 0, 64, 4, 'b' }, { DEVICE_TYPE_FLOPPY, "wfd%d", "ATAPI floppy drive unit A", 1, 0, 8, 4, 'b' }, { DEVICE_TYPE_FLOPPY, "worm%d", "SCSI optical disk / CDR", 23, 0, 1, 4, 'b' }, + { DEVICE_TYPE_NETWORK, "ax", "ASIX AX88140A PCI ethernet card" }, { DEVICE_TYPE_NETWORK, "fpa", "DEC DEFPA PCI FDDI card" }, { DEVICE_TYPE_NETWORK, "sr", "SDL T1/E1 sync serial PCI card" }, { DEVICE_TYPE_NETWORK, "cc3i", "SDL HSSI sync serial PCI card" }, |
