diff options
| -rw-r--r-- | sys/amd64/amd64/initcpu.c | 18 | ||||
| -rw-r--r-- | sys/conf/NOTES | 4 | ||||
| -rw-r--r-- | sys/conf/options.i386 | 1 | ||||
| -rw-r--r-- | sys/conf/options.pc98 | 1 | ||||
| -rw-r--r-- | sys/i386/conf/NOTES | 4 | ||||
| -rw-r--r-- | sys/i386/i386/initcpu.c | 18 |
6 files changed, 46 insertions, 0 deletions
diff --git a/sys/amd64/amd64/initcpu.c b/sys/amd64/amd64/initcpu.c index 8a9a2a5..6cd77e3 100644 --- a/sys/amd64/amd64/initcpu.c +++ b/sys/amd64/amd64/initcpu.c @@ -575,6 +575,24 @@ initializecpu(void) init_mendocino(); break; } + } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) { +#if defined(I686_CPU) && defined(CPU_ATHLON_SSE_HACK) + /* + * Sometimes the BIOS doesn't enable SSE instructions. + * According to AMD document 20734, the mobile + * Duron, the (mobile) Athlon 4 and the Athlon MP + * support SSE. These correspond to cpu_id 0x66X + * or 0x67X. + */ + if ((cpu_feature & CPUID_XMM) == 0 && + ((cpu_id & ~0xf) == 0x660 || + (cpu_id & ~0xf) == 0x670)) { + u_int regs[4]; + wrmsr(0xC0010015, rdmsr(0xC0010015) & ~0x08000); + do_cpuid(1, regs); + cpu_feature = regs[3]; + } +#endif } break; #endif diff --git a/sys/conf/NOTES b/sys/conf/NOTES index e8c6cc5..2d02bff 100644 --- a/sys/conf/NOTES +++ b/sys/conf/NOTES @@ -175,6 +175,9 @@ cpu I686_CPU # aka Pentium Pro(tm) # # Options for CPU features. # +# CPU_ATHLON_SSE_HACK tries to enable SSE instructions when the BIOS has +# forgotten to enable them. +# # CPU_BLUELIGHTNING_FPU_OP_CACHE enables FPU operand cache on IBM # BlueLightning CPU. It works only with Cyrix FPU, and this option # should not be used with Intel FPU. @@ -256,6 +259,7 @@ cpu I686_CPU # aka Pentium Pro(tm) # NOTE 3: This option may cause failures for software that requires # locked cycles in order to operate correctly. # +options CPU_ATHLON_SSE_HACK options CPU_BLUELIGHTNING_FPU_OP_CACHE options CPU_BLUELIGHTNING_3X options CPU_BTB_EN diff --git a/sys/conf/options.i386 b/sys/conf/options.i386 index e40bc60..880a61e 100644 --- a/sys/conf/options.i386 +++ b/sys/conf/options.i386 @@ -64,6 +64,7 @@ CYRIX_CACHE_WORKS opt_cpu.h CYRIX_CACHE_REALLY_WORKS opt_cpu.h NO_MEMORY_HOLE opt_cpu.h CPU_ENABLE_SSE opt_cpu.h +CPU_ATHLON_SSE_HACK opt_cpu.h # The CPU type affects the endian conversion functions all over the kernel. I386_CPU opt_global.h diff --git a/sys/conf/options.pc98 b/sys/conf/options.pc98 index cc40038..1c6bbf9 100644 --- a/sys/conf/options.pc98 +++ b/sys/conf/options.pc98 @@ -64,6 +64,7 @@ CYRIX_CACHE_WORKS opt_cpu.h CYRIX_CACHE_REALLY_WORKS opt_cpu.h NO_MEMORY_HOLE opt_cpu.h CPU_ENABLE_SSE opt_cpu.h +CPU_ATHLON_SSE_HACK opt_cpu.h # The CPU type affects the endian conversion functions all over the kernel. I386_CPU opt_global.h diff --git a/sys/i386/conf/NOTES b/sys/i386/conf/NOTES index e8c6cc5..2d02bff 100644 --- a/sys/i386/conf/NOTES +++ b/sys/i386/conf/NOTES @@ -175,6 +175,9 @@ cpu I686_CPU # aka Pentium Pro(tm) # # Options for CPU features. # +# CPU_ATHLON_SSE_HACK tries to enable SSE instructions when the BIOS has +# forgotten to enable them. +# # CPU_BLUELIGHTNING_FPU_OP_CACHE enables FPU operand cache on IBM # BlueLightning CPU. It works only with Cyrix FPU, and this option # should not be used with Intel FPU. @@ -256,6 +259,7 @@ cpu I686_CPU # aka Pentium Pro(tm) # NOTE 3: This option may cause failures for software that requires # locked cycles in order to operate correctly. # +options CPU_ATHLON_SSE_HACK options CPU_BLUELIGHTNING_FPU_OP_CACHE options CPU_BLUELIGHTNING_3X options CPU_BTB_EN diff --git a/sys/i386/i386/initcpu.c b/sys/i386/i386/initcpu.c index 8a9a2a5..6cd77e3 100644 --- a/sys/i386/i386/initcpu.c +++ b/sys/i386/i386/initcpu.c @@ -575,6 +575,24 @@ initializecpu(void) init_mendocino(); break; } + } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) { +#if defined(I686_CPU) && defined(CPU_ATHLON_SSE_HACK) + /* + * Sometimes the BIOS doesn't enable SSE instructions. + * According to AMD document 20734, the mobile + * Duron, the (mobile) Athlon 4 and the Athlon MP + * support SSE. These correspond to cpu_id 0x66X + * or 0x67X. + */ + if ((cpu_feature & CPUID_XMM) == 0 && + ((cpu_id & ~0xf) == 0x660 || + (cpu_id & ~0xf) == 0x670)) { + u_int regs[4]; + wrmsr(0xC0010015, rdmsr(0xC0010015) & ~0x08000); + do_cpuid(1, regs); + cpu_feature = regs[3]; + } +#endif } break; #endif |
