diff options
96 files changed, 6799 insertions, 6281 deletions
@@ -203,7 +203,7 @@ _TARGET_ARCH?= ${MACHINE_ARCH} # The user can define ALWAYS_CHECK_MAKE to have this check performed # for all targets. # -.if defined(ALWAYS_CHECK_MAKE) +.if defined(ALWAYS_CHECK_MAKE) || !defined(.PARSEDIR) ${TGTS}: upgrade_checks .else buildworld: upgrade_checks @@ -358,7 +358,7 @@ MMAKE= ${MMAKEENV} ${MAKE} \ -D_UPGRADING \ -DNOMAN -DNO_MAN -DNOSHARED -DNO_SHARED \ -DNO_CPU_CFLAGS -DNO_WERROR \ - DESTDIR= MK_TESTS=no PROGNAME=${MYMAKE:T} + DESTDIR= -DNO_TESTS PROGNAME=${MYMAKE:T} make bmake: .PHONY @echo diff --git a/crypto/openssh/readconf.c b/crypto/openssh/readconf.c index 9145b46..16f62fe 100644 --- a/crypto/openssh/readconf.c +++ b/crypto/openssh/readconf.c @@ -1643,7 +1643,7 @@ initialize_options(Options * options) options->tun_remote = -1; options->local_command = NULL; options->permit_local_command = -1; - options->use_roaming = -1; + options->use_roaming = 0; options->visual_host_key = -1; options->ip_qos_interactive = -1; options->ip_qos_bulk = -1; @@ -1825,8 +1825,7 @@ fill_default_options(Options * options) options->tun_remote = SSH_TUNID_ANY; if (options->permit_local_command == -1) options->permit_local_command = 0; - if (options->use_roaming == -1) - options->use_roaming = 1; + options->use_roaming = 0; if (options->visual_host_key == -1) options->visual_host_key = 0; if (options->ip_qos_interactive == -1) diff --git a/gnu/usr.bin/groff/tmac/mdoc.local.in b/gnu/usr.bin/groff/tmac/mdoc.local.in index 6d3708f..6d9928a 100644 --- a/gnu/usr.bin/groff/tmac/mdoc.local.in +++ b/gnu/usr.bin/groff/tmac/mdoc.local.in @@ -50,7 +50,7 @@ .ds doc-str-Lb-libstdthreads C11 Threads Library (libstdthreads, \-lstdthreads) . .\" Default .Os value -.ds doc-default-operating-system FreeBSD\~10.2 +.ds doc-default-operating-system FreeBSD\~10.3 . .\" FreeBSD releases not found in doc-common .ds doc-operating-system-FreeBSD-7.4 7.4 @@ -62,6 +62,7 @@ .ds doc-operating-system-FreeBSD-10.0 10.0 .ds doc-operating-system-FreeBSD-10.1 10.1 .ds doc-operating-system-FreeBSD-10.2 10.2 +.ds doc-operating-system-FreeBSD-10.3 10.3 .ds doc-operating-system-FreeBSD-11.0 11.0 . .\" Definitions for other *BSDs not (yet) in doc-common diff --git a/lib/clang/clang.build.mk b/lib/clang/clang.build.mk index e29efc8..7be7efa 100644 --- a/lib/clang/clang.build.mk +++ b/lib/clang/clang.build.mk @@ -27,8 +27,8 @@ TARGET_ABI= gnueabi TARGET_ABI= unknown .endif -TARGET_TRIPLE?= ${TARGET_ARCH:C/amd64/x86_64/}-${TARGET_ABI}-freebsd10.2 -BUILD_TRIPLE?= ${BUILD_ARCH:C/amd64/x86_64/}-unknown-freebsd10.2 +TARGET_TRIPLE?= ${TARGET_ARCH:C/amd64/x86_64/}-${TARGET_ABI}-freebsd10.3 +BUILD_TRIPLE?= ${BUILD_ARCH:C/amd64/x86_64/}-unknown-freebsd10.3 CFLAGS+= -DLLVM_DEFAULT_TARGET_TRIPLE=\"${TARGET_TRIPLE}\" \ -DLLVM_HOST_TRIPLE=\"${BUILD_TRIPLE}\" \ -DDEFAULT_SYSROOT=\"${TOOLS_PREFIX}\" diff --git a/lib/libpmc/pmc.h b/lib/libpmc/pmc.h index e17a584..ed468da 100644 --- a/lib/libpmc/pmc.h +++ b/lib/libpmc/pmc.h @@ -36,14 +36,15 @@ * Driver statistics. */ struct pmc_driverstats { - int pm_intr_ignored; /* #interrupts ignored */ - int pm_intr_processed; /* #interrupts processed */ - int pm_intr_bufferfull; /* #interrupts with ENOSPC */ - int pm_syscalls; /* #syscalls */ - int pm_syscall_errors; /* #syscalls with errors */ - int pm_buffer_requests; /* #buffer requests */ - int pm_buffer_requests_failed; /* #failed buffer requests */ - int pm_log_sweeps; /* #sample buffer processing passes */ + unsigned int pm_intr_ignored; /* #interrupts ignored */ + unsigned int pm_intr_processed; /* #interrupts processed */ + unsigned int pm_intr_bufferfull; /* #interrupts with ENOSPC */ + unsigned int pm_syscalls; /* #syscalls */ + unsigned int pm_syscall_errors; /* #syscalls with errors */ + unsigned int pm_buffer_requests; /* #buffer requests */ + unsigned int pm_buffer_requests_failed; /* #failed buffer requests */ + unsigned int pm_log_sweeps; /* #sample buffer processing + passes */ }; /* diff --git a/release/doc/share/xml/security.xml b/release/doc/share/xml/security.xml index 8bd3cbe..fc05ae1 100644 --- a/release/doc/share/xml/security.xml +++ b/release/doc/share/xml/security.xml @@ -57,14 +57,14 @@ <row> <entry><link xlink:href="&security.url;/FreeBSD-SA-16:01.sctp.asc">FreeBSD-SA-16:01.sctp</link></entry> - <entry>15 January 2016</entry> + <entry>14 January 2016</entry> <entry><para>ICMPv6 error message vulnerability</para></entry> </row> <row> <entry><link xlink:href="&security.url;/FreeBSD-SA-16:02.ntp.asc">FreeBSD-SA-16:02.ntp</link></entry> - <entry>15 January 2016</entry> + <entry>14 January 2016</entry> <entry><para>Panic threshold bypass vulnerability</para></entry> </row> @@ -72,7 +72,7 @@ <row> <entry><link xlink:href="&security.url;/FreeBSD-SA-16:03.linux.asc">FreeBSD-SA-16:03.linux</link></entry> - <entry>15 January 2016</entry> + <entry>14 January 2016</entry> <entry><para>Incorrect <literal>futex</literal> handling</para></entry> </row> @@ -80,7 +80,7 @@ <row> <entry><link xlink:href="&security.url;/FreeBSD-SA-16:04.linux.asc">FreeBSD-SA-16:04.linux</link></entry> - <entry>15 January 2016</entry> + <entry>14 January 2016</entry> <entry><para>&man.setgroups.2; system call vulnerability</para></entry> </row> @@ -88,17 +88,25 @@ <row> <entry><link xlink:href="&security.url;/FreeBSD-SA-16:05.tcp.asc">FreeBSD-SA-16:05.tcp</link></entry> - <entry>15 January 2016</entry> + <entry>14 January 2016</entry> <entry><para>MD5 signature denial of service</para></entry> </row> <row> <entry><link xlink:href="&security.url;/FreeBSD-SA-16:06.bsnmpd.asc">FreeBSD-SA-16:06.bsnmpd</link></entry> - <entry>15 January 2016</entry> + <entry>14 January 2016</entry> <entry><para>Insecure default configuration file permissions</para></entry> </row> + + <row> + <entry><link + xlink:href="&security.url;/FreeBSD-SA-16:07.openssh.asc">FreeBSD-SA-16:07.openssh</link></entry> + <entry>14 January 2016</entry> + <entry><para><application>OpenSSH</application> client + information leak</para></entry> + </row> </tbody> </tgroup> </informaltable> diff --git a/share/man/man4/sfxge.4 b/share/man/man4/sfxge.4 index c6319fc..b924986 100644 --- a/share/man/man4/sfxge.4 +++ b/share/man/man4/sfxge.4 @@ -148,6 +148,14 @@ Number of packets with payload that must arrive in-order following loss before a connection is eligible for LRO. The idea is we should avoid coalescing segments when the sender is recovering from loss, because reducing the ACK rate can damage performance. +.It Va hw.sfxge.mcdi_logging +Enable logging of MCDI protocol messages (only available if enabled at compile-time). +.It Va hw.sfxge.N.mcdi_logging +Enable or disable logging of MCDI protocol messages on a per-port basis. The default for each +port will be the value of +.Va hw.sfxge.mcdi_logging. +The logging may also be enabled or disabled after the driver is loaded using the sysctl +.Va dev.sfxge.%d.mcdi_logging. .El .Sh SUPPORT For general information and support, diff --git a/share/mk/local.sys.mk b/share/mk/local.sys.mk index d379e8f..b54e622 100644 --- a/share/mk/local.sys.mk +++ b/share/mk/local.sys.mk @@ -3,7 +3,7 @@ .if defined(.PARSEDIR) SRCTOP:= ${.PARSEDIR:tA:H:H} .else -SRCTOP:= ${.MAKE.MAKEFILES:M*/local.sys.mk:H:H:H} +SRCTOP:= ${.MAKEFILE_LIST:M*/local.sys.mk:H:H:H} .endif .if ${.CURDIR} == ${SRCTOP} diff --git a/share/mk/sys.mk b/share/mk/sys.mk index 96cdc72..0afbbd5 100644 --- a/share/mk/sys.mk +++ b/share/mk/sys.mk @@ -144,6 +144,8 @@ OBJCFLAGS ?= ${OBJCINCLUDES} ${CFLAGS} -Wno-import OBJCOPY ?= objcopy +OBJDUMP ?= objdump + PC ?= pc PFLAGS ?= diff --git a/sys/conf/files.amd64 b/sys/conf/files.amd64 index cfc7884..268892b 100644 --- a/sys/conf/files.amd64 +++ b/sys/conf/files.amd64 @@ -346,6 +346,7 @@ dev/sfxge/common/hunt_rx.c optional sfxge pci dev/sfxge/common/hunt_sram.c optional sfxge pci dev/sfxge/common/hunt_tx.c optional sfxge pci dev/sfxge/common/hunt_vpd.c optional sfxge pci +dev/sfxge/common/medford_nic.c optional sfxge pci dev/sfxge/common/siena_mac.c optional sfxge pci dev/sfxge/common/siena_mcdi.c optional sfxge pci dev/sfxge/common/siena_nic.c optional sfxge pci diff --git a/sys/conf/newvers.sh b/sys/conf/newvers.sh index 97bec5c..70babeca 100644 --- a/sys/conf/newvers.sh +++ b/sys/conf/newvers.sh @@ -31,8 +31,8 @@ # $FreeBSD$ TYPE="FreeBSD" -REVISION="10.2" -BRANCH="STABLE" +REVISION="10.3" +BRANCH="PRERELEASE" if [ "X${BRANCH_OVERRIDE}" != "X" ]; then BRANCH=${BRANCH_OVERRIDE} fi diff --git a/sys/dev/e1000/if_igb.c b/sys/dev/e1000/if_igb.c index 798adee..088ba1e 100644 --- a/sys/dev/e1000/if_igb.c +++ b/sys/dev/e1000/if_igb.c @@ -401,6 +401,13 @@ SYSCTL_INT(_hw_igb, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN, &igb_rx_process_limit, 0, "Maximum number of received packets to process at a time, -1 means unlimited"); +/* How many packets txeof tries to clean at a time */ +static int igb_tx_process_limit = -1; +TUNABLE_INT("hw.igb.tx_process_limit", &igb_tx_process_limit); +SYSCTL_INT(_hw_igb, OID_AUTO, tx_process_limit, CTLFLAG_RDTUN, + &igb_tx_process_limit, 0, + "Maximum number of sent packets to process at a time, -1 means unlimited"); + #ifdef DEV_NETMAP /* see ixgbe.c for details */ #include <dev/netmap/if_igb_netmap.h> #endif /* DEV_NETMAP */ @@ -519,11 +526,15 @@ igb_attach(device_t dev) e1000_get_bus_info(&adapter->hw); - /* Sysctl for limiting the amount of work done in the taskqueue */ + /* Sysctls for limiting the amount of work done in the taskqueues */ igb_set_sysctl_value(adapter, "rx_processing_limit", "max number of rx packets to process", &adapter->rx_process_limit, igb_rx_process_limit); + igb_set_sysctl_value(adapter, "tx_processing_limit", + "max number of tx packets to process", + &adapter->tx_process_limit, igb_tx_process_limit); + /* * Validate number of transmit and receive descriptors. It * must not exceed hardware maximum, and must be multiple @@ -3934,7 +3945,7 @@ igb_txeof(struct tx_ring *txr) struct adapter *adapter = txr->adapter; struct ifnet *ifp = adapter->ifp; u32 work, processed = 0; - u16 limit = txr->process_limit; + int limit = adapter->tx_process_limit; struct igb_tx_buf *buf; union e1000_adv_tx_desc *txd; diff --git a/sys/dev/e1000/if_igb.h b/sys/dev/e1000/if_igb.h index f2d0926..d41d8b0 100644 --- a/sys/dev/e1000/if_igb.h +++ b/sys/dev/e1000/if_igb.h @@ -300,7 +300,6 @@ struct tx_ring { volatile u16 tx_avail; u16 next_avail_desc; u16 next_to_clean; - u16 process_limit; u16 num_desc; enum { IGB_QUEUE_IDLE = 1, @@ -479,6 +478,7 @@ struct adapter { int has_manage; int wol; int rx_process_limit; + int tx_process_limit; u16 vf_ifp; /* a VF interface */ bool in_detach; /* Used only in igb_ioctl */ diff --git a/sys/dev/hwpmc/hwpmc_mod.c b/sys/dev/hwpmc/hwpmc_mod.c index 10f9304..46dd0c3 100644 --- a/sys/dev/hwpmc/hwpmc_mod.c +++ b/sys/dev/hwpmc/hwpmc_mod.c @@ -1287,8 +1287,16 @@ pmc_process_csw_in(struct thread *td) */ if (PMC_TO_MODE(pm) == PMC_MODE_TS) { mtx_pool_lock_spin(pmc_mtxpool, pm); + + /* + * Use the saved value calculated after the most recent + * thread switch out to start this counter. Reset + * the saved count in case another thread from this + * process switches in before any threads switch out. + */ newvalue = PMC_PCPU_SAVED(cpu,ri) = pp->pp_pmcs[ri].pp_pmcval; + pp->pp_pmcs[ri].pp_pmcval = pm->pm_sc.pm_reloadcount; mtx_pool_unlock_spin(pmc_mtxpool, pm); } else { KASSERT(PMC_TO_MODE(pm) == PMC_MODE_TC, @@ -1303,6 +1311,15 @@ pmc_process_csw_in(struct thread *td) PMCDBG3(CSW,SWI,1,"cpu=%d ri=%d new=%jd", cpu, ri, newvalue); pcd->pcd_write_pmc(cpu, adjri, newvalue); + + /* If a sampling mode PMC, reset stalled state. */ + if (PMC_TO_MODE(pm) == PMC_MODE_TS) + CPU_CLR_ATOMIC(cpu, &pm->pm_stalled); + + /* Indicate that we desire this to run. */ + CPU_SET_ATOMIC(cpu, &pm->pm_cpustate); + + /* Start the PMC. */ pcd->pcd_start_pmc(cpu, adjri); } @@ -1397,8 +1414,14 @@ pmc_process_csw_out(struct thread *td) ("[pmc,%d] ri mismatch pmc(%d) ri(%d)", __LINE__, PMC_TO_ROWINDEX(pm), ri)); - /* Stop hardware if not already stopped */ - if (pm->pm_stalled == 0) + /* + * Change desired state, and then stop if not stalled. + * This two-step dance should avoid race conditions where + * an interrupt re-enables the PMC after this code has + * already checked the pm_stalled flag. + */ + CPU_CLR_ATOMIC(cpu, &pm->pm_cpustate); + if (!CPU_ISSET(cpu, &pm->pm_stalled)) pcd->pcd_stop_pmc(cpu, adjri); /* reduce this PMC's runcount */ @@ -1421,31 +1444,43 @@ pmc_process_csw_out(struct thread *td) pcd->pcd_read_pmc(cpu, adjri, &newvalue); - tmp = newvalue - PMC_PCPU_SAVED(cpu,ri); - - PMCDBG3(CSW,SWO,1,"cpu=%d ri=%d tmp=%jd", cpu, ri, - tmp); - if (mode == PMC_MODE_TS) { + PMCDBG3(CSW,SWO,1,"cpu=%d ri=%d tmp=%jd (samp)", + cpu, ri, PMC_PCPU_SAVED(cpu,ri) - newvalue); /* * For sampling process-virtual PMCs, - * we expect the count to be - * decreasing as the 'value' - * programmed into the PMC is the - * number of events to be seen till - * the next sampling interrupt. + * newvalue is the number of events to be seen + * until the next sampling interrupt. + * We can just add the events left from this + * invocation to the counter, then adjust + * in case we overflow our range. + * + * (Recall that we reload the counter every + * time we use it.) */ - if (tmp < 0) - tmp += pm->pm_sc.pm_reloadcount; mtx_pool_lock_spin(pmc_mtxpool, pm); - pp->pp_pmcs[ri].pp_pmcval -= tmp; - if ((int64_t) pp->pp_pmcs[ri].pp_pmcval <= 0) - pp->pp_pmcs[ri].pp_pmcval += + + pp->pp_pmcs[ri].pp_pmcval += newvalue; + if (pp->pp_pmcs[ri].pp_pmcval > + pm->pm_sc.pm_reloadcount) + pp->pp_pmcs[ri].pp_pmcval -= pm->pm_sc.pm_reloadcount; + KASSERT(pp->pp_pmcs[ri].pp_pmcval > 0 && + pp->pp_pmcs[ri].pp_pmcval <= + pm->pm_sc.pm_reloadcount, + ("[pmc,%d] pp_pmcval outside of expected " + "range cpu=%d ri=%d pp_pmcval=%jx " + "pm_reloadcount=%jx", __LINE__, cpu, ri, + pp->pp_pmcs[ri].pp_pmcval, + pm->pm_sc.pm_reloadcount)); mtx_pool_unlock_spin(pmc_mtxpool, pm); } else { + tmp = newvalue - PMC_PCPU_SAVED(cpu,ri); + + PMCDBG3(CSW,SWO,1,"cpu=%d ri=%d tmp=%jd (count)", + cpu, ri, tmp); /* * For counting process-virtual PMCs, @@ -2263,8 +2298,9 @@ pmc_release_pmc_descriptor(struct pmc *pm) pmc_select_cpu(cpu); /* switch off non-stalled CPUs */ + CPU_CLR_ATOMIC(cpu, &pm->pm_cpustate); if (pm->pm_state == PMC_STATE_RUNNING && - pm->pm_stalled == 0) { + !CPU_ISSET(cpu, &pm->pm_stalled)) { phw = pmc_pcpu[cpu]->pc_hwpmcs[ri]; @@ -2678,8 +2714,15 @@ pmc_start(struct pmc *pm) if ((error = pcd->pcd_write_pmc(cpu, adjri, PMC_IS_SAMPLING_MODE(mode) ? pm->pm_sc.pm_reloadcount : - pm->pm_sc.pm_initial)) == 0) + pm->pm_sc.pm_initial)) == 0) { + /* If a sampling mode PMC, reset stalled state. */ + if (PMC_IS_SAMPLING_MODE(mode)) + CPU_CLR_ATOMIC(cpu, &pm->pm_stalled); + + /* Indicate that we desire this to run. Start it. */ + CPU_SET_ATOMIC(cpu, &pm->pm_cpustate); error = pcd->pcd_start_pmc(cpu, adjri); + } critical_exit(); pmc_restore_cpu_binding(&pb); @@ -2741,6 +2784,7 @@ pmc_stop(struct pmc *pm) ri = PMC_TO_ROWINDEX(pm); pcd = pmc_ri_to_classdep(md, ri, &adjri); + CPU_CLR_ATOMIC(cpu, &pm->pm_cpustate); critical_enter(); if ((error = pcd->pcd_stop_pmc(cpu, adjri)) == 0) error = pcd->pcd_read_pmc(cpu, adjri, &pm->pm_sc.pm_initial); @@ -4049,12 +4093,13 @@ pmc_process_interrupt(int cpu, int ring, struct pmc *pm, struct trapframe *tf, ps = psb->ps_write; if (ps->ps_nsamples) { /* in use, reader hasn't caught up */ - pm->pm_stalled = 1; + CPU_SET_ATOMIC(cpu, &pm->pm_stalled); atomic_add_int(&pmc_stats.pm_intr_bufferfull, 1); PMCDBG6(SAM,INT,1,"(spc) cpu=%d pm=%p tf=%p um=%d wr=%d rd=%d", cpu, pm, (void *) tf, inuserspace, (int) (psb->ps_write - psb->ps_samples), (int) (psb->ps_read - psb->ps_samples)); + callchaindepth = 1; error = ENOMEM; goto done; } @@ -4112,7 +4157,8 @@ pmc_process_interrupt(int cpu, int ring, struct pmc *pm, struct trapframe *tf, done: /* mark CPU as needing processing */ - CPU_SET_ATOMIC(cpu, &pmc_cpumask); + if (callchaindepth != PMC_SAMPLE_INUSE) + CPU_SET_ATOMIC(cpu, &pmc_cpumask); return (error); } @@ -4126,10 +4172,9 @@ pmc_process_interrupt(int cpu, int ring, struct pmc *pm, struct trapframe *tf, static void pmc_capture_user_callchain(int cpu, int ring, struct trapframe *tf) { - int i; struct pmc *pm; struct thread *td; - struct pmc_sample *ps; + struct pmc_sample *ps, *ps_end; struct pmc_samplebuffer *psb; #ifdef INVARIANTS int ncallchains; @@ -4148,15 +4193,17 @@ pmc_capture_user_callchain(int cpu, int ring, struct trapframe *tf) /* * Iterate through all deferred callchain requests. + * Walk from the current read pointer to the current + * write pointer. */ - ps = psb->ps_samples; - for (i = 0; i < pmc_nsamples; i++, ps++) { - + ps = psb->ps_read; + ps_end = psb->ps_write; + do { if (ps->ps_nsamples != PMC_SAMPLE_INUSE) - continue; + goto next; if (ps->ps_td != td) - continue; + goto next; KASSERT(ps->ps_cpu == cpu, ("[pmc,%d] cpu mismatch ps_cpu=%d pcpu=%d", __LINE__, @@ -4181,7 +4228,12 @@ pmc_capture_user_callchain(int cpu, int ring, struct trapframe *tf) #ifdef INVARIANTS ncallchains++; #endif - } + +next: + /* increment the pointer, modulo sample ring size */ + if (++ps == psb->ps_fence) + ps = psb->ps_samples; + } while (ps != ps_end); KASSERT(ncallchains > 0, ("[pmc,%d] cpu %d didn't find a sample to collect", __LINE__, @@ -4191,6 +4243,9 @@ pmc_capture_user_callchain(int cpu, int ring, struct trapframe *tf) ("[pmc,%d] invalid td_pinned value", __LINE__)); sched_unpin(); /* Can migrate safely now. */ + /* mark CPU as needing processing */ + CPU_SET_ATOMIC(cpu, &pmc_cpumask); + return; } @@ -4304,10 +4359,11 @@ pmc_process_samples(int cpu, int ring) if (pm == NULL || /* !cfg'ed */ pm->pm_state != PMC_STATE_RUNNING || /* !active */ !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)) || /* !sampling */ - pm->pm_stalled == 0) /* !stalled */ + !CPU_ISSET(cpu, &pm->pm_cpustate) || /* !desired */ + !CPU_ISSET(cpu, &pm->pm_stalled)) /* !stalled */ continue; - pm->pm_stalled = 0; + CPU_CLR_ATOMIC(cpu, &pm->pm_stalled); (*pcd->pcd_start_pmc)(cpu, adjri); } } @@ -4426,23 +4482,31 @@ pmc_process_exit(void *arg __unused, struct proc *p) ("[pmc,%d] pm %p != pp_pmcs[%d] %p", __LINE__, pm, ri, pp->pp_pmcs[ri].pp_pmc)); - (void) pcd->pcd_stop_pmc(cpu, adjri); - KASSERT(pm->pm_runcount > 0, ("[pmc,%d] bad runcount ri %d rc %d", __LINE__, ri, pm->pm_runcount)); - /* Stop hardware only if it is actually running */ - if (pm->pm_state == PMC_STATE_RUNNING && - pm->pm_stalled == 0) { - pcd->pcd_read_pmc(cpu, adjri, &newvalue); - tmp = newvalue - - PMC_PCPU_SAVED(cpu,ri); - - mtx_pool_lock_spin(pmc_mtxpool, pm); - pm->pm_gv.pm_savedvalue += tmp; - pp->pp_pmcs[ri].pp_pmcval += tmp; - mtx_pool_unlock_spin(pmc_mtxpool, pm); + /* + * Change desired state, and then stop if not + * stalled. This two-step dance should avoid + * race conditions where an interrupt re-enables + * the PMC after this code has already checked + * the pm_stalled flag. + */ + if (CPU_ISSET(cpu, &pm->pm_cpustate)) { + CPU_CLR_ATOMIC(cpu, &pm->pm_cpustate); + if (!CPU_ISSET(cpu, &pm->pm_stalled)) { + (void) pcd->pcd_stop_pmc(cpu, adjri); + pcd->pcd_read_pmc(cpu, adjri, + &newvalue); + tmp = newvalue - + PMC_PCPU_SAVED(cpu,ri); + + mtx_pool_lock_spin(pmc_mtxpool, pm); + pm->pm_gv.pm_savedvalue += tmp; + pp->pp_pmcs[ri].pp_pmcval += tmp; + mtx_pool_unlock_spin(pmc_mtxpool, pm); + } } atomic_subtract_rel_int(&pm->pm_runcount,1); diff --git a/sys/dev/ixgbe/if_ix.c b/sys/dev/ixgbe/if_ix.c index a2e71e1..0bc3e16 100644 --- a/sys/dev/ixgbe/if_ix.c +++ b/sys/dev/ixgbe/if_ix.c @@ -163,6 +163,8 @@ static void ixgbe_add_device_sysctls(struct adapter *); static void ixgbe_add_hw_stats(struct adapter *); /* Sysctl handlers */ +static void ixgbe_set_sysctl_value(struct adapter *, const char *, + const char *, int *, int); static int ixgbe_set_flowcntl(SYSCTL_HANDLER_ARGS); static int ixgbe_set_advertise(SYSCTL_HANDLER_ARGS); static int ixgbe_sysctl_thermal_test(SYSCTL_HANDLER_ARGS); @@ -436,6 +438,15 @@ ixgbe_attach(device_t dev) goto err_out; } + /* Sysctls for limiting the amount of work done in the taskqueues */ + ixgbe_set_sysctl_value(adapter, "rx_processing_limit", + "max number of rx packets to process", + &adapter->rx_process_limit, ixgbe_rx_process_limit); + + ixgbe_set_sysctl_value(adapter, "tx_processing_limit", + "max number of tx packets to process", + &adapter->tx_process_limit, ixgbe_tx_process_limit); + /* Do descriptor calc and sanity checks */ if (((ixgbe_txd * sizeof(union ixgbe_adv_tx_desc)) % DBA_ALIGN) != 0 || ixgbe_txd < MIN_TXD || ixgbe_txd > MAX_TXD) { @@ -2678,9 +2689,6 @@ ixgbe_initialize_transmit_units(struct adapter *adapter) /* Cache the tail address */ txr->tail = IXGBE_TDT(txr->me); - /* Set the processing limit */ - txr->process_limit = ixgbe_tx_process_limit; - /* Disable Head Writeback */ switch (hw->mac.type) { case ixgbe_mac_82598EB: @@ -2890,9 +2898,6 @@ ixgbe_initialize_receive_units(struct adapter *adapter) IXGBE_WRITE_REG(hw, IXGBE_RDH(i), 0); IXGBE_WRITE_REG(hw, IXGBE_RDT(i), 0); - /* Set the processing limit */ - rxr->process_limit = ixgbe_rx_process_limit; - /* Set the driver rx tail address */ rxr->tail = IXGBE_RDT(rxr->me); } @@ -4202,6 +4207,16 @@ ixgbe_add_hw_stats(struct adapter *adapter) "1024-1522 byte frames transmitted"); } +static void +ixgbe_set_sysctl_value(struct adapter *adapter, const char *name, + const char *description, int *limit, int value) +{ + *limit = value; + SYSCTL_ADD_INT(device_get_sysctl_ctx(adapter->dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), + OID_AUTO, name, CTLFLAG_RW, limit, value, description); +} + /* ** Set flow control using sysctl: ** Flow control values: diff --git a/sys/dev/ixgbe/if_ixv.c b/sys/dev/ixgbe/if_ixv.c index fbcf948..0d0393c 100644 --- a/sys/dev/ixgbe/if_ixv.c +++ b/sys/dev/ixgbe/if_ixv.c @@ -115,6 +115,8 @@ static void ixv_save_stats(struct adapter *); static void ixv_init_stats(struct adapter *); static void ixv_update_stats(struct adapter *); static void ixv_add_stats_sysctls(struct adapter *); +static void ixv_set_sysctl_value(struct adapter *, const char *, + const char *, int *, int); /* The MSI/X Interrupt handlers */ static void ixv_msix_que(void *); @@ -301,6 +303,15 @@ ixv_attach(device_t dev) goto err_out; } + /* Sysctls for limiting the amount of work done in the taskqueues */ + ixv_set_sysctl_value(adapter, "rx_processing_limit", + "max number of rx packets to process", + &adapter->rx_process_limit, ixv_rx_process_limit); + + ixv_set_sysctl_value(adapter, "tx_processing_limit", + "max number of tx packets to process", + &adapter->tx_process_limit, ixv_tx_process_limit); + /* Do descriptor calc and sanity checks */ if (((ixv_txd * sizeof(union ixgbe_adv_tx_desc)) % DBA_ALIGN) != 0 || ixv_txd < MIN_TXD || ixv_txd > MAX_TXD) { @@ -1552,9 +1563,6 @@ ixv_initialize_transmit_units(struct adapter *adapter) /* Set Tx Tail register */ txr->tail = IXGBE_VFTDT(i); - /* Set the processing limit */ - txr->process_limit = ixv_tx_process_limit; - /* Set Ring parameters */ IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i), (tdba & 0x00000000ffffffffULL)); @@ -1634,8 +1642,6 @@ ixv_initialize_receive_units(struct adapter *adapter) IXGBE_WRITE_REG(hw, IXGBE_VFRDH(rxr->me), 0); IXGBE_WRITE_REG(hw, IXGBE_VFRDT(rxr->me), adapter->num_rx_desc - 1); - /* Set the processing limit */ - rxr->process_limit = ixv_rx_process_limit; /* Set Rx Tail register */ rxr->tail = IXGBE_VFRDT(rxr->me); @@ -2038,6 +2044,16 @@ ixv_add_stats_sysctls(struct adapter *adapter) "# of times not enough descriptors were available during TX"); } +static void +ixv_set_sysctl_value(struct adapter *adapter, const char *name, + const char *description, int *limit, int value) +{ + *limit = value; + SYSCTL_ADD_INT(device_get_sysctl_ctx(adapter->dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), + OID_AUTO, name, CTLFLAG_RW, limit, value, description); +} + /********************************************************************** * * This routine is called only when em_display_debug_stats is enabled. diff --git a/sys/dev/ixgbe/ix_txrx.c b/sys/dev/ixgbe/ix_txrx.c index 1c35b8e..0d4fd68 100644 --- a/sys/dev/ixgbe/ix_txrx.c +++ b/sys/dev/ixgbe/ix_txrx.c @@ -966,12 +966,12 @@ ixgbe_tso_setup(struct tx_ring *txr, struct mbuf *mp, void ixgbe_txeof(struct tx_ring *txr) { -#ifdef DEV_NETMAP struct adapter *adapter = txr->adapter; +#ifdef DEV_NETMAP struct ifnet *ifp = adapter->ifp; #endif u32 work, processed = 0; - u16 limit = txr->process_limit; + u32 limit = adapter->tx_process_limit; struct ixgbe_tx_buf *buf; union ixgbe_adv_tx_desc *txd; @@ -1728,7 +1728,7 @@ ixgbe_rxeof(struct ix_queue *que) struct lro_entry *queued; int i, nextp, processed = 0; u32 staterr = 0; - u16 count = rxr->process_limit; + u32 count = adapter->rx_process_limit; union ixgbe_adv_rx_desc *cur; struct ixgbe_rx_buf *rbuf, *nbuf; u16 pkt_info; diff --git a/sys/dev/ixgbe/ixgbe.h b/sys/dev/ixgbe/ixgbe.h index 6f220f9..df1da13 100644 --- a/sys/dev/ixgbe/ixgbe.h +++ b/sys/dev/ixgbe/ixgbe.h @@ -323,7 +323,6 @@ struct tx_ring { volatile u16 tx_avail; u16 next_avail_desc; u16 next_to_clean; - u16 process_limit; u16 num_desc; u32 txd_cmd; bus_dma_tag_t txtag; @@ -365,7 +364,6 @@ struct rx_ring { u16 next_to_check; u16 num_desc; u16 mbuf_sz; - u16 process_limit; char mtx_name[16]; struct ixgbe_rx_buf *rx_buffers; bus_dma_tag_t ptag; @@ -472,6 +470,7 @@ struct adapter { */ struct tx_ring *tx_rings; u32 num_tx_desc; + u32 tx_process_limit; /* * Receive rings: @@ -480,6 +479,7 @@ struct adapter { struct rx_ring *rx_rings; u64 active_queues; u32 num_rx_desc; + u32 rx_process_limit; /* Multicast array memory */ u8 *mta; diff --git a/sys/dev/sfxge/common/ef10_impl.h b/sys/dev/sfxge/common/ef10_impl.h new file mode 100644 index 0000000..9b9f0aa --- /dev/null +++ b/sys/dev/sfxge/common/ef10_impl.h @@ -0,0 +1,54 @@ +/*- + * Copyright (c) 2015 Solarflare Communications Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + * + * $FreeBSD$ + */ + +#ifndef _SYS_EF10_IMPL_H +#define _SYS_EF10_IMPL_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if (EFSYS_OPT_HUNTINGTON && EFSYS_OPT_MEDFORD) +#define EF10_MAX_PIOBUF_NBUFS MAX(HUNT_PIOBUF_NBUFS, MEDFORD_PIOBUF_NBUFS) +#elif EFSYS_OPT_HUNTINGTON +#define EF10_MAX_PIOBUF_NBUFS HUNT_PIOBUF_NBUFS +#elif EFSYS_OPT_MEDFORD +#define EF10_MAX_PIOBUF_NBUFS MEDFORD_PIOBUF_NBUFS +#endif + + + +#ifdef __cplusplus +} +#endif + +#endif /* _SYS_EF10_IMPL_H */ diff --git a/sys/dev/sfxge/common/ef10_tlv_layout.h b/sys/dev/sfxge/common/ef10_tlv_layout.h index e413a5d..4063165 100644 --- a/sys/dev/sfxge/common/ef10_tlv_layout.h +++ b/sys/dev/sfxge/common/ef10_tlv_layout.h @@ -194,7 +194,9 @@ struct tlv_port_mac { /* Static VPD. * * This is the portion of VPD which is set at manufacturing time and not - * expected to change. It is formatted as a standard PCI VPD block. + * expected to change. It is formatted as a standard PCI VPD block. There are + * global and per-pf TLVs for this, the global TLV is new for Medford and is + * used in preference to the per-pf TLV. */ #define TLV_TAG_PF_STATIC_VPD(pf) (0x00030000 + (pf)) @@ -205,11 +207,21 @@ struct tlv_pf_static_vpd { uint8_t bytes[]; }; +#define TLV_TAG_GLOBAL_STATIC_VPD (0x001f0000) + +struct tlv_global_static_vpd { + uint32_t tag; + uint32_t length; + uint8_t bytes[]; +}; + /* Dynamic VPD. * * This is the portion of VPD which may be changed (e.g. by firmware updates). - * It is formatted as a standard PCI VPD block. + * It is formatted as a standard PCI VPD block. There are global and per-pf TLVs + * for this, the global TLV is new for Medford and is used in preference to the + * per-pf TLV. */ #define TLV_TAG_PF_DYNAMIC_VPD(pf) (0x10030000 + (pf)) @@ -220,11 +232,21 @@ struct tlv_pf_dynamic_vpd { uint8_t bytes[]; }; +#define TLV_TAG_GLOBAL_DYNAMIC_VPD (0x10200000) + +struct tlv_global_dynamic_vpd { + uint32_t tag; + uint32_t length; + uint8_t bytes[]; +}; + /* "DBI" PCI config space changes. * * This is a set of edits made to the default PCI config space values before - * the device is allowed to enumerate. + * the device is allowed to enumerate. There are global and per-pf TLVs for + * this, the global TLV is new for Medford and is used in preference to the + * per-pf TLV. */ #define TLV_TAG_PF_DBI(pf) (0x00040000 + (pf)) @@ -240,6 +262,19 @@ struct tlv_pf_dbi { }; +#define TLV_TAG_GLOBAL_DBI (0x00210000) + +struct tlv_global_dbi { + uint32_t tag; + uint32_t length; + struct { + uint16_t addr; + uint16_t byte_enables; + uint32_t value; + } items[]; +}; + + /* Partition subtype codes. * * A subtype may optionally be stored for each type of partition present in @@ -289,7 +324,7 @@ struct tlv_pcie_config { int16_t max_pf_number; /**< Largest PF RID (lower PFs may be hidden) */ uint16_t pf_aper; /**< BIU aperture for PF BAR2 */ uint16_t vf_aper; /**< BIU aperture for VF BAR0 */ - uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */ + uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */ #define TLV_MAX_PF_DEFAULT (-1) /* Use FW default for largest PF RID */ #define TLV_APER_DEFAULT (0xFFFF) /* Use FW default for a given aperture */ }; @@ -305,13 +340,13 @@ struct tlv_per_pf_pcie_config { uint32_t tag; uint32_t length; uint8_t vfs_total; - uint8_t port_allocation; + uint8_t port_allocation; uint16_t vectors_per_pf; uint16_t vectors_per_vf; uint8_t pf_bar0_aperture; uint8_t pf_bar2_aperture; uint8_t vf_bar0_aperture; - uint8_t vf_base; + uint8_t vf_base; uint16_t supp_pagesz; uint16_t msix_vec_base; }; @@ -320,7 +355,8 @@ struct tlv_per_pf_pcie_config { /* Development ONLY. This is a single TLV tag for all the gubbins * that can be set through the MC command-line other than the PCIe * settings. This is a temporary measure. */ -#define TLV_TAG_TMP_GUBBINS (0x10090000) +#define TLV_TAG_TMP_GUBBINS (0x10090000) /* legacy symbol - do not use */ +#define TLV_TAG_TMP_GUBBINS_HUNT TLV_TAG_TMP_GUBBINS struct tlv_tmp_gubbins { uint32_t tag; @@ -330,7 +366,7 @@ struct tlv_tmp_gubbins { uint64_t tx1_tags; /* Bitmap */ uint64_t dl_tags; /* Bitmap */ uint32_t flags; -#define TLV_DPCPU_TX_STRIPE (1) /* TX striping is on */ +#define TLV_DPCPU_TX_STRIPE (1) /* No longer used, has no effect */ #define TLV_DPCPU_BIU_TAGS (2) /* Use BIU tag manager */ #define TLV_DPCPU_TX0_TAGS (4) /* tx0_tags is valid */ #define TLV_DPCPU_TX1_TAGS (8) /* tx1_tags is valid */ @@ -393,16 +429,16 @@ struct tlv_firmware_options { }; /* Voltage settings - * + * * Intended for boards with A0 silicon where the core voltage may - * need tweaking. Most likely set once when the pass voltage is + * need tweaking. Most likely set once when the pass voltage is * determined. */ #define TLV_TAG_0V9_SETTINGS (0x000c0000) struct tlv_0v9_settings { uint32_t tag; - uint32_t length; + uint32_t length; uint16_t flags; /* Boards with high 0v9 settings may need active cooling */ #define TLV_TAG_0V9_REQUIRES_FAN (1) uint16_t target_voltage; /* In millivolts */ @@ -411,17 +447,18 @@ struct tlv_0v9_settings { uint16_t warn_low; /* In millivolts */ uint16_t warn_high; /* In millivolts */ uint16_t panic_low; /* In millivolts */ - uint16_t panic_high; /* In millivolts */ + uint16_t panic_high; /* In millivolts */ }; /* Clock configuration */ -#define TLV_TAG_CLOCK_CONFIG (0x000d0000) +#define TLV_TAG_CLOCK_CONFIG (0x000d0000) /* legacy symbol - do not use */ +#define TLV_TAG_CLOCK_CONFIG_HUNT TLV_TAG_CLOCK_CONFIG struct tlv_clock_config { uint32_t tag; - uint32_t length; + uint32_t length; uint16_t clk_sys; /* MHz */ uint16_t clk_dpcpu; /* MHz */ uint16_t clk_icore; /* MHz */ @@ -460,7 +497,8 @@ struct tlv_global_mac { uint16_t reserved2; }; -#define TLV_TAG_ATB_0V9_TARGET (0x000f0000) +#define TLV_TAG_ATB_0V9_TARGET (0x000f0000) /* legacy symbol - do not use */ +#define TLV_TAG_ATB_0V9_TARGET_HUNT TLV_TAG_ATB_0V9_TARGET /* The target value for the 0v9 power rail measured on-chip at the * analogue test bus */ @@ -485,7 +523,7 @@ struct tlv_pcie_config_r2 { uint16_t visible_pfs; /**< Bitmap of visible PFs */ uint16_t pf_aper; /**< BIU aperture for PF BAR2 */ uint16_t vf_aper; /**< BIU aperture for VF BAR0 */ - uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */ + uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */ }; /* Dynamic port mode. @@ -688,4 +726,58 @@ struct tlv_ocsd { #define TLV_OCSD_ENABLED 1 /* Default */ }; +/* Descriptor cache config. + * + * Sets the sizes of the TX and RX descriptor caches as a power of 2. It also + * sets the total number of VIs. When the number of VIs is reduced VIs are taken + * away from the highest numbered port first, so a vi_count of 1024 means 1024 + * VIs on the first port and 0 on the second (on a Torino). + */ + +#define TLV_TAG_DESCRIPTOR_CACHE_CONFIG (0x101d0000) + +struct tlv_descriptor_cache_config { + uint32_t tag; + uint32_t length; + uint8_t rx_desc_cache_size; + uint8_t tx_desc_cache_size; + uint16_t vi_count; +}; +#define TLV_DESC_CACHE_DEFAULT (0xff) +#define TLV_VI_COUNT_DEFAULT (0xffff) + +/* RX event merging config (read batching). + * + * Sets the global maximum number of events for the merging bins, and the + * global timeout configuration for the bins. + */ + +#define TLV_TAG_RX_EVENT_MERGING_CONFIG (0x101e0000) + +struct tlv_rx_event_merging_config { + uint32_t tag; + uint32_t length; + uint32_t max_events; +#define TLV_RX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1) + uint32_t timeout_ns; +}; +#define TLV_RX_EVENT_MERGING_MAX_EVENTS_DEFAULT 7 +#define TLV_RX_EVENT_MERGING_TIMEOUT_NS_DEFAULT 8740 + +#define TLV_TAG_PCIE_LINK_SETTINGS (0x101f0000) +struct tlv_pcie_link_settings { + uint32_t tag; + uint32_t length; + uint16_t gen; /* Target PCIe generation: 1, 2, 3 */ + uint16_t width; /* Number of lanes */ +}; + +#define TLV_TAG_LICENSE (0x20800000) + +typedef struct tlv_license { + uint32_t tag; + uint32_t length; + uint8_t data[]; +} tlv_license_t; + #endif /* CI_MGMT_TLV_LAYOUT_H */ diff --git a/sys/dev/sfxge/common/efsys.h b/sys/dev/sfxge/common/efsys.h index bb03091..7bc1fe0 100644 --- a/sys/dev/sfxge/common/efsys.h +++ b/sys/dev/sfxge/common/efsys.h @@ -225,6 +225,7 @@ sfxge_map_mbuf_fast(bus_dma_tag_t tag, bus_dmamap_t map, #define __deref_out_bcount_opt(n) #define __checkReturn +#define __success(_x) #define __drv_when(_p, _c) @@ -237,6 +238,7 @@ sfxge_map_mbuf_fast(bus_dma_tag_t tag, bus_dmamap_t map, #define EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE 0 #define EFSYS_OPT_SIENA 1 #define EFSYS_OPT_HUNTINGTON 1 +#define EFSYS_OPT_MEDFORD 0 #ifdef DEBUG #define EFSYS_OPT_CHECK_REG 1 #else @@ -244,6 +246,8 @@ sfxge_map_mbuf_fast(bus_dma_tag_t tag, bus_dmamap_t map, #endif #define EFSYS_OPT_MCDI 1 +#define EFSYS_OPT_MCDI_LOGGING 0 +#define EFSYS_OPT_MCDI_PROXY_AUTH 0 #define EFSYS_OPT_MAC_FALCON_GMAC 0 #define EFSYS_OPT_MAC_FALCON_XMAC 0 @@ -283,9 +287,7 @@ sfxge_map_mbuf_fast(bus_dma_tag_t tag, bus_dmamap_t map, #define EFSYS_OPT_RX_SCALE 1 #define EFSYS_OPT_QSTATS 1 #define EFSYS_OPT_FILTER 1 -#define EFSYS_OPT_MCAST_FILTER_LIST 1 #define EFSYS_OPT_RX_SCATTER 0 -#define EFSYS_OPT_RX_HDR_SPLIT 0 #define EFSYS_OPT_EV_PREFETCH 0 diff --git a/sys/dev/sfxge/common/efx.h b/sys/dev/sfxge/common/efx.h index 3435951..0483c9a 100644 --- a/sys/dev/sfxge/common/efx.h +++ b/sys/dev/sfxge/common/efx.h @@ -40,27 +40,38 @@ extern "C" { #endif -#define EFX_STATIC_ASSERT(_cond) ((void)sizeof(char[(_cond) ? 1 : -1])) +#define EFX_STATIC_ASSERT(_cond) \ + ((void)sizeof(char[(_cond) ? 1 : -1])) -#define EFX_ARRAY_SIZE(_array) (sizeof(_array) / sizeof((_array)[0])) +#define EFX_ARRAY_SIZE(_array) \ + (sizeof(_array) / sizeof((_array)[0])) -#define EFX_FIELD_OFFSET(_type, _field) ((size_t) &(((_type *)0)->_field)) +#define EFX_FIELD_OFFSET(_type, _field) \ + ((size_t) &(((_type *)0)->_field)) + +/* Return codes */ + +typedef __success(return == 0) int efx_rc_t; + + +/* Chip families */ typedef enum efx_family_e { EFX_FAMILY_INVALID, EFX_FAMILY_FALCON, EFX_FAMILY_SIENA, EFX_FAMILY_HUNTINGTON, + EFX_FAMILY_MEDFORD, EFX_FAMILY_NTYPES } efx_family_t; -extern __checkReturn int +extern __checkReturn efx_rc_t efx_family( __in uint16_t venid, __in uint16_t devid, __out efx_family_t *efp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_infer_family( __in efsys_bar_t *esbp, __out efx_family_t *efp); @@ -75,13 +86,14 @@ efx_infer_family( #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */ -#define EFX_PCI_DEVID_HUNTINGTON 0x0913 /* SFL9122 PF */ #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */ #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */ -#define EFX_PCI_DEVID_HUNTINGTON_VF 0x1913 /* SFL9122 VF */ #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */ +#define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913 +#define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */ +#define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */ #define EFX_MEM_BAR 2 @@ -124,7 +136,7 @@ typedef struct efx_nic_s efx_nic_t; #define EFX_NIC_FUNC_TRUSTED 0x00000004 -extern __checkReturn int +extern __checkReturn efx_rc_t efx_nic_create( __in efx_family_t family, __in efsys_identifier_t *esip, @@ -132,34 +144,34 @@ efx_nic_create( __in efsys_lock_t *eslp, __deref_out efx_nic_t **enpp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_nic_probe( __in efx_nic_t *enp); #if EFSYS_OPT_PCIE_TUNE -extern __checkReturn int +extern __checkReturn efx_rc_t efx_nic_pcie_tune( __in efx_nic_t *enp, unsigned int nlanes); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_nic_pcie_extended_sync( __in efx_nic_t *enp); #endif /* EFSYS_OPT_PCIE_TUNE */ -extern __checkReturn int +extern __checkReturn efx_rc_t efx_nic_init( __in efx_nic_t *enp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_nic_reset( __in efx_nic_t *enp); #if EFSYS_OPT_DIAG -extern __checkReturn int +extern __checkReturn efx_rc_t efx_nic_register_test( __in efx_nic_t *enp); @@ -179,8 +191,8 @@ efx_nic_destroy( #if EFSYS_OPT_MCDI -#if EFSYS_OPT_HUNTINGTON -/* Huntington requires MCDIv2 commands */ +#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD +/* Huntington and Medford require MCDIv2 commands */ #define WITH_MCDI_V2 1 #endif @@ -191,20 +203,36 @@ typedef enum efx_mcdi_exception_e { EFX_MCDI_EXCEPTION_MC_BADASSERT, } efx_mcdi_exception_t; +#if EFSYS_OPT_MCDI_LOGGING +typedef enum efx_log_msg_e +{ + EFX_LOG_INVALID, + EFX_LOG_MCDI_REQUEST, + EFX_LOG_MCDI_RESPONSE, +} efx_log_msg_t; +#endif /* EFSYS_OPT_MCDI_LOGGING */ + typedef struct efx_mcdi_transport_s { void *emt_context; efsys_mem_t *emt_dma_mem; void (*emt_execute)(void *, efx_mcdi_req_t *); void (*emt_ev_cpl)(void *); void (*emt_exception)(void *, efx_mcdi_exception_t); +#if EFSYS_OPT_MCDI_LOGGING + void (*emt_logger)(void *, efx_log_msg_t, + void *, size_t, void *, size_t); +#endif /* EFSYS_OPT_MCDI_LOGGING */ +#if EFSYS_OPT_MCDI_PROXY_AUTH + void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t); +#endif /* EFSYS_OPT_MCDI_PROXY_AUTH */ } efx_mcdi_transport_t; -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mcdi_init( __in efx_nic_t *enp, __in const efx_mcdi_transport_t *mtp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mcdi_reboot( __in efx_nic_t *enp); @@ -246,7 +274,7 @@ typedef enum efx_intr_type_e { #define EFX_INTR_SIZE (sizeof (efx_oword_t)) -extern __checkReturn int +extern __checkReturn efx_rc_t efx_intr_init( __in efx_nic_t *enp, __in efx_intr_type_t type, @@ -266,7 +294,7 @@ efx_intr_disable_unlocked( #define EFX_INTR_NEVQS 32 -extern __checkReturn int +extern __checkReturn efx_rc_t efx_intr_trigger( __in efx_nic_t *enp, __in unsigned int level); @@ -418,17 +446,17 @@ typedef enum efx_link_mode_e { #define EFX_MAC_PDU_MIN 60 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX) -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mac_pdu_set( __in efx_nic_t *enp, __in size_t pdu); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mac_addr_set( __in efx_nic_t *enp, __in uint8_t *addr); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mac_filter_set( __in efx_nic_t *enp, __in boolean_t all_unicst, @@ -436,13 +464,13 @@ efx_mac_filter_set( __in boolean_t all_mulcst, __in boolean_t brdcst); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mac_multicast_list_set( __in efx_nic_t *enp, __in_ecount(6*count) uint8_t const *addrs, __in int count); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mac_filter_default_rxq_set( __in efx_nic_t *enp, __in efx_rxq_t *erp, @@ -452,12 +480,12 @@ extern void efx_mac_filter_default_rxq_clear( __in efx_nic_t *enp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mac_drain( __in efx_nic_t *enp, __in boolean_t enabled); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mac_up( __in efx_nic_t *enp, __out boolean_t *mac_upp); @@ -465,7 +493,7 @@ efx_mac_up( #define EFX_FCNTL_RESPOND 0x00000001 #define EFX_FCNTL_GENERATE 0x00000002 -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mac_fcntl_set( __in efx_nic_t *enp, __in unsigned int fcntl, @@ -477,38 +505,6 @@ efx_mac_fcntl_get( __out unsigned int *fcntl_wantedp, __out unsigned int *fcntl_linkp); -#define EFX_MAC_HASH_BITS (1 << 8) - -extern __checkReturn int -efx_pktfilter_init( - __in efx_nic_t *enp); - -extern void -efx_pktfilter_fini( - __in efx_nic_t *enp); - -extern __checkReturn int -efx_pktfilter_set( - __in efx_nic_t *enp, - __in boolean_t unicst, - __in boolean_t brdcst); - -extern __checkReturn int -efx_mac_hash_set( - __in efx_nic_t *enp, - __in_ecount(EFX_MAC_HASH_BITS) unsigned int const *bucket); - -#if EFSYS_OPT_MCAST_FILTER_LIST -extern __checkReturn int -efx_pktfilter_mcast_list_set( - __in efx_nic_t *enp, - __in uint8_t const *addrs, - __in int count); -#endif /* EFSYS_OPT_MCAST_FILTER_LIST */ - -extern __checkReturn int -efx_pktfilter_mcast_all( - __in efx_nic_t *enp); #if EFSYS_OPT_MAC_STATS @@ -536,24 +532,24 @@ efx_mac_stat_name( * Thus, drivers should zero this buffer before use, so that not-understood * statistics read back as zero. */ -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mac_stats_upload( __in efx_nic_t *enp, __in efsys_mem_t *esmp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mac_stats_periodic( __in efx_nic_t *enp, __in efsys_mem_t *esmp, __in uint16_t period_ms, __in boolean_t events); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mac_stats_update( __in efx_nic_t *enp, __in efsys_mem_t *esmp, __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, - __out_opt uint32_t *generationp); + __inout_opt uint32_t *generationp); #endif /* EFSYS_OPT_MAC_STATS */ @@ -566,6 +562,7 @@ typedef enum efx_mon_type_e { EFX_MON_MAX6647, EFX_MON_SFC90X0, EFX_MON_SFC91X0, + EFX_MON_SFC92X0, EFX_MON_NTYPES } efx_mon_type_t; @@ -577,7 +574,7 @@ efx_mon_name( #endif /* EFSYS_OPT_NAMES */ -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mon_init( __in efx_nic_t *enp); @@ -586,7 +583,7 @@ efx_mon_init( #define EFX_MON_STATS_PAGE_SIZE 0x100 #define EFX_MON_MASK_ELEMENT_SIZE 32 -/* START MKCONFIG GENERATED MonitorHeaderStatsBlock c79c86b62a144846 */ +/* START MKCONFIG GENERATED MonitorHeaderStatsBlock c09b13f732431f23 */ typedef enum efx_mon_stat_e { EFX_MON_STAT_2_5V, EFX_MON_STAT_VCCP1, @@ -657,6 +654,12 @@ typedef enum efx_mon_stat_e { EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP, EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC, EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC, + EFX_MON_STAT_SODIMM_VOUT, + EFX_MON_STAT_SODIMM_0_TEMP, + EFX_MON_STAT_SODIMM_1_TEMP, + EFX_MON_STAT_PHY0_VCC, + EFX_MON_STAT_PHY1_VCC, + EFX_MON_STAT_CONTROLLER_TDIODE_TEMP, EFX_MON_NSTATS } efx_mon_stat_t; @@ -684,11 +687,11 @@ efx_mon_stat_name( #endif /* EFSYS_OPT_NAMES */ -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mon_stats_update( __in efx_nic_t *enp, __in efsys_mem_t *esmp, - __out_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values); + __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values); #endif /* EFSYS_OPT_MON_STATS */ @@ -707,7 +710,7 @@ efx_mon_fini( #define MAXMMD ((1 << 5) - 1) -extern __checkReturn int +extern __checkReturn efx_rc_t efx_phy_verify( __in efx_nic_t *enp); @@ -721,14 +724,14 @@ typedef enum efx_phy_led_mode_e { EFX_PHY_LED_NMODES } efx_phy_led_mode_t; -extern __checkReturn int +extern __checkReturn efx_rc_t efx_phy_led_set( __in efx_nic_t *enp, __in efx_phy_led_mode_t mode); #endif /* EFSYS_OPT_PHY_LED_CONTROL */ -extern __checkReturn int +extern __checkReturn efx_rc_t efx_port_init( __in efx_nic_t *enp); @@ -786,7 +789,7 @@ efx_loopback_mask( __in efx_loopback_kind_t loopback_kind, __out efx_qword_t *maskp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_port_loopback_set( __in efx_nic_t *enp, __in efx_link_mode_t link_mode, @@ -803,7 +806,7 @@ efx_loopback_type_name( #endif /* EFSYS_OPT_LOOPBACK */ -extern __checkReturn int +extern __checkReturn efx_rc_t efx_port_poll( __in efx_nic_t *enp, __out_opt efx_link_mode_t *link_modep); @@ -839,7 +842,7 @@ efx_phy_adv_cap_get( __in uint32_t flag, __out uint32_t *maskp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_phy_adv_cap_set( __in efx_nic_t *enp, __in uint32_t mask); @@ -849,7 +852,7 @@ efx_phy_lp_cap_get( __in efx_nic_t *enp, __out uint32_t *maskp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_phy_oui_get( __in efx_nic_t *enp, __out uint32_t *ouip); @@ -942,11 +945,11 @@ efx_phy_stat_name( #define EFX_PHY_STATS_SIZE 0x100 -extern __checkReturn int +extern __checkReturn efx_rc_t efx_phy_stats_update( __in efx_nic_t *enp, __in efsys_mem_t *esmp, - __out_ecount(EFX_PHY_NSTATS) uint32_t *stat); + __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); #endif /* EFSYS_OPT_PHY_STATS */ @@ -963,14 +966,14 @@ efx_phy_prop_name( #define EFX_PHY_PROP_DEFAULT 0x00000001 -extern __checkReturn int +extern __checkReturn efx_rc_t efx_phy_prop_get( __in efx_nic_t *enp, __in unsigned int id, __in uint32_t flags, __out uint32_t *valp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_phy_prop_set( __in efx_nic_t *enp, __in unsigned int id, @@ -1030,16 +1033,16 @@ typedef enum efx_bist_value_e { EFX_BIST_NVALUES, } efx_bist_value_t; -extern __checkReturn int +extern __checkReturn efx_rc_t efx_bist_enable_offline( __in efx_nic_t *enp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_bist_start( __in efx_nic_t *enp, __in efx_bist_type_t type); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_bist_poll( __in efx_nic_t *enp, __in efx_bist_type_t type, @@ -1093,6 +1096,7 @@ typedef struct efx_nic_cfg_s { uint32_t enc_buftbl_limit; uint32_t enc_piobuf_limit; uint32_t enc_piobuf_size; + uint32_t enc_piobuf_min_alloc_size; uint32_t enc_evq_timer_quantum_ns; uint32_t enc_evq_timer_max_us; uint32_t enc_clk_mult; @@ -1120,20 +1124,20 @@ typedef struct efx_nic_cfg_s { uint32_t enc_mcdi_phy_stat_mask; #endif /* EFSYS_OPT_PHY_STATS */ #endif /* EFSYS_OPT_SIENA */ -#if (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) +#if (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) #if EFSYS_OPT_MON_STATS uint32_t *enc_mcdi_sensor_maskp; uint32_t enc_mcdi_sensor_mask_size; #endif /* EFSYS_OPT_MON_STATS */ -#endif /* (EFSYS_OPT_SIENA | EFSYS_OPT_HUNTINGTON) */ +#endif /* (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */ #if EFSYS_OPT_BIST uint32_t enc_bist_mask; #endif /* EFSYS_OPT_BIST */ -#if EFSYS_OPT_HUNTINGTON +#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD uint32_t enc_pf; uint32_t enc_vf; uint32_t enc_privilege_mask; -#endif /* EFSYS_OPT_HUNTINGTON */ +#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ boolean_t enc_bug26807_workaround; boolean_t enc_bug35388_workaround; boolean_t enc_bug41750_workaround; @@ -1151,8 +1155,11 @@ typedef struct efx_nic_cfg_s { boolean_t enc_hw_tx_insert_vlan_enabled; /* Datapath firmware vadapter/vport/vswitch support */ boolean_t enc_datapath_cap_evb; + boolean_t enc_rx_disable_scatter_supported; + boolean_t enc_allow_set_mac_with_installed_filters; /* External port identifier */ uint8_t enc_external_port; + uint32_t enc_mcdi_max_payload_length; } efx_nic_cfg_t; #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff) @@ -1184,7 +1191,7 @@ typedef struct efx_drv_limits_s uint32_t edl_max_pio_alloc_count; } efx_drv_limits_t; -extern __checkReturn int +extern __checkReturn efx_rc_t efx_nic_set_drv_limits( __inout efx_nic_t *enp, __in efx_drv_limits_t *edlp); @@ -1194,14 +1201,14 @@ typedef enum efx_nic_region_e { EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */ } efx_nic_region_t; -extern __checkReturn int +extern __checkReturn efx_rc_t efx_nic_get_bar_region( __in efx_nic_t *enp, __in efx_nic_region_t region, __out uint32_t *offsetp, __out size_t *sizep); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_nic_get_vi_pool( __in efx_nic_t *enp, __out uint32_t *evq_countp, @@ -1230,48 +1237,48 @@ typedef struct efx_vpd_value_s { #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8)) -extern __checkReturn int +extern __checkReturn efx_rc_t efx_vpd_init( __in efx_nic_t *enp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_vpd_size( __in efx_nic_t *enp, __out size_t *sizep); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_vpd_read( __in efx_nic_t *enp, __out_bcount(size) caddr_t data, __in size_t size); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_vpd_verify( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_vpd_reinit( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_vpd_get( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size, __inout efx_vpd_value_t *evvp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_vpd_set( __in efx_nic_t *enp, __inout_bcount(size) caddr_t data, __in size_t size, __in efx_vpd_value_t *evvp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_vpd_next( __in efx_nic_t *enp, __inout_bcount(size) caddr_t data, @@ -1279,7 +1286,7 @@ efx_vpd_next( __out efx_vpd_value_t *evvp, __inout unsigned int *contp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_vpd_write( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, @@ -1311,25 +1318,25 @@ typedef enum efx_nvram_type_e { EFX_NVRAM_NTYPES, } efx_nvram_type_t; -extern __checkReturn int +extern __checkReturn efx_rc_t efx_nvram_init( __in efx_nic_t *enp); #if EFSYS_OPT_DIAG -extern __checkReturn int +extern __checkReturn efx_rc_t efx_nvram_test( __in efx_nic_t *enp); #endif /* EFSYS_OPT_DIAG */ -extern __checkReturn int +extern __checkReturn efx_rc_t efx_nvram_size( __in efx_nic_t *enp, __in efx_nvram_type_t type, __out size_t *sizep); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_nvram_rw_start( __in efx_nic_t *enp, __in efx_nvram_type_t type, @@ -1340,14 +1347,14 @@ efx_nvram_rw_finish( __in efx_nic_t *enp, __in efx_nvram_type_t type); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_nvram_get_version( __in efx_nic_t *enp, __in efx_nvram_type_t type, __out uint32_t *subtypep, __out_ecount(4) uint16_t version[4]); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_nvram_read_chunk( __in efx_nic_t *enp, __in efx_nvram_type_t type, @@ -1355,26 +1362,26 @@ efx_nvram_read_chunk( __out_bcount(size) caddr_t data, __in size_t size); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_nvram_set_version( __in efx_nic_t *enp, __in efx_nvram_type_t type, __in_ecount(4) uint16_t version[4]); /* Validate contents of TLV formatted partition */ -extern __checkReturn int +extern __checkReturn efx_rc_t efx_nvram_tlv_validate( __in efx_nic_t *enp, __in uint32_t partn, __in_bcount(partn_size) caddr_t partn_data, __in size_t partn_size); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_nvram_erase( __in efx_nic_t *enp, __in efx_nvram_type_t type); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_nvram_write_chunk( __in efx_nic_t *enp, __in efx_nvram_type_t type, @@ -1390,13 +1397,13 @@ efx_nvram_fini( #if EFSYS_OPT_BOOTCFG -extern int +extern efx_rc_t efx_bootcfg_read( __in efx_nic_t *enp, __out_bcount(size) caddr_t data, __in size_t size); -extern int +extern efx_rc_t efx_bootcfg_write( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, @@ -1446,34 +1453,34 @@ typedef union efx_lightsout_offload_param_u { } elop_ns; } efx_lightsout_offload_param_t; -extern __checkReturn int +extern __checkReturn efx_rc_t efx_wol_init( __in efx_nic_t *enp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_wol_filter_clear( __in efx_nic_t *enp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_wol_filter_add( __in efx_nic_t *enp, __in efx_wol_type_t type, __in efx_wol_param_t *paramp, __out uint32_t *filter_idp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_wol_filter_remove( __in efx_nic_t *enp, __in uint32_t filter_id); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_lightsout_offload_add( __in efx_nic_t *enp, __in efx_lightsout_offload_type_t type, __in efx_lightsout_offload_param_t *paramp, __out uint32_t *filter_idp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_lightsout_offload_remove( __in efx_nic_t *enp, __in efx_lightsout_offload_type_t type, @@ -1503,14 +1510,14 @@ typedef void __in boolean_t negate, __out efx_qword_t *eqp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_sram_test( __in efx_nic_t *enp, __in efx_pattern_type_t type); #endif /* EFSYS_OPT_DIAG */ -extern __checkReturn int +extern __checkReturn efx_rc_t efx_sram_buf_tbl_set( __in efx_nic_t *enp, __in uint32_t id, @@ -1579,7 +1586,7 @@ typedef enum efx_ev_qstat_e { #endif /* EFSYS_OPT_QSTATS */ -extern __checkReturn int +extern __checkReturn efx_rc_t efx_ev_init( __in efx_nic_t *enp); @@ -1593,7 +1600,7 @@ efx_ev_fini( #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t)) #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE) -extern __checkReturn int +extern __checkReturn efx_rc_t efx_ev_qcreate( __in efx_nic_t *enp, __in unsigned int index, @@ -1768,12 +1775,12 @@ efx_ev_qpoll( __in const efx_ev_callbacks_t *eecp, __in_opt void *arg); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_ev_qmoderate( __in efx_evq_t *eep, __in unsigned int us); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_ev_qprime( __in efx_evq_t *eep, __in unsigned int count); @@ -1802,7 +1809,7 @@ efx_ev_qdestroy( /* RX */ -extern __checkReturn int +extern __checkReturn efx_rc_t efx_rx_init( __inout efx_nic_t *enp); @@ -1810,17 +1817,8 @@ extern void efx_rx_fini( __in efx_nic_t *enp); -#if EFSYS_OPT_RX_HDR_SPLIT - __checkReturn int -efx_rx_hdr_split_enable( - __in efx_nic_t *enp, - __in unsigned int hdr_buf_size, - __in unsigned int pld_buf_size); - -#endif /* EFSYS_OPT_RX_HDR_SPLIT */ - #if EFSYS_OPT_RX_SCATTER - __checkReturn int + __checkReturn efx_rc_t efx_rx_scatter_enable( __in efx_nic_t *enp, __in unsigned int buf_size); @@ -1855,37 +1853,37 @@ typedef enum efx_rx_scale_support_e { EFX_RX_SCALE_SHARED /* Read-only key/indirection table */ } efx_rx_scale_support_t; - extern __checkReturn int +extern __checkReturn efx_rc_t efx_rx_hash_support_get( __in efx_nic_t *enp, __out efx_rx_hash_support_t *supportp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_rx_scale_support_get( __in efx_nic_t *enp, __out efx_rx_scale_support_t *supportp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_rx_scale_mode_set( __in efx_nic_t *enp, __in efx_rx_hash_alg_t alg, __in efx_rx_hash_type_t type, __in boolean_t insert); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_rx_scale_tbl_set( __in efx_nic_t *enp, __in_ecount(n) unsigned int *table, __in size_t n); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_rx_scale_key_set( __in efx_nic_t *enp, __in_ecount(n) uint8_t *key, __in size_t n); -extern uint32_t +extern __checkReturn uint32_t efx_psuedo_hdr_hash_get( __in efx_nic_t *enp, __in efx_rx_hash_alg_t func, @@ -1893,7 +1891,7 @@ efx_psuedo_hdr_hash_get( #endif /* EFSYS_OPT_RX_SCALE */ -extern __checkReturn int +extern __checkReturn efx_rc_t efx_psuedo_hdr_pkt_length_get( __in efx_nic_t *enp, __in uint8_t *buffer, @@ -1909,13 +1907,11 @@ efx_psuedo_hdr_pkt_length_get( typedef enum efx_rxq_type_e { EFX_RXQ_TYPE_DEFAULT, - EFX_RXQ_TYPE_SPLIT_HEADER, - EFX_RXQ_TYPE_SPLIT_PAYLOAD, EFX_RXQ_TYPE_SCATTER, EFX_RXQ_NTYPES } efx_rxq_type_t; -extern __checkReturn int +extern __checkReturn efx_rc_t efx_rx_qcreate( __in efx_nic_t *enp, __in unsigned int index, @@ -1952,7 +1948,7 @@ efx_rx_qpush( __in unsigned int added, __inout unsigned int *pushedp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_rx_qflush( __in efx_rxq_t *erp); @@ -1981,7 +1977,7 @@ typedef enum efx_tx_qstat_e { #endif /* EFSYS_OPT_QSTATS */ -extern __checkReturn int +extern __checkReturn efx_rc_t efx_tx_init( __in efx_nic_t *enp); @@ -2004,7 +2000,10 @@ efx_tx_fini( #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */ -extern __checkReturn int +#define EFX_TXQ_CKSUM_IPV4 0x0001 +#define EFX_TXQ_CKSUM_TCPUDP 0x0002 + +extern __checkReturn efx_rc_t efx_tx_qcreate( __in efx_nic_t *enp, __in unsigned int index, @@ -2017,7 +2016,7 @@ efx_tx_qcreate( __deref_out efx_txq_t **etpp, __out unsigned int *addedp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_tx_qpost( __in efx_txq_t *etp, __in_ecount(n) efx_buffer_t *eb, @@ -2025,7 +2024,7 @@ efx_tx_qpost( __in unsigned int completed, __inout unsigned int *addedp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_tx_qpace( __in efx_txq_t *etp, __in unsigned int ns); @@ -2036,7 +2035,7 @@ efx_tx_qpush( __in unsigned int added, __in unsigned int pushed); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_tx_qflush( __in efx_txq_t *etp); @@ -2044,7 +2043,7 @@ extern void efx_tx_qenable( __in efx_txq_t *etp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_tx_qpio_enable( __in efx_txq_t *etp); @@ -2052,21 +2051,21 @@ extern void efx_tx_qpio_disable( __in efx_txq_t *etp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_tx_qpio_write( __in efx_txq_t *etp, __in_ecount(buf_length) uint8_t *buffer, __in size_t buf_length, __in size_t pio_buf_offset); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_tx_qpio_post( __in efx_txq_t *etp, __in size_t pkt_length, __in unsigned int completed, __inout unsigned int *addedp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_tx_qdesc_post( __in efx_txq_t *etp, __in_ecount(n) efx_desc_t *ed, @@ -2206,7 +2205,7 @@ typedef struct efx_filter_spec_s { #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff -extern __checkReturn int +extern __checkReturn efx_rc_t efx_filter_init( __in efx_nic_t *enp); @@ -2214,21 +2213,21 @@ extern void efx_filter_fini( __in efx_nic_t *enp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_filter_insert( __in efx_nic_t *enp, __inout efx_filter_spec_t *spec); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_filter_remove( __in efx_nic_t *enp, __inout efx_filter_spec_t *spec); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_filter_restore( __in efx_nic_t *enp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_filter_supported_filters( __in efx_nic_t *enp, __out uint32_t *list, @@ -2236,24 +2235,24 @@ efx_filter_supported_filters( extern void efx_filter_spec_init_rx( - __inout efx_filter_spec_t *spec, + __out efx_filter_spec_t *spec, __in efx_filter_priority_t priority, __in efx_filter_flag_t flags, __in efx_rxq_t *erp); extern void efx_filter_spec_init_tx( - __inout efx_filter_spec_t *spec, + __out efx_filter_spec_t *spec, __in efx_txq_t *etp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_filter_spec_set_ipv4_local( __inout efx_filter_spec_t *spec, __in uint8_t proto, __in uint32_t host, __in uint16_t port); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_filter_spec_set_ipv4_full( __inout efx_filter_spec_t *spec, __in uint8_t proto, @@ -2262,17 +2261,17 @@ efx_filter_spec_set_ipv4_full( __in uint32_t rhost, __in uint16_t rport); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_filter_spec_set_eth_local( __inout efx_filter_spec_t *spec, __in uint16_t vid, __in const uint8_t *addr); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_filter_spec_set_uc_def( __inout efx_filter_spec_t *spec); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_filter_spec_set_mc_def( __inout efx_filter_spec_t *spec); diff --git a/sys/dev/sfxge/common/efx_bootcfg.c b/sys/dev/sfxge/common/efx_bootcfg.c index 330f69d..16ee337 100644 --- a/sys/dev/sfxge/common/efx_bootcfg.c +++ b/sys/dev/sfxge/common/efx_bootcfg.c @@ -31,9 +31,7 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" -#include "efx_types.h" #include "efx_impl.h" #if EFSYS_OPT_BOOTCFG @@ -64,7 +62,7 @@ efx_bootcfg_csum( return (checksum); } -static __checkReturn int +static __checkReturn efx_rc_t efx_bootcfg_verify( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, @@ -73,7 +71,7 @@ efx_bootcfg_verify( { size_t offset = 0; size_t used = 0; - int rc; + efx_rc_t rc; /* Start parsing tags immediatly after the checksum */ for (offset = 1; offset < size; ) { @@ -125,12 +123,12 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - int + efx_rc_t efx_bootcfg_read( __in efx_nic_t *enp, __out_bcount(size) caddr_t data, @@ -139,7 +137,7 @@ efx_bootcfg_read( uint8_t *payload = NULL; size_t used_bytes; size_t sector_length; - int rc; + efx_rc_t rc; rc = efx_nvram_size(enp, EFX_NVRAM_BOOTROM_CFG, §or_length); if (rc != 0) @@ -238,12 +236,12 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - int + efx_rc_t efx_bootcfg_write( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, @@ -256,7 +254,7 @@ efx_bootcfg_write( size_t used_bytes; size_t offset; size_t remaining; - int rc; + efx_rc_t rc; rc = efx_nvram_size(enp, EFX_NVRAM_BOOTROM_CFG, §or_length); if (rc != 0) @@ -342,7 +340,7 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } diff --git a/sys/dev/sfxge/common/efx_check.h b/sys/dev/sfxge/common/efx_check.h index 9e590a4..199fab0 100644 --- a/sys/dev/sfxge/common/efx_check.h +++ b/sys/dev/sfxge/common/efx_check.h @@ -52,32 +52,32 @@ /* Verify chip implements accessed registers */ #if EFSYS_OPT_CHECK_REG -# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) -# error "CHECK_REG requires FALCON or SIENA or HUNTINGTON" +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || \ + EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) +# error "CHECK_REG requires FALCON or SIENA or HUNTINGTON or MEDFORD" # endif #endif /* EFSYS_OPT_CHECK_REG */ /* Decode fatal errors */ #if EFSYS_OPT_DECODE_INTR_FATAL # if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA) -# if EFSYS_OPT_HUNTINGTON -# error "INTR_FATAL not supported on HUNTINGTON" -# endif # error "INTR_FATAL requires FALCON or SIENA" # endif #endif /* EFSYS_OPT_DECODE_INTR_FATAL */ /* Support diagnostic hardware tests */ #if EFSYS_OPT_DIAG -# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) -# error "DIAG requires FALCON or SIENA or HUNTINGTON" +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || \ + EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) +# error "DIAG requires FALCON or SIENA or HUNTINGTON or MEDFORD" # endif #endif /* EFSYS_OPT_DIAG */ /* Support optimized EVQ data access */ #if EFSYS_OPT_EV_PREFETCH -# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) -# error "EV_PREFETCH requires FALCON or SIENA or HUNTINGTON" +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || \ + EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) +# error "EV_PREFETCH requires FALCON or SIENA or HUNTINGTON or MEDFORD" # endif #endif /* EFSYS_OPT_EV_PREFETCH */ @@ -90,21 +90,23 @@ /* Support hardware packet filters */ #if EFSYS_OPT_FILTER -# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) -# error "FILTER requires FALCON or SIENA or HUNTINGTON" +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || \ + EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) +# error "FILTER requires FALCON or SIENA or HUNTINGTON or MEDFORD" # endif #endif /* EFSYS_OPT_FILTER */ -#if EFSYS_OPT_HUNTINGTON +#if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) # if !EFSYS_OPT_FILTER -# error "HUNTINGTON requires FILTER" +# error "HUNTINGTON or MEDFORD requires FILTER" # endif #endif /* EFSYS_OPT_HUNTINGTON */ /* Support hardware loopback modes */ #if EFSYS_OPT_LOOPBACK -# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) -# error "LOOPBACK requires FALCON or SIENA or HUNTINGTON" +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || \ + EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) +# error "LOOPBACK requires FALCON or SIENA or HUNTINGTON or MEDFORD" # endif #endif /* EFSYS_OPT_LOOPBACK */ @@ -124,28 +126,39 @@ /* Support MAC statistics */ #if EFSYS_OPT_MAC_STATS -# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) -# error "MAC_STATS requires FALCON or SIENA or HUNTINGTON" +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || \ + EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) +# error "MAC_STATS requires FALCON or SIENA or HUNTINGTON or MEDFORD" # endif #endif /* EFSYS_OPT_MAC_STATS */ /* Support management controller messages */ #if EFSYS_OPT_MCDI -# if !(EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) -# if EFSYS_OPT_FALCON -# error "MCDI not supported on FALCON" -# endif -# error "MCDI requires SIENA or HUNTINGTON" +# if !(EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) +# error "MCDI requires SIENA or HUNTINGTON or MEDFORD" # endif #endif /* EFSYS_OPT_MCDI */ -#if EFSYS_OPT_SIENA && !EFSYS_OPT_MCDI -# error "SIENA requires MCDI" -#endif -#if EFSYS_OPT_HUNTINGTON && !EFSYS_OPT_MCDI -# error "HUNTINGTON requires MCDI" +#if (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) +# if !EFSYS_OPT_MCDI +# error "SIENA or HUNTINGTON or MEDFORD requires MCDI" +# endif #endif +/* Support MCDI logging */ +#if EFSYS_OPT_MCDI_LOGGING +# if !EFSYS_OPT_MCDI +# error "MCDI_LOGGING requires MCDI" +# endif +#endif /* EFSYS_OPT_MCDI_LOGGING */ + +/* Support MCDI proxy authorization */ +#if EFSYS_OPT_MCDI_PROXY_AUTH +# if !EFSYS_OPT_MCDI +# error "MCDI_PROXY_AUTH requires MCDI" +# endif +#endif /* EFSYS_OPT_MCDI_PROXY_AUTH */ + /* Support LM87 monitor */ #if EFSYS_OPT_MON_LM87 # if !EFSYS_OPT_FALCON @@ -167,27 +180,28 @@ # endif #endif /* EFSYS_OPT_MON_NULL */ -/* Support Siena monitor */ +/* Obsolete option */ #ifdef EFSYS_OPT_MON_SIENA -# error "MON_SIENA is obsolete use MON_MCDI" +# error "MON_SIENA is obsolete (replaced by MON_MCDI)." #endif /* EFSYS_OPT_MON_SIENA*/ -/* Support Huntington monitor */ +/* Obsolete option */ #ifdef EFSYS_OPT_MON_HUNTINGTON -# error "MON_HUNTINGTON is obsolete use MON_MCDI" +# error "MON_HUNTINGTON is obsolete (replaced by MON_MCDI)." #endif /* EFSYS_OPT_MON_HUNTINGTON*/ /* Support monitor statistics (voltage/temperature) */ #if EFSYS_OPT_MON_STATS -# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) -# error "MON_STATS requires FALCON or SIENA or HUNTINGTON" +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || \ + EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) +# error "MON_STATS requires FALCON or SIENA or HUNTINGTON or MEDFORD" # endif #endif /* EFSYS_OPT_MON_STATS */ /* Support Monitor via mcdi */ #if EFSYS_OPT_MON_MCDI -# if !(EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) -# error "MON_MCDI requires SIENA or HUNTINGTON" +# if !(EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) +# error "MON_MCDI requires SIENA or HUNTINGTON or MEDFORD" # endif #endif /* EFSYS_OPT_MON_MCDI*/ @@ -202,8 +216,9 @@ /* Support non volatile configuration */ #if EFSYS_OPT_NVRAM -# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) -# error "NVRAM requires FALCON or SIENA or HUNTINGTON" +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || \ + EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) +# error "NVRAM requires FALCON or SIENA or HUNTINGTON or MEDFORD" # endif #endif /* EFSYS_OPT_NVRAM */ @@ -244,9 +259,9 @@ # endif #endif /* EFSYS_OPT_PCIE_TUNE */ -/* Support PHY BIST diagnostics */ +/* Obsolete option */ #if EFSYS_OPT_PHY_BIST -# error "PHY_BIST is obsolete. It has been replaced by the BIST option." +# error "PHY_BIST is obsolete (replaced by BIST)." #endif /* EFSYS_OPT_PHY_BIST */ /* Support PHY flags */ @@ -326,41 +341,43 @@ /* Support EVQ/RXQ/TXQ statistics */ #if EFSYS_OPT_QSTATS -# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) -# error "QSTATS requires FALCON or SIENA or HUNTINGTON" +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || \ + EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) +# error "QSTATS requires FALCON or SIENA or HUNTINGTON or MEDFORD" # endif #endif /* EFSYS_OPT_QSTATS */ -/* Support receive header split */ -#if EFSYS_OPT_RX_HDR_SPLIT -# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) -# error "RX_HDR_SPLIT requires FALCON or SIENA or HUNTINGTON" -# endif +/* Obsolete option */ +#ifdef EFSYS_OPT_RX_HDR_SPLIT +# error "RX_HDR_SPLIT is obsolete and is not supported" #endif /* EFSYS_OPT_RX_HDR_SPLIT */ /* Support receive scaling (RSS) */ #if EFSYS_OPT_RX_SCALE -# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) -# error "RX_SCALE requires FALCON or SIENA or HUNTINGTON" +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || \ + EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) +# error "RX_SCALE requires FALCON or SIENA or HUNTINGTON or MEDFORD" # endif #endif /* EFSYS_OPT_RX_SCALE */ /* Support receive scatter DMA */ #if EFSYS_OPT_RX_SCATTER -# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) -# error "RX_SCATTER requires FALCON or SIENA or HUNTINGTON" +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || \ + EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) +# error "RX_SCATTER requires FALCON or SIENA or HUNTINGTON or MEDFORD" # endif #endif /* EFSYS_OPT_RX_SCATTER */ /* Obsolete option */ #ifdef EFSYS_OPT_STAT_NAME -# error "EFSYS_OPT_STAT_NAME is obsolete (replaced by EFSYS_OPT_NAMES)." +# error "STAT_NAME is obsolete (replaced by NAMES)." #endif /* Support PCI Vital Product Data (VPD) */ #if EFSYS_OPT_VPD -# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) -# error "VPD requires FALCON or SIENA or HUNTINGTON" +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || \ + EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) +# error "VPD requires FALCON or SIENA or HUNTINGTON or MEDFORD" # endif #endif /* EFSYS_OPT_VPD */ @@ -371,17 +388,16 @@ # endif #endif /* EFSYS_OPT_WOL */ -/* Support calculating multicast pktfilter in common code */ -#if EFSYS_OPT_MCAST_FILTER_LIST -# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) -# error "MCAST_FILTER_LIST requires FALCON or SIENA or HUNTINGTON" -# endif +/* Obsolete option */ +#ifdef EFSYS_OPT_MCAST_FILTER_LIST +# error "MCAST_FILTER_LIST is obsolete and is not supported" #endif /* EFSYS_OPT_MCAST_FILTER_LIST */ /* Support BIST */ #if EFSYS_OPT_BIST -# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON) -# error "BIST requires FALCON or SIENA or HUNTINGTON" +# if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA || \ + EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) +# error "BIST requires FALCON or SIENA or HUNTINGTON or MEDFORD" # endif #endif /* EFSYS_OPT_BIST */ diff --git a/sys/dev/sfxge/common/efx_crc32.c b/sys/dev/sfxge/common/efx_crc32.c index 7e4cfc4..23d77ae 100644 --- a/sys/dev/sfxge/common/efx_crc32.c +++ b/sys/dev/sfxge/common/efx_crc32.c @@ -31,9 +31,7 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" -#include "efx_types.h" #include "efx_impl.h" /* @@ -41,7 +39,7 @@ __FBSDID("$FreeBSD$"); * with polynomial 0x04c11db7 (bit-reversed 0xedb88320) */ -static const uint32_t crc32_table[256] = { +static const uint32_t efx_crc32_table[256] = { 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, @@ -120,7 +118,7 @@ efx_crc32_calculate( for (index = 0; index < length; index++) { uint32_t data = *(input++); - crc = (crc >> 8) ^ crc32_table[(crc ^ data) & 0xff]; + crc = (crc >> 8) ^ efx_crc32_table[(crc ^ data) & 0xff]; } return (crc); diff --git a/sys/dev/sfxge/common/efx_ev.c b/sys/dev/sfxge/common/efx_ev.c index 9669fc4..037dbfa 100644 --- a/sys/dev/sfxge/common/efx_ev.c +++ b/sys/dev/sfxge/common/efx_ev.c @@ -31,12 +31,11 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" -#include "efx_types.h" -#include "efx_regs.h" #include "efx_impl.h" +#if EFSYS_OPT_MON_MCDI #include "mcdi_mon.h" +#endif #if EFSYS_OPT_QSTATS #define EFX_EV_QSTAT_INCR(_eep, _stat) \ @@ -56,7 +55,7 @@ __FBSDID("$FreeBSD$"); #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_ev_init( __in efx_nic_t *enp); @@ -64,7 +63,7 @@ static void falconsiena_ev_fini( __in efx_nic_t *enp); -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_ev_qcreate( __in efx_nic_t *enp, __in unsigned int index, @@ -77,7 +76,7 @@ static void falconsiena_ev_qdestroy( __in efx_evq_t *eep); -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_ev_qprime( __in efx_evq_t *eep, __in unsigned int count); @@ -94,7 +93,7 @@ falconsiena_ev_qpost( __in efx_evq_t *eep, __in uint16_t data); -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_ev_qmoderate( __in efx_evq_t *eep, __in unsigned int us); @@ -139,28 +138,28 @@ static efx_ev_ops_t __efx_ev_siena_ops = { }; #endif /* EFSYS_OPT_SIENA */ -#if EFSYS_OPT_HUNTINGTON -static efx_ev_ops_t __efx_ev_hunt_ops = { - hunt_ev_init, /* eevo_init */ - hunt_ev_fini, /* eevo_fini */ - hunt_ev_qcreate, /* eevo_qcreate */ - hunt_ev_qdestroy, /* eevo_qdestroy */ - hunt_ev_qprime, /* eevo_qprime */ - hunt_ev_qpost, /* eevo_qpost */ - hunt_ev_qmoderate, /* eevo_qmoderate */ +#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD +static efx_ev_ops_t __efx_ev_ef10_ops = { + ef10_ev_init, /* eevo_init */ + ef10_ev_fini, /* eevo_fini */ + ef10_ev_qcreate, /* eevo_qcreate */ + ef10_ev_qdestroy, /* eevo_qdestroy */ + ef10_ev_qprime, /* eevo_qprime */ + ef10_ev_qpost, /* eevo_qpost */ + ef10_ev_qmoderate, /* eevo_qmoderate */ #if EFSYS_OPT_QSTATS - hunt_ev_qstats_update, /* eevo_qstats_update */ + ef10_ev_qstats_update, /* eevo_qstats_update */ #endif }; -#endif /* EFSYS_OPT_HUNTINGTON */ +#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ - __checkReturn int + __checkReturn efx_rc_t efx_ev_init( __in efx_nic_t *enp) { efx_ev_ops_t *eevop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); @@ -185,10 +184,16 @@ efx_ev_init( #if EFSYS_OPT_HUNTINGTON case EFX_FAMILY_HUNTINGTON: - eevop = (efx_ev_ops_t *)&__efx_ev_hunt_ops; + eevop = (efx_ev_ops_t *)&__efx_ev_ef10_ops; break; #endif /* EFSYS_OPT_HUNTINGTON */ +#if EFSYS_OPT_MEDFORD + case EFX_FAMILY_MEDFORD: + eevop = (efx_ev_ops_t *)&__efx_ev_ef10_ops; + break; +#endif /* EFSYS_OPT_MEDFORD */ + default: EFSYS_ASSERT(0); rc = ENOTSUP; @@ -208,7 +213,7 @@ fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); enp->en_eevop = NULL; enp->en_mod_flags &= ~EFX_MOD_EV; @@ -235,7 +240,7 @@ efx_ev_fini( } - __checkReturn int + __checkReturn efx_rc_t efx_ev_qcreate( __in efx_nic_t *enp, __in unsigned int index, @@ -247,7 +252,7 @@ efx_ev_qcreate( efx_ev_ops_t *eevop = enp->en_eevop; efx_nic_cfg_t *encp = &(enp->en_nic_cfg); efx_evq_t *eep; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV); @@ -279,7 +284,7 @@ fail2: EFSYS_PROBE(fail2); EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -301,14 +306,14 @@ efx_ev_qdestroy( EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep); } - __checkReturn int + __checkReturn efx_rc_t efx_ev_qprime( __in efx_evq_t *eep, __in unsigned int count) { efx_nic_t *enp = eep->ee_enp; efx_ev_ops_t *eevop = enp->en_eevop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); @@ -325,7 +330,7 @@ efx_ev_qprime( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -409,14 +414,14 @@ efx_ev_qpost( eevop->eevo_qpost(eep, data); } - __checkReturn int + __checkReturn efx_rc_t efx_ev_qmoderate( __in efx_evq_t *eep, __in unsigned int us) { efx_nic_t *enp = eep->ee_enp; efx_ev_ops_t *eevop = enp->en_eevop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC); @@ -426,7 +431,7 @@ efx_ev_qmoderate( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -448,7 +453,7 @@ efx_ev_qstats_update( #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_ev_init( __in efx_nic_t *enp) { @@ -492,7 +497,7 @@ falconsiena_ev_rx_not_ok( EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC); (*flagsp) |= EFX_DISCARD; -#if (EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER) +#if EFSYS_OPT_RX_SCATTER /* * Lookout for payload queue ran dry errors and ignore them. * @@ -507,7 +512,7 @@ falconsiena_ev_rx_not_ok( (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) && (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0)) ignore = B_TRUE; -#endif /* EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER */ +#endif /* EFSYS_OPT_RX_SCATTER */ } if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) { @@ -568,10 +573,10 @@ falconsiena_ev_rx( uint32_t size; uint32_t label; boolean_t ok; -#if (EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER) +#if EFSYS_OPT_RX_SCATTER boolean_t sop; boolean_t jumbo_cont; -#endif /* EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER */ +#endif /* EFSYS_OPT_RX_SCATTER */ uint32_t hdr_type; boolean_t is_v6; uint16_t flags; @@ -586,10 +591,10 @@ falconsiena_ev_rx( label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL); ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0); -#if (EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER) +#if EFSYS_OPT_RX_SCATTER sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0); jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0); -#endif /* EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER */ +#endif /* EFSYS_OPT_RX_SCATTER */ hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE); @@ -644,13 +649,13 @@ falconsiena_ev_rx( break; } -#if EFSYS_OPT_RX_SCATTER || EFSYS_OPT_RX_HDR_SPLIT +#if EFSYS_OPT_RX_SCATTER /* Report scatter and header/lookahead split buffer flags */ if (sop) flags |= EFX_PKT_START; if (jumbo_cont) flags |= EFX_PKT_CONT; -#endif /* EFSYS_OPT_RX_SCATTER || EFSYS_OPT_RX_HDR_SPLIT */ +#endif /* EFSYS_OPT_RX_SCATTER */ /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */ if (!ok) { @@ -990,7 +995,7 @@ falconsiena_ev_mcdi( #if EFSYS_OPT_MON_STATS efx_mon_stat_t id; efx_mon_stat_value_t value; - int rc; + efx_rc_t rc; if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0) should_abort = eecp->eec_monitor(arg, id, value); @@ -1047,7 +1052,7 @@ out: #endif /* EFSYS_OPT_MCDI */ -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_ev_qprime( __in efx_evq_t *eep, __in unsigned int count) @@ -1220,7 +1225,7 @@ falconsiena_ev_qpost( EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword); } -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_ev_qmoderate( __in efx_evq_t *eep, __in unsigned int us) @@ -1229,7 +1234,7 @@ falconsiena_ev_qmoderate( efx_nic_cfg_t *encp = &(enp->en_nic_cfg); unsigned int locked; efx_dword_t dword; - int rc; + efx_rc_t rc; if (us > encp->enc_evq_timer_max_us) { rc = EINVAL; @@ -1274,12 +1279,12 @@ falconsiena_ev_qmoderate( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_ev_qcreate( __in efx_nic_t *enp, __in unsigned int index, @@ -1291,7 +1296,7 @@ falconsiena_ev_qcreate( efx_nic_cfg_t *encp = &(enp->en_nic_cfg); uint32_t size; efx_oword_t oword; - int rc; + efx_rc_t rc; EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS)); EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS)); @@ -1352,7 +1357,7 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } diff --git a/sys/dev/sfxge/common/efx_filter.c b/sys/dev/sfxge/common/efx_filter.c index 7ae7ea5..a4b59cc 100644 --- a/sys/dev/sfxge/common/efx_filter.c +++ b/sys/dev/sfxge/common/efx_filter.c @@ -31,10 +31,7 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" -#include "efx_types.h" -#include "efx_regs.h" #include "efx_impl.h" @@ -42,7 +39,7 @@ __FBSDID("$FreeBSD$"); #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_filter_init( __in efx_nic_t *enp); @@ -50,22 +47,22 @@ static void falconsiena_filter_fini( __in efx_nic_t *enp); -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_filter_restore( __in efx_nic_t *enp); -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_filter_add( __in efx_nic_t *enp, __inout efx_filter_spec_t *spec, __in boolean_t may_replace); -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_filter_delete( __in efx_nic_t *enp, __inout efx_filter_spec_t *spec); -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_filter_supported_filters( __in efx_nic_t *enp, __out uint32_t *list, @@ -97,19 +94,19 @@ static efx_filter_ops_t __efx_filter_siena_ops = { }; #endif /* EFSYS_OPT_SIENA */ -#if EFSYS_OPT_HUNTINGTON -static efx_filter_ops_t __efx_filter_hunt_ops = { - hunt_filter_init, /* efo_init */ - hunt_filter_fini, /* efo_fini */ - hunt_filter_restore, /* efo_restore */ - hunt_filter_add, /* efo_add */ - hunt_filter_delete, /* efo_delete */ - hunt_filter_supported_filters, /* efo_supported_filters */ - hunt_filter_reconfigure, /* efo_reconfigure */ +#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD +static efx_filter_ops_t __efx_filter_ef10_ops = { + ef10_filter_init, /* efo_init */ + ef10_filter_fini, /* efo_fini */ + ef10_filter_restore, /* efo_restore */ + ef10_filter_add, /* efo_add */ + ef10_filter_delete, /* efo_delete */ + ef10_filter_supported_filters, /* efo_supported_filters */ + ef10_filter_reconfigure, /* efo_reconfigure */ }; -#endif /* EFSYS_OPT_HUNTINGTON */ +#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ - __checkReturn int + __checkReturn efx_rc_t efx_filter_insert( __in efx_nic_t *enp, __inout efx_filter_spec_t *spec) @@ -123,7 +120,7 @@ efx_filter_insert( return (efop->efo_add(enp, spec, B_FALSE)); } - __checkReturn int + __checkReturn efx_rc_t efx_filter_remove( __in efx_nic_t *enp, __inout efx_filter_spec_t *spec) @@ -141,11 +138,11 @@ efx_filter_remove( return (efop->efo_delete(enp, spec)); } - __checkReturn int + __checkReturn efx_rc_t efx_filter_restore( __in efx_nic_t *enp) { - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER); @@ -155,17 +152,17 @@ efx_filter_restore( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_filter_init( __in efx_nic_t *enp) { efx_filter_ops_t *efop; - int rc; + efx_rc_t rc; /* Check that efx_filter_spec_t is 64 bytes. */ EFX_STATIC_ASSERT(sizeof (efx_filter_spec_t) == 64); @@ -189,10 +186,16 @@ efx_filter_init( #if EFSYS_OPT_HUNTINGTON case EFX_FAMILY_HUNTINGTON: - efop = (efx_filter_ops_t *)&__efx_filter_hunt_ops; + efop = (efx_filter_ops_t *)&__efx_filter_ef10_ops; break; #endif /* EFSYS_OPT_HUNTINGTON */ +#if EFSYS_OPT_MEDFORD + case EFX_FAMILY_MEDFORD: + efop = (efx_filter_ops_t *)&__efx_filter_ef10_ops; + break; +#endif /* EFSYS_OPT_MEDFORD */ + default: EFSYS_ASSERT(0); rc = ENOTSUP; @@ -209,7 +212,7 @@ efx_filter_init( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); enp->en_efop = NULL; enp->en_mod_flags &= ~EFX_MOD_FILTER; @@ -230,13 +233,13 @@ efx_filter_fini( enp->en_mod_flags &= ~EFX_MOD_FILTER; } - __checkReturn int + __checkReturn efx_rc_t efx_filter_supported_filters( __in efx_nic_t *enp, __out uint32_t *list, __out size_t *length) { - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); @@ -249,12 +252,12 @@ efx_filter_supported_filters( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_filter_reconfigure( __in efx_nic_t *enp, __in_ecount(6) uint8_t const *mac_addr, @@ -265,7 +268,7 @@ efx_filter_reconfigure( __in_ecount(6*count) uint8_t const *addrs, __in int count) { - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); @@ -282,14 +285,14 @@ efx_filter_reconfigure( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } void efx_filter_spec_init_rx( - __inout efx_filter_spec_t *spec, + __out efx_filter_spec_t *spec, __in efx_filter_priority_t priority, __in efx_filter_flag_t flags, __in efx_rxq_t *erp) @@ -308,7 +311,7 @@ efx_filter_spec_init_rx( void efx_filter_spec_init_tx( - __inout efx_filter_spec_t *spec, + __out efx_filter_spec_t *spec, __in efx_txq_t *etp) { EFSYS_ASSERT3P(spec, !=, NULL); @@ -324,7 +327,7 @@ efx_filter_spec_init_tx( /* * Specify IPv4 host, transport protocol and port in a filter specification */ -__checkReturn int +__checkReturn efx_rc_t efx_filter_spec_set_ipv4_local( __inout efx_filter_spec_t *spec, __in uint8_t proto, @@ -346,7 +349,7 @@ efx_filter_spec_set_ipv4_local( /* * Specify IPv4 hosts, transport protocol and ports in a filter specification */ -__checkReturn int +__checkReturn efx_rc_t efx_filter_spec_set_ipv4_full( __inout efx_filter_spec_t *spec, __in uint8_t proto, @@ -373,7 +376,7 @@ efx_filter_spec_set_ipv4_full( /* * Specify local Ethernet address and/or VID in filter specification */ -__checkReturn int +__checkReturn efx_rc_t efx_filter_spec_set_eth_local( __inout efx_filter_spec_t *spec, __in uint16_t vid, @@ -399,7 +402,7 @@ efx_filter_spec_set_eth_local( /* * Specify matching otherwise-unmatched unicast in a filter specification */ -__checkReturn int +__checkReturn efx_rc_t efx_filter_spec_set_uc_def( __inout efx_filter_spec_t *spec) { @@ -412,7 +415,7 @@ efx_filter_spec_set_uc_def( /* * Specify matching otherwise-unmatched multicast in a filter specification */ -__checkReturn int +__checkReturn efx_rc_t efx_filter_spec_set_mc_def( __inout efx_filter_spec_t *spec) { @@ -442,12 +445,12 @@ efx_filter_spec_set_mc_def( */ #define FILTER_CTL_SRCH_MAX 200 -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_filter_spec_from_gen_spec( __out falconsiena_filter_spec_t *fs_spec, __in efx_filter_spec_t *gen_spec) { - int rc; + efx_rc_t rc; boolean_t is_full = B_FALSE; if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) @@ -591,7 +594,7 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -909,14 +912,14 @@ falconsiena_filter_build( return (key); } -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_filter_push_entry( __inout efx_nic_t *enp, __in falconsiena_filter_type_t type, __in int index, __in efx_oword_t *eop) { - int rc; + efx_rc_t rc; switch (type) { case EFX_FS_FILTER_RX_TCP_FULL: @@ -986,7 +989,7 @@ falconsiena_filter_equal( return (B_TRUE); } -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_filter_search( __in falconsiena_filter_tbl_t *fsftp, __in falconsiena_filter_spec_t *spec, @@ -1069,14 +1072,14 @@ falconsiena_filter_tbl_clear( EFSYS_UNLOCK(enp->en_eslp, state); } -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_filter_init( __in efx_nic_t *enp) { falconsiena_filter_t *fsfp; falconsiena_filter_tbl_t *fsftp; int tbl_id; - int rc; + efx_rc_t rc; EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (falconsiena_filter_t), fsfp); @@ -1158,7 +1161,7 @@ fail2: falconsiena_filter_fini(enp); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -1202,7 +1205,7 @@ falconsiena_filter_fini( } /* Restore filter state after a reset */ -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_filter_restore( __in efx_nic_t *enp) { @@ -1213,7 +1216,7 @@ falconsiena_filter_restore( efx_oword_t filter; int filter_idx; int state; - int rc; + efx_rc_t rc; EFSYS_LOCK(enp->en_eslp, state); @@ -1245,20 +1248,20 @@ fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); EFSYS_UNLOCK(enp->en_eslp, state); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_filter_add( __in efx_nic_t *enp, __inout efx_filter_spec_t *spec, __in boolean_t may_replace) { - int rc; + efx_rc_t rc; falconsiena_filter_spec_t fs_spec; falconsiena_filter_t *fsfp = enp->en_filter.ef_falconsiena_filter; falconsiena_filter_tbl_id_t tbl_id; @@ -1331,21 +1334,20 @@ fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_filter_delete( __in efx_nic_t *enp, __inout efx_filter_spec_t *spec) { - int rc; + efx_rc_t rc; falconsiena_filter_spec_t fs_spec; falconsiena_filter_t *fsfp = enp->en_filter.ef_falconsiena_filter; falconsiena_filter_tbl_id_t tbl_id; falconsiena_filter_tbl_t *fsftp; - falconsiena_filter_spec_t *saved_spec; efx_oword_t filter; int filter_idx; unsigned int depth; @@ -1369,8 +1371,6 @@ falconsiena_filter_delete( if (rc != 0) goto fail2; - saved_spec = &fsftp->fsft_spec[filter_idx]; - falconsiena_filter_clear_entry(enp, fsftp, filter_idx); if (fsftp->fsft_used == 0) falconsiena_filter_reset_search_depth(fsfp, tbl_id); @@ -1383,13 +1383,13 @@ fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } #define MAX_SUPPORTED 4 -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_filter_supported_filters( __in efx_nic_t *enp, __out uint32_t *list, @@ -1397,7 +1397,7 @@ falconsiena_filter_supported_filters( { int index = 0; uint32_t rx_matches[MAX_SUPPORTED]; - int rc; + efx_rc_t rc; if (list == NULL) { rc = EINVAL; diff --git a/sys/dev/sfxge/common/efx_hash.c b/sys/dev/sfxge/common/efx_hash.c index 3005c1b..db8b12c 100644 --- a/sys/dev/sfxge/common/efx_hash.c +++ b/sys/dev/sfxge/common/efx_hash.c @@ -42,9 +42,7 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" -#include "efx_types.h" #include "efx_impl.h" /* Hash initial value */ diff --git a/sys/dev/sfxge/common/efx_impl.h b/sys/dev/sfxge/common/efx_impl.h index 6f72d5f..5397ffe 100644 --- a/sys/dev/sfxge/common/efx_impl.h +++ b/sys/dev/sfxge/common/efx_impl.h @@ -58,6 +58,14 @@ #include "hunt_impl.h" #endif /* EFSYS_OPT_HUNTINGTON */ +#if EFSYS_OPT_MEDFORD +#include "medford_impl.h" +#endif /* EFSYS_OPT_MEDFORD */ + +#if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) +#include "ef10_impl.h" +#endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */ + #ifdef __cplusplus extern "C" { #endif @@ -92,44 +100,44 @@ typedef enum efx_mac_type_e { } efx_mac_type_t; typedef struct efx_ev_ops_s { - int (*eevo_init)(efx_nic_t *); + efx_rc_t (*eevo_init)(efx_nic_t *); void (*eevo_fini)(efx_nic_t *); - int (*eevo_qcreate)(efx_nic_t *, unsigned int, + efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int, efsys_mem_t *, size_t, uint32_t, efx_evq_t *); void (*eevo_qdestroy)(efx_evq_t *); - int (*eevo_qprime)(efx_evq_t *, unsigned int); + efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int); void (*eevo_qpost)(efx_evq_t *, uint16_t); - int (*eevo_qmoderate)(efx_evq_t *, unsigned int); + efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int); #if EFSYS_OPT_QSTATS void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *); #endif } efx_ev_ops_t; typedef struct efx_tx_ops_s { - int (*etxo_init)(efx_nic_t *); + efx_rc_t (*etxo_init)(efx_nic_t *); void (*etxo_fini)(efx_nic_t *); - int (*etxo_qcreate)(efx_nic_t *, + efx_rc_t (*etxo_qcreate)(efx_nic_t *, unsigned int, unsigned int, efsys_mem_t *, size_t, uint32_t, uint16_t, efx_evq_t *, efx_txq_t *, unsigned int *); void (*etxo_qdestroy)(efx_txq_t *); - int (*etxo_qpost)(efx_txq_t *, efx_buffer_t *, + efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *, unsigned int, unsigned int, unsigned int *); void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int); - int (*etxo_qpace)(efx_txq_t *, unsigned int); - int (*etxo_qflush)(efx_txq_t *); + efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int); + efx_rc_t (*etxo_qflush)(efx_txq_t *); void (*etxo_qenable)(efx_txq_t *); - int (*etxo_qpio_enable)(efx_txq_t *); + efx_rc_t (*etxo_qpio_enable)(efx_txq_t *); void (*etxo_qpio_disable)(efx_txq_t *); - int (*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t, + efx_rc_t (*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t, size_t); - int (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int, + efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int, unsigned int *); - int (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *, + efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *, unsigned int, unsigned int, unsigned int *); void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t, @@ -147,29 +155,29 @@ typedef struct efx_tx_ops_s { } efx_tx_ops_t; typedef struct efx_rx_ops_s { - int (*erxo_init)(efx_nic_t *); + efx_rc_t (*erxo_init)(efx_nic_t *); void (*erxo_fini)(efx_nic_t *); -#if EFSYS_OPT_RX_HDR_SPLIT - int (*erxo_hdr_split_enable)(efx_nic_t *, unsigned int, - unsigned int); -#endif #if EFSYS_OPT_RX_SCATTER - int (*erxo_scatter_enable)(efx_nic_t *, unsigned int); + efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int); #endif #if EFSYS_OPT_RX_SCALE - int (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t, + efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t, efx_rx_hash_type_t, boolean_t); - int (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t); - int (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *, + efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t); + efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *, size_t); -#endif + uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t, + uint8_t *); +#endif /* EFSYS_OPT_RX_SCALE */ + efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *, + uint16_t *); void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t, unsigned int, unsigned int, unsigned int); void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *); - int (*erxo_qflush)(efx_rxq_t *); + efx_rc_t (*erxo_qflush)(efx_rxq_t *); void (*erxo_qenable)(efx_rxq_t *); - int (*erxo_qcreate)(efx_nic_t *enp, unsigned int, + efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int, unsigned int, efx_rxq_type_t, efsys_mem_t *, size_t, uint32_t, efx_evq_t *, efx_rxq_t *); @@ -177,54 +185,54 @@ typedef struct efx_rx_ops_s { } efx_rx_ops_t; typedef struct efx_mac_ops_s { - int (*emo_reset)(efx_nic_t *); /* optional */ - int (*emo_poll)(efx_nic_t *, efx_link_mode_t *); - int (*emo_up)(efx_nic_t *, boolean_t *); - int (*emo_addr_set)(efx_nic_t *); - int (*emo_reconfigure)(efx_nic_t *); - int (*emo_multicast_list_set)(efx_nic_t *); - int (*emo_filter_default_rxq_set)(efx_nic_t *, + efx_rc_t (*emo_reset)(efx_nic_t *); /* optional */ + efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *); + efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *); + efx_rc_t (*emo_addr_set)(efx_nic_t *); + efx_rc_t (*emo_reconfigure)(efx_nic_t *); + efx_rc_t (*emo_multicast_list_set)(efx_nic_t *); + efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *, efx_rxq_t *, boolean_t); void (*emo_filter_default_rxq_clear)(efx_nic_t *); #if EFSYS_OPT_LOOPBACK - int (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t, + efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t, efx_loopback_type_t); #endif /* EFSYS_OPT_LOOPBACK */ #if EFSYS_OPT_MAC_STATS - int (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *); - int (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *, + efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *); + efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *, uint16_t, boolean_t); - int (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, + efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, efsys_stat_t *, uint32_t *); #endif /* EFSYS_OPT_MAC_STATS */ } efx_mac_ops_t; typedef struct efx_phy_ops_s { - int (*epo_power)(efx_nic_t *, boolean_t); /* optional */ - int (*epo_reset)(efx_nic_t *); - int (*epo_reconfigure)(efx_nic_t *); - int (*epo_verify)(efx_nic_t *); - int (*epo_uplink_check)(efx_nic_t *, + efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */ + efx_rc_t (*epo_reset)(efx_nic_t *); + efx_rc_t (*epo_reconfigure)(efx_nic_t *); + efx_rc_t (*epo_verify)(efx_nic_t *); + efx_rc_t (*epo_uplink_check)(efx_nic_t *, boolean_t *); /* optional */ - int (*epo_downlink_check)(efx_nic_t *, efx_link_mode_t *, + efx_rc_t (*epo_downlink_check)(efx_nic_t *, efx_link_mode_t *, unsigned int *, uint32_t *); - int (*epo_oui_get)(efx_nic_t *, uint32_t *); + efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *); #if EFSYS_OPT_PHY_STATS - int (*epo_stats_update)(efx_nic_t *, efsys_mem_t *, + efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *, uint32_t *); #endif /* EFSYS_OPT_PHY_STATS */ #if EFSYS_OPT_PHY_PROPS #if EFSYS_OPT_NAMES const char *(*epo_prop_name)(efx_nic_t *, unsigned int); #endif /* EFSYS_OPT_PHY_PROPS */ - int (*epo_prop_get)(efx_nic_t *, unsigned int, uint32_t, + efx_rc_t (*epo_prop_get)(efx_nic_t *, unsigned int, uint32_t, uint32_t *); - int (*epo_prop_set)(efx_nic_t *, unsigned int, uint32_t); + efx_rc_t (*epo_prop_set)(efx_nic_t *, unsigned int, uint32_t); #endif /* EFSYS_OPT_PHY_PROPS */ #if EFSYS_OPT_BIST - int (*epo_bist_enable_offline)(efx_nic_t *); - int (*epo_bist_start)(efx_nic_t *, efx_bist_type_t); - int (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t, + efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *); + efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t); + efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t, efx_bist_result_t *, uint32_t *, unsigned long *, size_t); void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t); @@ -233,19 +241,19 @@ typedef struct efx_phy_ops_s { #if EFSYS_OPT_FILTER typedef struct efx_filter_ops_s { - int (*efo_init)(efx_nic_t *); - void (*efo_fini)(efx_nic_t *); - int (*efo_restore)(efx_nic_t *); - int (*efo_add)(efx_nic_t *, efx_filter_spec_t *, - boolean_t may_replace); - int (*efo_delete)(efx_nic_t *, efx_filter_spec_t *); - int (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *); - int (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t, + efx_rc_t (*efo_init)(efx_nic_t *); + void (*efo_fini)(efx_nic_t *); + efx_rc_t (*efo_restore)(efx_nic_t *); + efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *, + boolean_t may_replace); + efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *); + efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *); + efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t, boolean_t, boolean_t, boolean_t, uint8_t const *, int); } efx_filter_ops_t; -extern __checkReturn int +extern __checkReturn efx_rc_t efx_filter_reconfigure( __in efx_nic_t *enp, __in_ecount(6) uint8_t const *mac_addr, @@ -258,15 +266,6 @@ efx_filter_reconfigure( #endif /* EFSYS_OPT_FILTER */ -typedef struct efx_pktfilter_ops_s { - int (*epfo_set)(efx_nic_t *, - boolean_t unicst, - boolean_t brdcast); -#if EFSYS_OPT_MCAST_FILTER_LIST - int (*epfo_mcast_list_set)(efx_nic_t *, uint8_t const *addrs, int count); -#endif /* EFSYS_OPT_MCAST_FILTER_LIST */ - int (*epfo_mcast_all)(efx_nic_t *); -} efx_pktfilter_ops_t; typedef struct efx_port_s { efx_mac_type_t ep_mac_type; @@ -324,11 +323,11 @@ typedef struct efx_port_s { } efx_port_t; typedef struct efx_mon_ops_s { - int (*emo_reset)(efx_nic_t *); - int (*emo_reconfigure)(efx_nic_t *); + efx_rc_t (*emo_reset)(efx_nic_t *); + efx_rc_t (*emo_reconfigure)(efx_nic_t *); #if EFSYS_OPT_MON_STATS - int (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, - efx_mon_stat_value_t *); + efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, + efx_mon_stat_value_t *); #endif /* EFSYS_OPT_MON_STATS */ } efx_mon_ops_t; @@ -338,11 +337,15 @@ typedef struct efx_mon_s { } efx_mon_t; typedef struct efx_intr_ops_s { - int (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *); + efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *); void (*eio_enable)(efx_nic_t *); void (*eio_disable)(efx_nic_t *); void (*eio_disable_unlocked)(efx_nic_t *); - int (*eio_trigger)(efx_nic_t *, unsigned int); + efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int); + void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *); + void (*eio_status_message)(efx_nic_t *, unsigned int, + boolean_t *); + void (*eio_fatal)(efx_nic_t *); void (*eio_fini)(efx_nic_t *); } efx_intr_ops_t; @@ -354,19 +357,19 @@ typedef struct efx_intr_s { } efx_intr_t; typedef struct efx_nic_ops_s { - int (*eno_probe)(efx_nic_t *); - int (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*); - int (*eno_reset)(efx_nic_t *); - int (*eno_init)(efx_nic_t *); - int (*eno_get_vi_pool)(efx_nic_t *, uint32_t *); - int (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t, + efx_rc_t (*eno_probe)(efx_nic_t *); + efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*); + efx_rc_t (*eno_reset)(efx_nic_t *); + efx_rc_t (*eno_init)(efx_nic_t *); + efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *); + efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t, uint32_t *, size_t *); #if EFSYS_OPT_DIAG - int (*eno_sram_test)(efx_nic_t *, efx_sram_pattern_fn_t); - int (*eno_register_test)(efx_nic_t *); + efx_rc_t (*eno_sram_test)(efx_nic_t *, efx_sram_pattern_fn_t); + efx_rc_t (*eno_register_test)(efx_nic_t *); #endif /* EFSYS_OPT_DIAG */ - void (*eno_fini)(efx_nic_t *); - void (*eno_unprobe)(efx_nic_t *); + void (*eno_fini)(efx_nic_t *); + void (*eno_unprobe)(efx_nic_t *); } efx_nic_ops_t; #ifndef EFX_TXQ_LIMIT_TARGET @@ -437,9 +440,9 @@ typedef struct efx_filter_s { #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA falconsiena_filter_t *ef_falconsiena_filter; #endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */ -#if EFSYS_OPT_HUNTINGTON - hunt_filter_table_t *ef_hunt_filter_table; -#endif /* EFSYS_OPT_HUNTINGTON */ +#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD + ef10_filter_table_t *ef_ef10_filter_table; +#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ } efx_filter_t; extern void @@ -452,15 +455,15 @@ falconsiena_filter_tbl_clear( #if EFSYS_OPT_MCDI typedef struct efx_mcdi_ops_s { - int (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *); + efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *); void (*emco_request_copyin)(efx_nic_t *, efx_mcdi_req_t *, unsigned int, boolean_t, boolean_t); - boolean_t (*emco_request_poll)(efx_nic_t *); void (*emco_request_copyout)(efx_nic_t *, efx_mcdi_req_t *); - int (*emco_poll_reboot)(efx_nic_t *); + efx_rc_t (*emco_poll_reboot)(efx_nic_t *); + boolean_t (*emco_poll_response)(efx_nic_t *); + void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t); void (*emco_fini)(efx_nic_t *); - int (*emco_fw_update_supported)(efx_nic_t *, boolean_t *); - int (*emco_macaddr_change_supported)(efx_nic_t *, boolean_t *); + efx_rc_t (*emco_feature_supported)(efx_nic_t *, efx_mcdi_feature_id_t, boolean_t *); } efx_mcdi_ops_t; typedef struct efx_mcdi_s { @@ -474,49 +477,54 @@ typedef struct efx_mcdi_s { #if EFSYS_OPT_NVRAM typedef struct efx_nvram_ops_s { #if EFSYS_OPT_DIAG - int (*envo_test)(efx_nic_t *); + efx_rc_t (*envo_test)(efx_nic_t *); #endif /* EFSYS_OPT_DIAG */ - int (*envo_size)(efx_nic_t *, efx_nvram_type_t, size_t *); - int (*envo_get_version)(efx_nic_t *, efx_nvram_type_t, - uint32_t *, uint16_t *); - int (*envo_rw_start)(efx_nic_t *, efx_nvram_type_t, size_t *); - int (*envo_read_chunk)(efx_nic_t *, efx_nvram_type_t, - unsigned int, caddr_t, size_t); - int (*envo_erase)(efx_nic_t *, efx_nvram_type_t); - int (*envo_write_chunk)(efx_nic_t *, efx_nvram_type_t, - unsigned int, caddr_t, size_t); - void (*envo_rw_finish)(efx_nic_t *, efx_nvram_type_t); - int (*envo_set_version)(efx_nic_t *, efx_nvram_type_t, uint16_t *); - + efx_rc_t (*envo_size)(efx_nic_t *, efx_nvram_type_t, size_t *); + efx_rc_t (*envo_get_version)(efx_nic_t *, efx_nvram_type_t, + uint32_t *, uint16_t *); + efx_rc_t (*envo_rw_start)(efx_nic_t *, efx_nvram_type_t, size_t *); + efx_rc_t (*envo_read_chunk)(efx_nic_t *, efx_nvram_type_t, + unsigned int, caddr_t, size_t); + efx_rc_t (*envo_erase)(efx_nic_t *, efx_nvram_type_t); + efx_rc_t (*envo_write_chunk)(efx_nic_t *, efx_nvram_type_t, + unsigned int, caddr_t, size_t); + void (*envo_rw_finish)(efx_nic_t *, efx_nvram_type_t); + efx_rc_t (*envo_set_version)(efx_nic_t *, efx_nvram_type_t, + uint16_t *); + + efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t, + uint32_t *); } efx_nvram_ops_t; #endif /* EFSYS_OPT_NVRAM */ #if EFSYS_OPT_VPD typedef struct efx_vpd_ops_s { - int (*evpdo_init)(efx_nic_t *); - int (*evpdo_size)(efx_nic_t *, size_t *); - int (*evpdo_read)(efx_nic_t *, caddr_t, size_t); - int (*evpdo_verify)(efx_nic_t *, caddr_t, size_t); - int (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t); - int (*evpdo_get)(efx_nic_t *, caddr_t, size_t, efx_vpd_value_t *); - int (*evpdo_set)(efx_nic_t *, caddr_t, size_t, efx_vpd_value_t *); - int (*evpdo_next)(efx_nic_t *, caddr_t, size_t, efx_vpd_value_t *, - unsigned int *); - int (*evpdo_write)(efx_nic_t *, caddr_t, size_t); - void (*evpdo_fini)(efx_nic_t *); + efx_rc_t (*evpdo_init)(efx_nic_t *); + efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *); + efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t); + efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t); + efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t); + efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t, + efx_vpd_value_t *); + efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t, + efx_vpd_value_t *); + efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t, + efx_vpd_value_t *, unsigned int *); + efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t); + void (*evpdo_fini)(efx_nic_t *); } efx_vpd_ops_t; #endif /* EFSYS_OPT_VPD */ #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_nvram_partitions( __in efx_nic_t *enp, __out_bcount(size) caddr_t data, __in size_t size, __out unsigned int *npartnp); - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_nvram_metadata( __in efx_nic_t *enp, __in uint32_t partn, @@ -525,20 +533,21 @@ efx_mcdi_nvram_metadata( __out_bcount_opt(size) char *descp, __in size_t size); - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_nvram_info( __in efx_nic_t *enp, __in uint32_t partn, __out_opt size_t *sizep, __out_opt uint32_t *addressp, - __out_opt uint32_t *erase_sizep); + __out_opt uint32_t *erase_sizep, + __out_opt uint32_t *write_sizep); - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_nvram_update_start( __in efx_nic_t *enp, __in uint32_t partn); - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_nvram_read( __in efx_nic_t *enp, __in uint32_t partn, @@ -546,14 +555,14 @@ efx_mcdi_nvram_read( __out_bcount(size) caddr_t data, __in size_t size); - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_nvram_erase( __in efx_nic_t *enp, __in uint32_t partn, __in uint32_t offset, __in size_t size); - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_nvram_write( __in efx_nic_t *enp, __in uint32_t partn, @@ -561,7 +570,7 @@ efx_mcdi_nvram_write( __out_bcount(size) caddr_t data, __in size_t size); - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_nvram_update_finish( __in efx_nic_t *enp, __in uint32_t partn, @@ -569,7 +578,7 @@ efx_mcdi_nvram_update_finish( #if EFSYS_OPT_DIAG - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_nvram_test( __in efx_nic_t *enp, __in uint32_t partn); @@ -611,7 +620,6 @@ struct efx_nic_s { efx_filter_t en_filter; efx_filter_ops_t *en_efop; #endif /* EFSYS_OPT_FILTER */ - efx_pktfilter_ops_t *en_epfop; #if EFSYS_OPT_MCDI efx_mcdi_t en_mcdi; #endif /* EFSYS_OPT_MCDI */ @@ -659,26 +667,30 @@ struct efx_nic_s { int enu_unused; } siena; #endif /* EFSYS_OPT_SIENA */ -#if EFSYS_OPT_HUNTINGTON + int enu_unused; + } en_u; +#if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) + union en_arch { struct { - int enu_vi_base; - int enu_vi_count; + int ena_vi_base; + int ena_vi_count; + int ena_vi_shift; #if EFSYS_OPT_VPD - caddr_t enu_svpd; - size_t enu_svpd_length; + caddr_t ena_svpd; + size_t ena_svpd_length; #endif /* EFSYS_OPT_VPD */ - efx_piobuf_handle_t enu_piobuf_handle[HUNT_PIOBUF_NBUFS]; - uint32_t enu_piobuf_count; - uint32_t enu_pio_alloc_map[HUNT_PIOBUF_NBUFS]; - uint32_t enu_pio_write_vi_base; + efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS]; + uint32_t ena_piobuf_count; + uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS]; + uint32_t ena_pio_write_vi_base; /* Memory BAR mapping regions */ - uint32_t enu_uc_mem_map_offset; - size_t enu_uc_mem_map_size; - uint32_t enu_wc_mem_map_offset; - size_t enu_wc_mem_map_size; - } hunt; -#endif /* EFSYS_OPT_HUNTINGTON */ - } en_u; + uint32_t ena_uc_mem_map_offset; + size_t ena_uc_mem_map_size; + uint32_t ena_wc_mem_map_offset; + size_t ena_wc_mem_map_size; + } ef10; + } en_arch; +#endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */ }; @@ -792,6 +804,10 @@ struct efx_txq_s { rev = 'D'; \ break; \ \ + case EFX_FAMILY_MEDFORD: \ + rev = 'E'; \ + break; \ + \ default: \ rev = '?'; \ break; \ @@ -1044,11 +1060,11 @@ struct efx_txq_s { _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) -extern __checkReturn int +extern __checkReturn efx_rc_t efx_nic_biu_test( __in efx_nic_t *enp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mac_select( __in efx_nic_t *enp); @@ -1059,7 +1075,7 @@ efx_mac_multicast_hash_compute( __out efx_oword_t *hash_low, __out efx_oword_t *hash_high); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_phy_probe( __in efx_nic_t *enp); @@ -1071,25 +1087,25 @@ efx_phy_unprobe( /* VPD utility functions */ -extern __checkReturn int +extern __checkReturn efx_rc_t efx_vpd_hunk_length( __in_bcount(size) caddr_t data, __in size_t size, __out size_t *lengthp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_vpd_hunk_verify( __in_bcount(size) caddr_t data, __in size_t size, __out_opt boolean_t *cksummedp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_vpd_hunk_reinit( __in_bcount(size) caddr_t data, __in size_t size, __in boolean_t wantpid); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_vpd_hunk_get( __in_bcount(size) caddr_t data, __in size_t size, @@ -1098,17 +1114,17 @@ efx_vpd_hunk_get( __out unsigned int *payloadp, __out uint8_t *paylenp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_vpd_hunk_next( __in_bcount(size) caddr_t data, __in size_t size, __out efx_vpd_tag_t *tagp, __out efx_vpd_keyword_t *keyword, - __out_bcount_opt(*paylenp) unsigned int *payloadp, + __out_opt unsigned int *payloadp, __out_opt uint8_t *paylenp, __inout unsigned int *contp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_vpd_hunk_set( __in_bcount(size) caddr_t data, __in size_t size, @@ -1127,13 +1143,13 @@ typedef struct efx_register_set_s { efx_oword_t mask; } efx_register_set_t; -extern __checkReturn int +extern __checkReturn efx_rc_t efx_nic_test_registers( __in efx_nic_t *enp, __in efx_register_set_t *rsp, __in size_t count); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_nic_test_tables( __in efx_nic_t *enp, __in efx_register_set_t *rsp, @@ -1144,14 +1160,14 @@ efx_nic_test_tables( #if EFSYS_OPT_MCDI -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mcdi_set_workaround( __in efx_nic_t *enp, __in uint32_t type, __in boolean_t enabled, __out_opt uint32_t *flagsp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mcdi_get_workarounds( __in efx_nic_t *enp, __out_opt uint32_t *implementedp, diff --git a/sys/dev/sfxge/common/efx_intr.c b/sys/dev/sfxge/common/efx_intr.c index d40f57f..eb570fc 100644 --- a/sys/dev/sfxge/common/efx_intr.c +++ b/sys/dev/sfxge/common/efx_intr.c @@ -31,16 +31,13 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" -#include "efx_types.h" -#include "efx_regs.h" #include "efx_impl.h" #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_intr_init( __in efx_nic_t *enp, __in efx_intr_type_t type, @@ -58,7 +55,7 @@ static void falconsiena_intr_disable_unlocked( __in efx_nic_t *enp); -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_intr_trigger( __in efx_nic_t *enp, __in unsigned int level); @@ -67,15 +64,27 @@ static void falconsiena_intr_fini( __in efx_nic_t *enp); +static void +falconsiena_intr_status_line( + __in efx_nic_t *enp, + __out boolean_t *fatalp, + __out uint32_t *qmaskp); -static __checkReturn boolean_t -falconsiena_intr_check_fatal( - __in efx_nic_t *enp); +static void +falconsiena_intr_status_message( + __in efx_nic_t *enp, + __in unsigned int message, + __out boolean_t *fatalp); static void falconsiena_intr_fatal( __in efx_nic_t *enp); +static __checkReturn boolean_t +falconsiena_intr_check_fatal( + __in efx_nic_t *enp); + + #endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */ @@ -86,6 +95,9 @@ static efx_intr_ops_t __efx_intr_falcon_ops = { falconsiena_intr_disable, /* eio_disable */ falconsiena_intr_disable_unlocked, /* eio_disable_unlocked */ falconsiena_intr_trigger, /* eio_trigger */ + falconsiena_intr_status_line, /* eio_status_line */ + falconsiena_intr_status_message, /* eio_status_message */ + falconsiena_intr_fatal, /* eio_fatal */ falconsiena_intr_fini, /* eio_fini */ }; #endif /* EFSYS_OPT_FALCON */ @@ -97,23 +109,28 @@ static efx_intr_ops_t __efx_intr_siena_ops = { falconsiena_intr_disable, /* eio_disable */ falconsiena_intr_disable_unlocked, /* eio_disable_unlocked */ falconsiena_intr_trigger, /* eio_trigger */ + falconsiena_intr_status_line, /* eio_status_line */ + falconsiena_intr_status_message, /* eio_status_message */ + falconsiena_intr_fatal, /* eio_fatal */ falconsiena_intr_fini, /* eio_fini */ }; #endif /* EFSYS_OPT_SIENA */ -#if EFSYS_OPT_HUNTINGTON -static efx_intr_ops_t __efx_intr_hunt_ops = { - hunt_intr_init, /* eio_init */ - hunt_intr_enable, /* eio_enable */ - hunt_intr_disable, /* eio_disable */ - hunt_intr_disable_unlocked, /* eio_disable_unlocked */ - hunt_intr_trigger, /* eio_trigger */ - hunt_intr_fini, /* eio_fini */ +#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD +static efx_intr_ops_t __efx_intr_ef10_ops = { + ef10_intr_init, /* eio_init */ + ef10_intr_enable, /* eio_enable */ + ef10_intr_disable, /* eio_disable */ + ef10_intr_disable_unlocked, /* eio_disable_unlocked */ + ef10_intr_trigger, /* eio_trigger */ + ef10_intr_status_line, /* eio_status_line */ + ef10_intr_status_message, /* eio_status_message */ + ef10_intr_fatal, /* eio_fatal */ + ef10_intr_fini, /* eio_fini */ }; -#endif /* EFSYS_OPT_HUNTINGTON */ +#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ - - __checkReturn int + __checkReturn efx_rc_t efx_intr_init( __in efx_nic_t *enp, __in efx_intr_type_t type, @@ -121,7 +138,7 @@ efx_intr_init( { efx_intr_t *eip = &(enp->en_intr); efx_intr_ops_t *eiop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); @@ -152,10 +169,16 @@ efx_intr_init( #if EFSYS_OPT_HUNTINGTON case EFX_FAMILY_HUNTINGTON: - eiop = (efx_intr_ops_t *)&__efx_intr_hunt_ops; + eiop = (efx_intr_ops_t *)&__efx_intr_ef10_ops; break; #endif /* EFSYS_OPT_HUNTINGTON */ +#if EFSYS_OPT_MEDFORD + case EFX_FAMILY_MEDFORD: + eiop = (efx_intr_ops_t *)&__efx_intr_ef10_ops; + break; +#endif /* EFSYS_OPT_MEDFORD */ + default: EFSYS_ASSERT(B_FALSE); rc = ENOTSUP; @@ -174,7 +197,7 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -235,7 +258,7 @@ efx_intr_disable_unlocked( } - __checkReturn int + __checkReturn efx_rc_t efx_intr_trigger( __in efx_nic_t *enp, __in unsigned int level) @@ -256,35 +279,12 @@ efx_intr_status_line( __out uint32_t *qmaskp) { efx_intr_t *eip = &(enp->en_intr); - efx_dword_t dword; + efx_intr_ops_t *eiop = eip->ei_eiop; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); - /* Ensure Huntington and Falcon/Siena ISR at same location */ - EFX_STATIC_ASSERT(FR_BZ_INT_ISR0_REG_OFST == - ER_DZ_BIU_INT_ISR_REG_OFST); - - /* - * Read the queue mask and implicitly acknowledge the - * interrupt. - */ - EFX_BAR_READD(enp, FR_BZ_INT_ISR0_REG, &dword, B_FALSE); - *qmaskp = EFX_DWORD_FIELD(dword, EFX_DWORD_0); - - EFSYS_PROBE1(qmask, uint32_t, *qmaskp); - -#if EFSYS_OPT_HUNTINGTON - if (enp->en_family == EFX_FAMILY_HUNTINGTON) { - /* Huntington reports fatal errors via events */ - *fatalp = B_FALSE; - return; - } -#endif - if (*qmaskp & (1U << eip->ei_level)) - *fatalp = falconsiena_intr_check_fatal(enp); - else - *fatalp = B_FALSE; + eiop->eio_status_line(enp, fatalp, qmaskp); } void @@ -294,39 +294,25 @@ efx_intr_status_message( __out boolean_t *fatalp) { efx_intr_t *eip = &(enp->en_intr); + efx_intr_ops_t *eiop = eip->ei_eiop; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); -#if EFSYS_OPT_HUNTINGTON - if (enp->en_family == EFX_FAMILY_HUNTINGTON) { - /* Huntington reports fatal errors via events */ - *fatalp = B_FALSE; - return; - } -#endif - if (message == eip->ei_level) - *fatalp = falconsiena_intr_check_fatal(enp); - else - *fatalp = B_FALSE; + eiop->eio_status_message(enp, message, fatalp); } void efx_intr_fatal( __in efx_nic_t *enp) { + efx_intr_t *eip = &(enp->en_intr); + efx_intr_ops_t *eiop = eip->ei_eiop; + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); -#if EFSYS_OPT_HUNTINGTON - if (enp->en_family == EFX_FAMILY_HUNTINGTON) { - /* Huntington reports fatal errors via events */ - return; - } -#endif -#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA - falconsiena_intr_fatal(enp); -#endif + eiop->eio_fatal(enp); } @@ -336,7 +322,7 @@ efx_intr_fatal( #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_intr_init( __in efx_nic_t *enp, __in efx_intr_type_t type, @@ -417,7 +403,7 @@ falconsiena_intr_disable_unlocked( &oword, B_FALSE); } -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_intr_trigger( __in efx_nic_t *enp, __in unsigned int level) @@ -426,7 +412,7 @@ falconsiena_intr_trigger( efx_oword_t oword; unsigned int count; uint32_t sel; - int rc; + efx_rc_t rc; /* bug16757: No event queues can be initialized */ EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV)); @@ -480,7 +466,7 @@ falconsiena_intr_trigger( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -509,6 +495,51 @@ falconsiena_intr_check_fatal( return (B_FALSE); } +static void +falconsiena_intr_status_line( + __in efx_nic_t *enp, + __out boolean_t *fatalp, + __out uint32_t *qmaskp) +{ + efx_intr_t *eip = &(enp->en_intr); + efx_dword_t dword; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); + + /* + * Read the queue mask and implicitly acknowledge the + * interrupt. + */ + EFX_BAR_READD(enp, FR_BZ_INT_ISR0_REG, &dword, B_FALSE); + *qmaskp = EFX_DWORD_FIELD(dword, EFX_DWORD_0); + + EFSYS_PROBE1(qmask, uint32_t, *qmaskp); + + if (*qmaskp & (1U << eip->ei_level)) + *fatalp = falconsiena_intr_check_fatal(enp); + else + *fatalp = B_FALSE; +} + +static void +falconsiena_intr_status_message( + __in efx_nic_t *enp, + __in unsigned int message, + __out boolean_t *fatalp) +{ + efx_intr_t *eip = &(enp->en_intr); + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); + + if (message == eip->ei_level) + *fatalp = falconsiena_intr_check_fatal(enp); + else + *fatalp = B_FALSE; +} + + static void falconsiena_intr_fatal( __in efx_nic_t *enp) diff --git a/sys/dev/sfxge/common/efx_mac.c b/sys/dev/sfxge/common/efx_mac.c index a701797..c8794a6 100644 --- a/sys/dev/sfxge/common/efx_mac.c +++ b/sys/dev/sfxge/common/efx_mac.c @@ -31,9 +31,7 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" -#include "efx_types.h" #include "efx_impl.h" #if EFSYS_OPT_MAC_FALCON_GMAC @@ -46,9 +44,9 @@ __FBSDID("$FreeBSD$"); #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_mac_multicast_list_set( - __in efx_nic_t *enp); + __in efx_nic_t *enp); #endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */ @@ -166,7 +164,7 @@ static efx_mac_ops_t *__efx_mac_ops[] = { #endif }; - __checkReturn int + __checkReturn efx_rc_t efx_mac_pdu_set( __in efx_nic_t *enp, __in size_t pdu) @@ -174,7 +172,7 @@ efx_mac_pdu_set( efx_port_t *epp = &(enp->en_port); efx_mac_ops_t *emop = epp->ep_emop; uint32_t old_pdu; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); @@ -205,12 +203,12 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_mac_addr_set( __in efx_nic_t *enp, __in uint8_t *addr) @@ -219,7 +217,7 @@ efx_mac_addr_set( efx_mac_ops_t *emop = epp->ep_emop; uint8_t old_addr[6]; uint32_t oui; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); @@ -250,12 +248,12 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_mac_filter_set( __in efx_nic_t *enp, __in boolean_t all_unicst, @@ -269,7 +267,7 @@ efx_mac_filter_set( boolean_t old_mulcst; boolean_t old_all_mulcst; boolean_t old_brdcst; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); @@ -290,7 +288,7 @@ efx_mac_filter_set( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); epp->ep_all_unicst = old_all_unicst; epp->ep_mulcst = old_mulcst; @@ -300,14 +298,14 @@ fail1: return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_mac_drain( __in efx_nic_t *enp, __in boolean_t enabled) { efx_port_t *epp = &(enp->en_port); efx_mac_ops_t *emop = epp->ep_emop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); @@ -334,19 +332,19 @@ efx_mac_drain( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_mac_up( __in efx_nic_t *enp, __out boolean_t *mac_upp) { efx_port_t *epp = &(enp->en_port); efx_mac_ops_t *emop = epp->ep_emop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); @@ -357,12 +355,12 @@ efx_mac_up( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_mac_fcntl_set( __in efx_nic_t *enp, __in unsigned int fcntl, @@ -374,7 +372,7 @@ efx_mac_fcntl_set( unsigned int old_fcntl; boolean_t old_autoneg; unsigned int old_adv_cap; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); @@ -432,7 +430,7 @@ fail2: epp->ep_adv_cap_mask = old_adv_cap; fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -462,56 +460,7 @@ efx_mac_fcntl_get( *fcntl_wantedp = wanted; } -/* - * FIXME: efx_mac_hash_set() should be deleted once all its callers have been - * updated to use efx_mac_multicast_list_set(). - * Then efx_port_t.ep_multicst_hash could be made Falcon/Siena specific as - * well. - */ - __checkReturn int -efx_mac_hash_set( - __in efx_nic_t *enp, - __in_ecount(EFX_MAC_HASH_BITS) unsigned int const *bucket) -{ - efx_port_t *epp = &(enp->en_port); - efx_mac_ops_t *emop = epp->ep_emop; - efx_oword_t old_hash[2]; - unsigned int index; - int rc; - - EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); - - memcpy(old_hash, epp->ep_multicst_hash, sizeof (old_hash)); - - /* Set the lower 128 bits of the hash */ - EFX_ZERO_OWORD(epp->ep_multicst_hash[0]); - for (index = 0; index < 128; index++) { - if (bucket[index] != 0) - EFX_SET_OWORD_BIT(epp->ep_multicst_hash[0], index); - } - - /* Set the upper 128 bits of the hash */ - EFX_ZERO_OWORD(epp->ep_multicst_hash[1]); - for (index = 0; index < 128; index++) { - if (bucket[index + 128] != 0) - EFX_SET_OWORD_BIT(epp->ep_multicst_hash[1], index); - } - - if ((rc = emop->emo_reconfigure(enp)) != 0) - goto fail1; - - return (0); - -fail1: - EFSYS_PROBE1(fail1, int, rc); - - memcpy(epp->ep_multicst_hash, old_hash, sizeof (old_hash)); - - return (rc); -} - - __checkReturn int + __checkReturn efx_rc_t efx_mac_multicast_list_set( __in efx_nic_t *enp, __in_ecount(6*count) uint8_t const *addrs, @@ -521,7 +470,7 @@ efx_mac_multicast_list_set( efx_mac_ops_t *emop = epp->ep_emop; uint8_t *old_mulcst_addr_list = NULL; uint32_t old_mulcst_addr_count; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); @@ -581,13 +530,13 @@ fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_mac_filter_default_rxq_set( __in efx_nic_t *enp, __in efx_rxq_t *erp, @@ -595,7 +544,7 @@ efx_mac_filter_default_rxq_set( { efx_port_t *epp = &(enp->en_port); efx_mac_ops_t *emop = epp->ep_emop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); @@ -609,7 +558,7 @@ efx_mac_filter_default_rxq_set( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -733,14 +682,14 @@ efx_mac_stat_name( #endif /* EFSYS_OPT_NAMES */ - __checkReturn int + __checkReturn efx_rc_t efx_mac_stats_upload( __in efx_nic_t *enp, __in efsys_mem_t *esmp) { efx_port_t *epp = &(enp->en_port); efx_mac_ops_t *emop = epp->ep_emop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); @@ -759,12 +708,12 @@ efx_mac_stats_upload( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_mac_stats_periodic( __in efx_nic_t *enp, __in efsys_mem_t *esmp, @@ -773,7 +722,7 @@ efx_mac_stats_periodic( { efx_port_t *epp = &(enp->en_port); efx_mac_ops_t *emop = epp->ep_emop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); @@ -793,22 +742,22 @@ efx_mac_stats_periodic( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_mac_stats_update( __in efx_nic_t *enp, __in efsys_mem_t *esmp, __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *essp, - __out_opt uint32_t *generationp) + __inout_opt uint32_t *generationp) { efx_port_t *epp = &(enp->en_port); efx_mac_ops_t *emop = epp->ep_emop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); @@ -823,7 +772,7 @@ efx_mac_stats_update( #endif /* EFSYS_OPT_MAC_STATS */ - __checkReturn int + __checkReturn efx_rc_t efx_mac_select( __in efx_nic_t *enp) { @@ -904,7 +853,7 @@ chosen: return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -912,6 +861,8 @@ fail1: #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA +#define EFX_MAC_HASH_BITS (1 << 8) + /* Compute the multicast hash as used on Falcon and Siena. */ static void falconsiena_mac_multicast_hash_compute( @@ -943,14 +894,14 @@ falconsiena_mac_multicast_hash_compute( } } -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_mac_multicast_list_set( - __in efx_nic_t *enp) + __in efx_nic_t *enp) { efx_port_t *epp = &(enp->en_port); efx_mac_ops_t *emop = epp->ep_emop; efx_oword_t old_hash[2]; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); @@ -968,7 +919,7 @@ falconsiena_mac_multicast_list_set( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); memcpy(epp->ep_multicst_hash, old_hash, sizeof (old_hash)); diff --git a/sys/dev/sfxge/common/efx_mcdi.c b/sys/dev/sfxge/common/efx_mcdi.c index e1c4b45..07224c7 100644 --- a/sys/dev/sfxge/common/efx_mcdi.c +++ b/sys/dev/sfxge/common/efx_mcdi.c @@ -31,11 +31,7 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" -#include "efx_types.h" -#include "efx_regs.h" -#include "efx_regs_mcdi.h" #include "efx_impl.h" #if EFSYS_OPT_MCDI @@ -46,42 +42,40 @@ __FBSDID("$FreeBSD$"); static efx_mcdi_ops_t __efx_mcdi_siena_ops = { siena_mcdi_init, /* emco_init */ siena_mcdi_request_copyin, /* emco_request_copyin */ - siena_mcdi_request_poll, /* emco_request_poll */ siena_mcdi_request_copyout, /* emco_request_copyout */ siena_mcdi_poll_reboot, /* emco_poll_reboot */ + siena_mcdi_poll_response, /* emco_poll_response */ + siena_mcdi_read_response, /* emco_read_response */ siena_mcdi_fini, /* emco_fini */ - siena_mcdi_fw_update_supported, /* emco_fw_update_supported */ - siena_mcdi_macaddr_change_supported, - /* emco_macaddr_change_supported */ + siena_mcdi_feature_supported, /* emco_feature_supported */ }; #endif /* EFSYS_OPT_SIENA */ -#if EFSYS_OPT_HUNTINGTON - -static efx_mcdi_ops_t __efx_mcdi_hunt_ops = { - hunt_mcdi_init, /* emco_init */ - hunt_mcdi_request_copyin, /* emco_request_copyin */ - hunt_mcdi_request_poll, /* emco_request_poll */ - hunt_mcdi_request_copyout, /* emco_request_copyout */ - hunt_mcdi_poll_reboot, /* emco_poll_reboot */ - hunt_mcdi_fini, /* emco_fini */ - hunt_mcdi_fw_update_supported, /* emco_fw_update_supported */ - hunt_mcdi_macaddr_change_supported, - /* emco_macaddr_change_supported */ +#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD + +static efx_mcdi_ops_t __efx_mcdi_ef10_ops = { + ef10_mcdi_init, /* emco_init */ + ef10_mcdi_request_copyin, /* emco_request_copyin */ + ef10_mcdi_request_copyout, /* emco_request_copyout */ + ef10_mcdi_poll_reboot, /* emco_poll_reboot */ + ef10_mcdi_poll_response, /* emco_poll_response */ + ef10_mcdi_read_response, /* emco_read_response */ + ef10_mcdi_fini, /* emco_fini */ + ef10_mcdi_feature_supported, /* emco_feature_supported */ }; -#endif /* EFSYS_OPT_HUNTINGTON */ +#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_init( __in efx_nic_t *enp, __in const efx_mcdi_transport_t *emtp) { efx_mcdi_ops_t *emcop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0); @@ -102,10 +96,16 @@ efx_mcdi_init( #if EFSYS_OPT_HUNTINGTON case EFX_FAMILY_HUNTINGTON: - emcop = (efx_mcdi_ops_t *)&__efx_mcdi_hunt_ops; + emcop = (efx_mcdi_ops_t *)&__efx_mcdi_ef10_ops; break; #endif /* EFSYS_OPT_HUNTINGTON */ +#if EFSYS_OPT_MEDFORD + case EFX_FAMILY_MEDFORD: + emcop = (efx_mcdi_ops_t *)&__efx_mcdi_ef10_ops; + break; +#endif /* EFSYS_OPT_MEDFORD */ + default: EFSYS_ASSERT(0); rc = ENOTSUP; @@ -136,7 +136,7 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); enp->en_mcdi.em_emcop = NULL; enp->en_mcdi.em_emtp = NULL; @@ -178,6 +178,62 @@ efx_mcdi_new_epoch( EFSYS_UNLOCK(enp->en_eslp, state); } +static void +efx_mcdi_request_copyin( + __in efx_nic_t *enp, + __in efx_mcdi_req_t *emrp, + __in unsigned int seq, + __in boolean_t ev_cpl, + __in boolean_t new_epoch) +{ + efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; + + emcop->emco_request_copyin(enp, emrp, seq, ev_cpl, new_epoch); +} + +static void +efx_mcdi_request_copyout( + __in efx_nic_t *enp, + __in efx_mcdi_req_t *emrp) +{ + efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; + + emcop->emco_request_copyout(enp, emrp); +} + +static efx_rc_t +efx_mcdi_poll_reboot( + __in efx_nic_t *enp) +{ + efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; + efx_rc_t rc; + + rc = emcop->emco_poll_reboot(enp); + return (rc); +} + +static boolean_t +efx_mcdi_poll_response( + __in efx_nic_t *enp) +{ + efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; + boolean_t available; + + available = emcop->emco_poll_response(enp); + return (available); +} + +static void +efx_mcdi_read_response( + __in efx_nic_t *enp, + __out void *bufferp, + __in size_t offset, + __in size_t length) +{ + efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; + + emcop->emco_read_response(enp, bufferp, offset, length); +} void efx_mcdi_request_start( @@ -186,7 +242,6 @@ efx_mcdi_request_start( __in boolean_t ev_cpl) { efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); - efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; unsigned int seq; boolean_t new_epoch; int state; @@ -195,9 +250,6 @@ efx_mcdi_request_start( EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI); EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI); - if (emcop == NULL || emcop->emco_request_copyin == NULL) - return; - /* * efx_mcdi_request_start() is naturally serialised against both * efx_mcdi_request_poll() and efx_mcdi_ev_cpl()/efx_mcdi_ev_death(), @@ -219,26 +271,194 @@ efx_mcdi_request_start( new_epoch = emip->emi_new_epoch; EFSYS_UNLOCK(enp->en_eslp, state); - emcop->emco_request_copyin(enp, emrp, seq, ev_cpl, new_epoch); + efx_mcdi_request_copyin(enp, emrp, seq, ev_cpl, new_epoch); +} + + + void +efx_mcdi_read_response_header( + __in efx_nic_t *enp, + __inout efx_mcdi_req_t *emrp) +{ +#if EFSYS_OPT_MCDI_LOGGING + const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp; +#endif /* EFSYS_OPT_MCDI_LOGGING */ + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); + efx_dword_t hdr[2]; + unsigned int hdr_len; + unsigned int data_len; + unsigned int seq; + unsigned int cmd; + unsigned int error; + efx_rc_t rc; + + EFSYS_ASSERT(emrp != NULL); + + efx_mcdi_read_response(enp, &hdr[0], 0, sizeof (hdr[0])); + hdr_len = sizeof (hdr[0]); + + cmd = EFX_DWORD_FIELD(hdr[0], MCDI_HEADER_CODE); + seq = EFX_DWORD_FIELD(hdr[0], MCDI_HEADER_SEQ); + error = EFX_DWORD_FIELD(hdr[0], MCDI_HEADER_ERROR); + + if (cmd != MC_CMD_V2_EXTN) { + data_len = EFX_DWORD_FIELD(hdr[0], MCDI_HEADER_DATALEN); + } else { + efx_mcdi_read_response(enp, &hdr[1], hdr_len, sizeof (hdr[1])); + hdr_len += sizeof (hdr[1]); + + cmd = EFX_DWORD_FIELD(hdr[1], MC_CMD_V2_EXTN_IN_EXTENDED_CMD); + data_len = + EFX_DWORD_FIELD(hdr[1], MC_CMD_V2_EXTN_IN_ACTUAL_LEN); + } + + if (error && (data_len == 0)) { + /* The MC has rebooted since the request was sent. */ + EFSYS_SPIN(EFX_MCDI_STATUS_SLEEP_US); + efx_mcdi_poll_reboot(enp); + rc = EIO; + goto fail1; + } + if ((cmd != emrp->emr_cmd) || + (seq != ((emip->emi_seq - 1) & EFX_MASK32(MCDI_HEADER_SEQ)))) { + /* Response is for a different request */ + rc = EIO; + goto fail2; + } + if (error) { + efx_dword_t err[2]; + unsigned int err_len = MIN(data_len, sizeof (err)); + int err_code = MC_CMD_ERR_EPROTO; + int err_arg = 0; + + /* Read error code (and arg num for MCDI v2 commands) */ + efx_mcdi_read_response(enp, &err, hdr_len, err_len); + + if (err_len >= (MC_CMD_ERR_CODE_OFST + sizeof (efx_dword_t))) + err_code = EFX_DWORD_FIELD(err[0], EFX_DWORD_0); +#ifdef WITH_MCDI_V2 + if (err_len >= (MC_CMD_ERR_ARG_OFST + sizeof (efx_dword_t))) + err_arg = EFX_DWORD_FIELD(err[1], EFX_DWORD_0); +#endif + emrp->emr_err_code = err_code; + emrp->emr_err_arg = err_arg; + +#if EFSYS_OPT_MCDI_PROXY_AUTH + if ((err_code == MC_CMD_ERR_PROXY_PENDING) && + (err_len == sizeof (err))) { + /* + * The MCDI request would normally fail with EPERM, but + * firmware has forwarded it to an authorization agent + * attached to a privileged PF. + * + * Save the authorization request handle. The client + * must wait for a PROXY_RESPONSE event, or timeout. + */ + emrp->emr_proxy_handle = err_arg; + } +#endif /* EFSYS_OPT_MCDI_PROXY_AUTH */ + +#if EFSYS_OPT_MCDI_LOGGING + if (emtp->emt_logger != NULL) { + emtp->emt_logger(emtp->emt_context, + EFX_LOG_MCDI_RESPONSE, + &hdr, hdr_len, + &err, err_len); + } +#endif /* EFSYS_OPT_MCDI_LOGGING */ + + if (!emrp->emr_quiet) { + EFSYS_PROBE3(mcdi_err_arg, int, emrp->emr_cmd, + int, err_code, int, err_arg); + } + + rc = efx_mcdi_request_errcode(err_code); + goto fail3; + } + + emrp->emr_rc = 0; + emrp->emr_out_length_used = data_len; +#if EFSYS_OPT_MCDI_PROXY_AUTH + emrp->emr_proxy_handle = 0; +#endif /* EFSYS_OPT_MCDI_PROXY_AUTH */ + return; + +fail3: + if (!emrp->emr_quiet) + EFSYS_PROBE(fail3); +fail2: + if (!emrp->emr_quiet) + EFSYS_PROBE(fail2); +fail1: + if (!emrp->emr_quiet) + EFSYS_PROBE1(fail1, efx_rc_t, rc); + + emrp->emr_rc = rc; + emrp->emr_out_length_used = 0; } + __checkReturn boolean_t efx_mcdi_request_poll( __in efx_nic_t *enp) { - efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; - boolean_t completed; + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); + efx_mcdi_req_t *emrp; + int state; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI); EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI); - completed = B_FALSE; + /* Serialise against post-watchdog efx_mcdi_ev* */ + EFSYS_LOCK(enp->en_eslp, state); + + EFSYS_ASSERT(emip->emi_pending_req != NULL); + EFSYS_ASSERT(!emip->emi_ev_cpl); + emrp = emip->emi_pending_req; + + /* Check for reboot atomically w.r.t efx_mcdi_request_start */ + if (emip->emi_poll_cnt++ == 0) { + if ((rc = efx_mcdi_poll_reboot(enp)) != 0) { + emip->emi_pending_req = NULL; + EFSYS_UNLOCK(enp->en_eslp, state); + goto fail1; + } + } + + /* Check if a response is available */ + if (efx_mcdi_poll_response(enp) == B_FALSE) { + EFSYS_UNLOCK(enp->en_eslp, state); + return (B_FALSE); + } + + /* Read the response header */ + efx_mcdi_read_response_header(enp, emrp); + + /* Request complete */ + emip->emi_pending_req = NULL; + + EFSYS_UNLOCK(enp->en_eslp, state); + + if ((rc = emrp->emr_rc) != 0) + goto fail2; + + efx_mcdi_request_copyout(enp, emrp); + return (B_TRUE); + +fail2: + if (!emrp->emr_quiet) + EFSYS_PROBE(fail2); +fail1: + if (!emrp->emr_quiet) + EFSYS_PROBE1(fail1, efx_rc_t, rc); - if (emcop != NULL && emcop->emco_request_poll != NULL) - completed = emcop->emco_request_poll(enp); + /* Reboot/Assertion */ + if (rc == EIO || rc == EINTR) + efx_mcdi_raise_exception(enp, emrp, rc); - return (completed); + return (B_TRUE); } __checkReturn boolean_t @@ -285,7 +505,7 @@ efx_mcdi_request_abort( return (aborted); } - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_request_errcode( __in unsigned int err) { @@ -346,6 +566,9 @@ efx_mcdi_request_errcode( case MC_CMD_ERR_MAC_EXIST: return (EEXIST); + case MC_CMD_ERR_PROXY_PENDING: + return (EAGAIN); + default: EFSYS_PROBE1(mc_pcol_error, int, err); return (EIO); @@ -378,16 +601,6 @@ efx_mcdi_raise_exception( emtp->emt_exception(emtp->emt_context, exception); } -static int -efx_mcdi_poll_reboot( - __in efx_nic_t *enp) -{ - efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; - - return (emcop->emco_poll_reboot(enp)); -} - - void efx_mcdi_execute( __in efx_nic_t *enp, @@ -450,27 +663,86 @@ efx_mcdi_ev_cpl( emip->emi_pending_req = NULL; EFSYS_UNLOCK(enp->en_eslp, state); - /* - * Fill out the remaining hdr fields, and copyout the payload - * if the user supplied an output buffer. - */ - if (errcode != 0) { - if (!emrp->emr_quiet) { - EFSYS_PROBE2(mcdi_err, int, emrp->emr_cmd, - int, errcode); - } - emrp->emr_out_length_used = 0; - emrp->emr_rc = efx_mcdi_request_errcode(errcode); + if (emip->emi_max_version >= 2) { + /* MCDIv2 response details do not fit into an event. */ + efx_mcdi_read_response_header(enp, emrp); } else { - emrp->emr_out_length_used = outlen; - emrp->emr_rc = 0; - + if (errcode != 0) { + if (!emrp->emr_quiet) { + EFSYS_PROBE2(mcdi_err, int, emrp->emr_cmd, + int, errcode); + } + emrp->emr_out_length_used = 0; + emrp->emr_rc = efx_mcdi_request_errcode(errcode); + } else { + emrp->emr_out_length_used = outlen; + emrp->emr_rc = 0; + } + } + if (errcode == 0) { emcop->emco_request_copyout(enp, emrp); } emtp->emt_ev_cpl(emtp->emt_context); } +#if EFSYS_OPT_MCDI_PROXY_AUTH + + __checkReturn efx_rc_t +efx_mcdi_get_proxy_handle( + __in efx_nic_t *enp, + __in efx_mcdi_req_t *emrp, + __out uint32_t *handlep) +{ + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); + efx_rc_t rc; + + /* + * Return proxy handle from MCDI request that returned with error + * MC_MCD_ERR_PROXY_PENDING. This handle is used to wait for a matching + * PROXY_RESPONSE event. + */ + if ((emrp == NULL) || (handlep == NULL)) { + rc = EINVAL; + goto fail1; + } + if ((emrp->emr_rc != 0) && + (emrp->emr_err_code == MC_CMD_ERR_PROXY_PENDING)) { + *handlep = emrp->emr_proxy_handle; + rc = 0; + } else { + *handlep = 0; + rc = ENOENT; + } + return (rc); + +fail1: + EFSYS_PROBE1(fail1, efx_rc_t, rc); + return (rc); +} + + void +efx_mcdi_ev_proxy_response( + __in efx_nic_t *enp, + __in unsigned int handle, + __in unsigned int status) +{ + const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp; + efx_rc_t rc; + + /* + * Handle results of an authorization request for a privileged MCDI + * command. If authorization was granted then we must re-issue the + * original MCDI request. If authorization failed or timed out, + * then the original MCDI request should be completed with the + * result code from this event. + */ + rc = (status == 0) ? 0 : efx_mcdi_request_errcode(status); + + emtp->emt_ev_proxy_response(emtp->emt_context, handle, rc); +} +#endif /* EFSYS_OPT_MCDI_PROXY_AUTH */ + void efx_mcdi_ev_death( __in efx_nic_t *enp, @@ -524,7 +796,7 @@ efx_mcdi_ev_death( emtp->emt_ev_cpl(emtp->emt_context); } - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_version( __in efx_nic_t *enp, __out_ecount_opt(4) uint16_t versionp[4], @@ -540,7 +812,7 @@ efx_mcdi_version( uint16_t version[4]; uint32_t build; efx_mcdi_boot_t status; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI); @@ -635,19 +907,19 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_do_reboot( __in efx_nic_t *enp, __in boolean_t after_assertion) { uint8_t payload[MAX(MC_CMD_REBOOT_IN_LEN, MC_CMD_REBOOT_OUT_LEN)]; efx_mcdi_req_t req; - int rc; + efx_rc_t rc; /* * We could require the caller to have caused en_mod_flags=0 to @@ -685,26 +957,26 @@ out: return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_reboot( __in efx_nic_t *enp) { return (efx_mcdi_do_reboot(enp, B_FALSE)); } - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_exit_assertion_handler( __in efx_nic_t *enp) { return (efx_mcdi_do_reboot(enp, B_TRUE)); } - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_read_assertion( __in efx_nic_t *enp) { @@ -716,7 +988,7 @@ efx_mcdi_read_assertion( unsigned int index; unsigned int ofst; int retry; - int rc; + efx_rc_t rc; /* * Before we attempt to chat to the MC, we should verify that the MC @@ -795,7 +1067,7 @@ out: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -805,7 +1077,7 @@ fail1: * Internal routines for for specific MCDI requests. */ - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_drv_attach( __in efx_nic_t *enp, __in boolean_t attach) @@ -815,7 +1087,7 @@ efx_mcdi_drv_attach( uint8_t payload[MAX(MC_CMD_DRV_ATTACH_IN_LEN, MC_CMD_DRV_ATTACH_EXT_OUT_LEN)]; uint32_t flags; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_DRV_ATTACH; @@ -878,12 +1150,12 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_get_board_cfg( __in efx_nic_t *enp, __out_opt uint32_t *board_typep, @@ -894,7 +1166,7 @@ efx_mcdi_get_board_cfg( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_GET_BOARD_CFG_IN_LEN, MC_CMD_GET_BOARD_CFG_OUT_LENMIN)]; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_GET_BOARD_CFG; @@ -959,12 +1231,12 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_get_resource_limits( __in efx_nic_t *enp, __out_opt uint32_t *nevqp, @@ -974,7 +1246,7 @@ efx_mcdi_get_resource_limits( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_GET_RESOURCE_LIMITS_IN_LEN, MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN)]; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_GET_RESOURCE_LIMITS; @@ -1007,12 +1279,12 @@ efx_mcdi_get_resource_limits( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_get_phy_cfg( __in efx_nic_t *enp) { @@ -1021,7 +1293,7 @@ efx_mcdi_get_phy_cfg( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_GET_PHY_CFG_IN_LEN, MC_CMD_GET_PHY_CFG_OUT_LEN)]; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_GET_PHY_CFG; @@ -1113,23 +1385,22 @@ efx_mcdi_get_phy_cfg( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_firmware_update_supported( __in efx_nic_t *enp, __out boolean_t *supportedp) { efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; - int rc; + efx_rc_t rc; - if (emcop != NULL && emcop->emco_fw_update_supported != NULL) { - if ((rc = emcop->emco_fw_update_supported(enp, supportedp)) - != 0) + if (emcop != NULL) { + if ((rc = emcop->emco_feature_supported(enp, + EFX_MCDI_FEATURE_FW_UPDATE, supportedp)) != 0) goto fail1; } else { /* Earlier devices always supported updates */ @@ -1139,22 +1410,22 @@ efx_mcdi_firmware_update_supported( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_macaddr_change_supported( __in efx_nic_t *enp, __out boolean_t *supportedp) { efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; - int rc; + efx_rc_t rc; - if (emcop != NULL && emcop->emco_macaddr_change_supported != NULL) { - if ((rc = emcop->emco_macaddr_change_supported(enp, supportedp)) - != 0) + if (emcop != NULL) { + if ((rc = emcop->emco_feature_supported(enp, + EFX_MCDI_FEATURE_MACADDR_CHANGE, supportedp)) != 0) goto fail1; } else { /* Earlier devices always supported MAC changes */ @@ -1164,25 +1435,75 @@ efx_mcdi_macaddr_change_supported( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); + + return (rc); +} + + __checkReturn efx_rc_t +efx_mcdi_link_control_supported( + __in efx_nic_t *enp, + __out boolean_t *supportedp) +{ + efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; + efx_rc_t rc; + + if (emcop != NULL) { + if ((rc = emcop->emco_feature_supported(enp, + EFX_MCDI_FEATURE_LINK_CONTROL, supportedp)) != 0) + goto fail1; + } else { + /* Earlier devices always supported link control */ + *supportedp = B_TRUE; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, efx_rc_t, rc); + + return (rc); +} + + __checkReturn efx_rc_t +efx_mcdi_mac_spoofing_supported( + __in efx_nic_t *enp, + __out boolean_t *supportedp) +{ + efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; + efx_rc_t rc; + + if (emcop != NULL) { + if ((rc = emcop->emco_feature_supported(enp, + EFX_MCDI_FEATURE_MAC_SPOOFING, supportedp)) != 0) + goto fail1; + } else { + /* Earlier devices always supported MAC spoofing */ + *supportedp = B_TRUE; + } + + return (0); + +fail1: + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } #if EFSYS_OPT_BIST -#if EFSYS_OPT_HUNTINGTON +#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD /* * Enter bist offline mode. This is a fw mode which puts the NIC into a state * where memory BIST tests can be run and not much else can interfere or happen. * A reboot is required to exit this mode. */ - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_bist_enable_offline( __in efx_nic_t *enp) { efx_mcdi_req_t req; - int rc; + efx_rc_t rc; EFX_STATIC_ASSERT(MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN == 0); EFX_STATIC_ASSERT(MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN == 0); @@ -1203,13 +1524,13 @@ efx_mcdi_bist_enable_offline( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -#endif /* EFSYS_OPT_HUNTINGTON */ +#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_bist_start( __in efx_nic_t *enp, __in efx_bist_type_t type) @@ -1217,7 +1538,7 @@ efx_mcdi_bist_start( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_START_BIST_IN_LEN, MC_CMD_START_BIST_OUT_LEN)]; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_START_BIST; @@ -1264,7 +1585,7 @@ efx_mcdi_bist_start( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -1273,14 +1594,14 @@ fail1: /* Enable logging of some events (e.g. link state changes) */ - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_log_ctrl( __in efx_nic_t *enp) { efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_LOG_CTRL_IN_LEN, MC_CMD_LOG_CTRL_OUT_LEN)]; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_LOG_CTRL; @@ -1303,7 +1624,7 @@ efx_mcdi_log_ctrl( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -1320,7 +1641,7 @@ typedef enum efx_stats_action_e EFX_STATS_DISABLE, } efx_stats_action_t; -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_mac_stats( __in efx_nic_t *enp, __in_opt efsys_mem_t *esmp, @@ -1334,7 +1655,7 @@ efx_mcdi_mac_stats( int enable = (action == EFX_STATS_ENABLE_NOEVENTS); int events = (action == EFX_STATS_ENABLE_EVENTS); int disable = (action == EFX_STATS_DISABLE); - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_MAC_STATS; @@ -1388,16 +1709,16 @@ efx_mcdi_mac_stats( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_mac_stats_clear( __in efx_nic_t *enp) { - int rc; + efx_rc_t rc; if ((rc = efx_mcdi_mac_stats(enp, NULL, EFX_STATS_CLEAR)) != 0) goto fail1; @@ -1405,17 +1726,17 @@ efx_mcdi_mac_stats_clear( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_mac_stats_upload( __in efx_nic_t *enp, __in efsys_mem_t *esmp) { - int rc; + efx_rc_t rc; /* * The MC DMAs aggregate statistics for our convenience, so we can @@ -1428,19 +1749,19 @@ efx_mcdi_mac_stats_upload( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_mac_stats_periodic( __in efx_nic_t *enp, __in efsys_mem_t *esmp, __in uint16_t period, __in boolean_t events) { - int rc; + efx_rc_t rc; /* * The MC DMAs aggregate statistics for our convenience, so we can @@ -1461,14 +1782,14 @@ efx_mcdi_mac_stats_periodic( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } #endif /* EFSYS_OPT_MAC_STATS */ -#if EFSYS_OPT_HUNTINGTON +#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD /* * This function returns the pf and vf number of a function. If it is a pf the @@ -1476,7 +1797,7 @@ fail1: * function. So if you have 3 vfs on pf 0 the 3 vfs will return (pf=0,vf=0), * (pf=0,vf=1), (pf=0,vf=2) aand the pf will return (pf=0, vf=0xffff). */ - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_get_function_info( __in efx_nic_t *enp, __out uint32_t *pfp, @@ -1485,7 +1806,7 @@ efx_mcdi_get_function_info( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_GET_FUNCTION_INFO_IN_LEN, MC_CMD_GET_FUNCTION_INFO_OUT_LEN)]; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_GET_FUNCTION_INFO; @@ -1515,12 +1836,12 @@ efx_mcdi_get_function_info( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_privilege_mask( __in efx_nic_t *enp, __in uint32_t pf, @@ -1530,7 +1851,7 @@ efx_mcdi_privilege_mask( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_PRIVILEGE_MASK_IN_LEN, MC_CMD_PRIVILEGE_MASK_OUT_LEN)]; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_PRIVILEGE_MASK; @@ -1562,14 +1883,14 @@ efx_mcdi_privilege_mask( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -#endif /* EFSYS_OPT_HUNTINGTON */ +#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_set_workaround( __in efx_nic_t *enp, __in uint32_t type, @@ -1579,7 +1900,7 @@ efx_mcdi_set_workaround( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_WORKAROUND_IN_LEN, MC_CMD_WORKAROUND_EXT_OUT_LEN)]; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_WORKAROUND; @@ -1608,13 +1929,13 @@ efx_mcdi_set_workaround( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_get_workarounds( __in efx_nic_t *enp, __out_opt uint32_t *implementedp, @@ -1622,7 +1943,7 @@ efx_mcdi_get_workarounds( { efx_mcdi_req_t req; uint8_t payload[MC_CMD_GET_WORKAROUNDS_OUT_LEN]; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_GET_WORKAROUNDS; @@ -1650,7 +1971,7 @@ efx_mcdi_get_workarounds( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } diff --git a/sys/dev/sfxge/common/efx_mcdi.h b/sys/dev/sfxge/common/efx_mcdi.h index ea02248..36b3d8d 100644 --- a/sys/dev/sfxge/common/efx_mcdi.h +++ b/sys/dev/sfxge/common/efx_mcdi.h @@ -34,7 +34,6 @@ #define _SYS_EFX_MCDI_H #include "efx.h" -#include "efx_regs.h" #include "efx_regs_mcdi.h" #ifdef __cplusplus @@ -55,14 +54,21 @@ struct efx_mcdi_req_s { uint8_t *emr_in_buf; size_t emr_in_length; /* Outputs: retcode, buffer, length, and length used*/ - int emr_rc; + efx_rc_t emr_rc; uint8_t *emr_out_buf; size_t emr_out_length; size_t emr_out_length_used; + /* Internals: low level transport details */ + unsigned int emr_err_code; + unsigned int emr_err_arg; +#if EFSYS_OPT_MCDI_PROXY_AUTH + uint32_t emr_proxy_handle; +#endif }; typedef struct efx_mcdi_iface_s { unsigned int emi_port; + unsigned int emi_max_version; unsigned int emi_seq; efx_mcdi_req_t *emi_pending_req; boolean_t emi_ev_cpl; @@ -82,6 +88,11 @@ efx_mcdi_execute_quiet( __in efx_nic_t *enp, __inout efx_mcdi_req_t *emrp); + extern void +efx_mcdi_read_response_header( + __in efx_nic_t *enp, + __inout efx_mcdi_req_t *emrp); + extern void efx_mcdi_ev_cpl( __in efx_nic_t *enp, @@ -89,12 +100,26 @@ efx_mcdi_ev_cpl( __in unsigned int outlen, __in int errcode); +#if EFSYS_OPT_MCDI_PROXY_AUTH +extern __checkReturn efx_rc_t +efx_mcdi_get_proxy_handle( + __in efx_nic_t *enp, + __in efx_mcdi_req_t *emrp, + __out uint32_t *handlep); + +extern void +efx_mcdi_ev_proxy_response( + __in efx_nic_t *enp, + __in unsigned int handle, + __in unsigned int status); +#endif + extern void efx_mcdi_ev_death( __in efx_nic_t *enp, __in int rc); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mcdi_request_errcode( __in unsigned int err); @@ -110,80 +135,91 @@ typedef enum efx_mcdi_boot_e { EFX_MCDI_BOOT_ROM, } efx_mcdi_boot_t; -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mcdi_version( __in efx_nic_t *enp, __out_ecount_opt(4) uint16_t versionp[4], __out_opt uint32_t *buildp, __out_opt efx_mcdi_boot_t *statusp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mcdi_read_assertion( __in efx_nic_t *enp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mcdi_exit_assertion_handler( __in efx_nic_t *enp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mcdi_drv_attach( __in efx_nic_t *enp, __in boolean_t attach); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mcdi_get_board_cfg( __in efx_nic_t *enp, __out_opt uint32_t *board_typep, __out_opt efx_dword_t *capabilitiesp, __out_ecount_opt(6) uint8_t mac_addrp[6]); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mcdi_get_phy_cfg( __in efx_nic_t *enp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mcdi_firmware_update_supported( __in efx_nic_t *enp, __out boolean_t *supportedp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mcdi_macaddr_change_supported( __in efx_nic_t *enp, __out boolean_t *supportedp); +extern __checkReturn efx_rc_t +efx_mcdi_link_control_supported( + __in efx_nic_t *enp, + __out boolean_t *supportedp); + +extern __checkReturn efx_rc_t +efx_mcdi_mac_spoofing_supported( + __in efx_nic_t *enp, + __out boolean_t *supportedp); + + #if EFSYS_OPT_BIST -#if EFSYS_OPT_HUNTINGTON -extern __checkReturn int +#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD +extern __checkReturn efx_rc_t efx_mcdi_bist_enable_offline( __in efx_nic_t *enp); -#endif /* EFSYS_OPT_HUNTINGTON */ -extern __checkReturn int +#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ +extern __checkReturn efx_rc_t efx_mcdi_bist_start( __in efx_nic_t *enp, __in efx_bist_type_t type); #endif /* EFSYS_OPT_BIST */ -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mcdi_get_resource_limits( __in efx_nic_t *enp, __out_opt uint32_t *nevqp, __out_opt uint32_t *nrxqp, __out_opt uint32_t *ntxqp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mcdi_log_ctrl( __in efx_nic_t *enp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mcdi_mac_stats_clear( __in efx_nic_t *enp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mcdi_mac_stats_upload( __in efx_nic_t *enp, __in efsys_mem_t *esmp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mcdi_mac_stats_periodic( __in efx_nic_t *enp, __in efsys_mem_t *esmp, @@ -192,7 +228,7 @@ efx_mcdi_mac_stats_periodic( #if EFSYS_OPT_LOOPBACK -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mcdi_get_loopback_modes( __in efx_nic_t *enp); #endif /* EFSYS_OPT_LOOPBACK */ @@ -350,6 +386,18 @@ efx_mcdi_get_loopback_modes( #define MCDI_CMD_DWORD_FIELD(_edp, _field) \ EFX_DWORD_FIELD(*_edp, MC_CMD_ ## _field) +#define EFX_MCDI_HAVE_PRIVILEGE(mask, priv) \ + (((mask) & (MC_CMD_PRIVILEGE_MASK_IN_GRP_ ## priv)) == \ + (MC_CMD_PRIVILEGE_MASK_IN_GRP_ ## priv)) + +typedef enum efx_mcdi_feature_id_e { + EFX_MCDI_FEATURE_FW_UPDATE = 0, + EFX_MCDI_FEATURE_LINK_CONTROL, + EFX_MCDI_FEATURE_MACADDR_CHANGE, + EFX_MCDI_FEATURE_MAC_SPOOFING, + EFX_MCDI_FEATURE_NIDS +} efx_mcdi_feature_id_t; + #ifdef __cplusplus } #endif diff --git a/sys/dev/sfxge/common/efx_mon.c b/sys/dev/sfxge/common/efx_mon.c index c5b356d..9803b43 100644 --- a/sys/dev/sfxge/common/efx_mon.c +++ b/sys/dev/sfxge/common/efx_mon.c @@ -31,10 +31,7 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" -#include "efx_types.h" -#include "efx_regs.h" #include "efx_impl.h" #if EFSYS_OPT_MON_NULL @@ -62,6 +59,7 @@ static const char *__efx_mon_name[] = { "max6647", "sfx90x0", "sfx91x0" + "sfx92x0" }; const char * @@ -119,43 +117,15 @@ static efx_mon_ops_t __efx_mon_mcdi_ops = { }; #endif -static efx_mon_ops_t *__efx_mon_ops[] = { - NULL, -#if EFSYS_OPT_MON_NULL - &__efx_mon_null_ops, -#else - NULL, -#endif -#if EFSYS_OPT_MON_LM87 - &__efx_mon_lm87_ops, -#else - NULL, -#endif -#if EFSYS_OPT_MON_MAX6647 - &__efx_mon_max6647_ops, -#else - NULL, -#endif -#if EFSYS_OPT_MON_MCDI - &__efx_mon_mcdi_ops, -#else - NULL, -#endif -#if EFSYS_OPT_MON_MCDI - &__efx_mon_mcdi_ops -#else - NULL -#endif -}; - __checkReturn int + __checkReturn efx_rc_t efx_mon_init( __in efx_nic_t *enp) { efx_nic_cfg_t *encp = &(enp->en_nic_cfg); efx_mon_t *emp = &(enp->en_mon); efx_mon_ops_t *emop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); @@ -170,8 +140,30 @@ efx_mon_init( emp->em_type = encp->enc_mon_type; EFSYS_ASSERT(encp->enc_mon_type != EFX_MON_INVALID); - EFSYS_ASSERT3U(emp->em_type, <, EFX_MON_NTYPES); - if ((emop = (efx_mon_ops_t *)__efx_mon_ops[emp->em_type]) == NULL) { + switch (emp->em_type) { +#if EFSYS_OPT_MON_NULL + case EFX_MON_NULL: + emop = &__efx_mon_null_ops; + break; +#endif +#if EFSYS_OPT_MON_LM87 + case EFX_MON_LM87: + emop = &__efx_mon_lm87_ops; + break; +#endif +#if EFSYS_OPT_MON_MAX6647 + case EFX_MON_MAX6647: + emop = &__efx_mon_max6647_ops; + break; +#endif +#if EFSYS_OPT_MON_MCDI + case EFX_MON_SFC90X0: + case EFX_MON_SFC91X0: + case EFX_MON_SFC92X0: + emop = &__efx_mon_mcdi_ops; + break; +#endif + default: rc = ENOTSUP; goto fail2; } @@ -205,7 +197,7 @@ fail2: enp->en_mod_flags &= ~EFX_MOD_MON; fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -214,7 +206,7 @@ fail1: #if EFSYS_OPT_NAMES -/* START MKCONFIG GENERATED MonitorStatNamesBlock b9328f15438c4d01 */ +/* START MKCONFIG GENERATED MonitorStatNamesBlock 01ee3ea01f23a0c4 */ static const char *__mon_stat_name[] = { "value_2_5v", "value_vccp1", @@ -285,6 +277,12 @@ static const char *__mon_stat_name[] = { "controller_slave_internal_temp", "controller_slave_vptat_ext_adc", "controller_slave_internal_temp_ext_adc", + "sodimm_vout", + "sodimm_0_temp", + "sodimm_1_temp", + "phy0_vcc", + "phy1_vcc", + "controller_tdiode_temp", }; /* END MKCONFIG GENERATED MonitorStatNamesBlock */ @@ -303,11 +301,11 @@ efx_mon_stat_name( #endif /* EFSYS_OPT_NAMES */ - __checkReturn int + __checkReturn efx_rc_t efx_mon_stats_update( __in efx_nic_t *enp, __in efsys_mem_t *esmp, - __out_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values) + __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values) { efx_mon_t *emp = &(enp->en_mon); efx_mon_ops_t *emop = emp->em_emop; @@ -326,7 +324,7 @@ efx_mon_fini( { efx_mon_t *emp = &(enp->en_mon); efx_mon_ops_t *emop = emp->em_emop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); @@ -337,7 +335,7 @@ efx_mon_fini( if (emop->emo_reset != NULL) { rc = emop->emo_reset(enp); if (rc != 0) - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); } emp->em_type = EFX_MON_INVALID; diff --git a/sys/dev/sfxge/common/efx_nic.c b/sys/dev/sfxge/common/efx_nic.c index b5ad65e..07acc56 100644 --- a/sys/dev/sfxge/common/efx_nic.c +++ b/sys/dev/sfxge/common/efx_nic.c @@ -31,13 +31,10 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" -#include "efx_types.h" -#include "efx_regs.h" #include "efx_impl.h" - __checkReturn int + __checkReturn efx_rc_t efx_family( __in uint16_t venid, __in uint16_t devid, @@ -49,7 +46,8 @@ efx_family( case EFX_PCI_DEVID_FALCON: *efp = EFX_FAMILY_FALCON; return (0); -#endif +#endif /* EFSYS_OPT_FALCON */ + #if EFSYS_OPT_SIENA case EFX_PCI_DEVID_SIENA_F1_UNINIT: /* @@ -63,7 +61,7 @@ efx_family( case EFX_PCI_DEVID_SIENA: *efp = EFX_FAMILY_SIENA; return (0); -#endif +#endif /* EFSYS_OPT_SIENA */ #if EFSYS_OPT_HUNTINGTON case EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT: @@ -76,16 +74,33 @@ efx_family( case EFX_PCI_DEVID_FARMINGDALE: case EFX_PCI_DEVID_GREENPORT: - case EFX_PCI_DEVID_HUNTINGTON: *efp = EFX_FAMILY_HUNTINGTON; return (0); case EFX_PCI_DEVID_FARMINGDALE_VF: case EFX_PCI_DEVID_GREENPORT_VF: - case EFX_PCI_DEVID_HUNTINGTON_VF: *efp = EFX_FAMILY_HUNTINGTON; return (0); -#endif +#endif /* EFSYS_OPT_HUNTINGTON */ + +#if EFSYS_OPT_MEDFORD + case EFX_PCI_DEVID_MEDFORD_PF_UNINIT: + /* + * Hardware default for PF0 of uninitialised Medford. + * manftest must be able to cope with this device id. + */ + *efp = EFX_FAMILY_MEDFORD; + return (0); + + case EFX_PCI_DEVID_MEDFORD: + *efp = EFX_FAMILY_MEDFORD; + return (0); + + case EFX_PCI_DEVID_MEDFORD_VF: + *efp = EFX_FAMILY_MEDFORD; + return (0); +#endif /* EFSYS_OPT_MEDFORD */ + default: break; } @@ -100,7 +115,7 @@ efx_family( * the hardware family by inspecting the hardware. Obviously the caller * must be damn sure they're really talking to a supported device. */ - __checkReturn int + __checkReturn efx_rc_t efx_infer_family( __in efsys_bar_t *esbp, __out efx_family_t *efp) @@ -108,12 +123,16 @@ efx_infer_family( efx_family_t family; efx_oword_t oword; unsigned int portnum; - int rc; + efx_rc_t rc; EFSYS_BAR_READO(esbp, FR_AZ_CS_DEBUG_REG_OFST, &oword, B_TRUE); portnum = EFX_OWORD_FIELD(oword, FRF_CZ_CS_PORT_NUM); - switch (portnum) { - case 0: { + if ((portnum == 1) || (portnum == 2)) { +#if EFSYS_OPT_SIENA + family = EFX_FAMILY_SIENA; + goto out; +#endif + } else if (portnum == 0) { efx_dword_t dword; uint32_t hw_rev; @@ -121,37 +140,31 @@ efx_infer_family( B_TRUE); hw_rev = EFX_DWORD_FIELD(dword, ERF_DZ_HW_REV_ID); if (hw_rev == ER_DZ_BIU_HW_REV_ID_REG_RESET) { -#if EFSYS_OPT_HUNTINGTON +#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD + /* + * BIU_HW_REV_ID is the same for Huntington and Medford. + * Assume Huntington, as Medford is very similar. + */ family = EFX_FAMILY_HUNTINGTON; - break; + goto out; #endif } else { #if EFSYS_OPT_FALCON family = EFX_FAMILY_FALCON; - break; + goto out; #endif } - rc = ENOTSUP; - goto fail1; - } - -#if EFSYS_OPT_SIENA - case 1: - case 2: - family = EFX_FAMILY_SIENA; - break; -#endif - default: - rc = ENOTSUP; - goto fail1; } + rc = ENOTSUP; + goto fail1; +out: if (efp != NULL) *efp = family; return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -159,12 +172,12 @@ fail1: #define EFX_BIU_MAGIC0 0x01234567 #define EFX_BIU_MAGIC1 0xfedcba98 - __checkReturn int + __checkReturn efx_rc_t efx_nic_biu_test( __in efx_nic_t *enp) { efx_oword_t oword; - int rc; + efx_rc_t rc; /* * Write magic values to scratch registers 0 and 1, then @@ -222,7 +235,7 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -268,23 +281,23 @@ static efx_nic_ops_t __efx_nic_siena_ops = { #if EFSYS_OPT_HUNTINGTON static efx_nic_ops_t __efx_nic_hunt_ops = { - hunt_nic_probe, /* eno_probe */ - hunt_nic_set_drv_limits, /* eno_set_drv_limits */ - hunt_nic_reset, /* eno_reset */ - hunt_nic_init, /* eno_init */ - hunt_nic_get_vi_pool, /* eno_get_vi_pool */ - hunt_nic_get_bar_region, /* eno_get_bar_region */ + ef10_nic_probe, /* eno_probe */ + ef10_nic_set_drv_limits, /* eno_set_drv_limits */ + ef10_nic_reset, /* eno_reset */ + ef10_nic_init, /* eno_init */ + ef10_nic_get_vi_pool, /* eno_get_vi_pool */ + ef10_nic_get_bar_region, /* eno_get_bar_region */ #if EFSYS_OPT_DIAG - hunt_sram_test, /* eno_sram_test */ - hunt_nic_register_test, /* eno_register_test */ + ef10_sram_test, /* eno_sram_test */ + ef10_nic_register_test, /* eno_register_test */ #endif /* EFSYS_OPT_DIAG */ - hunt_nic_fini, /* eno_fini */ - hunt_nic_unprobe, /* eno_unprobe */ + ef10_nic_fini, /* eno_fini */ + ef10_nic_unprobe, /* eno_unprobe */ }; #endif /* EFSYS_OPT_HUNTINGTON */ - __checkReturn int + __checkReturn efx_rc_t efx_nic_create( __in efx_family_t family, __in efsys_identifier_t *esip, @@ -293,7 +306,7 @@ efx_nic_create( __deref_out efx_nic_t **enpp) { efx_nic_t *enp; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID); EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES); @@ -371,17 +384,17 @@ fail2: EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_nic_probe( __in efx_nic_t *enp) { efx_nic_ops_t *enop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); #if EFSYS_OPT_MCDI @@ -406,14 +419,14 @@ fail2: enop->eno_unprobe(enp); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } #if EFSYS_OPT_PCIE_TUNE - __checkReturn int + __checkReturn efx_rc_t efx_nic_pcie_tune( __in efx_nic_t *enp, unsigned int nlanes) @@ -429,7 +442,7 @@ efx_nic_pcie_tune( return (ENOTSUP); } - __checkReturn int + __checkReturn efx_rc_t efx_nic_pcie_extended_sync( __in efx_nic_t *enp) { @@ -447,13 +460,13 @@ efx_nic_pcie_extended_sync( #endif /* EFSYS_OPT_PCIE_TUNE */ - __checkReturn int + __checkReturn efx_rc_t efx_nic_set_drv_limits( __inout efx_nic_t *enp, __in efx_drv_limits_t *edlp) { efx_nic_ops_t *enop = enp->en_enop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); @@ -466,12 +479,12 @@ efx_nic_set_drv_limits( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_nic_get_bar_region( __in efx_nic_t *enp, __in efx_nic_region_t region, @@ -479,7 +492,7 @@ efx_nic_get_bar_region( __out size_t *sizep) { efx_nic_ops_t *enop = enp->en_enop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); @@ -500,13 +513,13 @@ fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_nic_get_vi_pool( __in efx_nic_t *enp, __out uint32_t *evq_countp, @@ -515,7 +528,7 @@ efx_nic_get_vi_pool( { efx_nic_ops_t *enop = enp->en_enop; efx_nic_cfg_t *encp = &enp->en_nic_cfg; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); @@ -540,18 +553,18 @@ efx_nic_get_vi_pool( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_nic_init( __in efx_nic_t *enp) { efx_nic_ops_t *enop = enp->en_enop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); @@ -571,7 +584,7 @@ efx_nic_init( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -641,13 +654,13 @@ efx_nic_destroy( EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp); } - __checkReturn int + __checkReturn efx_rc_t efx_nic_reset( __in efx_nic_t *enp) { efx_nic_ops_t *enop = enp->en_enop; unsigned int mod_flags; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE); @@ -678,7 +691,7 @@ efx_nic_reset( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -694,12 +707,12 @@ efx_nic_cfg_get( #if EFSYS_OPT_DIAG - __checkReturn int + __checkReturn efx_rc_t efx_nic_register_test( __in efx_nic_t *enp) { efx_nic_ops_t *enop = enp->en_enop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); @@ -711,12 +724,12 @@ efx_nic_register_test( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_nic_test_registers( __in efx_nic_t *enp, __in efx_register_set_t *rsp, @@ -726,7 +739,7 @@ efx_nic_test_registers( efx_oword_t original; efx_oword_t reg; efx_oword_t buf; - int rc; + efx_rc_t rc; while (count > 0) { /* This function is only suitable for registers */ @@ -785,7 +798,7 @@ efx_nic_test_registers( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); /* Restore the old value */ EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original, B_TRUE); @@ -793,7 +806,7 @@ fail1: return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_nic_test_tables( __in efx_nic_t *enp, __in efx_register_set_t *rsp, @@ -805,7 +818,7 @@ efx_nic_test_tables( unsigned int address; efx_oword_t reg; efx_oword_t buf; - int rc; + efx_rc_t rc; EFSYS_ASSERT(pattern < EFX_PATTERN_NTYPES); func = __efx_sram_pattern_fns[pattern]; @@ -844,7 +857,7 @@ efx_nic_test_tables( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -955,7 +968,7 @@ efx_loopback_mask( *maskp = mask; } -__checkReturn int + __checkReturn efx_rc_t efx_mcdi_get_loopback_modes( __in efx_nic_t *enp) { @@ -965,7 +978,7 @@ efx_mcdi_get_loopback_modes( MC_CMD_GET_LOOPBACK_MODES_OUT_LEN)]; efx_qword_t mask; efx_qword_t modes; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_GET_LOOPBACK_MODES; @@ -1032,7 +1045,7 @@ efx_mcdi_get_loopback_modes( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } diff --git a/sys/dev/sfxge/common/efx_nvram.c b/sys/dev/sfxge/common/efx_nvram.c index 82bb1d9..7597636 100644 --- a/sys/dev/sfxge/common/efx_nvram.c +++ b/sys/dev/sfxge/common/efx_nvram.c @@ -31,10 +31,7 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" -#include "efx_types.h" -#include "efx_regs.h" #include "efx_impl.h" #if EFSYS_OPT_NVRAM @@ -53,6 +50,7 @@ static efx_nvram_ops_t __efx_nvram_falcon_ops = { falcon_nvram_write_chunk, /* envo_write_chunk */ falcon_nvram_rw_finish, /* envo_rw_finish */ falcon_nvram_set_version, /* envo_set_version */ + falcon_nvram_type_to_partn, /* envo_type_to_partn */ }; #endif /* EFSYS_OPT_FALCON */ @@ -71,34 +69,36 @@ static efx_nvram_ops_t __efx_nvram_siena_ops = { siena_nvram_write_chunk, /* envo_write_chunk */ siena_nvram_rw_finish, /* envo_rw_finish */ siena_nvram_set_version, /* envo_set_version */ + siena_nvram_type_to_partn, /* envo_type_to_partn */ }; #endif /* EFSYS_OPT_SIENA */ -#if EFSYS_OPT_HUNTINGTON +#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD -static efx_nvram_ops_t __efx_nvram_hunt_ops = { +static efx_nvram_ops_t __efx_nvram_ef10_ops = { #if EFSYS_OPT_DIAG - hunt_nvram_test, /* envo_test */ + ef10_nvram_test, /* envo_test */ #endif /* EFSYS_OPT_DIAG */ - hunt_nvram_size, /* envo_size */ - hunt_nvram_get_version, /* envo_get_version */ - hunt_nvram_rw_start, /* envo_rw_start */ - hunt_nvram_read_chunk, /* envo_read_chunk */ - hunt_nvram_erase, /* envo_erase */ - hunt_nvram_write_chunk, /* envo_write_chunk */ - hunt_nvram_rw_finish, /* envo_rw_finish */ - hunt_nvram_set_version, /* envo_set_version */ + ef10_nvram_size, /* envo_size */ + ef10_nvram_get_version, /* envo_get_version */ + ef10_nvram_rw_start, /* envo_rw_start */ + ef10_nvram_read_chunk, /* envo_read_chunk */ + ef10_nvram_erase, /* envo_erase */ + ef10_nvram_write_chunk, /* envo_write_chunk */ + ef10_nvram_rw_finish, /* envo_rw_finish */ + ef10_nvram_set_version, /* envo_set_version */ + ef10_nvram_type_to_partn, /* envo_type_to_partn */ }; -#endif /* EFSYS_OPT_HUNTINGTON */ +#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ - __checkReturn int + __checkReturn efx_rc_t efx_nvram_init( __in efx_nic_t *enp) { efx_nvram_ops_t *envop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); @@ -119,10 +119,16 @@ efx_nvram_init( #if EFSYS_OPT_HUNTINGTON case EFX_FAMILY_HUNTINGTON: - envop = (efx_nvram_ops_t *)&__efx_nvram_hunt_ops; + envop = (efx_nvram_ops_t *)&__efx_nvram_ef10_ops; break; #endif /* EFSYS_OPT_HUNTINGTON */ +#if EFSYS_OPT_MEDFORD + case EFX_FAMILY_MEDFORD: + envop = (efx_nvram_ops_t *)&__efx_nvram_ef10_ops; + break; +#endif /* EFSYS_OPT_MEDFORD */ + default: EFSYS_ASSERT(0); rc = ENOTSUP; @@ -135,19 +141,19 @@ efx_nvram_init( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } #if EFSYS_OPT_DIAG - __checkReturn int + __checkReturn efx_rc_t efx_nvram_test( __in efx_nic_t *enp) { efx_nvram_ops_t *envop = enp->en_envop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NVRAM); @@ -158,21 +164,21 @@ efx_nvram_test( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } #endif /* EFSYS_OPT_DIAG */ - __checkReturn int + __checkReturn efx_rc_t efx_nvram_size( __in efx_nic_t *enp, __in efx_nvram_type_t type, __out size_t *sizep) { efx_nvram_ops_t *envop = enp->en_envop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NVRAM); @@ -185,12 +191,12 @@ efx_nvram_size( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_nvram_get_version( __in efx_nic_t *enp, __in efx_nvram_type_t type, @@ -198,7 +204,7 @@ efx_nvram_get_version( __out_ecount(4) uint16_t version[4]) { efx_nvram_ops_t *envop = enp->en_envop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); @@ -212,19 +218,19 @@ efx_nvram_get_version( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_nvram_rw_start( __in efx_nic_t *enp, __in efx_nvram_type_t type, __out_opt size_t *chunk_sizep) { efx_nvram_ops_t *envop = enp->en_envop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NVRAM); @@ -242,12 +248,12 @@ efx_nvram_rw_start( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_nvram_read_chunk( __in efx_nic_t *enp, __in efx_nvram_type_t type, @@ -256,7 +262,7 @@ efx_nvram_read_chunk( __in size_t size) { efx_nvram_ops_t *envop = enp->en_envop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NVRAM); @@ -272,18 +278,18 @@ efx_nvram_read_chunk( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_nvram_erase( __in efx_nic_t *enp, __in efx_nvram_type_t type) { efx_nvram_ops_t *envop = enp->en_envop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NVRAM); @@ -299,12 +305,12 @@ efx_nvram_erase( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_nvram_write_chunk( __in efx_nic_t *enp, __in efx_nvram_type_t type, @@ -313,7 +319,7 @@ efx_nvram_write_chunk( __in size_t size) { efx_nvram_ops_t *envop = enp->en_envop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NVRAM); @@ -329,7 +335,7 @@ efx_nvram_write_chunk( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -354,14 +360,14 @@ efx_nvram_rw_finish( enp->en_nvram_locked = EFX_NVRAM_INVALID; } - __checkReturn int + __checkReturn efx_rc_t efx_nvram_set_version( __in efx_nic_t *enp, __in efx_nvram_type_t type, __in_ecount(4) uint16_t version[4]) { efx_nvram_ops_t *envop = enp->en_envop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); @@ -382,7 +388,7 @@ efx_nvram_set_version( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -409,7 +415,7 @@ efx_nvram_fini( * Internal MCDI request handling */ - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_nvram_partitions( __in efx_nic_t *enp, __out_bcount(size) caddr_t data, @@ -420,7 +426,7 @@ efx_mcdi_nvram_partitions( uint8_t payload[MAX(MC_CMD_NVRAM_PARTITIONS_IN_LEN, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX)]; unsigned int npartn; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_NVRAM_PARTITIONS; @@ -465,12 +471,12 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_nvram_metadata( __in efx_nic_t *enp, __in uint32_t partn, @@ -482,7 +488,7 @@ efx_mcdi_nvram_metadata( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_NVRAM_METADATA_IN_LEN, MC_CMD_NVRAM_METADATA_OUT_LENMAX)]; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_NVRAM_METADATA; @@ -556,30 +562,31 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_nvram_info( __in efx_nic_t *enp, __in uint32_t partn, __out_opt size_t *sizep, __out_opt uint32_t *addressp, - __out_opt uint32_t *erase_sizep) + __out_opt uint32_t *erase_sizep, + __out_opt uint32_t *write_sizep) { uint8_t payload[MAX(MC_CMD_NVRAM_INFO_IN_LEN, - MC_CMD_NVRAM_INFO_OUT_LEN)]; + MC_CMD_NVRAM_INFO_V2_OUT_LEN)]; efx_mcdi_req_t req; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_NVRAM_INFO; req.emr_in_buf = payload; req.emr_in_length = MC_CMD_NVRAM_INFO_IN_LEN; req.emr_out_buf = payload; - req.emr_out_length = MC_CMD_NVRAM_INFO_OUT_LEN; + req.emr_out_length = MC_CMD_NVRAM_INFO_V2_OUT_LEN; MCDI_IN_SET_DWORD(req, NVRAM_INFO_IN_TYPE, partn); @@ -604,17 +611,24 @@ efx_mcdi_nvram_info( if (erase_sizep) *erase_sizep = MCDI_OUT_DWORD(req, NVRAM_INFO_OUT_ERASESIZE); + if (write_sizep) { + *write_sizep = + (req.emr_out_length_used < + MC_CMD_NVRAM_INFO_V2_OUT_LEN) ? + 0 : MCDI_OUT_DWORD(req, NVRAM_INFO_V2_OUT_WRITESIZE); + } + return (0); fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_nvram_update_start( __in efx_nic_t *enp, __in uint32_t partn) @@ -622,7 +636,7 @@ efx_mcdi_nvram_update_start( uint8_t payload[MAX(MC_CMD_NVRAM_UPDATE_START_IN_LEN, MC_CMD_NVRAM_UPDATE_START_OUT_LEN)]; efx_mcdi_req_t req; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_NVRAM_UPDATE_START; @@ -643,12 +657,12 @@ efx_mcdi_nvram_update_start( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_nvram_read( __in efx_nic_t *enp, __in uint32_t partn, @@ -659,7 +673,7 @@ efx_mcdi_nvram_read( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_NVRAM_READ_IN_LEN, MC_CMD_NVRAM_READ_OUT_LENMAX)]; - int rc; + efx_rc_t rc; if (size > MC_CMD_NVRAM_READ_OUT_LENMAX) { rc = EINVAL; @@ -698,12 +712,12 @@ efx_mcdi_nvram_read( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_nvram_erase( __in efx_nic_t *enp, __in uint32_t partn, @@ -713,7 +727,7 @@ efx_mcdi_nvram_erase( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_NVRAM_ERASE_IN_LEN, MC_CMD_NVRAM_ERASE_OUT_LEN)]; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_NVRAM_ERASE; @@ -736,12 +750,17 @@ efx_mcdi_nvram_erase( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int +/* + * The NVRAM_WRITE MCDI command is a V1 command and so is supported by both + * Sienna and EF10 based boards. However EF10 based boards support the use + * of this command with payloads up to the maximum MCDI V2 payload length. + */ + __checkReturn efx_rc_t efx_mcdi_nvram_write( __in efx_nic_t *enp, __in uint32_t partn, @@ -750,11 +769,18 @@ efx_mcdi_nvram_write( __in size_t size) { efx_mcdi_req_t req; - uint8_t payload[MAX(MC_CMD_NVRAM_WRITE_IN_LENMAX, - MC_CMD_NVRAM_WRITE_OUT_LEN)]; - int rc; - - if (size > MC_CMD_NVRAM_WRITE_IN_LENMAX) { + uint8_t payload[MAX(MCDI_CTL_SDU_LEN_MAX_V1, + MCDI_CTL_SDU_LEN_MAX_V2)]; + efx_rc_t rc; + size_t max_data_size; + + max_data_size = enp->en_nic_cfg.enc_mcdi_max_payload_length + - MC_CMD_NVRAM_WRITE_IN_LEN(0); + EFSYS_ASSERT3U(enp->en_nic_cfg.enc_mcdi_max_payload_length, >, 0); + EFSYS_ASSERT3U(max_data_size, <, + enp->en_nic_cfg.enc_mcdi_max_payload_length); + + if (size > max_data_size) { rc = EINVAL; goto fail1; } @@ -785,12 +811,12 @@ efx_mcdi_nvram_write( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_nvram_update_finish( __in efx_nic_t *enp, __in uint32_t partn, @@ -799,7 +825,7 @@ efx_mcdi_nvram_update_finish( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN, MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN)]; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_NVRAM_UPDATE_FINISH; @@ -821,14 +847,14 @@ efx_mcdi_nvram_update_finish( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } #if EFSYS_OPT_DIAG - __checkReturn int + __checkReturn efx_rc_t efx_mcdi_nvram_test( __in efx_nic_t *enp, __in uint32_t partn) @@ -837,7 +863,7 @@ efx_mcdi_nvram_test( uint8_t payload[MAX(MC_CMD_NVRAM_TEST_IN_LEN, MC_CMD_NVRAM_TEST_OUT_LEN)]; int result; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_NVRAM_TEST; @@ -876,7 +902,7 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } diff --git a/sys/dev/sfxge/common/efx_phy.c b/sys/dev/sfxge/common/efx_phy.c index 5d18dc7..dd966be 100644 --- a/sys/dev/sfxge/common/efx_phy.c +++ b/sys/dev/sfxge/common/efx_phy.c @@ -31,10 +31,7 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" -#include "efx_types.h" -#include "efx_regs.h" #include "efx_impl.h" #if EFSYS_OPT_FALCON #include "falcon_nvram.h" @@ -296,14 +293,14 @@ static efx_phy_ops_t __efx_phy_hunt_ops = { }; #endif /* EFSYS_OPT_HUNTINGTON */ - __checkReturn int + __checkReturn efx_rc_t efx_phy_probe( __in efx_nic_t *enp) { efx_port_t *epp = &(enp->en_port); efx_nic_cfg_t *encp = &(enp->en_nic_cfg); efx_phy_ops_t *epop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); @@ -372,7 +369,7 @@ efx_phy_probe( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); epp->ep_port = 0; epp->ep_phy_type = 0; @@ -380,7 +377,7 @@ fail1: return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_phy_verify( __in efx_nic_t *enp) { @@ -395,7 +392,7 @@ efx_phy_verify( #if EFSYS_OPT_PHY_LED_CONTROL - __checkReturn int + __checkReturn efx_rc_t efx_phy_led_set( __in efx_nic_t *enp, __in efx_phy_led_mode_t mode) @@ -404,7 +401,7 @@ efx_phy_led_set( efx_port_t *epp = &(enp->en_port); efx_phy_ops_t *epop = epp->ep_epop; uint32_t mask; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); @@ -432,7 +429,7 @@ done: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -465,7 +462,7 @@ efx_phy_adv_cap_get( } } - __checkReturn int + __checkReturn efx_rc_t efx_phy_adv_cap_set( __in efx_nic_t *enp, __in uint32_t mask) @@ -473,7 +470,7 @@ efx_phy_adv_cap_set( efx_port_t *epp = &(enp->en_port); efx_phy_ops_t *epop = epp->ep_epop; uint32_t old_mask; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); @@ -509,7 +506,7 @@ fail2: } fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -527,7 +524,7 @@ efx_phy_lp_cap_get( *maskp = epp->ep_lp_cap_mask; } - __checkReturn int + __checkReturn efx_rc_t efx_phy_oui_get( __in efx_nic_t *enp, __out uint32_t *ouip) @@ -627,11 +624,11 @@ efx_phy_stat_name( #endif /* EFSYS_OPT_NAMES */ - __checkReturn int + __checkReturn efx_rc_t efx_phy_stats_update( __in efx_nic_t *enp, __in efsys_mem_t *esmp, - __out_ecount(EFX_PHY_NSTATS) uint32_t *stat) + __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat) { efx_port_t *epp = &(enp->en_port); efx_phy_ops_t *epop = epp->ep_epop; @@ -662,7 +659,7 @@ efx_phy_prop_name( } #endif /* EFSYS_OPT_NAMES */ - __checkReturn int + __checkReturn efx_rc_t efx_phy_prop_get( __in efx_nic_t *enp, __in unsigned int id, @@ -678,7 +675,7 @@ efx_phy_prop_get( return (epop->epo_prop_get(enp, id, flags, valp)); } - __checkReturn int + __checkReturn efx_rc_t efx_phy_prop_set( __in efx_nic_t *enp, __in unsigned int id, @@ -696,13 +693,13 @@ efx_phy_prop_set( #if EFSYS_OPT_BIST - __checkReturn int + __checkReturn efx_rc_t efx_bist_enable_offline( __in efx_nic_t *enp) { efx_port_t *epp = &(enp->en_port); efx_phy_ops_t *epop = epp->ep_epop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); @@ -719,20 +716,20 @@ efx_bist_enable_offline( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_bist_start( __in efx_nic_t *enp, __in efx_bist_type_t type) { efx_port_t *epp = &(enp->en_port); efx_phy_ops_t *epop = epp->ep_epop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); @@ -755,12 +752,12 @@ efx_bist_start( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_bist_poll( __in efx_nic_t *enp, __in efx_bist_type_t type, @@ -771,7 +768,7 @@ efx_bist_poll( { efx_port_t *epp = &(enp->en_port); efx_phy_ops_t *epop = epp->ep_epop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); @@ -794,7 +791,7 @@ efx_bist_poll( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } diff --git a/sys/dev/sfxge/common/efx_port.c b/sys/dev/sfxge/common/efx_port.c index a750c15..ca2a69b 100644 --- a/sys/dev/sfxge/common/efx_port.c +++ b/sys/dev/sfxge/common/efx_port.c @@ -31,18 +31,16 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" -#include "efx_types.h" #include "efx_impl.h" - __checkReturn int + __checkReturn efx_rc_t efx_port_init( __in efx_nic_t *enp) { efx_port_t *epp = &(enp->en_port); efx_phy_ops_t *epop = epp->ep_epop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); @@ -94,14 +92,14 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); enp->en_mod_flags &= ~EFX_MOD_PORT; return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_port_poll( __in efx_nic_t *enp, __out_opt efx_link_mode_t *link_modep) @@ -109,7 +107,7 @@ efx_port_poll( efx_port_t *epp = &(enp->en_port); efx_mac_ops_t *emop = epp->ep_emop; efx_link_mode_t ignore_link_mode; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); @@ -126,14 +124,14 @@ efx_port_poll( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } #if EFSYS_OPT_LOOPBACK - __checkReturn int + __checkReturn efx_rc_t efx_port_loopback_set( __in efx_nic_t *enp, __in efx_link_mode_t link_mode, @@ -142,7 +140,7 @@ efx_port_loopback_set( efx_port_t *epp = &(enp->en_port); efx_nic_cfg_t *encp = &(enp->en_nic_cfg); efx_mac_ops_t *emop = epp->ep_emop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); @@ -168,7 +166,7 @@ efx_port_loopback_set( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } diff --git a/sys/dev/sfxge/common/efx_regs_ef10.h b/sys/dev/sfxge/common/efx_regs_ef10.h index 8401726..bd7619a 100644 --- a/sys/dev/sfxge/common/efx_regs_ef10.h +++ b/sys/dev/sfxge/common/efx_regs_ef10.h @@ -37,6 +37,13 @@ extern "C" { #endif +/************************************************************************** + * NOTE: the line below marks the start of the autogenerated section + * EF10 registers and descriptors + * + ************************************************************************** + */ + /* * BIU_HW_REV_ID_REG(32bit): * @@ -182,29 +189,6 @@ extern "C" { #define ERF_DZ_TX_DESC_LWORD_LBN 0 #define ERF_DZ_TX_DESC_LWORD_WIDTH 32 -/* - * The workaround for bug 35388 requires multiplexing writes through - * the ERF_DZ_TX_DESC_WPTR address. - * TX_DESC_UPD: 0ppppppppppp (bit 11 lost) - * EVQ_RPTR: 1000hhhhhhhh, 1001llllllll (split into high and low bits) - * EVQ_TMR: 11mmvvvvvvvv (bits 8:13 of value lost) - */ -#define ER_DD_EVQ_INDIRECT_OFST (ER_DZ_TX_DESC_UPD_REG_OFST + 2 * 4) -#define ER_DD_EVQ_INDIRECT_STEP ER_DZ_TX_DESC_UPD_REG_STEP -#define ERF_DD_EVQ_IND_RPTR_FLAGS_LBN 8 -#define ERF_DD_EVQ_IND_RPTR_FLAGS_WIDTH 4 -#define EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH 8 -#define EFE_DD_EVQ_IND_RPTR_FLAGS_LOW 9 -#define ERF_DD_EVQ_IND_RPTR_LBN 0 -#define ERF_DD_EVQ_IND_RPTR_WIDTH 8 -#define ERF_DD_EVQ_IND_TIMER_FLAGS_LBN 10 -#define ERF_DD_EVQ_IND_TIMER_FLAGS_WIDTH 2 -#define EFE_DD_EVQ_IND_TIMER_FLAGS 3 -#define ERF_DD_EVQ_IND_TIMER_MODE_LBN 8 -#define ERF_DD_EVQ_IND_TIMER_MODE_WIDTH 2 -#define ERF_DD_EVQ_IND_TIMER_VAL_LBN 0 -#define ERF_DD_EVQ_IND_TIMER_VAL_WIDTH 8 - /* ES_DRIVER_EV */ #define ESF_DZ_DRV_CODE_LBN 60 @@ -242,1310 +226,6 @@ extern "C" { #define ESF_DZ_EV_DATA_WIDTH 60 -/* ES_FF_UMSG_CPU2DL_DESC_FETCH */ -#define ESF_DZ_C2DDF_DSCR_CACHE_RPTR_LBN 208 -#define ESF_DZ_C2DDF_DSCR_CACHE_RPTR_WIDTH 6 -#define ESF_DZ_C2DDF_QID_LBN 160 -#define ESF_DZ_C2DDF_QID_WIDTH 11 -#define ESF_DZ_C2DDF_DSCR_BASE_PAGE_ID_LBN 64 -#define ESF_DZ_C2DDF_DSCR_BASE_PAGE_ID_WIDTH 18 -#define ESF_DZ_C2DDF_DSCR_HW_RPTR_LBN 48 -#define ESF_DZ_C2DDF_DSCR_HW_RPTR_WIDTH 12 -#define ESF_DZ_C2DDF_DSCR_HW_WPTR_LBN 32 -#define ESF_DZ_C2DDF_DSCR_HW_WPTR_WIDTH 12 -#define ESF_DZ_C2DDF_OID_LBN 16 -#define ESF_DZ_C2DDF_OID_WIDTH 12 -#define ESF_DZ_C2DDF_DSCR_SIZE_LBN 13 -#define ESF_DZ_C2DDF_DSCR_SIZE_WIDTH 3 -#define ESE_DZ_C2DDF_DSCR_SIZE_512 7 -#define ESE_DZ_C2DDF_DSCR_SIZE_1K 6 -#define ESE_DZ_C2DDF_DSCR_SIZE_2K 5 -#define ESE_DZ_C2DDF_DSCR_SIZE_4K 4 -#define ESF_DZ_C2DDF_BIU_ARGS_LBN 0 -#define ESF_DZ_C2DDF_BIU_ARGS_WIDTH 13 - - -/* ES_FF_UMSG_CPU2DL_DESC_PUSH */ -#define ESF_DZ_C2DDP_DSCR_HW_RPTR_LBN 224 -#define ESF_DZ_C2DDP_DSCR_HW_RPTR_WIDTH 12 -#define ESF_DZ_C2DDP_DESC_DW0_LBN 128 -#define ESF_DZ_C2DDP_DESC_DW0_WIDTH 32 -#define ESF_DZ_C2DDP_DESC_DW1_LBN 160 -#define ESF_DZ_C2DDP_DESC_DW1_WIDTH 32 -#define ESF_DZ_C2DDP_DESC_LBN 128 -#define ESF_DZ_C2DDP_DESC_WIDTH 64 -#define ESF_DZ_C2DDP_QID_LBN 64 -#define ESF_DZ_C2DDP_QID_WIDTH 11 -#define ESF_DZ_C2DDP_DSCR_HW_WPTR_LBN 32 -#define ESF_DZ_C2DDP_DSCR_HW_WPTR_WIDTH 12 -#define ESF_DZ_C2DDP_OID_LBN 16 -#define ESF_DZ_C2DDP_OID_WIDTH 12 -#define ESF_DZ_C2DDP_DSCR_SIZE_LBN 0 -#define ESF_DZ_C2DDP_DSCR_SIZE_WIDTH 3 -#define ESE_DZ_C2DDF_DSCR_SIZE_512 7 -#define ESE_DZ_C2DDF_DSCR_SIZE_1K 6 -#define ESE_DZ_C2DDF_DSCR_SIZE_2K 5 -#define ESE_DZ_C2DDF_DSCR_SIZE_4K 4 - - -/* ES_FF_UMSG_CPU2DL_GPRD */ -#define ESF_DZ_C2DG_ENCODED_HOST_ADDR_DW0_LBN 64 -#define ESF_DZ_C2DG_ENCODED_HOST_ADDR_DW0_WIDTH 32 -#define ESF_DZ_C2DG_ENCODED_HOST_ADDR_DW1_LBN 96 -#define ESF_DZ_C2DG_ENCODED_HOST_ADDR_DW1_WIDTH 16 -#define ESF_DZ_C2DG_ENCODED_HOST_ADDR_LBN 64 -#define ESF_DZ_C2DG_ENCODED_HOST_ADDR_WIDTH 48 -#define ESF_DZ_C2DG_SMC_ADDR_LBN 16 -#define ESF_DZ_C2DG_SMC_ADDR_WIDTH 16 -#define ESF_DZ_C2DG_BIU_ARGS_LBN 0 -#define ESF_DZ_C2DG_BIU_ARGS_WIDTH 14 - - -/* ES_FF_UMSG_CPU2EV_SOFT */ -#define ESF_DZ_C2ES_TBD_LBN 0 -#define ESF_DZ_C2ES_TBD_WIDTH 1 - - -/* ES_FF_UMSG_CPU2EV_TXCMPLT */ -#define ESF_DZ_C2ET_EV_SOFT2_LBN 48 -#define ESF_DZ_C2ET_EV_SOFT2_WIDTH 16 -#define ESF_DZ_C2ET_EV_CODE_LBN 42 -#define ESF_DZ_C2ET_EV_CODE_WIDTH 4 -#define ESF_DZ_C2ET_EV_OVERRIDE_HOLDOFF_LBN 41 -#define ESF_DZ_C2ET_EV_OVERRIDE_HOLDOFF_WIDTH 1 -#define ESF_DZ_C2ET_EV_DROP_EVENT_LBN 40 -#define ESF_DZ_C2ET_EV_DROP_EVENT_WIDTH 1 -#define ESF_DZ_C2ET_EV_CAN_MERGE_LBN 39 -#define ESF_DZ_C2ET_EV_CAN_MERGE_WIDTH 1 -#define ESF_DZ_C2ET_EV_SOFT1_LBN 32 -#define ESF_DZ_C2ET_EV_SOFT1_WIDTH 7 -#define ESF_DZ_C2ET_DSCR_IDX_LBN 16 -#define ESF_DZ_C2ET_DSCR_IDX_WIDTH 16 -#define ESF_DZ_C2ET_EV_QID_LBN 5 -#define ESF_DZ_C2ET_EV_QID_WIDTH 11 -#define ESF_DZ_C2ET_EV_QLABEL_LBN 0 -#define ESF_DZ_C2ET_EV_QLABEL_WIDTH 5 - - -/* ES_FF_UMSG_CPU2RXDP_INGR_BUFOP */ -#define ESF_DZ_C2RIB_EV_DISABLE_LBN 191 -#define ESF_DZ_C2RIB_EV_DISABLE_WIDTH 1 -#define ESF_DZ_C2RIB_EV_SOFT_LBN 188 -#define ESF_DZ_C2RIB_EV_SOFT_WIDTH 3 -#define ESF_DZ_C2RIB_EV_DESC_PTR_LBN 176 -#define ESF_DZ_C2RIB_EV_DESC_PTR_WIDTH 12 -#define ESF_DZ_C2RIB_EV_ARG1_LBN 160 -#define ESF_DZ_C2RIB_EV_ARG1_WIDTH 16 -#define ESF_DZ_C2RIB_ENCODED_HOST_ADDR_DW0_LBN 64 -#define ESF_DZ_C2RIB_ENCODED_HOST_ADDR_DW0_WIDTH 32 -#define ESF_DZ_C2RIB_ENCODED_HOST_ADDR_DW1_LBN 96 -#define ESF_DZ_C2RIB_ENCODED_HOST_ADDR_DW1_WIDTH 16 -#define ESF_DZ_C2RIB_ENCODED_HOST_ADDR_LBN 64 -#define ESF_DZ_C2RIB_ENCODED_HOST_ADDR_WIDTH 48 -#define ESF_DZ_C2RIB_BIU_ARGS_LBN 16 -#define ESF_DZ_C2RIB_BIU_ARGS_WIDTH 13 -#define ESF_DZ_C2RIB_EV_QID_LBN 5 -#define ESF_DZ_C2RIB_EV_QID_WIDTH 11 -#define ESF_DZ_C2RIB_EV_QLABEL_LBN 0 -#define ESF_DZ_C2RIB_EV_QLABEL_WIDTH 5 - - -/* ES_FF_UMSG_CPU2RXDP_INGR_PDISP */ -#define ESF_DZ_C2RIP_BUF_LEN_LBN 240 -#define ESF_DZ_C2RIP_BUF_LEN_WIDTH 16 -#define ESF_DZ_C2RIP_ENCODED_HOST_ADDR_DW0_LBN 192 -#define ESF_DZ_C2RIP_ENCODED_HOST_ADDR_DW0_WIDTH 32 -#define ESF_DZ_C2RIP_ENCODED_HOST_ADDR_DW1_LBN 224 -#define ESF_DZ_C2RIP_ENCODED_HOST_ADDR_DW1_WIDTH 16 -#define ESF_DZ_C2RIP_ENCODED_HOST_ADDR_LBN 192 -#define ESF_DZ_C2RIP_ENCODED_HOST_ADDR_WIDTH 48 -#define ESF_DZ_C2RIP_EV_DISABLE_LBN 191 -#define ESF_DZ_C2RIP_EV_DISABLE_WIDTH 1 -#define ESF_DZ_C2RIP_EV_SOFT_LBN 188 -#define ESF_DZ_C2RIP_EV_SOFT_WIDTH 3 -#define ESF_DZ_C2RIP_EV_DESC_PTR_LBN 176 -#define ESF_DZ_C2RIP_EV_DESC_PTR_WIDTH 12 -#define ESF_DZ_C2RIP_EV_ARG1_LBN 160 -#define ESF_DZ_C2RIP_EV_ARG1_WIDTH 16 -#define ESF_DZ_C2RIP_UPD_CRC_MODE_LBN 157 -#define ESF_DZ_C2RIP_UPD_CRC_MODE_WIDTH 3 -#define ESE_DZ_C2RIP_FCOIP_FCOE 4 -#define ESE_DZ_C2RIP_ISCSI_HDR_AND_PYLD 3 -#define ESE_DZ_C2RIP_ISCSI_HDR 2 -#define ESE_DZ_C2RIP_FCOE 1 -#define ESE_DZ_C2RIP_OFF 0 -#define ESF_DZ_C2RIP_BIU_ARGS_LBN 144 -#define ESF_DZ_C2RIP_BIU_ARGS_WIDTH 13 -#define ESF_DZ_C2RIP_EV_QID_LBN 133 -#define ESF_DZ_C2RIP_EV_QID_WIDTH 11 -#define ESF_DZ_C2RIP_EV_QLABEL_LBN 128 -#define ESF_DZ_C2RIP_EV_QLABEL_WIDTH 5 -#define ESF_DZ_C2RIP_PEDIT_DELTA_LBN 104 -#define ESF_DZ_C2RIP_PEDIT_DELTA_WIDTH 8 -#define ESF_DZ_C2RIP_PYLOAD_OFST_LBN 96 -#define ESF_DZ_C2RIP_PYLOAD_OFST_WIDTH 8 -#define ESF_DZ_C2RIP_L4_HDR_OFST_LBN 88 -#define ESF_DZ_C2RIP_L4_HDR_OFST_WIDTH 8 -#define ESF_DZ_C2RIP_L3_HDR_OFST_LBN 80 -#define ESF_DZ_C2RIP_L3_HDR_OFST_WIDTH 8 -#define ESF_DZ_C2RIP_IS_UDP_LBN 69 -#define ESF_DZ_C2RIP_IS_UDP_WIDTH 1 -#define ESF_DZ_C2RIP_IS_TCP_LBN 68 -#define ESF_DZ_C2RIP_IS_TCP_WIDTH 1 -#define ESF_DZ_C2RIP_IS_IPV6_LBN 67 -#define ESF_DZ_C2RIP_IS_IPV6_WIDTH 1 -#define ESF_DZ_C2RIP_IS_IPV4_LBN 66 -#define ESF_DZ_C2RIP_IS_IPV4_WIDTH 1 -#define ESF_DZ_C2RIP_IS_FCOE_LBN 65 -#define ESF_DZ_C2RIP_IS_FCOE_WIDTH 1 -#define ESF_DZ_C2RIP_PARSE_INCOMP_LBN 64 -#define ESF_DZ_C2RIP_PARSE_INCOMP_WIDTH 1 -#define ESF_DZ_C2RIP_FINFO_WRD3_LBN 48 -#define ESF_DZ_C2RIP_FINFO_WRD3_WIDTH 16 -#define ESF_DZ_C2RIP_FINFO_WRD2_LBN 32 -#define ESF_DZ_C2RIP_FINFO_WRD2_WIDTH 16 -#define ESF_DZ_C2RIP_FINFO_WRD1_LBN 16 -#define ESF_DZ_C2RIP_FINFO_WRD1_WIDTH 16 -#define ESF_DZ_C2RIP_FINFO_SRCDST_LBN 0 -#define ESF_DZ_C2RIP_FINFO_SRCDST_WIDTH 16 - - -/* ES_FF_UMSG_CPU2RXDP_INGR_SOFT */ -#define ESF_DZ_C2RIS_SOFT3_LBN 48 -#define ESF_DZ_C2RIS_SOFT3_WIDTH 16 -#define ESF_DZ_C2RIS_SOFT2_LBN 32 -#define ESF_DZ_C2RIS_SOFT2_WIDTH 16 -#define ESF_DZ_C2RIS_SOFT1_LBN 16 -#define ESF_DZ_C2RIS_SOFT1_WIDTH 16 -#define ESF_DZ_C2RIS_SOFT0_LBN 0 -#define ESF_DZ_C2RIS_SOFT0_WIDTH 16 - - -/* ES_FF_UMSG_CPU2SMC_BUFLKUP */ -#define ESF_DZ_C2SB_PAGE_ID_LBN 16 -#define ESF_DZ_C2SB_PAGE_ID_WIDTH 18 -#define ESF_DZ_C2SB_EXP_PAGE_ID_LBN 0 -#define ESF_DZ_C2SB_EXP_PAGE_ID_WIDTH 12 - - -/* ES_FF_UMSG_CPU2SMC_DESCOP */ -#define ESF_DZ_C2SD_LEN_LBN 112 -#define ESF_DZ_C2SD_LEN_WIDTH 14 -#define ESF_DZ_C2SD_ENCODED_HOST_ADDR_DW0_LBN 64 -#define ESF_DZ_C2SD_ENCODED_HOST_ADDR_DW0_WIDTH 32 -#define ESF_DZ_C2SD_ENCODED_HOST_ADDR_DW1_LBN 96 -#define ESF_DZ_C2SD_ENCODED_HOST_ADDR_DW1_WIDTH 16 -#define ESF_DZ_C2SD_ENCODED_HOST_ADDR_LBN 64 -#define ESF_DZ_C2SD_ENCODED_HOST_ADDR_WIDTH 48 -#define ESF_DZ_C2SD_OFFSET_LBN 80 -#define ESF_DZ_C2SD_OFFSET_WIDTH 8 -#define ESF_DZ_C2SD_QID_LBN 32 -#define ESF_DZ_C2SD_QID_WIDTH 11 -#define ESF_DZ_C2SD_CONT_LBN 16 -#define ESF_DZ_C2SD_CONT_WIDTH 1 -#define ESF_DZ_C2SD_TYPE_LBN 0 -#define ESF_DZ_C2SD_TYPE_WIDTH 1 - - -/* ES_FF_UMSG_CPU2SMC_GPOP */ -#define ESF_DZ_C2SG_DATA_DW0_LBN 64 -#define ESF_DZ_C2SG_DATA_DW0_WIDTH 32 -#define ESF_DZ_C2SG_DATA_DW1_LBN 96 -#define ESF_DZ_C2SG_DATA_DW1_WIDTH 32 -#define ESF_DZ_C2SG_DATA_LBN 64 -#define ESF_DZ_C2SG_DATA_WIDTH 64 -#define ESF_DZ_C2SG_SOFT_LBN 48 -#define ESF_DZ_C2SG_SOFT_WIDTH 4 -#define ESF_DZ_C2SG_REFLECT_LBN 32 -#define ESF_DZ_C2SG_REFLECT_WIDTH 1 -#define ESF_DZ_C2SG_ADDR_LBN 0 -#define ESF_DZ_C2SG_ADDR_WIDTH 16 - - -/* ES_FF_UMSG_CPU2TXDP_DMA_BUFREQ */ -#define ESF_DZ_C2TDB_BUF_LEN_LBN 176 -#define ESF_DZ_C2TDB_BUF_LEN_WIDTH 16 -#define ESF_DZ_C2TDB_ENCODED_HOST_ADDR_DW0_LBN 128 -#define ESF_DZ_C2TDB_ENCODED_HOST_ADDR_DW0_WIDTH 32 -#define ESF_DZ_C2TDB_ENCODED_HOST_ADDR_DW1_LBN 160 -#define ESF_DZ_C2TDB_ENCODED_HOST_ADDR_DW1_WIDTH 16 -#define ESF_DZ_C2TDB_ENCODED_HOST_ADDR_LBN 128 -#define ESF_DZ_C2TDB_ENCODED_HOST_ADDR_WIDTH 48 -#define ESF_DZ_C2TDB_SOFT_LBN 112 -#define ESF_DZ_C2TDB_SOFT_WIDTH 14 -#define ESF_DZ_C2TDB_DESC_IDX_LBN 96 -#define ESF_DZ_C2TDB_DESC_IDX_WIDTH 16 -#define ESF_DZ_C2TDB_UPD_CRC_MODE_LBN 93 -#define ESF_DZ_C2TDB_UPD_CRC_MODE_WIDTH 3 -#define ESE_DZ_C2RIP_FCOIP_FCOE 4 -#define ESE_DZ_C2RIP_ISCSI_HDR_AND_PYLD 3 -#define ESE_DZ_C2RIP_ISCSI_HDR 2 -#define ESE_DZ_C2RIP_FCOE 1 -#define ESE_DZ_C2RIP_OFF 0 -#define ESF_DZ_C2TDB_BIU_ARGS_LBN 80 -#define ESF_DZ_C2TDB_BIU_ARGS_WIDTH 13 -#define ESF_DZ_C2TDB_CONT_LBN 64 -#define ESF_DZ_C2TDB_CONT_WIDTH 1 -#define ESF_DZ_C2TDB_FINFO_WRD3_LBN 48 -#define ESF_DZ_C2TDB_FINFO_WRD3_WIDTH 16 -#define ESF_DZ_C2TDB_FINFO_WRD2_LBN 32 -#define ESF_DZ_C2TDB_FINFO_WRD2_WIDTH 16 -#define ESF_DZ_C2TDB_FINFO_WRD1_LBN 16 -#define ESF_DZ_C2TDB_FINFO_WRD1_WIDTH 16 -#define ESF_DZ_C2TDB_FINFO_SRCDST_LBN 0 -#define ESF_DZ_C2TDB_FINFO_SRCDST_WIDTH 16 - - -/* ES_FF_UMSG_CPU2TXDP_DMA_PKTABORT */ -#define ESF_DZ_C2TDP_SOFT_LBN 48 -#define ESF_DZ_C2TDP_SOFT_WIDTH 14 -#define ESF_DZ_C2TDP_DESC_IDX_LBN 32 -#define ESF_DZ_C2TDP_DESC_IDX_WIDTH 16 -#define ESF_DZ_C2TDP_BIU_ARGS_LBN 16 -#define ESF_DZ_C2TDP_BIU_ARGS_WIDTH 14 - - -/* ES_FF_UMSG_CPU2TXDP_DMA_SOFT */ -#define ESF_DZ_C2TDS_SOFT3_LBN 48 -#define ESF_DZ_C2TDS_SOFT3_WIDTH 16 -#define ESF_DZ_C2TDS_SOFT2_LBN 32 -#define ESF_DZ_C2TDS_SOFT2_WIDTH 16 -#define ESF_DZ_C2TDS_SOFT1_LBN 16 -#define ESF_DZ_C2TDS_SOFT1_WIDTH 16 -#define ESF_DZ_C2TDS_SOFT0_LBN 0 -#define ESF_DZ_C2TDS_SOFT0_WIDTH 16 - - -/* ES_FF_UMSG_CPU2TXDP_EGR */ -#define ESF_DZ_C2TE_RMON_SOFT_LBN 240 -#define ESF_DZ_C2TE_RMON_SOFT_WIDTH 1 -#define ESF_DZ_C2TE_VLAN_PRIO_LBN 224 -#define ESF_DZ_C2TE_VLAN_PRIO_WIDTH 3 -#define ESF_DZ_C2TE_VLAN_LBN 208 -#define ESF_DZ_C2TE_VLAN_WIDTH 1 -#define ESF_DZ_C2TE_QID_LBN 192 -#define ESF_DZ_C2TE_QID_WIDTH 11 -#define ESF_DZ_C2TE_PEDIT_DELTA_LBN 168 -#define ESF_DZ_C2TE_PEDIT_DELTA_WIDTH 8 -#define ESF_DZ_C2TE_PYLOAD_OFST_LBN 160 -#define ESF_DZ_C2TE_PYLOAD_OFST_WIDTH 8 -#define ESF_DZ_C2TE_L4_HDR_OFST_LBN 152 -#define ESF_DZ_C2TE_L4_HDR_OFST_WIDTH 8 -#define ESF_DZ_C2TE_L3_HDR_OFST_LBN 144 -#define ESF_DZ_C2TE_L3_HDR_OFST_WIDTH 8 -#define ESF_DZ_C2TE_IS_UDP_LBN 133 -#define ESF_DZ_C2TE_IS_UDP_WIDTH 1 -#define ESF_DZ_C2TE_IS_TCP_LBN 132 -#define ESF_DZ_C2TE_IS_TCP_WIDTH 1 -#define ESF_DZ_C2TE_IS_IPV6_LBN 131 -#define ESF_DZ_C2TE_IS_IPV6_WIDTH 1 -#define ESF_DZ_C2TE_IS_IPV4_LBN 130 -#define ESF_DZ_C2TE_IS_IPV4_WIDTH 1 -#define ESF_DZ_C2TE_IS_FCOE_LBN 129 -#define ESF_DZ_C2TE_IS_FCOE_WIDTH 1 -#define ESF_DZ_C2TE_PARSE_INCOMP_LBN 128 -#define ESF_DZ_C2TE_PARSE_INCOMP_WIDTH 1 -#define ESF_DZ_C2TE_UPD_CRC_MODE_LBN 98 -#define ESF_DZ_C2TE_UPD_CRC_MODE_WIDTH 3 -#define ESE_DZ_C2RIP_FCOIP_FCOE 4 -#define ESE_DZ_C2RIP_ISCSI_HDR_AND_PYLD 3 -#define ESE_DZ_C2RIP_ISCSI_HDR 2 -#define ESE_DZ_C2RIP_FCOE 1 -#define ESE_DZ_C2RIP_OFF 0 -#define ESF_DZ_C2TE_UPD_TCPUDPCSUM_MODE_LBN 97 -#define ESF_DZ_C2TE_UPD_TCPUDPCSUM_MODE_WIDTH 1 -#define ESF_DZ_C2TE_UPD_IPCSUM_MODE_LBN 96 -#define ESF_DZ_C2TE_UPD_IPCSUM_MODE_WIDTH 1 -#define ESF_DZ_C2TE_PKT_LEN_LBN 64 -#define ESF_DZ_C2TE_PKT_LEN_WIDTH 16 -#define ESF_DZ_C2TE_FINFO_WRD3_LBN 48 -#define ESF_DZ_C2TE_FINFO_WRD3_WIDTH 16 -#define ESF_DZ_C2TE_FINFO_WRD2_LBN 32 -#define ESF_DZ_C2TE_FINFO_WRD2_WIDTH 16 -#define ESF_DZ_C2TE_FINFO_WRD1_LBN 16 -#define ESF_DZ_C2TE_FINFO_WRD1_WIDTH 16 -#define ESF_DZ_C2TE_FINFO_SRCDST_LBN 0 -#define ESF_DZ_C2TE_FINFO_SRCDST_WIDTH 16 - - -/* ES_FF_UMSG_CPU2TXDP_EGR_SOFT */ -#define ESF_DZ_C2TES_SOFT3_LBN 48 -#define ESF_DZ_C2TES_SOFT3_WIDTH 16 -#define ESF_DZ_C2TES_SOFT2_LBN 32 -#define ESF_DZ_C2TES_SOFT2_WIDTH 16 -#define ESF_DZ_C2TES_SOFT1_LBN 16 -#define ESF_DZ_C2TES_SOFT1_WIDTH 16 -#define ESF_DZ_C2TES_SOFT0_LBN 0 -#define ESF_DZ_C2TES_SOFT0_WIDTH 16 - - -/* ES_FF_UMSG_DL2CPU_DESC_FETCH */ -#define ESF_DZ_D2CDF_REFL_DSCR_HW_WPTR_LBN 64 -#define ESF_DZ_D2CDF_REFL_DSCR_HW_WPTR_WIDTH 12 -#define ESF_DZ_D2CDF_FAIL_LBN 48 -#define ESF_DZ_D2CDF_FAIL_WIDTH 1 -#define ESF_DZ_D2CDF_QID_LBN 32 -#define ESF_DZ_D2CDF_QID_WIDTH 11 -#define ESF_DZ_D2CDF_NUM_DESC_LBN 16 -#define ESF_DZ_D2CDF_NUM_DESC_WIDTH 7 -#define ESF_DZ_D2CDF_NEW_DSCR_HW_RPTR_LBN 0 -#define ESF_DZ_D2CDF_NEW_DSCR_HW_RPTR_WIDTH 12 - - -/* ES_FF_UMSG_DL2CPU_GPRD */ -#define ESF_DZ_D2CG_BIU_ARGS_LBN 0 -#define ESF_DZ_D2CG_BIU_ARGS_WIDTH 14 - - -/* ES_FF_UMSG_DPCPU_PACER_TXQ_D_R_I_REQ */ -#define ESF_DZ_FRM_LEN_LBN 16 -#define ESF_DZ_FRM_LEN_WIDTH 15 -#define ESF_DZ_TXQ_ID_LBN 0 -#define ESF_DZ_TXQ_ID_WIDTH 10 - - -/* ES_FF_UMSG_PACER_BKT_TBL_RD_REQ */ -#define ESF_DZ_BKT_ID_LBN 0 -#define ESF_DZ_BKT_ID_WIDTH 10 - - -/* ES_FF_UMSG_PACER_BKT_TBL_RD_RSP */ -#define ESF_DZ_DUE_TIME_LBN 80 -#define ESF_DZ_DUE_TIME_WIDTH 16 -#define ESF_DZ_LAST_FILL_TIME_LBN 64 -#define ESF_DZ_LAST_FILL_TIME_WIDTH 16 -#define ESF_DZ_RATE_REC_LBN 48 -#define ESF_DZ_RATE_REC_WIDTH 16 -#define ESF_DZ_RATE_LBN 32 -#define ESF_DZ_RATE_WIDTH 16 -#define ESF_DZ_FILL_LEVEL_LBN 16 -#define ESF_DZ_FILL_LEVEL_WIDTH 16 -#define ESF_DZ_IDLE_LBN 15 -#define ESF_DZ_IDLE_WIDTH 1 -#define ESF_DZ_USED_LBN 14 -#define ESF_DZ_USED_WIDTH 1 -#define ESF_DZ_MAX_FILL_REG_LBN 12 -#define ESF_DZ_MAX_FILL_REG_WIDTH 2 -#define ESF_DZ_BKT_ID_LBN 0 -#define ESF_DZ_BKT_ID_WIDTH 10 - - -/* ES_FF_UMSG_PACER_BKT_TBL_WR_REQ */ -#define ESF_DZ_RATE_REC_LBN 48 -#define ESF_DZ_RATE_REC_WIDTH 16 -#define ESF_DZ_RATE_LBN 32 -#define ESF_DZ_RATE_WIDTH 16 -#define ESF_DZ_FILL_LEVEL_LBN 16 -#define ESF_DZ_FILL_LEVEL_WIDTH 16 -#define ESF_DZ_IDLE_LBN 15 -#define ESF_DZ_IDLE_WIDTH 1 -#define ESF_DZ_USED_LBN 14 -#define ESF_DZ_USED_WIDTH 1 -#define ESF_DZ_MAX_FILL_REG_LBN 12 -#define ESF_DZ_MAX_FILL_REG_WIDTH 2 -#define ESF_DZ_BKT_ID_LBN 0 -#define ESF_DZ_BKT_ID_WIDTH 10 - - -/* ES_FF_UMSG_PACER_TXQ_TBL_RD_REQ */ -#define ESF_DZ_TXQ_ID_LBN 0 -#define ESF_DZ_TXQ_ID_WIDTH 10 - - -/* ES_FF_UMSG_PACER_TXQ_TBL_RD_RSP */ -#define ESF_DZ_MAX_BKT2_LBN 112 -#define ESF_DZ_MAX_BKT2_WIDTH 10 -#define ESF_DZ_MAX_BKT1_LBN 96 -#define ESF_DZ_MAX_BKT1_WIDTH 10 -#define ESF_DZ_MAX_BKT0_LBN 80 -#define ESF_DZ_MAX_BKT0_WIDTH 10 -#define ESF_DZ_MIN_BKT_LBN 64 -#define ESF_DZ_MIN_BKT_WIDTH 10 -#define ESF_DZ_LABEL_LBN 48 -#define ESF_DZ_LABEL_WIDTH 4 -#define ESF_DZ_PQ_FLAGS_LBN 32 -#define ESF_DZ_PQ_FLAGS_WIDTH 3 -#define ESF_DZ_DSBL_LBN 16 -#define ESF_DZ_DSBL_WIDTH 1 -#define ESF_DZ_TXQ_ID_LBN 0 -#define ESF_DZ_TXQ_ID_WIDTH 10 - - -/* ES_FF_UMSG_PACER_TXQ_TBL_WR_REQ */ -#define ESF_DZ_MAX_BKT2_LBN 112 -#define ESF_DZ_MAX_BKT2_WIDTH 10 -#define ESF_DZ_MAX_BKT1_LBN 96 -#define ESF_DZ_MAX_BKT1_WIDTH 10 -#define ESF_DZ_MAX_BKT0_LBN 80 -#define ESF_DZ_MAX_BKT0_WIDTH 10 -#define ESF_DZ_MIN_BKT_LBN 64 -#define ESF_DZ_MIN_BKT_WIDTH 10 -#define ESF_DZ_LABEL_LBN 48 -#define ESF_DZ_LABEL_WIDTH 4 -#define ESF_DZ_PQ_FLAGS_LBN 32 -#define ESF_DZ_PQ_FLAGS_WIDTH 3 -#define ESF_DZ_DSBL_LBN 16 -#define ESF_DZ_DSBL_WIDTH 1 -#define ESF_DZ_TXQ_ID_LBN 0 -#define ESF_DZ_TXQ_ID_WIDTH 10 - - -/* ES_FF_UMSG_PE */ -#define ESF_DZ_PE_PKT_OFST_LBN 47 -#define ESF_DZ_PE_PKT_OFST_WIDTH 17 -#define ESF_DZ_PE_PEDIT_DELTA_LBN 40 -#define ESF_DZ_PE_PEDIT_DELTA_WIDTH 8 -#define ESF_DZ_PE_PYLOAD_OFST_LBN 32 -#define ESF_DZ_PE_PYLOAD_OFST_WIDTH 8 -#define ESF_DZ_PE_L4_HDR_OFST_LBN 24 -#define ESF_DZ_PE_L4_HDR_OFST_WIDTH 8 -#define ESF_DZ_PE_L3_HDR_OFST_LBN 16 -#define ESF_DZ_PE_L3_HDR_OFST_WIDTH 8 -#define ESF_DZ_PE_HAVE_UDP_HDR_LBN 5 -#define ESF_DZ_PE_HAVE_UDP_HDR_WIDTH 1 -#define ESF_DZ_PE_HAVE_TCP_HDR_LBN 4 -#define ESF_DZ_PE_HAVE_TCP_HDR_WIDTH 1 -#define ESF_DZ_PE_HAVE_IPV6_HDR_LBN 3 -#define ESF_DZ_PE_HAVE_IPV6_HDR_WIDTH 1 -#define ESF_DZ_PE_HAVE_IPV4_HDR_LBN 2 -#define ESF_DZ_PE_HAVE_IPV4_HDR_WIDTH 1 -#define ESF_DZ_PE_HAVE_FCOE_LBN 1 -#define ESF_DZ_PE_HAVE_FCOE_WIDTH 1 -#define ESF_DZ_PE_PARSE_INCOMP_LBN 0 -#define ESF_DZ_PE_PARSE_INCOMP_WIDTH 1 - - -/* ES_FF_UMSG_RXDP_EGR2CPU_SOFT */ -#define ESF_DZ_RE2CS_SOFT3_LBN 48 -#define ESF_DZ_RE2CS_SOFT3_WIDTH 16 -#define ESF_DZ_RE2CS_SOFT2_LBN 32 -#define ESF_DZ_RE2CS_SOFT2_WIDTH 16 -#define ESF_DZ_RE2CS_SOFT1_LBN 16 -#define ESF_DZ_RE2CS_SOFT1_WIDTH 16 -#define ESF_DZ_RE2CS_SOFT0_LBN 0 -#define ESF_DZ_RE2CS_SOFT0_WIDTH 16 - - -/* ES_FF_UMSG_RXDP_INGR2CPU */ -#define ESF_DZ_RI2C_QUEUE_ID_LBN 224 -#define ESF_DZ_RI2C_QUEUE_ID_WIDTH 11 -#define ESF_DZ_RI2C_LEN_LBN 208 -#define ESF_DZ_RI2C_LEN_WIDTH 16 -#define ESF_DZ_RI2C_L4_CLASS_LBN 205 -#define ESF_DZ_RI2C_L4_CLASS_WIDTH 3 -#define ESF_DZ_RI2C_L3_CLASS_LBN 202 -#define ESF_DZ_RI2C_L3_CLASS_WIDTH 3 -#define ESF_DZ_RI2C_ETHTAG_CLASS_LBN 199 -#define ESF_DZ_RI2C_ETHTAG_CLASS_WIDTH 3 -#define ESF_DZ_RI2C_ETHBASE_CLASS_LBN 196 -#define ESF_DZ_RI2C_ETHBASE_CLASS_WIDTH 3 -#define ESF_DZ_RI2C_MAC_CLASS_LBN 195 -#define ESF_DZ_RI2C_MAC_CLASS_WIDTH 1 -#define ESF_DZ_RI2C_PKT_OFST_LBN 176 -#define ESF_DZ_RI2C_PKT_OFST_WIDTH 16 -#define ESF_DZ_RI2C_PEDIT_DELTA_LBN 168 -#define ESF_DZ_RI2C_PEDIT_DELTA_WIDTH 8 -#define ESF_DZ_RI2C_PYLOAD_OFST_LBN 160 -#define ESF_DZ_RI2C_PYLOAD_OFST_WIDTH 8 -#define ESF_DZ_RI2C_L4_HDR_OFST_LBN 152 -#define ESF_DZ_RI2C_L4_HDR_OFST_WIDTH 8 -#define ESF_DZ_RI2C_L3_HDR_OFST_LBN 144 -#define ESF_DZ_RI2C_L3_HDR_OFST_WIDTH 8 -#define ESF_DZ_RI2C_HAVE_UDP_HDR_LBN 133 -#define ESF_DZ_RI2C_HAVE_UDP_HDR_WIDTH 1 -#define ESF_DZ_RI2C_HAVE_TCP_HDR_LBN 132 -#define ESF_DZ_RI2C_HAVE_TCP_HDR_WIDTH 1 -#define ESF_DZ_RI2C_HAVE_IPV6_HDR_LBN 131 -#define ESF_DZ_RI2C_HAVE_IPV6_HDR_WIDTH 1 -#define ESF_DZ_RI2C_HAVE_IPV4_HDR_LBN 130 -#define ESF_DZ_RI2C_HAVE_IPV4_HDR_WIDTH 1 -#define ESF_DZ_RI2C_HAVE_FCOE_LBN 129 -#define ESF_DZ_RI2C_HAVE_FCOE_WIDTH 1 -#define ESF_DZ_RI2C_PARSE_INCOMP_LBN 128 -#define ESF_DZ_RI2C_PARSE_INCOMP_WIDTH 1 -#define ESF_DZ_RI2C_EFINFO_WRD3_LBN 112 -#define ESF_DZ_RI2C_EFINFO_WRD3_WIDTH 16 -#define ESF_DZ_RI2C_EFINFO_WRD2_LBN 96 -#define ESF_DZ_RI2C_EFINFO_WRD2_WIDTH 16 -#define ESF_DZ_RI2C_EFINFO_WRD1_LBN 80 -#define ESF_DZ_RI2C_EFINFO_WRD1_WIDTH 16 -#define ESF_DZ_RI2C_EFINFO_WRD0_LBN 64 -#define ESF_DZ_RI2C_EFINFO_WRD0_WIDTH 16 -#define ESF_DZ_RI2C_FINFO_WRD3_LBN 48 -#define ESF_DZ_RI2C_FINFO_WRD3_WIDTH 16 -#define ESF_DZ_RI2C_FINFO_WRD2_LBN 32 -#define ESF_DZ_RI2C_FINFO_WRD2_WIDTH 16 -#define ESF_DZ_RI2C_FINFO_WRD1_LBN 16 -#define ESF_DZ_RI2C_FINFO_WRD1_WIDTH 16 -#define ESF_DZ_RI2C_FINFO_SRCDST_LBN 0 -#define ESF_DZ_RI2C_FINFO_SRCDST_WIDTH 16 - - -/* ES_FF_UMSG_SMC2CPU_BUFLKUP */ -#define ESF_DZ_S2CB_ENCODED_PAGE_ADDR_DW0_LBN 0 -#define ESF_DZ_S2CB_ENCODED_PAGE_ADDR_DW0_WIDTH 32 -#define ESF_DZ_S2CB_ENCODED_PAGE_ADDR_DW1_LBN 32 -#define ESF_DZ_S2CB_ENCODED_PAGE_ADDR_DW1_WIDTH 16 -#define ESF_DZ_S2CB_ENCODED_PAGE_ADDR_LBN 0 -#define ESF_DZ_S2CB_ENCODED_PAGE_ADDR_WIDTH 48 -#define ESF_DZ_S2CB_FAIL_LBN 32 -#define ESF_DZ_S2CB_FAIL_WIDTH 1 - - -/* ES_FF_UMSG_SMC2CPU_DESCRD */ -#define ESF_DZ_S2CD_BUF_LEN_LBN 112 -#define ESF_DZ_S2CD_BUF_LEN_WIDTH 14 -#define ESF_DZ_S2CD_ENCODED_HOST_ADDR_DW0_LBN 64 -#define ESF_DZ_S2CD_ENCODED_HOST_ADDR_DW0_WIDTH 32 -#define ESF_DZ_S2CD_ENCODED_HOST_ADDR_DW1_LBN 96 -#define ESF_DZ_S2CD_ENCODED_HOST_ADDR_DW1_WIDTH 16 -#define ESF_DZ_S2CD_ENCODED_HOST_ADDR_LBN 64 -#define ESF_DZ_S2CD_ENCODED_HOST_ADDR_WIDTH 48 -#define ESF_DZ_S2CD_CONT_LBN 16 -#define ESF_DZ_S2CD_CONT_WIDTH 1 -#define ESF_DZ_S2CD_TYPE_LBN 0 -#define ESF_DZ_S2CD_TYPE_WIDTH 1 - - -/* ES_FF_UMSG_SMC2CPU_GPRD */ -#define ESF_DZ_S2CG_DATA_DW0_LBN 64 -#define ESF_DZ_S2CG_DATA_DW0_WIDTH 32 -#define ESF_DZ_S2CG_DATA_DW1_LBN 96 -#define ESF_DZ_S2CG_DATA_DW1_WIDTH 32 -#define ESF_DZ_S2CG_DATA_LBN 64 -#define ESF_DZ_S2CG_DATA_WIDTH 64 -#define ESF_DZ_S2CG_SOFT_LBN 48 -#define ESF_DZ_S2CG_SOFT_WIDTH 4 -#define ESF_DZ_S2CG_FAIL_LBN 32 -#define ESF_DZ_S2CG_FAIL_WIDTH 1 - - -/* ES_FF_UMSG_TXDP_DMA2CPU_PKTRDY */ -#define ESF_DZ_TD2CP_L4_CLASS_LBN 250 -#define ESF_DZ_TD2CP_L4_CLASS_WIDTH 3 -#define ESF_DZ_TD2CP_L3_CLASS_LBN 247 -#define ESF_DZ_TD2CP_L3_CLASS_WIDTH 3 -#define ESF_DZ_TD2CP_ETHTAG_CLASS_LBN 244 -#define ESF_DZ_TD2CP_ETHTAG_CLASS_WIDTH 3 -#define ESF_DZ_TD2CP_ETHBASE_CLASS_LBN 241 -#define ESF_DZ_TD2CP_ETHBASE_CLASS_WIDTH 3 -#define ESF_DZ_TD2CP_MAC_CLASS_LBN 240 -#define ESF_DZ_TD2CP_MAC_CLASS_WIDTH 1 -#define ESF_DZ_TD2CP_PCIE_ERR_OR_ABORT_LBN 239 -#define ESF_DZ_TD2CP_PCIE_ERR_OR_ABORT_WIDTH 1 -#define ESF_DZ_TD2CP_PKT_ABORT_LBN 238 -#define ESF_DZ_TD2CP_PKT_ABORT_WIDTH 1 -#define ESF_DZ_TD2CP_SOFT_LBN 224 -#define ESF_DZ_TD2CP_SOFT_WIDTH 14 -#define ESF_DZ_TD2CP_DESC_IDX_LBN 208 -#define ESF_DZ_TD2CP_DESC_IDX_WIDTH 16 -#define ESF_DZ_TD2CP_PKT_LEN_LBN 192 -#define ESF_DZ_TD2CP_PKT_LEN_WIDTH 16 -#define ESF_DZ_TD2CP_PKT_OFFST_OR_FIRST_DESC_IDX_LBN 176 -#define ESF_DZ_TD2CP_PKT_OFFST_OR_FIRST_DESC_IDX_WIDTH 7 -#define ESF_DZ_TD2CP_PEDIT_DELTA_LBN 168 -#define ESF_DZ_TD2CP_PEDIT_DELTA_WIDTH 8 -#define ESF_DZ_TD2CP_PYLOAD_OFST_LBN 160 -#define ESF_DZ_TD2CP_PYLOAD_OFST_WIDTH 8 -#define ESF_DZ_TD2CP_L4_HDR_OFST_LBN 152 -#define ESF_DZ_TD2CP_L4_HDR_OFST_WIDTH 8 -#define ESF_DZ_TD2CP_L3_HDR_OFST_LBN 144 -#define ESF_DZ_TD2CP_L3_HDR_OFST_WIDTH 8 -#define ESF_DZ_TD2CP_IS_UDP_LBN 133 -#define ESF_DZ_TD2CP_IS_UDP_WIDTH 1 -#define ESF_DZ_TD2CP_IS_TCP_LBN 132 -#define ESF_DZ_TD2CP_IS_TCP_WIDTH 1 -#define ESF_DZ_TD2CP_IS_IPV6_LBN 131 -#define ESF_DZ_TD2CP_IS_IPV6_WIDTH 1 -#define ESF_DZ_TD2CP_IS_IPV4_LBN 130 -#define ESF_DZ_TD2CP_IS_IPV4_WIDTH 1 -#define ESF_DZ_TD2CP_IS_FCOE_LBN 129 -#define ESF_DZ_TD2CP_IS_FCOE_WIDTH 1 -#define ESF_DZ_TD2CP_PARSE_INCOMP_LBN 128 -#define ESF_DZ_TD2CP_PARSE_INCOMP_WIDTH 1 -#define ESF_DZ_TD2CP_EFINFO_WRD3_LBN 112 -#define ESF_DZ_TD2CP_EFINFO_WRD3_WIDTH 16 -#define ESF_DZ_TD2CP_EFINFO_WRD2_LBN 96 -#define ESF_DZ_TD2CP_EFINFO_WRD2_WIDTH 16 -#define ESF_DZ_TD2CP_EFINFO_WRD1_LBN 80 -#define ESF_DZ_TD2CP_EFINFO_WRD1_WIDTH 16 -#define ESF_DZ_TD2CP_EFINFO_WRD0_LBN 64 -#define ESF_DZ_TD2CP_EFINFO_WRD0_WIDTH 16 -#define ESF_DZ_TD2CP_FINFO_WRD3_LBN 48 -#define ESF_DZ_TD2CP_FINFO_WRD3_WIDTH 16 -#define ESF_DZ_TD2CP_FINFO_WRD2_LBN 32 -#define ESF_DZ_TD2CP_FINFO_WRD2_WIDTH 16 -#define ESF_DZ_TD2CP_FINFO_WRD1_LBN 16 -#define ESF_DZ_TD2CP_FINFO_WRD1_WIDTH 16 -#define ESF_DZ_TD2CP_FINFO_SRCDST_LBN 0 -#define ESF_DZ_TD2CP_FINFO_SRCDST_WIDTH 16 - - -/* ES_FF_UMSG_TXDP_DMA2CPU_SOFT */ -#define ESF_DZ_TD2CS_SOFT3_LBN 48 -#define ESF_DZ_TD2CS_SOFT3_WIDTH 16 -#define ESF_DZ_TD2CS_SOFT2_LBN 32 -#define ESF_DZ_TD2CS_SOFT2_WIDTH 16 -#define ESF_DZ_TD2CS_SOFT1_LBN 16 -#define ESF_DZ_TD2CS_SOFT1_WIDTH 16 -#define ESF_DZ_TD2CS_SOFT0_LBN 0 -#define ESF_DZ_TD2CS_SOFT0_WIDTH 16 - - -/* ES_FF_UMSG_TXDP_EGR2CPU_SOFT */ -#define ESF_DZ_TE2CS_SOFT3_LBN 48 -#define ESF_DZ_TE2CS_SOFT3_WIDTH 16 -#define ESF_DZ_TE2CS_SOFT2_LBN 32 -#define ESF_DZ_TE2CS_SOFT2_WIDTH 16 -#define ESF_DZ_TE2CS_SOFT1_LBN 16 -#define ESF_DZ_TE2CS_SOFT1_WIDTH 16 -#define ESF_DZ_TE2CS_SOFT0_LBN 0 -#define ESF_DZ_TE2CS_SOFT0_WIDTH 16 - - -/* ES_FF_UMSG_VICTL2CPU */ -#define ESF_DZ_V2C_DESC_WORD3_LBN 112 -#define ESF_DZ_V2C_DESC_WORD3_WIDTH 17 -#define ESF_DZ_V2C_DESC_WORD2_LBN 96 -#define ESF_DZ_V2C_DESC_WORD2_WIDTH 16 -#define ESF_DZ_V2C_DESC_WORD1_LBN 80 -#define ESF_DZ_V2C_DESC_WORD1_WIDTH 16 -#define ESF_DZ_V2C_DESC_WORD0_LBN 64 -#define ESF_DZ_V2C_DESC_WORD0_WIDTH 16 -#define ESF_DZ_V2C_NEW_DSCR_WPTR_LBN 32 -#define ESF_DZ_V2C_NEW_DSCR_WPTR_WIDTH 12 -#define ESF_DZ_V2C_DESC_PUSH_LBN 16 -#define ESF_DZ_V2C_DESC_PUSH_WIDTH 1 - - -/* ES_LUE_DB_MATCH_ENTRY */ -#define ESF_DZ_LUE_DSCRMNTR_LBN 140 -#define ESF_DZ_LUE_DSCRMNTR_WIDTH 6 -#define ESF_DZ_LUE_MATCH_VAL_DW0_LBN 44 -#define ESF_DZ_LUE_MATCH_VAL_DW0_WIDTH 32 -#define ESF_DZ_LUE_MATCH_VAL_DW1_LBN 76 -#define ESF_DZ_LUE_MATCH_VAL_DW1_WIDTH 32 -#define ESF_DZ_LUE_MATCH_VAL_DW2_LBN 108 -#define ESF_DZ_LUE_MATCH_VAL_DW2_WIDTH 32 -#define ESF_DZ_LUE_MATCH_VAL_LBN 44 -#define ESF_DZ_LUE_MATCH_VAL_WIDTH 96 -#define ESF_DZ_LUE_ME_SOFT_LBN 35 -#define ESF_DZ_LUE_ME_SOFT_WIDTH 9 -#define ESF_DZ_LUE_TX_MCAST_LBN 33 -#define ESF_DZ_LUE_TX_MCAST_WIDTH 2 -#define ESF_DZ_LUE_TX_DOMAIN_LBN 25 -#define ESF_DZ_LUE_TX_DOMAIN_WIDTH 8 -#define ESF_DZ_LUE_RX_MCAST_LBN 24 -#define ESF_DZ_LUE_RX_MCAST_WIDTH 1 -#define ESE_DZ_LUE_MULTI 1 -#define ESE_DZ_LUE_SINGLE 0 -#define ESF_DZ_LUE_RCPNTR_LBN 0 -#define ESF_DZ_LUE_RCPNTR_WIDTH 24 - - -/* ES_LUE_DB_NONMATCH_ENTRY */ -#define ESF_DZ_LUE_DSCRMNTR_LBN 140 -#define ESF_DZ_LUE_DSCRMNTR_WIDTH 6 -#define ESF_DZ_LUE_TERMINAL_LBN 139 -#define ESF_DZ_LUE_TERMINAL_WIDTH 1 -#define ESF_DZ_LUE_LAST_LBN 138 -#define ESF_DZ_LUE_LAST_WIDTH 1 -#define ESF_DZ_LUE_NE_SOFT_LBN 137 -#define ESF_DZ_LUE_NE_SOFT_WIDTH 1 -#define ESF_DZ_LUE_RCPNTR_NUM_LBN 134 -#define ESF_DZ_LUE_RCPNTR_NUM_WIDTH 3 -#define ESF_DZ_LUE_RCPNTR0_LBN 110 -#define ESF_DZ_LUE_RCPNTR0_WIDTH 24 -#define ESF_DZ_LUE_RCPNTR1_LBN 86 -#define ESF_DZ_LUE_RCPNTR1_WIDTH 24 -#define ESF_DZ_LUE_RCPNTR2_LBN 62 -#define ESF_DZ_LUE_RCPNTR2_WIDTH 24 -#define ESF_DZ_LUE_RCPNTR3_LBN 38 -#define ESF_DZ_LUE_RCPNTR3_WIDTH 24 -#define ESF_DZ_LUE_RCPNTR4_LBN 14 -#define ESF_DZ_LUE_RCPNTR4_WIDTH 24 -#define ESF_DZ_LUE_RCPNTR_NE_PTR_LBN 0 -#define ESF_DZ_LUE_RCPNTR_NE_PTR_WIDTH 14 - - -/* ES_LUE_MC_DIRECT_REQUEST_MSG */ -#define ESF_DZ_MC2L_DR_PAD_DW0_LBN 22 -#define ESF_DZ_MC2L_DR_PAD_DW0_WIDTH 32 -#define ESF_DZ_MC2L_DR_PAD_DW1_LBN 54 -#define ESF_DZ_MC2L_DR_PAD_DW1_WIDTH 32 -#define ESF_DZ_MC2L_DR_PAD_DW2_LBN 86 -#define ESF_DZ_MC2L_DR_PAD_DW2_WIDTH 32 -#define ESF_DZ_MC2L_DR_PAD_DW3_LBN 118 -#define ESF_DZ_MC2L_DR_PAD_DW3_WIDTH 32 -#define ESF_DZ_MC2L_DR_PAD_DW4_LBN 150 -#define ESF_DZ_MC2L_DR_PAD_DW4_WIDTH 18 -#define ESF_DZ_MC2L_DR_PAD_LBN 22 -#define ESF_DZ_MC2L_DR_PAD_WIDTH 146 -#define ESF_DZ_MC2L_DR_ADDR_LBN 8 -#define ESF_DZ_MC2L_DR_ADDR_WIDTH 14 -#define ESF_DZ_MC2L_DR_THREAD_ID_LBN 5 -#define ESF_DZ_MC2L_DR_THREAD_ID_WIDTH 3 -#define ESF_DZ_MC2L_DR_CLIENT_ID_LBN 2 -#define ESF_DZ_MC2L_DR_CLIENT_ID_WIDTH 3 -#define ESF_DZ_MC2L_DR_OP_LBN 0 -#define ESF_DZ_MC2L_DR_OP_WIDTH 2 -#define ESE_DZ_LUE_GP_WR 3 -#define ESE_DZ_LUE_GP_RD 2 -#define ESE_DZ_LUE_DIR_REQ 1 -#define ESE_DZ_LUE_MATCH_REQ 0 - - -/* ES_LUE_MC_DIRECT_RESPONSE_MSG */ -#define ESF_DZ_L2MC_DR_PAD_LBN 146 -#define ESF_DZ_L2MC_DR_PAD_WIDTH 8 -#define ESF_DZ_L2MC_DR_RCPNT_PTR_LBN 132 -#define ESF_DZ_L2MC_DR_RCPNT_PTR_WIDTH 14 -#define ESF_DZ_L2MC_DR_RCPNT4_LBN 108 -#define ESF_DZ_L2MC_DR_RCPNT4_WIDTH 24 -#define ESF_DZ_L2MC_DR_RCPNT3_LBN 84 -#define ESF_DZ_L2MC_DR_RCPNT3_WIDTH 24 -#define ESF_DZ_L2MC_DR_RCPNT2_LBN 60 -#define ESF_DZ_L2MC_DR_RCPNT2_WIDTH 24 -#define ESF_DZ_L2MC_DR_RCPNT1_LBN 36 -#define ESF_DZ_L2MC_DR_RCPNT1_WIDTH 24 -#define ESF_DZ_L2MC_DR_RCPNT0_LBN 12 -#define ESF_DZ_L2MC_DR_RCPNT0_WIDTH 24 -#define ESF_DZ_L2MC_DR_RCPNT_NUM_LBN 9 -#define ESF_DZ_L2MC_DR_RCPNT_NUM_WIDTH 3 -#define ESF_DZ_L2MC_DR_LAST_LBN 8 -#define ESF_DZ_L2MC_DR_LAST_WIDTH 1 -#define ESF_DZ_L2MC_DR_THREAD_ID_LBN 5 -#define ESF_DZ_L2MC_DR_THREAD_ID_WIDTH 3 -#define ESF_DZ_L2MC_DR_CLIENT_ID_LBN 2 -#define ESF_DZ_L2MC_DR_CLIENT_ID_WIDTH 3 -#define ESF_DZ_L2MC_DR_OP_LBN 0 -#define ESF_DZ_L2MC_DR_OP_WIDTH 2 -#define ESE_DZ_LUE_GP_WR 3 -#define ESE_DZ_LUE_GP_RD 2 -#define ESE_DZ_LUE_DIR_REQ 1 -#define ESE_DZ_LUE_MATCH_REQ 0 - - -/* ES_LUE_MC_GP_RD_REQUEST_MSG */ -#define ESF_DZ_MC2L_GPR_PAD_DW0_LBN 22 -#define ESF_DZ_MC2L_GPR_PAD_DW0_WIDTH 32 -#define ESF_DZ_MC2L_GPR_PAD_DW1_LBN 54 -#define ESF_DZ_MC2L_GPR_PAD_DW1_WIDTH 32 -#define ESF_DZ_MC2L_GPR_PAD_DW2_LBN 86 -#define ESF_DZ_MC2L_GPR_PAD_DW2_WIDTH 32 -#define ESF_DZ_MC2L_GPR_PAD_DW3_LBN 118 -#define ESF_DZ_MC2L_GPR_PAD_DW3_WIDTH 32 -#define ESF_DZ_MC2L_GPR_PAD_DW4_LBN 150 -#define ESF_DZ_MC2L_GPR_PAD_DW4_WIDTH 18 -#define ESF_DZ_MC2L_GPR_PAD_LBN 22 -#define ESF_DZ_MC2L_GPR_PAD_WIDTH 146 -#define ESF_DZ_MC2L_GPR_ADDR_LBN 8 -#define ESF_DZ_MC2L_GPR_ADDR_WIDTH 14 -#define ESF_DZ_MC2L_GPR_THREAD_ID_LBN 5 -#define ESF_DZ_MC2L_GPR_THREAD_ID_WIDTH 3 -#define ESF_DZ_MC2L_GPR_CLIENT_ID_LBN 2 -#define ESF_DZ_MC2L_GPR_CLIENT_ID_WIDTH 3 -#define ESF_DZ_MC2L_GPR_OP_LBN 0 -#define ESF_DZ_MC2L_GPR_OP_WIDTH 2 -#define ESE_DZ_LUE_GP_WR 3 -#define ESE_DZ_LUE_GP_RD 2 -#define ESE_DZ_LUE_DIR_REQ 1 -#define ESE_DZ_LUE_MATCH_REQ 0 - - -/* ES_LUE_MC_GP_RD_RESPONSE_MSG */ -#define ESF_DZ_L2MC_GPR_DATA_DW0_LBN 8 -#define ESF_DZ_L2MC_GPR_DATA_DW0_WIDTH 32 -#define ESF_DZ_L2MC_GPR_DATA_DW1_LBN 40 -#define ESF_DZ_L2MC_GPR_DATA_DW1_WIDTH 32 -#define ESF_DZ_L2MC_GPR_DATA_DW2_LBN 72 -#define ESF_DZ_L2MC_GPR_DATA_DW2_WIDTH 32 -#define ESF_DZ_L2MC_GPR_DATA_DW3_LBN 104 -#define ESF_DZ_L2MC_GPR_DATA_DW3_WIDTH 32 -#define ESF_DZ_L2MC_GPR_DATA_DW4_LBN 136 -#define ESF_DZ_L2MC_GPR_DATA_DW4_WIDTH 18 -#define ESF_DZ_L2MC_GPR_DATA_LBN 8 -#define ESF_DZ_L2MC_GPR_DATA_WIDTH 146 -#define ESF_DZ_L2MC_GPR_THREAD_ID_LBN 5 -#define ESF_DZ_L2MC_GPR_THREAD_ID_WIDTH 3 -#define ESF_DZ_L2MC_GPR_CLIENT_ID_LBN 2 -#define ESF_DZ_L2MC_GPR_CLIENT_ID_WIDTH 3 -#define ESF_DZ_L2MC_GPR_OP_LBN 0 -#define ESF_DZ_L2MC_GPR_OP_WIDTH 2 -#define ESE_DZ_LUE_GP_WR 3 -#define ESE_DZ_LUE_GP_RD 2 -#define ESE_DZ_LUE_DIR_REQ 1 -#define ESE_DZ_LUE_MATCH_REQ 0 - - -/* ES_LUE_MC_GP_WR_REQUEST_MSG */ -#define ESF_DZ_MC2L_GPW_DATA_DW0_LBN 22 -#define ESF_DZ_MC2L_GPW_DATA_DW0_WIDTH 32 -#define ESF_DZ_MC2L_GPW_DATA_DW1_LBN 54 -#define ESF_DZ_MC2L_GPW_DATA_DW1_WIDTH 32 -#define ESF_DZ_MC2L_GPW_DATA_DW2_LBN 86 -#define ESF_DZ_MC2L_GPW_DATA_DW2_WIDTH 32 -#define ESF_DZ_MC2L_GPW_DATA_DW3_LBN 118 -#define ESF_DZ_MC2L_GPW_DATA_DW3_WIDTH 32 -#define ESF_DZ_MC2L_GPW_DATA_DW4_LBN 150 -#define ESF_DZ_MC2L_GPW_DATA_DW4_WIDTH 18 -#define ESF_DZ_MC2L_GPW_DATA_LBN 22 -#define ESF_DZ_MC2L_GPW_DATA_WIDTH 146 -#define ESF_DZ_MC2L_GPW_ADDR_LBN 8 -#define ESF_DZ_MC2L_GPW_ADDR_WIDTH 14 -#define ESF_DZ_MC2L_GPW_THREAD_ID_LBN 5 -#define ESF_DZ_MC2L_GPW_THREAD_ID_WIDTH 3 -#define ESF_DZ_MC2L_GPW_CLIENT_ID_LBN 2 -#define ESF_DZ_MC2L_GPW_CLIENT_ID_WIDTH 3 -#define ESF_DZ_MC2L_GPW_OP_LBN 0 -#define ESF_DZ_MC2L_GPW_OP_WIDTH 2 -#define ESE_DZ_LUE_GP_WR 3 -#define ESE_DZ_LUE_GP_RD 2 -#define ESE_DZ_LUE_DIR_REQ 1 -#define ESE_DZ_LUE_MATCH_REQ 0 - - -/* ES_LUE_MC_MATCH_REQUEST_MSG */ -#define ESF_DZ_MC2L_MR_PAD_LBN 137 -#define ESF_DZ_MC2L_MR_PAD_WIDTH 31 -#define ESF_DZ_MC2L_MR_HASH2_LBN 124 -#define ESF_DZ_MC2L_MR_HASH2_WIDTH 13 -#define ESF_DZ_MC2L_MR_HASH1_LBN 110 -#define ESF_DZ_MC2L_MR_HASH1_WIDTH 14 -#define ESF_DZ_MC2L_MR_MATCH_BITS_DW0_LBN 14 -#define ESF_DZ_MC2L_MR_MATCH_BITS_DW0_WIDTH 32 -#define ESF_DZ_MC2L_MR_MATCH_BITS_DW1_LBN 46 -#define ESF_DZ_MC2L_MR_MATCH_BITS_DW1_WIDTH 32 -#define ESF_DZ_MC2L_MR_MATCH_BITS_DW2_LBN 78 -#define ESF_DZ_MC2L_MR_MATCH_BITS_DW2_WIDTH 32 -#define ESF_DZ_MC2L_MR_MATCH_BITS_LBN 14 -#define ESF_DZ_MC2L_MR_MATCH_BITS_WIDTH 96 -#define ESF_DZ_MC2L_MR_DSCRMNTR_LBN 8 -#define ESF_DZ_MC2L_MR_DSCRMNTR_WIDTH 6 -#define ESF_DZ_MC2L_MR_THREAD_ID_LBN 5 -#define ESF_DZ_MC2L_MR_THREAD_ID_WIDTH 3 -#define ESF_DZ_MC2L_MR_CLIENT_ID_LBN 2 -#define ESF_DZ_MC2L_MR_CLIENT_ID_WIDTH 3 -#define ESF_DZ_MC2L_MR_OP_LBN 0 -#define ESF_DZ_MC2L_MR_OP_WIDTH 2 -#define ESE_DZ_LUE_GP_WR 3 -#define ESE_DZ_LUE_GP_RD 2 -#define ESE_DZ_LUE_DIR_REQ 1 -#define ESE_DZ_LUE_MATCH_REQ 0 - - -/* ES_LUE_MC_MATCH_RESPONSE_MSG */ -#define ESF_DZ_L2MC_MR_PAD_DW0_LBN 53 -#define ESF_DZ_L2MC_MR_PAD_DW0_WIDTH 32 -#define ESF_DZ_L2MC_MR_PAD_DW1_LBN 85 -#define ESF_DZ_L2MC_MR_PAD_DW1_WIDTH 32 -#define ESF_DZ_L2MC_MR_PAD_DW2_LBN 117 -#define ESF_DZ_L2MC_MR_PAD_DW2_WIDTH 32 -#define ESF_DZ_L2MC_MR_PAD_DW3_LBN 149 -#define ESF_DZ_L2MC_MR_PAD_DW3_WIDTH 5 -#define ESF_DZ_L2MC_MR_PAD_LBN 53 -#define ESF_DZ_L2MC_MR_PAD_WIDTH 101 -#define ESF_DZ_L2MC_MR_LUE_RCPNT_LBN 29 -#define ESF_DZ_L2MC_MR_LUE_RCPNT_WIDTH 24 -#define ESF_DZ_L2MC_MR_RX_MCAST_LBN 28 -#define ESF_DZ_L2MC_MR_RX_MCAST_WIDTH 1 -#define ESF_DZ_L2MC_MR_TX_DOMAIN_LBN 20 -#define ESF_DZ_L2MC_MR_TX_DOMAIN_WIDTH 8 -#define ESF_DZ_L2MC_MR_TX_MCAST_LBN 18 -#define ESF_DZ_L2MC_MR_TX_MCAST_WIDTH 2 -#define ESF_DZ_L2MC_MR_SOFT_LBN 9 -#define ESF_DZ_L2MC_MR_SOFT_WIDTH 9 -#define ESF_DZ_L2MC_MR_MATCH_LBN 8 -#define ESF_DZ_L2MC_MR_MATCH_WIDTH 1 -#define ESF_DZ_L2MC_MR_THREAD_ID_LBN 5 -#define ESF_DZ_L2MC_MR_THREAD_ID_WIDTH 3 -#define ESF_DZ_L2MC_MR_CLIENT_ID_LBN 2 -#define ESF_DZ_L2MC_MR_CLIENT_ID_WIDTH 3 -#define ESF_DZ_L2MC_MR_OP_LBN 0 -#define ESF_DZ_L2MC_MR_OP_WIDTH 2 -#define ESE_DZ_LUE_GP_WR 3 -#define ESE_DZ_LUE_GP_RD 2 -#define ESE_DZ_LUE_DIR_REQ 1 -#define ESE_DZ_LUE_MATCH_REQ 0 - - -/* ES_LUE_MSG_BASE_REQ */ -#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW0_LBN 8 -#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW0_WIDTH 32 -#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW1_LBN 40 -#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW1_WIDTH 32 -#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW2_LBN 72 -#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW2_WIDTH 32 -#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW3_LBN 104 -#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW3_WIDTH 32 -#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW4_LBN 136 -#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW4_WIDTH 32 -#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_LBN 8 -#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_WIDTH 160 -#define ESF_DZ_LUE_HW_REQ_BASE_THREAD_ID_LBN 5 -#define ESF_DZ_LUE_HW_REQ_BASE_THREAD_ID_WIDTH 3 -#define ESF_DZ_LUE_HW_REQ_BASE_CLIENT_ID_LBN 2 -#define ESF_DZ_LUE_HW_REQ_BASE_CLIENT_ID_WIDTH 3 -#define ESE_DZ_LUE_MC_ID 7 -#define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 -#define ESE_DZ_LUE_TX_DICPU_ID 1 -#define ESE_DZ_LUE_RX_DICPU_ID 0 -#define ESF_DZ_LUE_HW_REQ_BASE_OP_LBN 0 -#define ESF_DZ_LUE_HW_REQ_BASE_OP_WIDTH 2 -#define ESE_DZ_LUE_GP_WR 3 -#define ESE_DZ_LUE_GP_RD 2 -#define ESE_DZ_LUE_DIR_REQ 1 -#define ESE_DZ_LUE_MATCH_REQ 0 - - -/* ES_LUE_MSG_BASE_RESP */ -#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW0_LBN 8 -#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW0_WIDTH 32 -#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW1_LBN 40 -#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW1_WIDTH 32 -#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW2_LBN 72 -#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW2_WIDTH 32 -#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW3_LBN 104 -#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW3_WIDTH 32 -#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW4_LBN 136 -#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW4_WIDTH 18 -#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_LBN 8 -#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_WIDTH 146 -#define ESF_DZ_LUE_HW_RSP_BASE_THREAD_ID_LBN 5 -#define ESF_DZ_LUE_HW_RSP_BASE_THREAD_ID_WIDTH 3 -#define ESF_DZ_LUE_HW_RSP_BASE_CLIENT_ID_LBN 2 -#define ESF_DZ_LUE_HW_RSP_BASE_CLIENT_ID_WIDTH 3 -#define ESE_DZ_LUE_MC_ID 7 -#define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 -#define ESE_DZ_LUE_TX_DICPU_ID 1 -#define ESE_DZ_LUE_RX_DICPU_ID 0 -#define ESF_DZ_LUE_HW_RSP_BASE_OP_LBN 0 -#define ESF_DZ_LUE_HW_RSP_BASE_OP_WIDTH 2 -#define ESE_DZ_LUE_GP_WR 3 -#define ESE_DZ_LUE_GP_RD 2 -#define ESE_DZ_LUE_DIR_REQ 1 -#define ESE_DZ_LUE_MATCH_REQ 0 - - -/* ES_LUE_MSG_DIRECT_REQ */ -#define ESF_DZ_LUE_HW_REQ_DIR_ADDR_LBN 8 -#define ESF_DZ_LUE_HW_REQ_DIR_ADDR_WIDTH 14 -#define ESF_DZ_LUE_HW_REQ_DIR_THREAD_ID_LBN 5 -#define ESF_DZ_LUE_HW_REQ_DIR_THREAD_ID_WIDTH 3 -#define ESF_DZ_LUE_HW_REQ_DIR_CLIENT_ID_LBN 2 -#define ESF_DZ_LUE_HW_REQ_DIR_CLIENT_ID_WIDTH 3 -#define ESE_DZ_LUE_MC_ID 7 -#define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 -#define ESE_DZ_LUE_TX_DICPU_ID 1 -#define ESE_DZ_LUE_RX_DICPU_ID 0 -#define ESF_DZ_LUE_HW_REQ_DIR_OP_LBN 0 -#define ESF_DZ_LUE_HW_REQ_DIR_OP_WIDTH 2 -#define ESE_DZ_LUE_GP_WR 3 -#define ESE_DZ_LUE_GP_RD 2 -#define ESE_DZ_LUE_DIR_REQ 1 -#define ESE_DZ_LUE_MATCH_REQ 0 - - -/* ES_LUE_MSG_DIRECT_RESP */ -#define ESF_DZ_LUE_HW_RSP_DIR_RCPNT_PTR_LBN 132 -#define ESF_DZ_LUE_HW_RSP_DIR_RCPNT_PTR_WIDTH 14 -#define ESF_DZ_LUE_HW_RSP_DIR_RCPNT4_LBN 108 -#define ESF_DZ_LUE_HW_RSP_DIR_RCPNT4_WIDTH 24 -#define ESF_DZ_LUE_HW_RSP_DIR_RCPNT3_LBN 84 -#define ESF_DZ_LUE_HW_RSP_DIR_RCPNT3_WIDTH 24 -#define ESF_DZ_LUE_HW_RSP_DIR_RCPNT2_LBN 60 -#define ESF_DZ_LUE_HW_RSP_DIR_RCPNT2_WIDTH 24 -#define ESF_DZ_LUE_HW_RSP_DIR_RCPNT1_LBN 36 -#define ESF_DZ_LUE_HW_RSP_DIR_RCPNT1_WIDTH 24 -#define ESF_DZ_LUE_HW_RSP_DIR_RCPNT0_LBN 12 -#define ESF_DZ_LUE_HW_RSP_DIR_RCPNT0_WIDTH 24 -#define ESF_DZ_LUE_HW_RSP_DIR_RCPNT_NUM_LBN 9 -#define ESF_DZ_LUE_HW_RSP_DIR_RCPNT_NUM_WIDTH 3 -#define ESF_DZ_LUE_HW_RSP_DIR_LAST_LBN 8 -#define ESF_DZ_LUE_HW_RSP_DIR_LAST_WIDTH 1 -#define ESF_DZ_LUE_HW_RSP_DIR_THREAD_ID_LBN 5 -#define ESF_DZ_LUE_HW_RSP_DIR_THREAD_ID_WIDTH 3 -#define ESF_DZ_LUE_HW_RSP_DIR_CLIENT_ID_LBN 2 -#define ESF_DZ_LUE_HW_RSP_DIR_CLIENT_ID_WIDTH 3 -#define ESE_DZ_LUE_MC_ID 7 -#define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 -#define ESE_DZ_LUE_TX_DICPU_ID 1 -#define ESE_DZ_LUE_RX_DICPU_ID 0 -#define ESF_DZ_LUE_HW_RSP_DIR_OP_LBN 0 -#define ESF_DZ_LUE_HW_RSP_DIR_OP_WIDTH 2 -#define ESE_DZ_LUE_GP_WR 3 -#define ESE_DZ_LUE_GP_RD 2 -#define ESE_DZ_LUE_DIR_REQ 1 -#define ESE_DZ_LUE_MATCH_REQ 0 - - -/* ES_LUE_MSG_GP_RD_REQ */ -#define ESF_DZ_LUE_HW_REQ_GPRD_ADDR_LBN 8 -#define ESF_DZ_LUE_HW_REQ_GPRD_ADDR_WIDTH 14 -#define ESF_DZ_LUE_HW_REQ_GPRD_THREAD_ID_LBN 5 -#define ESF_DZ_LUE_HW_REQ_GPRD_THREAD_ID_WIDTH 3 -#define ESF_DZ_LUE_HW_REQ_GPRD_CLIENT_ID_LBN 2 -#define ESF_DZ_LUE_HW_REQ_GPRD_CLIENT_ID_WIDTH 3 -#define ESE_DZ_LUE_MC_ID 7 -#define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 -#define ESE_DZ_LUE_TX_DICPU_ID 1 -#define ESE_DZ_LUE_RX_DICPU_ID 0 -#define ESF_DZ_LUE_HW_REQ_GPRD_OP_LBN 0 -#define ESF_DZ_LUE_HW_REQ_GPRD_OP_WIDTH 2 -#define ESE_DZ_LUE_GP_WR 3 -#define ESE_DZ_LUE_GP_RD 2 -#define ESE_DZ_LUE_DIR_REQ 1 -#define ESE_DZ_LUE_MATCH_REQ 0 - - -/* ES_LUE_MSG_GP_RD_RESP */ -#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW0_LBN 8 -#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW0_WIDTH 32 -#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW1_LBN 40 -#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW1_WIDTH 32 -#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW2_LBN 72 -#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW2_WIDTH 32 -#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW3_LBN 104 -#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW3_WIDTH 32 -#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW4_LBN 136 -#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW4_WIDTH 18 -#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_LBN 8 -#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_WIDTH 146 -#define ESF_DZ_LUE_HW_RSP_GPRD_THREAD_ID_LBN 5 -#define ESF_DZ_LUE_HW_RSP_GPRD_THREAD_ID_WIDTH 3 -#define ESF_DZ_LUE_HW_RSP_GPRD_CLIENT_ID_LBN 2 -#define ESF_DZ_LUE_HW_RSP_GPRD_CLIENT_ID_WIDTH 3 -#define ESE_DZ_LUE_MC_ID 7 -#define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 -#define ESE_DZ_LUE_TX_DICPU_ID 1 -#define ESE_DZ_LUE_RX_DICPU_ID 0 -#define ESF_DZ_LUE_HW_RSP_GPRD_OP_LBN 0 -#define ESF_DZ_LUE_HW_RSP_GPRD_OP_WIDTH 2 -#define ESE_DZ_LUE_GP_WR 3 -#define ESE_DZ_LUE_GP_RD 2 -#define ESE_DZ_LUE_DIR_REQ 1 -#define ESE_DZ_LUE_MATCH_REQ 0 - - -/* ES_LUE_MSG_GP_WR_REQ */ -#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW0_LBN 22 -#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW0_WIDTH 32 -#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW1_LBN 54 -#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW1_WIDTH 32 -#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW2_LBN 86 -#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW2_WIDTH 32 -#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW3_LBN 118 -#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW3_WIDTH 32 -#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW4_LBN 150 -#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW4_WIDTH 18 -#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_LBN 22 -#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_WIDTH 146 -#define ESF_DZ_LUE_HW_REQ_GPWR_ADDR_LBN 8 -#define ESF_DZ_LUE_HW_REQ_GPWR_ADDR_WIDTH 14 -#define ESF_DZ_LUE_HW_REQ_GPWR_THREAD_ID_LBN 5 -#define ESF_DZ_LUE_HW_REQ_GPWR_THREAD_ID_WIDTH 3 -#define ESF_DZ_LUE_HW_REQ_GPWR_CLIENT_ID_LBN 2 -#define ESF_DZ_LUE_HW_REQ_GPWR_CLIENT_ID_WIDTH 3 -#define ESE_DZ_LUE_MC_ID 7 -#define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 -#define ESE_DZ_LUE_TX_DICPU_ID 1 -#define ESE_DZ_LUE_RX_DICPU_ID 0 -#define ESF_DZ_LUE_HW_REQ_GPWR_OP_LBN 0 -#define ESF_DZ_LUE_HW_REQ_GPWR_OP_WIDTH 2 -#define ESE_DZ_LUE_GP_WR 3 -#define ESE_DZ_LUE_GP_RD 2 -#define ESE_DZ_LUE_DIR_REQ 1 -#define ESE_DZ_LUE_MATCH_REQ 0 - - -/* ES_LUE_MSG_MATCH_REQ */ -#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_REQ_COUNT_LBN 137 -#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_REQ_COUNT_WIDTH 8 -#define ESF_DZ_LUE_HW_REQ_MATCH_HASH2_LBN 124 -#define ESF_DZ_LUE_HW_REQ_MATCH_HASH2_WIDTH 13 -#define ESF_DZ_LUE_HW_REQ_MATCH_HASH1_LBN 110 -#define ESF_DZ_LUE_HW_REQ_MATCH_HASH1_WIDTH 14 -#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW0_LBN 14 -#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW0_WIDTH 32 -#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW1_LBN 46 -#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW1_WIDTH 32 -#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW2_LBN 78 -#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW2_WIDTH 32 -#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_LBN 14 -#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_WIDTH 96 -#define ESF_DZ_LUE_HW_REQ_MATCH_DSCRMNTR_LBN 8 -#define ESF_DZ_LUE_HW_REQ_MATCH_DSCRMNTR_WIDTH 6 -#define ESF_DZ_LUE_HW_REQ_MATCH_THREAD_ID_LBN 5 -#define ESF_DZ_LUE_HW_REQ_MATCH_THREAD_ID_WIDTH 3 -#define ESF_DZ_LUE_HW_REQ_MATCH_CLIENT_ID_LBN 2 -#define ESF_DZ_LUE_HW_REQ_MATCH_CLIENT_ID_WIDTH 3 -#define ESE_DZ_LUE_MC_ID 7 -#define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 -#define ESE_DZ_LUE_TX_DICPU_ID 1 -#define ESE_DZ_LUE_RX_DICPU_ID 0 -#define ESF_DZ_LUE_HW_REQ_MATCH_OP_LBN 0 -#define ESF_DZ_LUE_HW_REQ_MATCH_OP_WIDTH 2 -#define ESE_DZ_LUE_GP_WR 3 -#define ESE_DZ_LUE_GP_RD 2 -#define ESE_DZ_LUE_DIR_REQ 1 -#define ESE_DZ_LUE_MATCH_REQ 0 - - -/* ES_LUE_MSG_MATCH_RESP */ -#define ESF_DZ_LUE_HW_RSP_MATCH_LUE_RCPNT_LBN 29 -#define ESF_DZ_LUE_HW_RSP_MATCH_LUE_RCPNT_WIDTH 24 -#define ESF_DZ_LUE_HW_RSP_MATCH_RX_MCAST_LBN 28 -#define ESF_DZ_LUE_HW_RSP_MATCH_RX_MCAST_WIDTH 1 -#define ESF_DZ_LUE_HW_RSP_MATCH_TX_DOMAIN_LBN 20 -#define ESF_DZ_LUE_HW_RSP_MATCH_TX_DOMAIN_WIDTH 8 -#define ESF_DZ_LUE_HW_RSP_MATCH_TX_MCAST_LBN 18 -#define ESF_DZ_LUE_HW_RSP_MATCH_TX_MCAST_WIDTH 2 -#define ESF_DZ_LUE_HW_RSP_MATCH_SOFT_LBN 9 -#define ESF_DZ_LUE_HW_RSP_MATCH_SOFT_WIDTH 9 -#define ESF_DZ_LUE_HW_RSP_MATCH_MATCH_LBN 8 -#define ESF_DZ_LUE_HW_RSP_MATCH_MATCH_WIDTH 1 -#define ESF_DZ_LUE_HW_RSP_MATCH_THREAD_ID_LBN 5 -#define ESF_DZ_LUE_HW_RSP_MATCH_THREAD_ID_WIDTH 3 -#define ESF_DZ_LUE_HW_RSP_MATCH_CLIENT_ID_LBN 2 -#define ESF_DZ_LUE_HW_RSP_MATCH_CLIENT_ID_WIDTH 3 -#define ESE_DZ_LUE_MC_ID 7 -#define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 -#define ESE_DZ_LUE_TX_DICPU_ID 1 -#define ESE_DZ_LUE_RX_DICPU_ID 0 -#define ESF_DZ_LUE_HW_RSP_MATCH_OP_LBN 0 -#define ESF_DZ_LUE_HW_RSP_MATCH_OP_WIDTH 2 -#define ESE_DZ_LUE_GP_WR 3 -#define ESE_DZ_LUE_GP_RD 2 -#define ESE_DZ_LUE_DIR_REQ 1 -#define ESE_DZ_LUE_MATCH_REQ 0 - - -/* ES_LUE_RCPNTR_TYPE */ -#define ESF_DZ_LUE_RXQ_LBN 14 -#define ESF_DZ_LUE_RXQ_WIDTH 10 -#define ESF_DZ_LUE_RSS_INFO_LBN 8 -#define ESF_DZ_LUE_RSS_INFO_WIDTH 6 -#define ESF_DZ_LUE_DEST_LBN 5 -#define ESF_DZ_LUE_DEST_WIDTH 3 -#define ESF_DZ_LUE_SOFT_LBN 0 -#define ESF_DZ_LUE_SOFT_WIDTH 5 - - -/* ES_LUE_UMSG_LU2DI_HASH_RESP */ -#define ESF_DZ_L2DHR_LASTREC_ENTRY_STATUS_LBN 50 -#define ESF_DZ_L2DHR_LASTREC_ENTRY_STATUS_WIDTH 1 -#define ESF_DZ_L2DHR_MULTITYPE_STATUS_LBN 50 -#define ESF_DZ_L2DHR_MULTITYPE_STATUS_WIDTH 1 -#define ESF_DZ_L2DHR_LASTREC_STATUS_LBN 49 -#define ESF_DZ_L2DHR_LASTREC_STATUS_WIDTH 1 -#define ESF_DZ_L2DHR_MATCH_STATUS_LBN 48 -#define ESF_DZ_L2DHR_MATCH_STATUS_WIDTH 1 -#define ESF_DZ_L2DHR_HASH_LBN 0 -#define ESF_DZ_L2DHR_HASH_WIDTH 32 - - -/* ES_LUE_UMSG_LU2DI_RXLU_MULTI_MATCH_RESP */ -#define ESF_DZ_L2DRMMR_SOFT_LBN 112 -#define ESF_DZ_L2DRMMR_SOFT_WIDTH 9 -#define ESF_DZ_L2DRMMR_RCPNTR_PTR_LBN 96 -#define ESF_DZ_L2DRMMR_RCPNTR_PTR_WIDTH 14 -#define ESF_DZ_L2DRMMR_TX_MCAST_LBN 80 -#define ESF_DZ_L2DRMMR_TX_MCAST_WIDTH 2 -#define ESF_DZ_L2DRMMR_MULTITYPE_STATUS_LBN 67 -#define ESF_DZ_L2DRMMR_MULTITYPE_STATUS_WIDTH 1 -#define ESF_DZ_L2DRMMR_LASTREC_ENTRY_STATUS_LBN 66 -#define ESF_DZ_L2DRMMR_LASTREC_ENTRY_STATUS_WIDTH 1 -#define ESF_DZ_L2DRMMR_LASTREC_STATUS_LBN 65 -#define ESF_DZ_L2DRMMR_LASTREC_STATUS_WIDTH 1 -#define ESF_DZ_L2DRMMR_MATCH_STATUS_LBN 64 -#define ESF_DZ_L2DRMMR_MATCH_STATUS_WIDTH 1 - - -/* ES_LUE_UMSG_LU2DI_RXLU_MULTI_RECORD_RESP */ -#define ESF_DZ_L2DRMRR_SOFT_LBN 112 -#define ESF_DZ_L2DRMRR_SOFT_WIDTH 9 -#define ESF_DZ_L2DRMRR_RCPNTR_PTR_LBN 96 -#define ESF_DZ_L2DRMRR_RCPNTR_PTR_WIDTH 14 -#define ESF_DZ_L2DRMRR_RCPNTR_NUM_LBN 80 -#define ESF_DZ_L2DRMRR_RCPNTR_NUM_WIDTH 3 -#define ESF_DZ_L2DRMRR_MULTITYPE_STATUS_LBN 67 -#define ESF_DZ_L2DRMRR_MULTITYPE_STATUS_WIDTH 1 -#define ESF_DZ_L2DRMRR_LASTREC_ENTRY_STATUS_LBN 66 -#define ESF_DZ_L2DRMRR_LASTREC_ENTRY_STATUS_WIDTH 1 -#define ESF_DZ_L2DRMRR_LASTREC_STATUS_LBN 65 -#define ESF_DZ_L2DRMRR_LASTREC_STATUS_WIDTH 1 -#define ESF_DZ_L2DRMRR_MATCH_STATUS_LBN 64 -#define ESF_DZ_L2DRMRR_MATCH_STATUS_WIDTH 1 -#define ESF_DZ_L2DRMRR_RCPNTR_SOFT_LBN 48 -#define ESF_DZ_L2DRMRR_RCPNTR_SOFT_WIDTH 6 -#define ESF_DZ_L2DRMRR_RCPNTR_RSS_INFO_LBN 32 -#define ESF_DZ_L2DRMRR_RCPNTR_RSS_INFO_WIDTH 5 -#define ESF_DZ_L2DRMRR_RCPNTR_RXQ_LBN 16 -#define ESF_DZ_L2DRMRR_RCPNTR_RXQ_WIDTH 10 -#define ESF_DZ_L2DRMRR_HOST_LBN 7 -#define ESF_DZ_L2DRMRR_HOST_WIDTH 1 -#define ESF_DZ_L2DRMRR_MC_LBN 6 -#define ESF_DZ_L2DRMRR_MC_WIDTH 1 -#define ESF_DZ_L2DRMRR_PORT0_MAC_LBN 5 -#define ESF_DZ_L2DRMRR_PORT0_MAC_WIDTH 1 -#define ESF_DZ_L2DRMRR_PORT1_MAC_LBN 4 -#define ESF_DZ_L2DRMRR_PORT1_MAC_WIDTH 1 - - -/* ES_LUE_UMSG_LU2DI_RXLU_SINGLE_MATCH_RESP */ -#define ESF_DZ_L2DRSMR_MULTITYPE_STATUS_LBN 67 -#define ESF_DZ_L2DRSMR_MULTITYPE_STATUS_WIDTH 1 -#define ESF_DZ_L2DRSMR_LASTREC_ENTRY_STATUS_LBN 66 -#define ESF_DZ_L2DRSMR_LASTREC_ENTRY_STATUS_WIDTH 1 -#define ESF_DZ_L2DRSMR_LASTREC_STATUS_LBN 65 -#define ESF_DZ_L2DRSMR_LASTREC_STATUS_WIDTH 1 -#define ESF_DZ_L2DRSMR_MATCH_STATUS_LBN 64 -#define ESF_DZ_L2DRSMR_MATCH_STATUS_WIDTH 1 -#define ESF_DZ_L2DRSMR_RCPNTR_SOFT_LBN 48 -#define ESF_DZ_L2DRSMR_RCPNTR_SOFT_WIDTH 6 -#define ESF_DZ_L2DRSMR_RCPNTR_RSS_INFO_LBN 32 -#define ESF_DZ_L2DRSMR_RCPNTR_RSS_INFO_WIDTH 5 -#define ESF_DZ_L2DRSMR_RCPNTR_RXQ_LBN 16 -#define ESF_DZ_L2DRSMR_RCPNTR_RXQ_WIDTH 10 -#define ESF_DZ_L2DRSMR_HOST_LBN 7 -#define ESF_DZ_L2DRSMR_HOST_WIDTH 1 -#define ESF_DZ_L2DRSMR_MC_LBN 6 -#define ESF_DZ_L2DRSMR_MC_WIDTH 1 -#define ESF_DZ_L2DRSMR_PORT0_MAC_LBN 5 -#define ESF_DZ_L2DRSMR_PORT0_MAC_WIDTH 1 -#define ESF_DZ_L2DRSMR_PORT1_MAC_LBN 4 -#define ESF_DZ_L2DRSMR_PORT1_MAC_WIDTH 1 - - -/* ES_LUE_UMSG_LU2DI_TXLU_MATCH_RESP */ -#define ESF_DZ_L2DTMR_RCPNTR_SOFT_LBN 112 -#define ESF_DZ_L2DTMR_RCPNTR_SOFT_WIDTH 6 -#define ESF_DZ_L2DTMR_RCPNTR_RSS_INFO_LBN 96 -#define ESF_DZ_L2DTMR_RCPNTR_RSS_INFO_WIDTH 5 -#define ESF_DZ_L2DTMR_RCPNTR__RXQ_LBN 80 -#define ESF_DZ_L2DTMR_RCPNTR__RXQ_WIDTH 10 -#define ESF_DZ_L2DTMR_MULTITYPE_STATUS_LBN 67 -#define ESF_DZ_L2DTMR_MULTITYPE_STATUS_WIDTH 1 -#define ESF_DZ_L2DTMR_LASTREC_ENTRY_STATUS_LBN 66 -#define ESF_DZ_L2DTMR_LASTREC_ENTRY_STATUS_WIDTH 1 -#define ESF_DZ_L2DTMR_LASTREC_STATUS_LBN 65 -#define ESF_DZ_L2DTMR_LASTREC_STATUS_WIDTH 1 -#define ESF_DZ_L2DTMR_MATCH_STATUS_LBN 64 -#define ESF_DZ_L2DTMR_MATCH_STATUS_WIDTH 1 -#define ESF_DZ_L2DTMR_ME_SOFT_LBN 48 -#define ESF_DZ_L2DTMR_ME_SOFT_WIDTH 9 -#define ESF_DZ_L2DTMR_TX_MCAST_LBN 32 -#define ESF_DZ_L2DTMR_TX_MCAST_WIDTH 2 -#define ESF_DZ_L2DTMR_TX_DOMAIN_LBN 16 -#define ESF_DZ_L2DTMR_TX_DOMAIN_WIDTH 8 -#define ESF_DZ_L2DTMR_PORT1_MAC_LBN 6 -#define ESF_DZ_L2DTMR_PORT1_MAC_WIDTH 1 -#define ESF_DZ_L2DTMR_PMEM_LBN 6 -#define ESF_DZ_L2DTMR_PMEM_WIDTH 1 -#define ESF_DZ_L2DTMR_PORT0_MAC_LBN 5 -#define ESF_DZ_L2DTMR_PORT0_MAC_WIDTH 1 - - /* ES_MC_EVENT */ #define ESF_DZ_MC_CODE_LBN 60 #define ESF_DZ_MC_CODE_WIDTH 4 @@ -1561,45 +241,6 @@ extern "C" { #define ESF_DZ_MC_SOFT_WIDTH 58 -/* ES_MC_XGMAC_FLTR_RULE_DEF */ -#define ESF_DZ_MC_XFRC_MODE_LBN 416 -#define ESF_DZ_MC_XFRC_MODE_WIDTH 1 -#define ESE_DZ_MC_XFRC_MODE_LAYERED 1 -#define ESE_DZ_MC_XFRC_MODE_SIMPLE 0 -#define ESF_DZ_MC_XFRC_HASH_LBN 384 -#define ESF_DZ_MC_XFRC_HASH_WIDTH 32 -#define ESF_DZ_MC_XFRC_LAYER4_BYTE_MASK_DW0_LBN 256 -#define ESF_DZ_MC_XFRC_LAYER4_BYTE_MASK_DW0_WIDTH 32 -#define ESF_DZ_MC_XFRC_LAYER4_BYTE_MASK_DW1_LBN 288 -#define ESF_DZ_MC_XFRC_LAYER4_BYTE_MASK_DW1_WIDTH 32 -#define ESF_DZ_MC_XFRC_LAYER4_BYTE_MASK_DW2_LBN 320 -#define ESF_DZ_MC_XFRC_LAYER4_BYTE_MASK_DW2_WIDTH 32 -#define ESF_DZ_MC_XFRC_LAYER4_BYTE_MASK_DW3_LBN 352 -#define ESF_DZ_MC_XFRC_LAYER4_BYTE_MASK_DW3_WIDTH 32 -#define ESF_DZ_MC_XFRC_LAYER4_BYTE_MASK_LBN 256 -#define ESF_DZ_MC_XFRC_LAYER4_BYTE_MASK_WIDTH 128 -#define ESF_DZ_MC_XFRC_LAYER3_BYTE_MASK_DW0_LBN 128 -#define ESF_DZ_MC_XFRC_LAYER3_BYTE_MASK_DW0_WIDTH 32 -#define ESF_DZ_MC_XFRC_LAYER3_BYTE_MASK_DW1_LBN 160 -#define ESF_DZ_MC_XFRC_LAYER3_BYTE_MASK_DW1_WIDTH 32 -#define ESF_DZ_MC_XFRC_LAYER3_BYTE_MASK_DW2_LBN 192 -#define ESF_DZ_MC_XFRC_LAYER3_BYTE_MASK_DW2_WIDTH 32 -#define ESF_DZ_MC_XFRC_LAYER3_BYTE_MASK_DW3_LBN 224 -#define ESF_DZ_MC_XFRC_LAYER3_BYTE_MASK_DW3_WIDTH 32 -#define ESF_DZ_MC_XFRC_LAYER3_BYTE_MASK_LBN 128 -#define ESF_DZ_MC_XFRC_LAYER3_BYTE_MASK_WIDTH 128 -#define ESF_DZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_DW0_LBN 0 -#define ESF_DZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_DW0_WIDTH 32 -#define ESF_DZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_DW1_LBN 32 -#define ESF_DZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_DW1_WIDTH 32 -#define ESF_DZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_DW2_LBN 64 -#define ESF_DZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_DW2_WIDTH 32 -#define ESF_DZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_DW3_LBN 96 -#define ESF_DZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_DW3_WIDTH 32 -#define ESF_DZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_LBN 0 -#define ESF_DZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_WIDTH 128 - - /* ES_RX_EVENT */ #define ESF_DZ_RX_CODE_LBN 60 #define ESF_DZ_RX_CODE_WIDTH 4 @@ -1654,10 +295,8 @@ extern "C" { #define ESE_DZ_MAC_CLASS_UCAST 0 #define ESF_DZ_RX_EV_SOFT1_LBN 32 #define ESF_DZ_RX_EV_SOFT1_WIDTH 3 -#define ESF_DZ_RX_EV_RSVD1_LBN 31 -#define ESF_DZ_RX_EV_RSVD1_WIDTH 1 -#define ESF_DZ_RX_ABORT_LBN 30 -#define ESF_DZ_RX_ABORT_WIDTH 1 +#define ESF_DZ_RX_EV_RSVD1_LBN 30 +#define ESF_DZ_RX_EV_RSVD1_WIDTH 2 #define ESF_DZ_RX_ECC_ERR_LBN 29 #define ESF_DZ_RX_ECC_ERR_WIDTH 1 #define ESF_DZ_RX_CRC1_ERR_LBN 28 @@ -1693,601 +332,6 @@ extern "C" { #define ESF_DZ_RX_KER_BUF_ADDR_WIDTH 48 -/* ES_RX_USER_DESC */ -#define ESF_DZ_RX_USR_RESERVED_LBN 62 -#define ESF_DZ_RX_USR_RESERVED_WIDTH 2 -#define ESF_DZ_RX_USR_BYTE_CNT_LBN 48 -#define ESF_DZ_RX_USR_BYTE_CNT_WIDTH 14 -#define ESF_DZ_RX_USR_BUF_PAGE_SIZE_LBN 44 -#define ESF_DZ_RX_USR_BUF_PAGE_SIZE_WIDTH 4 -#define ESE_DZ_USR_BUF_PAGE_SZ_4MB 10 -#define ESE_DZ_USR_BUF_PAGE_SZ_1MB 8 -#define ESE_DZ_USR_BUF_PAGE_SZ_64KB 4 -#define ESE_DZ_USR_BUF_PAGE_SZ_4KB 0 -#define ESF_DZ_RX_USR_BUF_ID_OFFSET_DW0_LBN 0 -#define ESF_DZ_RX_USR_BUF_ID_OFFSET_DW0_WIDTH 32 -#define ESF_DZ_RX_USR_BUF_ID_OFFSET_DW1_LBN 32 -#define ESF_DZ_RX_USR_BUF_ID_OFFSET_DW1_WIDTH 12 -#define ESF_DZ_RX_USR_BUF_ID_OFFSET_LBN 0 -#define ESF_DZ_RX_USR_BUF_ID_OFFSET_WIDTH 44 -#define ESF_DZ_RX_USR_4KBPS_BUF_ID_LBN 12 -#define ESF_DZ_RX_USR_4KBPS_BUF_ID_WIDTH 32 -#define ESF_DZ_RX_USR_64KBPS_BUF_ID_LBN 16 -#define ESF_DZ_RX_USR_64KBPS_BUF_ID_WIDTH 28 -#define ESF_DZ_RX_USR_1MBPS_BUF_ID_LBN 20 -#define ESF_DZ_RX_USR_1MBPS_BUF_ID_WIDTH 24 -#define ESF_DZ_RX_USR_4MBPS_BUF_ID_LBN 22 -#define ESF_DZ_RX_USR_4MBPS_BUF_ID_WIDTH 22 -#define ESF_DZ_RX_USR_4MBPS_BYTE_OFFSET_LBN 0 -#define ESF_DZ_RX_USR_4MBPS_BYTE_OFFSET_WIDTH 22 -#define ESF_DZ_RX_USR_1MBPS_BYTE_OFFSET_LBN 0 -#define ESF_DZ_RX_USR_1MBPS_BYTE_OFFSET_WIDTH 20 -#define ESF_DZ_RX_USR_64KBPS_BYTE_OFFSET_LBN 0 -#define ESF_DZ_RX_USR_64KBPS_BYTE_OFFSET_WIDTH 16 -#define ESF_DZ_RX_USR_4KBPS_BYTE_OFFSET_LBN 0 -#define ESF_DZ_RX_USR_4KBPS_BYTE_OFFSET_WIDTH 12 - - -/* ES_RX_U_QSTATE_TBL0_ENTRY */ -#define ESF_DZ_RX_U_DC_FILL_LBN 112 -#define ESF_DZ_RX_U_DC_FILL_WIDTH 7 -#define ESF_DZ_RX_U_SOFT7_B1R1_0_LBN 112 -#define ESF_DZ_RX_U_SOFT7_B1R1_0_WIDTH 7 -#define ESF_DZ_RX_U_DSCR_HW_RPTR_LBN 96 -#define ESF_DZ_RX_U_DSCR_HW_RPTR_WIDTH 12 -#define ESF_DZ_RX_U_SOFT12_B1R2_0_LBN 96 -#define ESF_DZ_RX_U_SOFT12_B1R2_0_WIDTH 12 -#define ESF_DZ_RX_U_DC_RPTR_LBN 80 -#define ESF_DZ_RX_U_DC_RPTR_WIDTH 6 -#define ESF_DZ_RX_U_SOFT6_B1R1_0_LBN 80 -#define ESF_DZ_RX_U_SOFT6_B1R1_0_WIDTH 6 -#define ESF_DZ_RX_U_NOTIFY_PENDING_LBN 70 -#define ESF_DZ_RX_U_NOTIFY_PENDING_WIDTH 1 -#define ESF_DZ_RX_U_SOFT1_B1R0_6_LBN 70 -#define ESF_DZ_RX_U_SOFT1_B1R0_6_WIDTH 1 -#define ESF_DZ_RX_U_DATA_ACTIVE_LBN 69 -#define ESF_DZ_RX_U_DATA_ACTIVE_WIDTH 1 -#define ESF_DZ_RX_U_SOFT1_B1R0_5_LBN 69 -#define ESF_DZ_RX_U_SOFT1_B1R0_5_WIDTH 1 -#define ESF_DZ_RX_U_FAST_PATH_LBN 68 -#define ESF_DZ_RX_U_FAST_PATH_WIDTH 1 -#define ESF_DZ_RX_U_SOFT1_B1R0_4_LBN 68 -#define ESF_DZ_RX_U_SOFT1_B1R0_4_WIDTH 1 -#define ESF_DZ_RX_U_CHAIN_LBN 67 -#define ESF_DZ_RX_U_CHAIN_WIDTH 1 -#define ESF_DZ_RX_U_SOFT1_B1R0_3_LBN 67 -#define ESF_DZ_RX_U_SOFT1_B1R0_3_WIDTH 1 -#define ESF_DZ_RX_U_DESC_ACTIVE_LBN 66 -#define ESF_DZ_RX_U_DESC_ACTIVE_WIDTH 1 -#define ESF_DZ_RX_U_SOFT1_B1R0_2_LBN 66 -#define ESF_DZ_RX_U_SOFT1_B1R0_2_WIDTH 1 -#define ESF_DZ_RX_U_TIMESTAMP_LBN 65 -#define ESF_DZ_RX_U_TIMESTAMP_WIDTH 1 -#define ESF_DZ_RX_U_SOFT1_B1R0_1_LBN 65 -#define ESF_DZ_RX_U_SOFT1_B1R0_1_WIDTH 1 -#define ESF_DZ_RX_U_Q_ENABLE_LBN 64 -#define ESF_DZ_RX_U_Q_ENABLE_WIDTH 1 -#define ESF_DZ_RX_U_SOFT1_B1R0_0_LBN 64 -#define ESF_DZ_RX_U_SOFT1_B1R0_0_WIDTH 1 -#define ESF_DZ_RX_U_UPD_CRC_MODE_LBN 29 -#define ESF_DZ_RX_U_UPD_CRC_MODE_WIDTH 3 -#define ESE_DZ_C2RIP_FCOIP_MPA 5 -#define ESE_DZ_C2RIP_FCOIP_FCOE 4 -#define ESE_DZ_C2RIP_ISCSI_HDR_AND_PYLD 3 -#define ESE_DZ_C2RIP_ISCSI_HDR 2 -#define ESE_DZ_C2RIP_FCOE 1 -#define ESE_DZ_C2RIP_OFF 0 -#define ESF_DZ_RX_U_SOFT16_B0R1_LBN 16 -#define ESF_DZ_RX_U_SOFT16_B0R1_WIDTH 16 -#define ESF_DZ_RX_U_BIU_ARGS_LBN 16 -#define ESF_DZ_RX_U_BIU_ARGS_WIDTH 13 -#define ESF_DZ_RX_U_EV_QID_LBN 5 -#define ESF_DZ_RX_U_EV_QID_WIDTH 11 -#define ESF_DZ_RX_U_SOFT16_B0R0_LBN 0 -#define ESF_DZ_RX_U_SOFT16_B0R0_WIDTH 16 -#define ESF_DZ_RX_U_EV_QLABEL_LBN 0 -#define ESF_DZ_RX_U_EV_QLABEL_WIDTH 5 - - -/* ES_RX_U_QSTATE_TBL1_ENTRY */ -#define ESF_DZ_RX_U_DSCR_BASE_PAGE_ID_LBN 64 -#define ESF_DZ_RX_U_DSCR_BASE_PAGE_ID_WIDTH 18 -#define ESF_DZ_RX_U_SOFT18_B1R0_0_LBN 64 -#define ESF_DZ_RX_U_SOFT18_B1R0_0_WIDTH 18 -#define ESF_DZ_RX_U_QST1_SPARE_LBN 53 -#define ESF_DZ_RX_U_QST1_SPARE_WIDTH 11 -#define ESF_DZ_RX_U_SOFT16_B0R3_0_LBN 48 -#define ESF_DZ_RX_U_SOFT16_B0R3_0_WIDTH 16 -#define ESF_DZ_RX_U_NO_FLUSH_LBN 52 -#define ESF_DZ_RX_U_NO_FLUSH_WIDTH 1 -#define ESF_DZ_RX_U_HDR_SPLIT_LBN 51 -#define ESF_DZ_RX_U_HDR_SPLIT_WIDTH 1 -#define ESF_DZ_RX_U_DOORBELL_ENABLED_LBN 50 -#define ESF_DZ_RX_U_DOORBELL_ENABLED_WIDTH 1 -#define ESF_DZ_RX_U_WORK_PENDING_LBN 49 -#define ESF_DZ_RX_U_WORK_PENDING_WIDTH 1 -#define ESF_DZ_RX_U_ERROR_LBN 48 -#define ESF_DZ_RX_U_ERROR_WIDTH 1 -#define ESF_DZ_RX_U_DSCR_SW_WPTR_LBN 32 -#define ESF_DZ_RX_U_DSCR_SW_WPTR_WIDTH 12 -#define ESF_DZ_RX_U_SOFT12_B0R2_0_LBN 32 -#define ESF_DZ_RX_U_SOFT12_B0R2_0_WIDTH 12 -#define ESF_DZ_RX_U_OWNER_ID_LBN 16 -#define ESF_DZ_RX_U_OWNER_ID_WIDTH 12 -#define ESF_DZ_RX_U_SOFT12_B0R1_0_LBN 16 -#define ESF_DZ_RX_U_SOFT12_B0R1_0_WIDTH 12 -#define ESF_DZ_RX_U_DSCR_SIZE_LBN 0 -#define ESF_DZ_RX_U_DSCR_SIZE_WIDTH 3 -#define ESE_DZ_RX_DSCR_SIZE_512 7 -#define ESE_DZ_RX_DSCR_SIZE_1K 6 -#define ESE_DZ_RX_DSCR_SIZE_2K 5 -#define ESE_DZ_RX_DSCR_SIZE_4K 4 -#define ESF_DZ_RX_U_SOFT3_B0R0_0_LBN 0 -#define ESF_DZ_RX_U_SOFT3_B0R0_0_WIDTH 3 - - -/* ES_SGMII_DEV_PTNR_ABILITY_1000BX_MD */ -#define ESF_DZ_SGMII_DPA_NXT_PG_LBN 15 -#define ESF_DZ_SGMII_DPA_NXT_PG_WIDTH 1 -#define ESF_DZ_SGMII_DPA_ACK_LBN 14 -#define ESF_DZ_SGMII_DPA_ACK_WIDTH 1 -#define ESF_DZ_SGMII_DPA_REMOTE_FLT_LBN 12 -#define ESF_DZ_SGMII_DPA_REMOTE_FLT_WIDTH 2 -#define ESE_DZ_SGMII_DPA_RF_AN_ERR 3 -#define ESE_DZ_SGMII_DPA_RF_OFFLINE 2 -#define ESE_DZ_SGMII_DPA_RF_LINK_FAIL 1 -#define ESE_DZ_SGMII_DPA_RF_NONE 0 -#define ESF_DZ_SGMII_DPA_PS_LBN 7 -#define ESF_DZ_SGMII_DPA_PS_WIDTH 2 -#define ESF_DZ_SGMII_DPA_HD_LBN 6 -#define ESF_DZ_SGMII_DPA_HD_WIDTH 1 -#define ESF_DZ_SGMII_DPA_FD_LBN 5 -#define ESF_DZ_SGMII_DPA_FD_WIDTH 1 - - -/* ES_SGMII_DEV_PTNR_ABILITY_SGMII_MD */ -#define ESF_DZ_SGMII_DPA_CPR_LINK_STATE_LBN 15 -#define ESF_DZ_SGMII_DPA_CPR_LINK_STATE_WIDTH 1 -#define ESF_DZ_SGMII_DPA_ACK_LBN 14 -#define ESF_DZ_SGMII_DPA_ACK_WIDTH 1 -#define ESF_DZ_SGMII_CPR_BPLX_STS_LBN 12 -#define ESF_DZ_SGMII_CPR_BPLX_STS_WIDTH 1 -#define ESF_DZ_SGMII_DPA_COPPER_SPEED_LBN 10 -#define ESF_DZ_SGMII_DPA_COPPER_SPEED_WIDTH 2 -#define ESE_DZ_SGMII_DPA_CPR_1GBS 2 -#define ESE_DZ_SGMII_DPA_CPR_100MBS 1 -#define ESE_DZ_SGMII_DPA_CPR_10MBS 0 - - -/* ES_SMC_BUFTBL_CNTRL_ENTRY */ -#define ESF_DZ_SMC_SW_CNTXT_DW0_LBN 16 -#define ESF_DZ_SMC_SW_CNTXT_DW0_WIDTH 32 -#define ESF_DZ_SMC_SW_CNTXT_DW1_LBN 48 -#define ESF_DZ_SMC_SW_CNTXT_DW1_WIDTH 24 -#define ESF_DZ_SMC_SW_CNTXT_LBN 16 -#define ESF_DZ_SMC_SW_CNTXT_WIDTH 56 -#define ESF_DZ_SMC_PAGE_SIZE_LBN 12 -#define ESF_DZ_SMC_PAGE_SIZE_WIDTH 4 -#define ESF_DZ_SMC_OWNER_ID_LBN 0 -#define ESF_DZ_SMC_OWNER_ID_WIDTH 12 - - -/* ES_SMC_BUFTBL_TRANSL_ENTRY */ -#define ESF_DZ_SMC_PAGE_INDEX0_DW0_LBN 36 -#define ESF_DZ_SMC_PAGE_INDEX0_DW0_WIDTH 32 -#define ESF_DZ_SMC_PAGE_INDEX0_DW1_LBN 68 -#define ESF_DZ_SMC_PAGE_INDEX0_DW1_WIDTH 4 -#define ESF_DZ_SMC_PAGE_INDEX0_LBN 36 -#define ESF_DZ_SMC_PAGE_INDEX0_WIDTH 36 -#define ESF_DZ_SMC_PAGE_INDEX1_DW0_LBN 0 -#define ESF_DZ_SMC_PAGE_INDEX1_DW0_WIDTH 32 -#define ESF_DZ_SMC_PAGE_INDEX1_DW1_LBN 32 -#define ESF_DZ_SMC_PAGE_INDEX1_DW1_WIDTH 4 -#define ESF_DZ_SMC_PAGE_INDEX1_LBN 0 -#define ESF_DZ_SMC_PAGE_INDEX1_WIDTH 36 - - -/* ES_SMC_DSCR_CACHE_ENTRY */ -#define ESF_DZ_SMC_BTE_PAD_LBN 64 -#define ESF_DZ_SMC_BTE_PAD_WIDTH 8 -#define ESF_DZ_SMC_DSCR_DW0_LBN 0 -#define ESF_DZ_SMC_DSCR_DW0_WIDTH 32 -#define ESF_DZ_SMC_DSCR_DW1_LBN 32 -#define ESF_DZ_SMC_DSCR_DW1_WIDTH 32 -#define ESF_DZ_SMC_DSCR_LBN 0 -#define ESF_DZ_SMC_DSCR_WIDTH 64 - - -/* ES_SMC_GEN_STORAGE_ENTRY */ -#define ESF_DZ_SMC_DATA_DW0_LBN 0 -#define ESF_DZ_SMC_DATA_DW0_WIDTH 32 -#define ESF_DZ_SMC_DATA_DW1_LBN 32 -#define ESF_DZ_SMC_DATA_DW1_WIDTH 32 -#define ESF_DZ_SMC_DATA_DW2_LBN 64 -#define ESF_DZ_SMC_DATA_DW2_WIDTH 8 -#define ESF_DZ_SMC_DATA_LBN 0 -#define ESF_DZ_SMC_DATA_WIDTH 72 - - -/* ES_SMC_MSG_BASE_REQ */ -#define ESF_DZ_MC2S_BASE_REQ_MSG_DATA_DW0_LBN 11 -#define ESF_DZ_MC2S_BASE_REQ_MSG_DATA_DW0_WIDTH 32 -#define ESF_DZ_MC2S_BASE_REQ_MSG_DATA_DW1_LBN 43 -#define ESF_DZ_MC2S_BASE_REQ_MSG_DATA_DW1_WIDTH 32 -#define ESF_DZ_MC2S_BASE_REQ_MSG_DATA_DW2_LBN 75 -#define ESF_DZ_MC2S_BASE_REQ_MSG_DATA_DW2_WIDTH 26 -#define ESF_DZ_MC2S_BASE_REQ_MSG_DATA_LBN 11 -#define ESF_DZ_MC2S_BASE_REQ_MSG_DATA_WIDTH 90 -#define ESF_DZ_MC2S_BASE_SOFT_LBN 7 -#define ESF_DZ_MC2S_BASE_SOFT_WIDTH 4 -#define ESF_DZ_MC2S_BASE_CLIENT_ID_LBN 3 -#define ESF_DZ_MC2S_BASE_CLIENT_ID_WIDTH 4 -#define ESE_DZ_SMC_MACRO_ENGINE_ID 15 -#define ESE_DZ_SMC_TX_DICPU_ID 14 -#define ESE_DZ_SMC_RX_DICPU_ID 13 -#define ESE_DZ_SMC_MC_ID 12 -#define ESE_DZ_SMC_DL_ID 10 -#define ESE_DZ_SMC_EV_ID 8 -#define ESE_DZ_SMC_TX_DPCPU1_ID 5 -#define ESE_DZ_SMC_TX_DPCPU0_ID 4 -#define ESE_DZ_SMC_RX_DPCPU_ID 0 -#define ESF_DZ_MC2S_BASE_OP_LBN 0 -#define ESF_DZ_MC2S_BASE_OP_WIDTH 3 -#define ESE_DZ_SMC_REQ_WR 4 -#define ESE_DZ_SMC_RESP_WR 4 -#define ESE_DZ_SMC_REQ_RD 3 -#define ESE_DZ_SMC_RESP_RD 3 -#define ESE_DZ_SMC_REQ_DSCR_WRITE 2 -#define ESE_DZ_SMC_RESP_DSCR_WRITE 2 -#define ESE_DZ_SMC_REQ_DSCR_READ 1 -#define ESE_DZ_SMC_RESP_DSCR_READ 1 -#define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 -#define ESE_DZ_SMC_RESP_BUFTBL_LOOKUP 0 - - -/* ES_SMC_MSG_BUFTBL_LOOKUP_REQ */ -#define ESF_DZ_MC2S_BL_BUF_ID_LBN 28 -#define ESF_DZ_MC2S_BL_BUF_ID_WIDTH 18 -#define ESF_DZ_MC2S_BL_EXP_PAGE_SIZE_LBN 24 -#define ESF_DZ_MC2S_BL_EXP_PAGE_SIZE_WIDTH 4 -#define ESE_DZ_SMC_PAGE_SIZE_4M 10 -#define ESE_DZ_SMC_PAGE_SIZE_1M 8 -#define ESE_DZ_SMC_PAGE_SIZE_64K 4 -#define ESE_DZ_SMC_PAGE_SIZE_4K 0 -#define ESF_DZ_MC2S_BL_EXP_OWNER_ID_LBN 12 -#define ESF_DZ_MC2S_BL_EXP_OWNER_ID_WIDTH 12 -#define ESF_DZ_MC2S_BL_REFLECT_LBN 11 -#define ESF_DZ_MC2S_BL_REFLECT_WIDTH 1 -#define ESF_DZ_MC2S_BL_SOFT_LBN 7 -#define ESF_DZ_MC2S_BL_SOFT_WIDTH 4 -#define ESF_DZ_MC2S_BL_CLIENT_ID_LBN 3 -#define ESF_DZ_MC2S_BL_CLIENT_ID_WIDTH 4 -#define ESE_DZ_SMC_MACRO_ENGINE_ID 15 -#define ESE_DZ_SMC_TX_DICPU_ID 14 -#define ESE_DZ_SMC_RX_DICPU_ID 13 -#define ESE_DZ_SMC_MC_ID 12 -#define ESE_DZ_SMC_DL_ID 10 -#define ESE_DZ_SMC_EV_ID 8 -#define ESE_DZ_SMC_TX_DPCPU1_ID 5 -#define ESE_DZ_SMC_TX_DPCPU0_ID 4 -#define ESE_DZ_SMC_RX_DPCPU_ID 0 -#define ESF_DZ_MC2S_BL_OP_LBN 0 -#define ESF_DZ_MC2S_BL_OP_WIDTH 3 -#define ESE_DZ_SMC_REQ_WR 4 -#define ESE_DZ_SMC_REQ_RD 3 -#define ESE_DZ_SMC_REQ_DSCR_WRITE 2 -#define ESE_DZ_SMC_REQ_DSCR_READ 1 -#define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 - - -/* ES_SMC_MSG_BUFTBL_LOOKUP_RESP */ -#define ESF_DZ_S2MC_BL_BUFTBL_ENTRY_DW0_LBN 12 -#define ESF_DZ_S2MC_BL_BUFTBL_ENTRY_DW0_WIDTH 32 -#define ESF_DZ_S2MC_BL_BUFTBL_ENTRY_DW1_LBN 44 -#define ESF_DZ_S2MC_BL_BUFTBL_ENTRY_DW1_WIDTH 4 -#define ESF_DZ_S2MC_BL_BUFTBL_ENTRY_LBN 12 -#define ESF_DZ_S2MC_BL_BUFTBL_ENTRY_WIDTH 36 -#define ESF_DZ_S2MC_BL_FAIL_LBN 11 -#define ESF_DZ_S2MC_BL_FAIL_WIDTH 1 -#define ESF_DZ_S2MC_BL_SOFT_LBN 7 -#define ESF_DZ_S2MC_BL_SOFT_WIDTH 4 -#define ESF_DZ_S2MC_BL_CLIENT_ID_LBN 3 -#define ESF_DZ_S2MC_BL_CLIENT_ID_WIDTH 4 -#define ESE_DZ_SMC_MACRO_ENGINE_ID 15 -#define ESE_DZ_SMC_TX_DICPU_ID 14 -#define ESE_DZ_SMC_RX_DICPU_ID 13 -#define ESE_DZ_SMC_MC_ID 12 -#define ESE_DZ_SMC_DL_ID 10 -#define ESE_DZ_SMC_EV_ID 8 -#define ESE_DZ_SMC_TX_DPCPU1_ID 5 -#define ESE_DZ_SMC_TX_DPCPU0_ID 4 -#define ESE_DZ_SMC_RX_DPCPU_ID 0 -#define ESF_DZ_S2MC_BL_OP_LBN 0 -#define ESF_DZ_S2MC_BL_OP_WIDTH 3 -#define ESE_DZ_SMC_REQ_WR 4 -#define ESE_DZ_SMC_REQ_RD 3 -#define ESE_DZ_SMC_REQ_DSCR_WRITE 2 -#define ESE_DZ_SMC_REQ_DSCR_READ 1 -#define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 - - -/* ES_SMC_MSG_DSCR_RD_REQ */ -#define ESF_DZ_MC2S_DR_DSCR_OFST_LBN 24 -#define ESF_DZ_MC2S_DR_DSCR_OFST_WIDTH 6 -#define ESF_DZ_MC2S_DR_QID_LBN 13 -#define ESF_DZ_MC2S_DR_QID_WIDTH 11 -#define ESF_DZ_MC2S_DR_IS_TX_LBN 12 -#define ESF_DZ_MC2S_DR_IS_TX_WIDTH 1 -#define ESF_DZ_MC2S_DR_REFLECT_LBN 11 -#define ESF_DZ_MC2S_DR_REFLECT_WIDTH 1 -#define ESF_DZ_MC2S_DR_SOFT_LBN 7 -#define ESF_DZ_MC2S_DR_SOFT_WIDTH 4 -#define ESF_DZ_MC2S_DR_CLIENT_ID_LBN 3 -#define ESF_DZ_MC2S_DR_CLIENT_ID_WIDTH 4 -#define ESE_DZ_SMC_MACRO_ENGINE_ID 15 -#define ESE_DZ_SMC_TX_DICPU_ID 14 -#define ESE_DZ_SMC_RX_DICPU_ID 13 -#define ESE_DZ_SMC_MC_ID 12 -#define ESE_DZ_SMC_DL_ID 10 -#define ESE_DZ_SMC_EV_ID 8 -#define ESE_DZ_SMC_TX_DPCPU1_ID 5 -#define ESE_DZ_SMC_TX_DPCPU0_ID 4 -#define ESE_DZ_SMC_RX_DPCPU_ID 0 -#define ESF_DZ_MC2S_DR_OP_LBN 0 -#define ESF_DZ_MC2S_DR_OP_WIDTH 3 -#define ESE_DZ_SMC_REQ_WR 4 -#define ESE_DZ_SMC_REQ_RD 3 -#define ESE_DZ_SMC_REQ_DSCR_WRITE 2 -#define ESE_DZ_SMC_REQ_DSCR_READ 1 -#define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 - - -/* ES_SMC_MSG_DSCR_RD_RESP */ -#define ESF_DZ_S2MC_DR_DSCR_DW0_LBN 12 -#define ESF_DZ_S2MC_DR_DSCR_DW0_WIDTH 32 -#define ESF_DZ_S2MC_DR_DSCR_DW1_LBN 44 -#define ESF_DZ_S2MC_DR_DSCR_DW1_WIDTH 32 -#define ESF_DZ_S2MC_DR_DSCR_LBN 12 -#define ESF_DZ_S2MC_DR_DSCR_WIDTH 64 -#define ESF_DZ_S2MC_DR_FAIL_LBN 11 -#define ESF_DZ_S2MC_DR_FAIL_WIDTH 1 -#define ESF_DZ_S2MC_DR_SOFT_LBN 7 -#define ESF_DZ_S2MC_DR_SOFT_WIDTH 4 -#define ESF_DZ_S2MC_DR_CLIENT_ID_LBN 3 -#define ESF_DZ_S2MC_DR_CLIENT_ID_WIDTH 4 -#define ESE_DZ_SMC_MACRO_ENGINE_ID 15 -#define ESE_DZ_SMC_TX_DICPU_ID 14 -#define ESE_DZ_SMC_RX_DICPU_ID 13 -#define ESE_DZ_SMC_MC_ID 12 -#define ESE_DZ_SMC_DL_ID 10 -#define ESE_DZ_SMC_EV_ID 8 -#define ESE_DZ_SMC_TX_DPCPU1_ID 5 -#define ESE_DZ_SMC_TX_DPCPU0_ID 4 -#define ESE_DZ_SMC_RX_DPCPU_ID 0 -#define ESF_DZ_S2MC_DR_OP_LBN 0 -#define ESF_DZ_S2MC_DR_OP_WIDTH 3 -#define ESE_DZ_SMC_REQ_WR 4 -#define ESE_DZ_SMC_REQ_RD 3 -#define ESE_DZ_SMC_REQ_DSCR_WRITE 2 -#define ESE_DZ_SMC_REQ_DSCR_READ 1 -#define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 - - -/* ES_SMC_MSG_DSCR_WR_REQ */ -#define ESF_DZ_MC2S_DW_DSCR_DW0_LBN 30 -#define ESF_DZ_MC2S_DW_DSCR_DW0_WIDTH 32 -#define ESF_DZ_MC2S_DW_DSCR_DW1_LBN 62 -#define ESF_DZ_MC2S_DW_DSCR_DW1_WIDTH 32 -#define ESF_DZ_MC2S_DW_DSCR_LBN 30 -#define ESF_DZ_MC2S_DW_DSCR_WIDTH 64 -#define ESF_DZ_MC2S_DW_DSCR_OFST_LBN 24 -#define ESF_DZ_MC2S_DW_DSCR_OFST_WIDTH 6 -#define ESF_DZ_MC2S_DW_QID_LBN 13 -#define ESF_DZ_MC2S_DW_QID_WIDTH 11 -#define ESF_DZ_MC2S_DW_IS_TX_LBN 12 -#define ESF_DZ_MC2S_DW_IS_TX_WIDTH 1 -#define ESF_DZ_MC2S_DW_REFLECT_LBN 11 -#define ESF_DZ_MC2S_DW_REFLECT_WIDTH 1 -#define ESF_DZ_MC2S_DW_SOFT_LBN 7 -#define ESF_DZ_MC2S_DW_SOFT_WIDTH 4 -#define ESF_DZ_MC2S_DW_CLIENT_ID_LBN 3 -#define ESF_DZ_MC2S_DW_CLIENT_ID_WIDTH 4 -#define ESE_DZ_SMC_MACRO_ENGINE_ID 15 -#define ESE_DZ_SMC_TX_DICPU_ID 14 -#define ESE_DZ_SMC_RX_DICPU_ID 13 -#define ESE_DZ_SMC_MC_ID 12 -#define ESE_DZ_SMC_DL_ID 10 -#define ESE_DZ_SMC_EV_ID 8 -#define ESE_DZ_SMC_TX_DPCPU1_ID 5 -#define ESE_DZ_SMC_TX_DPCPU0_ID 4 -#define ESE_DZ_SMC_RX_DPCPU_ID 0 -#define ESF_DZ_MC2S_DW_OP_LBN 0 -#define ESF_DZ_MC2S_DW_OP_WIDTH 3 -#define ESE_DZ_SMC_REQ_WR 4 -#define ESE_DZ_SMC_REQ_RD 3 -#define ESE_DZ_SMC_REQ_DSCR_WRITE 2 -#define ESE_DZ_SMC_REQ_DSCR_READ 1 -#define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 - - -/* ES_SMC_MSG_DSCR_WR_RESP */ -#define ESF_DZ_S2MC_DW_FAIL_LBN 11 -#define ESF_DZ_S2MC_DW_FAIL_WIDTH 1 -#define ESF_DZ_S2MC_DW_SOFT_LBN 7 -#define ESF_DZ_S2MC_DW_SOFT_WIDTH 4 -#define ESF_DZ_S2MC_DW_CLIENT_ID_LBN 3 -#define ESF_DZ_S2MC_DW_CLIENT_ID_WIDTH 4 -#define ESE_DZ_SMC_MACRO_ENGINE_ID 15 -#define ESE_DZ_SMC_TX_DICPU_ID 14 -#define ESE_DZ_SMC_RX_DICPU_ID 13 -#define ESE_DZ_SMC_MC_ID 12 -#define ESE_DZ_SMC_DL_ID 10 -#define ESE_DZ_SMC_EV_ID 8 -#define ESE_DZ_SMC_TX_DPCPU1_ID 5 -#define ESE_DZ_SMC_TX_DPCPU0_ID 4 -#define ESE_DZ_SMC_RX_DPCPU_ID 0 -#define ESF_DZ_S2MC_DW_OP_LBN 0 -#define ESF_DZ_S2MC_DW_OP_WIDTH 3 -#define ESE_DZ_SMC_REQ_WR 4 -#define ESE_DZ_SMC_REQ_RD 3 -#define ESE_DZ_SMC_REQ_DSCR_WRITE 2 -#define ESE_DZ_SMC_REQ_DSCR_READ 1 -#define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 - - -/* ES_SMC_MSG_RD_REQ */ -#define ESF_DZ_MC2S_RD_ADDR_LBN 12 -#define ESF_DZ_MC2S_RD_ADDR_WIDTH 17 -#define ESF_DZ_MC2S_RD_REFLECT_LBN 11 -#define ESF_DZ_MC2S_RD_REFLECT_WIDTH 1 -#define ESF_DZ_MC2S_RD_SOFT_LBN 7 -#define ESF_DZ_MC2S_RD_SOFT_WIDTH 4 -#define ESF_DZ_MC2S_RD_CLIENT_ID_LBN 3 -#define ESF_DZ_MC2S_RD_CLIENT_ID_WIDTH 4 -#define ESE_DZ_SMC_MACRO_ENGINE_ID 15 -#define ESE_DZ_SMC_TX_DICPU_ID 14 -#define ESE_DZ_SMC_RX_DICPU_ID 13 -#define ESE_DZ_SMC_MC_ID 12 -#define ESE_DZ_SMC_DL_ID 10 -#define ESE_DZ_SMC_EV_ID 8 -#define ESE_DZ_SMC_TX_DPCPU1_ID 5 -#define ESE_DZ_SMC_TX_DPCPU0_ID 4 -#define ESE_DZ_SMC_RX_DPCPU_ID 0 -#define ESF_DZ_MC2S_RD_OP_LBN 0 -#define ESF_DZ_MC2S_RD_OP_WIDTH 3 -#define ESE_DZ_SMC_REQ_WR 4 -#define ESE_DZ_SMC_REQ_RD 3 -#define ESE_DZ_SMC_REQ_DSCR_WRITE 2 -#define ESE_DZ_SMC_REQ_DSCR_READ 1 -#define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 - - -/* ES_SMC_MSG_RD_RESP */ -#define ESF_DZ_S2MC_RD_DATA_DW0_LBN 12 -#define ESF_DZ_S2MC_RD_DATA_DW0_WIDTH 32 -#define ESF_DZ_S2MC_RD_DATA_DW1_LBN 44 -#define ESF_DZ_S2MC_RD_DATA_DW1_WIDTH 32 -#define ESF_DZ_S2MC_RD_DATA_DW2_LBN 76 -#define ESF_DZ_S2MC_RD_DATA_DW2_WIDTH 8 -#define ESF_DZ_S2MC_RD_DATA_LBN 12 -#define ESF_DZ_S2MC_RD_DATA_WIDTH 72 -#define ESF_DZ_S2MC_RD_FAIL_LBN 11 -#define ESF_DZ_S2MC_RD_FAIL_WIDTH 1 -#define ESF_DZ_S2MC_RD_SOFT_LBN 7 -#define ESF_DZ_S2MC_RD_SOFT_WIDTH 4 -#define ESF_DZ_S2MC_RD_CLIENT_ID_LBN 3 -#define ESF_DZ_S2MC_RD_CLIENT_ID_WIDTH 4 -#define ESE_DZ_SMC_MACRO_ENGINE_ID 15 -#define ESE_DZ_SMC_TX_DICPU_ID 14 -#define ESE_DZ_SMC_RX_DICPU_ID 13 -#define ESE_DZ_SMC_MC_ID 12 -#define ESE_DZ_SMC_DL_ID 10 -#define ESE_DZ_SMC_EV_ID 8 -#define ESE_DZ_SMC_TX_DPCPU1_ID 5 -#define ESE_DZ_SMC_TX_DPCPU0_ID 4 -#define ESE_DZ_SMC_RX_DPCPU_ID 0 -#define ESF_DZ_S2MC_RD_OP_LBN 0 -#define ESF_DZ_S2MC_RD_OP_WIDTH 3 -#define ESE_DZ_SMC_REQ_WR 4 -#define ESE_DZ_SMC_REQ_RD 3 -#define ESE_DZ_SMC_REQ_DSCR_WRITE 2 -#define ESE_DZ_SMC_REQ_DSCR_READ 1 -#define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 - - -/* ES_SMC_MSG_RESP */ -#define ESF_DZ_S2MC_BASE_RSP_DATA_DW0_LBN 12 -#define ESF_DZ_S2MC_BASE_RSP_DATA_DW0_WIDTH 32 -#define ESF_DZ_S2MC_BASE_RSP_DATA_DW1_LBN 44 -#define ESF_DZ_S2MC_BASE_RSP_DATA_DW1_WIDTH 32 -#define ESF_DZ_S2MC_BASE_RSP_DATA_DW2_LBN 76 -#define ESF_DZ_S2MC_BASE_RSP_DATA_DW2_WIDTH 8 -#define ESF_DZ_S2MC_BASE_RSP_DATA_LBN 12 -#define ESF_DZ_S2MC_BASE_RSP_DATA_WIDTH 72 -#define ESF_DZ_S2MC_BASE_FAIL_LBN 11 -#define ESF_DZ_S2MC_BASE_FAIL_WIDTH 1 -#define ESF_DZ_S2MC_BASE_SOFT_LBN 7 -#define ESF_DZ_S2MC_BASE_SOFT_WIDTH 4 -#define ESF_DZ_S2MC_BASE_CLIENT_ID_LBN 3 -#define ESF_DZ_S2MC_BASE_CLIENT_ID_WIDTH 4 -#define ESE_DZ_SMC_MACRO_ENGINE_ID 15 -#define ESE_DZ_SMC_TX_DICPU_ID 14 -#define ESE_DZ_SMC_RX_DICPU_ID 13 -#define ESE_DZ_SMC_MC_ID 12 -#define ESE_DZ_SMC_DL_ID 10 -#define ESE_DZ_SMC_EV_ID 8 -#define ESE_DZ_SMC_TX_DPCPU1_ID 5 -#define ESE_DZ_SMC_TX_DPCPU0_ID 4 -#define ESE_DZ_SMC_RX_DPCPU_ID 0 -#define ESF_DZ_S2MC_BASE_OP_LBN 0 -#define ESF_DZ_S2MC_BASE_OP_WIDTH 3 -#define ESE_DZ_SMC_REQ_WR 4 -#define ESE_DZ_SMC_REQ_RD 3 -#define ESE_DZ_SMC_REQ_DSCR_WRITE 2 -#define ESE_DZ_SMC_REQ_DSCR_READ 1 -#define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 - - -/* ES_SMC_MSG_WR_REQ */ -#define ESF_DZ_MC2S_WR_DATA_DW0_LBN 29 -#define ESF_DZ_MC2S_WR_DATA_DW0_WIDTH 32 -#define ESF_DZ_MC2S_WR_DATA_DW1_LBN 61 -#define ESF_DZ_MC2S_WR_DATA_DW1_WIDTH 32 -#define ESF_DZ_MC2S_WR_DATA_DW2_LBN 93 -#define ESF_DZ_MC2S_WR_DATA_DW2_WIDTH 8 -#define ESF_DZ_MC2S_WR_DATA_LBN 29 -#define ESF_DZ_MC2S_WR_DATA_WIDTH 72 -#define ESF_DZ_MC2S_WR_ADDR_LBN 12 -#define ESF_DZ_MC2S_WR_ADDR_WIDTH 17 -#define ESF_DZ_MC2S_WR_REFLECT_LBN 11 -#define ESF_DZ_MC2S_WR_REFLECT_WIDTH 1 -#define ESF_DZ_MC2S_WR_SOFT_LBN 7 -#define ESF_DZ_MC2S_WR_SOFT_WIDTH 4 -#define ESF_DZ_MC2S_WR_CLIENT_ID_LBN 3 -#define ESF_DZ_MC2S_WR_CLIENT_ID_WIDTH 4 -#define ESE_DZ_SMC_MACRO_ENGINE_ID 15 -#define ESE_DZ_SMC_TX_DICPU_ID 14 -#define ESE_DZ_SMC_RX_DICPU_ID 13 -#define ESE_DZ_SMC_MC_ID 12 -#define ESE_DZ_SMC_DL_ID 10 -#define ESE_DZ_SMC_EV_ID 8 -#define ESE_DZ_SMC_TX_DPCPU1_ID 5 -#define ESE_DZ_SMC_TX_DPCPU0_ID 4 -#define ESE_DZ_SMC_RX_DPCPU_ID 0 -#define ESF_DZ_MC2S_WR_OP_LBN 0 -#define ESF_DZ_MC2S_WR_OP_WIDTH 3 -#define ESE_DZ_SMC_REQ_WR 4 -#define ESE_DZ_SMC_REQ_RD 3 -#define ESE_DZ_SMC_REQ_DSCR_WRITE 2 -#define ESE_DZ_SMC_REQ_DSCR_READ 1 -#define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 - - -/* ES_SMC_MSG_WR_RESP */ -#define ESF_DZ_S2MC_WR_FAIL_LBN 11 -#define ESF_DZ_S2MC_WR_FAIL_WIDTH 1 -#define ESF_DZ_S2MC_WR_SOFT_LBN 7 -#define ESF_DZ_S2MC_WR_SOFT_WIDTH 4 -#define ESF_DZ_S2MC_WR_CLIENT_ID_LBN 3 -#define ESF_DZ_S2MC_WR_CLIENT_ID_WIDTH 4 -#define ESE_DZ_SMC_MACRO_ENGINE_ID 15 -#define ESE_DZ_SMC_TX_DICPU_ID 14 -#define ESE_DZ_SMC_RX_DICPU_ID 13 -#define ESE_DZ_SMC_MC_ID 12 -#define ESE_DZ_SMC_DL_ID 10 -#define ESE_DZ_SMC_EV_ID 8 -#define ESE_DZ_SMC_TX_DPCPU1_ID 5 -#define ESE_DZ_SMC_TX_DPCPU0_ID 4 -#define ESE_DZ_SMC_RX_DPCPU_ID 0 -#define ESF_DZ_S2MC_WR_OP_LBN 0 -#define ESF_DZ_S2MC_WR_OP_WIDTH 3 -#define ESE_DZ_SMC_REQ_WR 4 -#define ESE_DZ_SMC_REQ_RD 3 -#define ESE_DZ_SMC_REQ_DSCR_WRITE 2 -#define ESE_DZ_SMC_REQ_DSCR_READ 1 -#define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 - - /* ES_TX_CSUM_TSTAMP_DESC */ #define ESF_DZ_TX_DESC_IS_OPT_LBN 63 #define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 @@ -2296,6 +340,12 @@ extern "C" { #define ESE_DZ_TX_OPTION_DESC_TSO 7 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 +#define ESF_DZ_TX_OPTION_TS_AT_TXDP_LBN 8 +#define ESF_DZ_TX_OPTION_TS_AT_TXDP_WIDTH 1 +#define ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM_LBN 7 +#define ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM_WIDTH 1 +#define ESF_DZ_TX_OPTION_INNER_IP_CSUM_LBN 6 +#define ESF_DZ_TX_OPTION_INNER_IP_CSUM_WIDTH 1 #define ESF_DZ_TX_TIMESTAMP_LBN 5 #define ESF_DZ_TX_TIMESTAMP_WIDTH 1 #define ESF_DZ_TX_OPTION_CRC_MODE_LBN 2 @@ -2323,10 +373,8 @@ extern "C" { #define ESF_DZ_TX_EV_RSVD_WIDTH 10 #define ESF_DZ_TX_SOFT2_LBN 32 #define ESF_DZ_TX_SOFT2_WIDTH 16 -#define ESF_DZ_TX_CAN_MERGE_LBN 31 -#define ESF_DZ_TX_CAN_MERGE_WIDTH 1 #define ESF_DZ_TX_SOFT1_LBN 24 -#define ESF_DZ_TX_SOFT1_WIDTH 7 +#define ESF_DZ_TX_SOFT1_WIDTH 8 #define ESF_DZ_TX_QLABEL_LBN 16 #define ESF_DZ_TX_QLABEL_WIDTH 5 #define ESF_DZ_TX_DESCR_INDX_LBN 0 @@ -2369,6 +417,10 @@ extern "C" { #define ESE_DZ_TX_OPTION_DESC_TSO 7 #define ESE_DZ_TX_OPTION_DESC_VLAN 6 #define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 +#define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 +#define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 +#define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 +#define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 #define ESF_DZ_TX_TSO_TCP_FLAGS_LBN 48 #define ESF_DZ_TX_TSO_TCP_FLAGS_WIDTH 8 #define ESF_DZ_TX_TSO_IP_ID_LBN 32 @@ -2377,140 +429,46 @@ extern "C" { #define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 -/* ES_TX_USER_DESC */ -#define ESF_DZ_TX_USR_TYPE_LBN 63 -#define ESF_DZ_TX_USR_TYPE_WIDTH 1 -#define ESF_DZ_TX_USR_CONT_LBN 62 -#define ESF_DZ_TX_USR_CONT_WIDTH 1 -#define ESF_DZ_TX_USR_BYTE_CNT_LBN 48 -#define ESF_DZ_TX_USR_BYTE_CNT_WIDTH 14 -#define ESF_DZ_TX_USR_BUF_PAGE_SIZE_LBN 44 -#define ESF_DZ_TX_USR_BUF_PAGE_SIZE_WIDTH 4 -#define ESE_DZ_USR_BUF_PAGE_SZ_4MB 10 -#define ESE_DZ_USR_BUF_PAGE_SZ_1MB 8 -#define ESE_DZ_USR_BUF_PAGE_SZ_64KB 4 -#define ESE_DZ_USR_BUF_PAGE_SZ_4KB 0 -#define ESF_DZ_TX_USR_BUF_ID_OFFSET_DW0_LBN 0 -#define ESF_DZ_TX_USR_BUF_ID_OFFSET_DW0_WIDTH 32 -#define ESF_DZ_TX_USR_BUF_ID_OFFSET_DW1_LBN 32 -#define ESF_DZ_TX_USR_BUF_ID_OFFSET_DW1_WIDTH 12 -#define ESF_DZ_TX_USR_BUF_ID_OFFSET_LBN 0 -#define ESF_DZ_TX_USR_BUF_ID_OFFSET_WIDTH 44 -#define ESF_DZ_TX_USR_4KBPS_BUF_ID_LBN 12 -#define ESF_DZ_TX_USR_4KBPS_BUF_ID_WIDTH 32 -#define ESF_DZ_TX_USR_64KBPS_BUF_ID_LBN 16 -#define ESF_DZ_TX_USR_64KBPS_BUF_ID_WIDTH 28 -#define ESF_DZ_TX_USR_1MBPS_BUF_ID_LBN 20 -#define ESF_DZ_TX_USR_1MBPS_BUF_ID_WIDTH 24 -#define ESF_DZ_TX_USR_4MBPS_BUF_ID_LBN 22 -#define ESF_DZ_TX_USR_4MBPS_BUF_ID_WIDTH 22 -#define ESF_DZ_TX_USR_4MBPS_BYTE_OFFSET_LBN 0 -#define ESF_DZ_TX_USR_4MBPS_BYTE_OFFSET_WIDTH 22 -#define ESF_DZ_TX_USR_1MBPS_BYTE_OFFSET_LBN 0 -#define ESF_DZ_TX_USR_1MBPS_BYTE_OFFSET_WIDTH 20 -#define ESF_DZ_TX_USR_64KBPS_BYTE_OFFSET_LBN 0 -#define ESF_DZ_TX_USR_64KBPS_BYTE_OFFSET_WIDTH 16 -#define ESF_DZ_TX_USR_4KBPS_BYTE_OFFSET_LBN 0 -#define ESF_DZ_TX_USR_4KBPS_BYTE_OFFSET_WIDTH 12 - - -/* ES_TX_U_QSTATE_TBL0_ENTRY */ -#define ESF_DZ_TX_U_DC_FILL_LBN 112 -#define ESF_DZ_TX_U_DC_FILL_WIDTH 7 -#define ESF_DZ_TX_U_SOFT7_B1R3_LBN 112 -#define ESF_DZ_TX_U_SOFT7_B1R3_WIDTH 7 -#define ESF_DZ_TX_U_DSCR_HW_RPTR_LBN 96 -#define ESF_DZ_TX_U_DSCR_HW_RPTR_WIDTH 12 -#define ESF_DZ_TX_U_SOFT12_B1R2_LBN 96 -#define ESF_DZ_TX_U_SOFT12_B1R2_WIDTH 12 -#define ESF_DZ_TX_U_DC_RPTR_LBN 80 -#define ESF_DZ_TX_U_DC_RPTR_WIDTH 6 -#define ESF_DZ_TX_U_SOFT6_B1R1_LBN 80 -#define ESF_DZ_TX_U_SOFT6_B1R1_WIDTH 6 -#define ESF_DZ_TX_U_CNTAG_LBN 68 -#define ESF_DZ_TX_U_CNTAG_WIDTH 1 -#define ESF_DZ_TX_U_SOFT5_B1R0_LBN 64 -#define ESF_DZ_TX_U_SOFT5_B1R0_WIDTH 5 -#define ESF_DZ_TX_U_TIMESTAMP_LBN 67 -#define ESF_DZ_TX_U_TIMESTAMP_WIDTH 1 -#define ESF_DZ_TX_U_PREFETCH_ACTIVE_LBN 66 -#define ESF_DZ_TX_U_PREFETCH_ACTIVE_WIDTH 1 -#define ESF_DZ_TX_U_PREFETCH_PENDING_LBN 65 -#define ESF_DZ_TX_U_PREFETCH_PENDING_WIDTH 1 -#define ESF_DZ_TX_U_DOORBELL_ENABLED_LBN 64 -#define ESF_DZ_TX_U_DOORBELL_ENABLED_WIDTH 1 -#define ESF_DZ_TX_U_UPD_UDPTCP_CSUM_MODE_LBN 33 -#define ESF_DZ_TX_U_UPD_UDPTCP_CSUM_MODE_WIDTH 1 -#define ESF_DZ_TX_U_SOFT2_B0R2_LBN 32 -#define ESF_DZ_TX_U_SOFT2_B0R2_WIDTH 2 -#define ESF_DZ_TX_U_UPD_IP_CSUM_MODE_LBN 32 -#define ESF_DZ_TX_U_UPD_IP_CSUM_MODE_WIDTH 1 -#define ESF_DZ_TX_U_UPD_CRC_MODE_LBN 29 -#define ESF_DZ_TX_U_UPD_CRC_MODE_WIDTH 3 -#define ESE_DZ_C2RIP_FCOIP_MPA 5 -#define ESE_DZ_C2RIP_FCOIP_FCOE 4 -#define ESE_DZ_C2RIP_ISCSI_HDR_AND_PYLD 3 -#define ESE_DZ_C2RIP_ISCSI_HDR 2 -#define ESE_DZ_C2RIP_FCOE 1 -#define ESE_DZ_C2RIP_OFF 0 -#define ESF_DZ_TX_U_SOFT16_B0R1_LBN 16 -#define ESF_DZ_TX_U_SOFT16_B0R1_WIDTH 16 -#define ESF_DZ_TX_U_BIU_ARGS_LBN 16 -#define ESF_DZ_TX_U_BIU_ARGS_WIDTH 13 -#define ESF_DZ_TX_U_EV_QID_LBN 5 -#define ESF_DZ_TX_U_EV_QID_WIDTH 11 -#define ESF_DZ_TX_U_SOFT16_B0R0_LBN 0 -#define ESF_DZ_TX_U_SOFT16_B0R0_WIDTH 16 -#define ESF_DZ_TX_U_EV_QLABEL_LBN 0 -#define ESF_DZ_TX_U_EV_QLABEL_WIDTH 5 - - -/* ES_TX_U_QSTATE_TBL1_ENTRY */ -#define ESF_DZ_TX_U_DSCR_BASE_PAGE_ID_LBN 64 -#define ESF_DZ_TX_U_DSCR_BASE_PAGE_ID_WIDTH 18 -#define ESF_DZ_TX_U_SOFT18_B1R0_LBN 64 -#define ESF_DZ_TX_U_SOFT18_B1R0_WIDTH 18 -#define ESF_DZ_TX_U_SOFT16_B0R3_LBN 48 -#define ESF_DZ_TX_U_SOFT16_B0R3_WIDTH 16 -#define ESF_DZ_TX_U_EMERGENCY_FETCH_FAILED_LBN 56 -#define ESF_DZ_TX_U_EMERGENCY_FETCH_FAILED_WIDTH 1 -#define ESF_DZ_TX_U_PACER_BYPASS_OK_LBN 55 -#define ESF_DZ_TX_U_PACER_BYPASS_OK_WIDTH 1 -#define ESF_DZ_TX_U_STALE_DL_FETCH_LBN 54 -#define ESF_DZ_TX_U_STALE_DL_FETCH_WIDTH 1 -#define ESF_DZ_TX_U_ROLLBACK_IDX_REACHED_LBN 52 -#define ESF_DZ_TX_U_ROLLBACK_IDX_REACHED_WIDTH 1 -#define ESF_DZ_TX_U_ROLLBACK_ACTIVE_LBN 51 -#define ESF_DZ_TX_U_ROLLBACK_ACTIVE_WIDTH 1 -#define ESF_DZ_TX_U_QUEUE_PAUSED_LBN 50 -#define ESF_DZ_TX_U_QUEUE_PAUSED_WIDTH 1 -#define ESF_DZ_TX_U_QUEUE_ENABLED_LBN 49 -#define ESF_DZ_TX_U_QUEUE_ENABLED_WIDTH 1 -#define ESF_DZ_TX_U_FLUSH_PENDING_LBN 48 -#define ESF_DZ_TX_U_FLUSH_PENDING_WIDTH 1 -#define ESF_DZ_TX_U_DSCR_HW_WPTR_LBN 32 -#define ESF_DZ_TX_U_DSCR_HW_WPTR_WIDTH 12 -#define ESF_DZ_TX_U_SOFT12_B0R2_LBN 32 -#define ESF_DZ_TX_U_SOFT12_B0R2_WIDTH 12 -#define ESF_DZ_TX_U_OWNER_ID_LBN 16 -#define ESF_DZ_TX_U_OWNER_ID_WIDTH 12 -#define ESF_DZ_TX_U_SOFT12_B0R1_LBN 16 -#define ESF_DZ_TX_U_SOFT12_B0R1_WIDTH 12 -#define ESF_DZ_TX_U_DSCR_SIZE_LBN 13 -#define ESF_DZ_TX_U_DSCR_SIZE_WIDTH 3 -#define ESF_DZ_TX_U_SOFT3_B0R0_LBN 0 -#define ESF_DZ_TX_U_SOFT3_B0R0_WIDTH 3 - - -/* ES_TX_U_QSTATE_TBL2_ENTRY */ -#define ESF_DZ_TX_FINFO_WRD3_LBN 48 -#define ESF_DZ_TX_FINFO_WRD3_WIDTH 16 -#define ESF_DZ_TX_FINFO_WRD2_LBN 32 -#define ESF_DZ_TX_FINFO_WRD2_WIDTH 16 -#define ESF_DZ_TX_FINFO_WRD1_LBN 16 -#define ESF_DZ_TX_FINFO_WRD1_WIDTH 16 -#define ESF_DZ_TX_FINFO_SRCDST_LBN 0 -#define ESF_DZ_TX_FINFO_SRCDST_WIDTH 16 +/* TX_TSO_FATSO2A_DESC */ +#define ESF_DZ_TX_DESC_IS_OPT_LBN 63 +#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 +#define ESF_DZ_TX_OPTION_TYPE_LBN 60 +#define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 +#define ESE_DZ_TX_OPTION_DESC_TSO 7 +#define ESE_DZ_TX_OPTION_DESC_VLAN 6 +#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 +#define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 +#define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 +#define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3 +#define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2 +#define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 +#define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 +#define ESF_DZ_TX_TSO_IP_ID_LBN 32 +#define ESF_DZ_TX_TSO_IP_ID_WIDTH 16 +#define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 +#define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 + + +/* TX_TSO_FATSO2B_DESC */ +#define ESF_DZ_TX_DESC_IS_OPT_LBN 63 +#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 +#define ESF_DZ_TX_OPTION_TYPE_LBN 60 +#define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 +#define ESE_DZ_TX_OPTION_DESC_TSO 7 +#define ESE_DZ_TX_OPTION_DESC_VLAN 6 +#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 +#define ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56 +#define ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4 +#define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3 +#define ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2 +#define ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1 +#define ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0 +#define ESF_DZ_TX_TSO_OUTER_IP_ID_LBN 16 +#define ESF_DZ_TX_TSO_OUTER_IP_ID_WIDTH 16 +#define ESF_DZ_TX_TSO_TCP_MSS_LBN 32 +#define ESF_DZ_TX_TSO_TCP_MSS_WIDTH 16 +#define ESF_DZ_TX_TSO_INNER_PE_CSUM_LBN 0 +#define ESF_DZ_TX_TSO_INNER_PE_CSUM_WIDTH 16 /* ES_TX_VLAN_DESC */ @@ -2529,412 +487,34 @@ extern "C" { #define ESF_DZ_TX_VLAN_TAG1_WIDTH 16 -/* ES_b2t_cpl_rsp */ -#define ESF_DZ_B2T_CPL_RSP_CPL_ECC_LBN 284 -#define ESF_DZ_B2T_CPL_RSP_CPL_ECC_WIDTH 32 -#define ESF_DZ_B2T_CPL_RSP_CPL_EOT_LBN 283 -#define ESF_DZ_B2T_CPL_RSP_CPL_EOT_WIDTH 1 -#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW0_LBN 27 -#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW0_WIDTH 32 -#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW1_LBN 59 -#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW1_WIDTH 32 -#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW2_LBN 91 -#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW2_WIDTH 32 -#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW3_LBN 123 -#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW3_WIDTH 32 -#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW4_LBN 155 -#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW4_WIDTH 32 -#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW5_LBN 187 -#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW5_WIDTH 32 -#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW6_LBN 219 -#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW6_WIDTH 32 -#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW7_LBN 251 -#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW7_WIDTH 32 -#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_LBN 27 -#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_WIDTH 256 -#define ESF_DZ_B2T_CPL_RSP_CPL_ERROR_LBN 26 -#define ESF_DZ_B2T_CPL_RSP_CPL_ERROR_WIDTH 1 -#define ESF_DZ_B2T_CPL_RSP_CPL_LAST_LBN 25 -#define ESF_DZ_B2T_CPL_RSP_CPL_LAST_WIDTH 1 -#define ESF_DZ_B2T_CPL_RSP_CPL_TAG_LBN 19 -#define ESF_DZ_B2T_CPL_RSP_CPL_TAG_WIDTH 6 -#define ESF_DZ_B2T_CPL_RSP_CPL_LEN_LBN 7 -#define ESF_DZ_B2T_CPL_RSP_CPL_LEN_WIDTH 12 -#define ESF_DZ_B2T_CPL_RSP_CPL_ADRS_LBN 0 -#define ESF_DZ_B2T_CPL_RSP_CPL_ADRS_WIDTH 7 - - -/* ES_fltr_info_wrd_mac_to_rx */ -#define ESF_DZ_FLTR_INFO_MAC_TO_RX_RESERVED2_LBN 112 -#define ESF_DZ_FLTR_INFO_MAC_TO_RX_RESERVED2_WIDTH 16 -#define ESF_DZ_FLTR_INFO_MAC_TO_RX_TIMESTAMP2_LBN 96 -#define ESF_DZ_FLTR_INFO_MAC_TO_RX_TIMESTAMP2_WIDTH 16 -#define ESF_DZ_FLTR_INFO_MAC_TO_RX_TIMESTAMP1_LBN 80 -#define ESF_DZ_FLTR_INFO_MAC_TO_RX_TIMESTAMP1_WIDTH 16 -#define ESF_DZ_FLTR_INFO_MAC_TO_RX_TIMESTAMP0_LBN 64 -#define ESF_DZ_FLTR_INFO_MAC_TO_RX_TIMESTAMP0_WIDTH 16 -#define ESF_DZ_FLTR_INFO_MAC_TO_RX_RESERVED1_LBN 48 -#define ESF_DZ_FLTR_INFO_MAC_TO_RX_RESERVED1_WIDTH 16 -#define ESF_DZ_FLTR_INFO_MAC_TO_RX_IPSEC_SA_LBN 32 -#define ESF_DZ_FLTR_INFO_MAC_TO_RX_IPSEC_SA_WIDTH 16 -#define ESF_DZ_FLTR_INFO_MAC_TO_RX_RESERVED0_LBN 8 -#define ESF_DZ_FLTR_INFO_MAC_TO_RX_RESERVED0_WIDTH 24 -#define ESF_DZ_FLTR_INFO_MAC_TO_RX_IPSEC_LBN 7 -#define ESF_DZ_FLTR_INFO_MAC_TO_RX_IPSEC_WIDTH 1 -#define ESF_DZ_FLTR_INFO_MAC_TO_RX_PRIORITY_LBN 4 -#define ESF_DZ_FLTR_INFO_MAC_TO_RX_PRIORITY_WIDTH 3 -#define ESF_DZ_FLTR_INFO_MAC_TO_RX_SRC_LBN 0 -#define ESF_DZ_FLTR_INFO_MAC_TO_RX_SRC_WIDTH 4 - - -/* ES_fltr_info_wrd_mc_pdma */ -#define ESF_DZ_FLTR_INFO_MC_PDMA_FLTR_OUT_LBN 64 -#define ESF_DZ_FLTR_INFO_MC_PDMA_FLTR_OUT_WIDTH 16 -#define ESE_DZ_FLTR_MULTICAST_VLAN 512 -#define ESE_DZ_FLTR_MAC_VLAN 256 -#define ESE_DZ_FLTR_STRUCTURED7 128 -#define ESE_DZ_FLTR_STRUCTURED6 64 -#define ESE_DZ_FLTR_STRUCTURED5 32 -#define ESE_DZ_FLTR_STRUCTURED4 16 -#define ESE_DZ_FLTR_STRUCTURED3 8 -#define ESE_DZ_FLTR_STRUCTURED2 4 -#define ESE_DZ_FLTR_STRUCTURED1 2 -#define ESE_DZ_FLTR_STRUCTURED0 1 -#define ESF_DZ_FLTR_INFO_MC_PDMA_TIMESTAMP_DW0_LBN 16 -#define ESF_DZ_FLTR_INFO_MC_PDMA_TIMESTAMP_DW0_WIDTH 32 -#define ESF_DZ_FLTR_INFO_MC_PDMA_TIMESTAMP_DW1_LBN 48 -#define ESF_DZ_FLTR_INFO_MC_PDMA_TIMESTAMP_DW1_WIDTH 16 -#define ESF_DZ_FLTR_INFO_MC_PDMA_TIMESTAMP_LBN 16 -#define ESF_DZ_FLTR_INFO_MC_PDMA_TIMESTAMP_WIDTH 48 -#define ESF_DZ_FLTR_INFO_MC_PDMA_DST_LBN 8 -#define ESF_DZ_FLTR_INFO_MC_PDMA_DST_WIDTH 8 -#define ESE_DZ_DST_NCSI 64 -#define ESE_DZ_DST_PORT0 32 -#define ESE_DZ_DST_PORT1 16 -#define ESE_DZ_DST_PORT0_IPSEC 8 -#define ESE_DZ_DST_PORT1_IPSEC 4 -#define ESE_DZ_DST_PM 2 -#define ESE_DZ_DST_TIMESTAMP 1 -#define ESF_DZ_FLTR_INFO_MC_PDMA_PRIORITY_LBN 4 -#define ESF_DZ_FLTR_INFO_MC_PDMA_PRIORITY_WIDTH 4 -#define ESF_DZ_FLTR_INFO_MC_PDMA_SRC_LBN 0 -#define ESF_DZ_FLTR_INFO_MC_PDMA_SRC_WIDTH 4 - - -/* ES_fltr_info_wrd_rxdi_to_rxdp */ -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_INNER_VLAN_LBN 112 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_INNER_VLAN_WIDTH 16 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_OUTER_VLAN_LBN 96 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_OUTER_VLAN_WIDTH 16 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_THASH1_LBN 80 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_THASH1_WIDTH 16 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_THASH0_LBN 64 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_THASH0_WIDTH 16 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_TIMESTAMP1_LBN 48 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_TIMESTAMP1_WIDTH 16 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_TIMESTAMP0_LBN 32 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_TIMESTAMP0_WIDTH 16 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_CNP_LBN 31 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_CNP_WIDTH 1 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_IVP_LBN 30 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_IVP_WIDTH 1 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_OVP_LBN 29 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_OVP_WIDTH 1 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_ST2_LBN 28 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_ST2_WIDTH 1 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_ST1_LBN 27 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_ST1_WIDTH 1 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_ST0_LBN 26 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_ST0_WIDTH 1 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_RX_QID_LBN 16 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_RX_QID_WIDTH 10 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_HOST_LBN 15 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_HOST_WIDTH 1 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_MC_LBN 14 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_MC_WIDTH 1 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_P0_LBN 13 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_P0_WIDTH 1 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_P1_LBN 12 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_P1_WIDTH 1 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_RESERVED1_LBN 11 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_RESERVED1_WIDTH 1 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_CRF_LBN 10 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_CRF_WIDTH 1 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_RESERVED0_LBN 9 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_RESERVED0_WIDTH 1 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_REPLAY_LBN 8 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_REPLAY_WIDTH 1 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_IPSEC_LBN 7 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_IPSEC_WIDTH 1 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_PRIORITY_LBN 4 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_PRIORITY_WIDTH 3 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_SRC_LBN 0 -#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_SRC_WIDTH 4 - - -/* ES_fltr_info_wrd_rxdp_to_host */ -#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED3_LBN 33 -#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED3_WIDTH 31 -#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RMON_SOFT_LBN 32 -#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RMON_SOFT_WIDTH 1 -#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED2_LBN 27 -#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED2_WIDTH 5 -#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RX_QID_LBN 16 -#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RX_QID_WIDTH 11 -#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_HOST_LBN 15 -#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_HOST_WIDTH 1 -#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_MC_LBN 14 -#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_MC_WIDTH 1 -#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_P0_LBN 13 -#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_P0_WIDTH 1 -#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_P1_LBN 12 -#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_P1_WIDTH 1 -#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED1_LBN 11 -#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED1_WIDTH 1 -#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_CRF_LBN 10 -#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_CRF_WIDTH 1 -#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED0_LBN 9 -#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED0_WIDTH 1 -#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_REPLAY_LBN 8 -#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_REPLAY_WIDTH 1 -#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_IPSEC_LBN 7 -#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_IPSEC_WIDTH 1 -#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_PRIORITY_LBN 4 -#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_PRIORITY_WIDTH 3 -#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_SRC_LBN 0 -#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_SRC_WIDTH 4 - - -/* ES_fltr_info_wrd_tx_to_mac */ -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_PRV_LBN 63 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_PRV_WIDTH 1 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_LB_LBN 62 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_LB_WIDTH 1 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_MS0_LBN 61 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_MS0_WIDTH 1 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_MS1_LBN 60 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_MS1_WIDTH 1 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_NDI_LBN 59 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_NDI_WIDTH 1 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_RESERVED2_LBN 48 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_RESERVED2_WIDTH 11 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_IPSEC_SA_LBN 32 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_IPSEC_SA_WIDTH 16 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_TX_STACK_ID_LBN 24 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_TX_STACK_ID_WIDTH 8 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_TX_DOMAIN_LBN 16 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_TX_DOMAIN_WIDTH 8 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_RESERVED1_LBN 14 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_RESERVED1_WIDTH 2 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_P0_LBN 13 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_P0_WIDTH 1 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_P1_LBN 12 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_P1_WIDTH 1 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_IP0_LBN 11 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_IP0_WIDTH 1 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_IP1_LBN 10 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_IP1_WIDTH 1 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_PM_LBN 9 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_PM_WIDTH 1 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_RESERVED0_LBN 8 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_RESERVED0_WIDTH 1 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_IPSEC_LBN 7 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_IPSEC_WIDTH 1 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_PRIORITY_LBN 4 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_PRIORITY_WIDTH 3 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_SRC_LBN 0 -#define ESF_DZ_FLTR_INFO_TX_TO_MAC_SRC_WIDTH 4 - - -/* ES_fltr_info_wrd_txdi_to_txdp */ -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_INNER_VLAN_LBN 112 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_INNER_VLAN_WIDTH 16 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_OUTER_VLAN_LBN 96 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_OUTER_VLAN_WIDTH 16 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_CNP_LBN 95 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_CNP_WIDTH 1 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_IVP_LBN 94 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_IVP_WIDTH 1 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_OVP_LBN 93 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_OVP_WIDTH 1 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED4_LBN 90 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED4_WIDTH 3 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_QID_LBN 80 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_QID_WIDTH 10 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_VRI_LBN 79 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_VRI_WIDTH 1 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED3_LBN 78 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED3_WIDTH 1 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_MTU_DIV4_LBN 66 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_MTU_DIV4_WIDTH 12 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_VRI_OP_LBN 64 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_VRI_OP_WIDTH 2 -#define ESE_DZ_VRI_OP_INSERT_REPLACE 3 -#define ESE_DZ_VRI_OP_INSERT_INSERT 2 -#define ESE_DZ_VRI_OP_REPLACE 1 -#define ESE_DZ_VRI_OP_INSERT 0 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_PRV_LBN 63 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_PRV_WIDTH 1 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_LB_LBN 62 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_LB_WIDTH 1 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_MS0_LBN 61 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_MS0_WIDTH 1 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_MS1_LBN 60 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_MS1_WIDTH 1 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_NDI_LBN 59 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_NDI_WIDTH 1 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_TXDP_CONTEXT_OUT_LBN 48 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_TXDP_CONTEXT_OUT_WIDTH 11 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_IPSEC_SA_LBN 32 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_IPSEC_SA_WIDTH 16 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_TX_STACK_ID_LBN 24 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_TX_STACK_ID_WIDTH 8 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_TX_DOMAIN_LBN 16 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_TX_DOMAIN_WIDTH 8 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED1_LBN 14 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED1_WIDTH 2 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_P0_LBN 13 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_P0_WIDTH 1 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_P1_LBN 12 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_P1_WIDTH 1 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_IP0_LBN 11 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_IP0_WIDTH 1 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_IP1_LBN 10 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_IP1_WIDTH 1 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_PM_LBN 9 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_PM_WIDTH 1 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED0_LBN 8 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED0_WIDTH 1 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_IPSEC_LBN 7 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_IPSEC_WIDTH 1 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_PRIORITY_LBN 4 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_PRIORITY_WIDTH 3 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_SRC_LBN 0 -#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_SRC_WIDTH 4 - - -/* ES_fltr_info_wrd_txdp_to_txdi */ -#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_VLAN_OP_LBN 62 -#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_VLAN_OP_WIDTH 2 -#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_RESERVED1_LBN 58 -#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_RESERVED1_WIDTH 4 -#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_TX_QID_LBN 48 -#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_TX_QID_WIDTH 10 -#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_INNER_VLAN_LBN 32 -#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_INNER_VLAN_WIDTH 16 -#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_OUTER_VLAN_LBN 16 -#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_OUTER_VLAN_WIDTH 16 -#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_TXDP_CONTEXT_IN_LBN 5 -#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_TXDP_CONTEXT_IN_WIDTH 11 -#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_RESERVED0_LBN 4 -#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_RESERVED0_WIDTH 1 -#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_SRC_LBN 0 -#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_SRC_WIDTH 4 - - -/* ES_nwk_ev_merge_blk_cmd */ -#define ESF_DZ_EV_MERGE_BLK_COMMAND_OP_LBN 28 -#define ESF_DZ_EV_MERGE_BLK_COMMAND_OP_WIDTH 4 -#define ESE_DZ_EV_MERGE_BLK_COMMAND_OP_FLUSH 2 -#define ESE_DZ_EV_MERGE_BLK_COMMAND_OP_ENABLE 1 -#define ESE_DZ_EV_MERGE_BLK_COMMAND_OP_DISABLE 0 -#define ESF_DZ_EV_MERGE_BLK_COMMAND_BUSY_LBN 31 -#define ESF_DZ_EV_MERGE_BLK_COMMAND_BUSY_WIDTH 1 -#define ESF_DZ_EV_MERGE_BLK_COMMAND_EVQ_IDX_LBN 0 -#define ESF_DZ_EV_MERGE_BLK_COMMAND_EVQ_IDX_WIDTH 11 - - -/* ES_txpm2ini_cpl_rsp */ -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_ECC_LBN 284 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_ECC_WIDTH 32 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_EOT_LBN 283 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_EOT_WIDTH 1 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW0_LBN 27 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW0_WIDTH 32 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW1_LBN 59 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW1_WIDTH 32 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW2_LBN 91 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW2_WIDTH 32 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW3_LBN 123 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW3_WIDTH 32 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW4_LBN 155 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW4_WIDTH 32 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW5_LBN 187 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW5_WIDTH 32 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW6_LBN 219 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW6_WIDTH 32 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW7_LBN 251 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW7_WIDTH 32 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_LBN 27 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_WIDTH 256 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_ERROR_LBN 26 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_ERROR_WIDTH 1 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_LAST_LBN 25 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_LAST_WIDTH 1 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_TAG_LBN 19 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_TAG_WIDTH 6 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_LEN_LBN 7 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_LEN_WIDTH 12 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_ADRS_LBN 0 -#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_ADRS_WIDTH 7 - - - -/* Enum INI_OP */ -#define ESE_DZ_RD_COMPL 0x3 -#define ESE_DZ_NOP 0x2 -#define ESE_DZ_WR 0x1 -#define ESE_DZ_RD 0x0 - -/* Enum INT_OP */ -#define ESE_DZ_LEGACY 0x2 -#define ESE_DZ_MSI 0x1 -#define ESE_DZ_MSIX 0x0 - -/* Enum MC_PDMA_BUFFER_ID */ -#define ESE_DZ_MC_PDMA_BUFFER_ALL 4 -#define ESE_DZ_MC_PDMA_BUFFER_RXDP 3 -#define ESE_DZ_MC_PDMA_BUFFER_NCSI 2 -#define ESE_DZ_MC_PDMA_BUFFER_NWPORT1 1 -#define ESE_DZ_MC_PDMA_BUFFER_NWPORT0 0 - -/* Enum MC_PDMA_INTERFACE_ID */ -#define ESE_DZ_MC_PDMA_INTERFACE_RXDP 3 -#define ESE_DZ_MC_PDMA_INTERFACE_NCSI 2 -#define ESE_DZ_MC_PDMA_INTERFACE_NWPORT1 1 -#define ESE_DZ_MC_PDMA_INTERFACE_NWPORT0 0 - -/* Enum PKT_STRM_CTL */ -#define ESE_DZ_EOP_TRUNC 0x3 -#define ESE_DZ_EOP_CRC_ERR 0x2 -#define ESE_DZ_EOP 0x1 -#define ESE_DZ_NOOP 0x0 - -/* Enum PM_EPI_PKT_MARKER */ -#define ESE_DZ_PM_EPI_LST 0x3 -#define ESE_DZ_PM_EPI_OBL 0x2 -#define ESE_DZ_PM_EPI_TBL 0x1 -#define ESE_DZ_PM_EPI_MDL 0x0 - -/* Enum PM_IPI_TO_PM_MM_COMMAND */ -#define ESE_DZ_FREE_CHAIN 0x3 -#define ESE_DZ_FREE_BUFFER 0x2 -#define ESE_DZ_ADD_BUFFER 0x1 -#define ESE_DZ_PM_MM_NOOP 0x0 - -/* Enum PM_MA_TO_PM_EPI_COMMAND */ -#define ESE_DZ_FROM_PORT_D 0x4 -#define ESE_DZ_FROM_PORT_C 0x3 -#define ESE_DZ_FROM_PORT_B 0x2 -#define ESE_DZ_FROM_PORT_A 0x1 -#define ESE_DZ_PM_EPI_NOOP 0x0 - -/* Enum PM_MA_TO_PM_IPI_COMMAND */ -#define ESE_DZ_TO_PORT_D 0x4 -#define ESE_DZ_TO_PORT_C 0x3 -#define ESE_DZ_TO_PORT_B 0x2 -#define ESE_DZ_TO_PORT_A 0x1 -#define ESE_DZ_PM_IPI_NOOP 0x0 +/************************************************************************* + * NOTE: the comment line above marks the end of the autogenerated section + */ + +/* + * The workaround for bug 35388 requires multiplexing writes through + * the ERF_DZ_TX_DESC_WPTR address. + * TX_DESC_UPD: 0ppppppppppp (bit 11 lost) + * EVQ_RPTR: 1000hhhhhhhh, 1001llllllll (split into high and low bits) + * EVQ_TMR: 11mmvvvvvvvv (bits 8:13 of value lost) + */ +#define ER_DD_EVQ_INDIRECT_OFST (ER_DZ_TX_DESC_UPD_REG_OFST + 2 * 4) +#define ER_DD_EVQ_INDIRECT_STEP ER_DZ_TX_DESC_UPD_REG_STEP +#define ERF_DD_EVQ_IND_RPTR_FLAGS_LBN 8 +#define ERF_DD_EVQ_IND_RPTR_FLAGS_WIDTH 4 +#define EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH 8 +#define EFE_DD_EVQ_IND_RPTR_FLAGS_LOW 9 +#define ERF_DD_EVQ_IND_RPTR_LBN 0 +#define ERF_DD_EVQ_IND_RPTR_WIDTH 8 +#define ERF_DD_EVQ_IND_TIMER_FLAGS_LBN 10 +#define ERF_DD_EVQ_IND_TIMER_FLAGS_WIDTH 2 +#define EFE_DD_EVQ_IND_TIMER_FLAGS 3 +#define ERF_DD_EVQ_IND_TIMER_MODE_LBN 8 +#define ERF_DD_EVQ_IND_TIMER_MODE_WIDTH 2 +#define ERF_DD_EVQ_IND_TIMER_VAL_LBN 0 +#define ERF_DD_EVQ_IND_TIMER_VAL_WIDTH 8 + + #ifdef __cplusplus } #endif diff --git a/sys/dev/sfxge/common/efx_regs_mcdi.h b/sys/dev/sfxge/common/efx_regs_mcdi.h index bd35970..a1d76ab 100644 --- a/sys/dev/sfxge/common/efx_regs_mcdi.h +++ b/sys/dev/sfxge/common/efx_regs_mcdi.h @@ -299,6 +299,9 @@ * have already installed filters. See the comment at * MC_CMD_WORKAROUND_BUG26807. */ #define MC_CMD_ERR_FILTERS_PRESENT 0x1014 +/* The clock whose frequency you've attempted to set set + * doesn't exist on this NIC */ +#define MC_CMD_ERR_NO_CLOCK 0x1015 #define MC_CMD_ERR_CODE_OFST 0 @@ -318,9 +321,11 @@ /* Point to the copycode entry point. */ #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4) #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4) +#define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4) /* Points to the recovery mode entry point. */ #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4) #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4) +#define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4) /* The command set exported by the boot ROM (MCDI v0) */ #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \ @@ -1456,9 +1461,11 @@ #define MC_CMD_FC_IN_DDR_TEST_START_B1_WIDTH 1 /* MC_CMD_FC_IN_DDR_TEST_POLL msgrequest */ -#define MC_CMD_FC_IN_DDR_TEST_POLL_LEN 8 +#define MC_CMD_FC_IN_DDR_TEST_POLL_LEN 12 #define MC_CMD_FC_IN_DDR_TEST_CMD_OFST 0 /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */ +/* Clear previous test result and prepare for restarting DDR test */ +#define MC_CMD_FC_IN_DDR_TEST_POLL_CLEAR_RESULT_FOR_DDR_TEST_OFST 8 /* MC_CMD_FC_IN_GET_ASSERT msgrequest */ #define MC_CMD_FC_IN_GET_ASSERT_LEN 4 @@ -1475,6 +1482,10 @@ #define MC_CMD_FC_IN_FPGA_BUILD_SERVICES 0x2 /* enum: Get the BSP version */ #define MC_CMD_FC_IN_FPGA_BUILD_BSP_VERSION 0x3 +/* enum: Get build register for V2 (SFA974X) */ +#define MC_CMD_FC_IN_FPGA_BUILD_BUILD_V2 0x4 +/* enum: GEt the services register for V2 (SFA974X) */ +#define MC_CMD_FC_IN_FPGA_BUILD_SERVICES_V2 0x5 /* MC_CMD_FC_IN_READ_MAP msgrequest */ #define MC_CMD_FC_IN_READ_MAP_LEN 8 @@ -1832,6 +1843,7 @@ #define MC_CMD_FC_IN_DDR_OP_OFST 4 #define MC_CMD_FC_IN_DDR_SET_SPD 0x0 /* enum */ #define MC_CMD_FC_IN_DDR_GET_STATUS 0x1 /* enum */ +#define MC_CMD_FC_IN_DDR_SET_INFO 0x2 /* enum */ #define MC_CMD_FC_IN_DDR_BANK_OFST 8 #define MC_CMD_FC_IN_DDR_BANK_B0 0x0 /* enum */ #define MC_CMD_FC_IN_DDR_BANK_B1 0x1 /* enum */ @@ -1855,6 +1867,15 @@ /* Page index of the spd data copied into MC_CMD_FC_IN_DDR_SPD */ #define MC_CMD_FC_IN_DDR_SPD_PAGE_ID_OFST 144 +/* MC_CMD_FC_IN_DDR_SET_INFO msgrequest */ +#define MC_CMD_FC_IN_DDR_SET_INFO_LEN 16 +/* MC_CMD_FC_IN_CMD_OFST 0 */ +/* MC_CMD_FC_IN_DDR_OP_OFST 4 */ +/* Affected bank */ +/* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ +/* Size of DDR */ +#define MC_CMD_FC_IN_DDR_SIZE_OFST 12 + /* MC_CMD_FC_IN_DDR_GET_STATUS msgrequest */ #define MC_CMD_FC_IN_DDR_GET_STATUS_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ @@ -2387,6 +2408,116 @@ #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_LBN 0 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_WIDTH 16 +/* MC_CMD_FC_OUT_FPGA_BUILD_V2 msgresponse */ +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_LEN 32 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_OFST 0 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_LBN 31 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_LBN 30 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_LBN 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_WIDTH 14 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_LBN 12 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_WIDTH 4 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_LBN 4 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_WIDTH 8 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_LBN 0 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_WIDTH 4 +/* Build timestamp (seconds since epoch) */ +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_TIMESTAMP_OFST 4 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_OFST 8 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_LBN 31 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_LBN 29 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_LBN 28 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_LBN 27 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_LBN 26 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_LBN 25 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_LBN 24 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_LBN 23 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_LBN 22 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_LBN 21 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_LBN 20 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_LBN 19 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_LBN 18 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_10G 0x0 /* enum */ +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_40G 0x1 /* enum */ +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_LBN 17 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_10G 0x0 /* enum */ +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_40G 0x1 /* enum */ +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_LBN 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_10G 0x0 /* enum */ +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_40G 0x1 /* enum */ +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_LBN 15 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_LBN 14 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_LBN 13 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_LBN 12 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_LBN 11 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_LBN 10 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_LBN 9 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_LBN 8 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_LBN 7 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_LBN 6 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_LBN 5 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_LBN 4 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_LBN 0 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_WIDTH 4 +#define MC_CMD_FC_FPGA_V2_TYPE_A3 0x0 /* enum */ +#define MC_CMD_FC_FPGA_V2_TYPE_A4 0x1 /* enum */ +#define MC_CMD_FC_FPGA_V2_TYPE_A5 0x2 /* enum */ +#define MC_CMD_FC_FPGA_V2_TYPE_A7 0x3 /* enum */ +#define MC_CMD_FC_FPGA_V2_TYPE_D3 0x8 /* enum */ +#define MC_CMD_FC_FPGA_V2_TYPE_D4 0x9 /* enum */ +#define MC_CMD_FC_FPGA_V2_TYPE_D5 0xa /* enum */ +#define MC_CMD_FC_FPGA_V2_TYPE_D7 0xb /* enum */ +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_OFST 12 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_LBN 0 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_WIDTH 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_LBN 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_WIDTH 1 +/* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */ +/* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */ +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_OFST 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_LBN 0 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_WIDTH 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_LBN 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_WIDTH 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_OFST 20 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_LBN 0 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_WIDTH 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_LBN 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_WIDTH 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_OFST 24 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_OFST 28 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_LBN 0 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_WIDTH 16 + /* MC_CMD_FC_OUT_FPGA_SERVICES msgresponse */ #define MC_CMD_FC_OUT_FPGA_SERVICES_LEN 32 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_OFST 0 @@ -2437,6 +2568,40 @@ #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_LBN 0 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_WIDTH 16 +/* MC_CMD_FC_OUT_FPGA_SERVICES_V2 msgresponse */ +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_LEN 32 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_OFST 0 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_LBN 31 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_LBN 30 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_LBN 16 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_WIDTH 14 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_LBN 12 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_WIDTH 4 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_LBN 4 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_WIDTH 8 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_LBN 0 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_WIDTH 4 +/* Build timestamp (seconds since epoch) */ +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_TIMESTAMP_OFST 4 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_OFST 8 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_LBN 0 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_LBN 8 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_OFST 12 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_LBN 0 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_WIDTH 16 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_LBN 16 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_WIDTH 1 +/* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */ +/* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */ +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_LO_OFST 24 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_OFST 28 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_LBN 0 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_WIDTH 16 + /* MC_CMD_FC_OUT_BSP_VERSION msgresponse */ #define MC_CMD_FC_OUT_BSP_VERSION_LEN 4 /* Qsys system ID */ @@ -2718,6 +2883,9 @@ /* MC_CMD_FC_OUT_DDR_SET_SPD msgresponse */ #define MC_CMD_FC_OUT_DDR_SET_SPD_LEN 0 +/* MC_CMD_FC_OUT_DDR_SET_INFO msgresponse */ +#define MC_CMD_FC_OUT_DDR_SET_INFO_LEN 0 + /* MC_CMD_FC_OUT_DDR_GET_STATUS msgresponse */ #define MC_CMD_FC_OUT_DDR_GET_STATUS_LEN 4 #define MC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_OFST 0 @@ -3131,6 +3299,8 @@ #define MC_CMD_AOE_OUT_INFO_FPGA_VERSION_OFST 12 /* FPGA type - read from CPLD straps */ #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_OFST 16 +#define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A5_C2 0x1 /* enum */ +#define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A7_C2 0x2 /* enum */ /* FPGA state (debug) */ #define MC_CMD_AOE_OUT_INFO_FPGA_STATE_OFST 20 /* FPGA image - partition from which loaded */ @@ -3144,23 +3314,28 @@ /* Random pieces of information */ #define MC_CMD_AOE_OUT_INFO_FLAGS_OFST 32 /* enum: Power to FPGA supplied by PEG connector, not PCIe bus */ -#define MC_CMD_AOE_OUT_INFO_PEG_POWER 0x1 +#define MC_CMD_AOE_OUT_INFO_PEG_POWER 0x1 /* enum: CPLD apparently good */ -#define MC_CMD_AOE_OUT_INFO_CPLD_GOOD 0x2 +#define MC_CMD_AOE_OUT_INFO_CPLD_GOOD 0x2 /* enum: FPGA working normally */ -#define MC_CMD_AOE_OUT_INFO_FPGA_GOOD 0x4 +#define MC_CMD_AOE_OUT_INFO_FPGA_GOOD 0x4 /* enum: FPGA is powered */ -#define MC_CMD_AOE_OUT_INFO_FPGA_POWER 0x8 +#define MC_CMD_AOE_OUT_INFO_FPGA_POWER 0x8 /* enum: Board has incompatible SODIMMs fitted */ -#define MC_CMD_AOE_OUT_INFO_BAD_SODIMM 0x10 +#define MC_CMD_AOE_OUT_INFO_BAD_SODIMM 0x10 /* enum: Board has ByteBlaster connected */ -#define MC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER 0x20 -/* Revision of Modena board */ +#define MC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER 0x20 +/* enum: FPGA Boot flash has an invalid header. */ +#define MC_CMD_AOE_OUT_INFO_FPGA_BAD_BOOT_HDR 0x40 +/* enum: FPGA Application flash is accessible. */ +#define MC_CMD_AOE_OUT_INFO_FPGA_APP_FLASH_GOOD 0x80 +/* Revision of Modena and Sorrento boards. Sorrento can be R1_2 or R1_3. */ #define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_OFST 36 #define MC_CMD_AOE_OUT_INFO_UNKNOWN 0x0 /* enum */ #define MC_CMD_AOE_OUT_INFO_R1_0 0x10 /* enum */ #define MC_CMD_AOE_OUT_INFO_R1_1 0x11 /* enum */ #define MC_CMD_AOE_OUT_INFO_R1_2 0x12 /* enum */ +#define MC_CMD_AOE_OUT_INFO_R1_3 0x13 /* enum */ /* Result of FC booting - not valid while a ByteBlaster is connected. */ #define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_OFST 40 /* enum: No error */ @@ -3931,15 +4106,30 @@ /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */ #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16 -/* Uncorrected error on transmit timestamps in NIC clock format */ +/* Uncorrected error on PTP transmit timestamps in NIC clock format */ #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0 -/* Uncorrected error on receive timestamps in NIC clock format */ +/* Uncorrected error on PTP receive timestamps in NIC clock format */ #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4 /* Uncorrected error on PPS output in NIC clock format */ #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8 /* Uncorrected error on PPS input in NIC clock format */ #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12 +/* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2 msgresponse */ +#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_LEN 24 +/* Uncorrected error on PTP transmit timestamps in NIC clock format */ +#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0 +/* Uncorrected error on PTP receive timestamps in NIC clock format */ +#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4 +/* Uncorrected error on PPS output in NIC clock format */ +#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_OFST 8 +/* Uncorrected error on PPS input in NIC clock format */ +#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_OFST 12 +/* Uncorrected error on non-PTP transmit timestamps in NIC clock format */ +#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_OFST 16 +/* Uncorrected error on non-PTP receive timestamps in NIC clock format */ +#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_OFST 20 + /* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */ #define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4 /* Results of testing */ @@ -4451,8 +4641,12 @@ /* MC_CMD_DRV_ATTACH_IN msgrequest */ #define MC_CMD_DRV_ATTACH_IN_LEN 12 -/* new state (0=detached, 1=attached) to set if UPDATE=1 */ +/* new state to set if UPDATE=1 */ #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0 +#define MC_CMD_DRV_ATTACH_LBN 0 +#define MC_CMD_DRV_ATTACH_WIDTH 1 +#define MC_CMD_DRV_PREBOOT_LBN 1 +#define MC_CMD_DRV_PREBOOT_WIDTH 1 /* 1 to set new state, or 0 to just report the existing state */ #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4 /* preferred datapath firmware (for Huntington; ignored for Siena) */ @@ -4474,12 +4668,12 @@ /* MC_CMD_DRV_ATTACH_OUT msgresponse */ #define MC_CMD_DRV_ATTACH_OUT_LEN 4 -/* previous or existing state (0=detached, 1=attached) */ +/* previous or existing state, see the bitmask at NEW_STATE */ #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0 /* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */ #define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8 -/* previous or existing state (0=detached, 1=attached) */ +/* previous or existing state, see the bitmask at NEW_STATE */ #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0 /* Flags associated with this function */ #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4 @@ -4491,6 +4685,10 @@ #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1 /* enum: The function can perform privileged operations */ #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2 +/* enum: The function does not have an active port associated with it. The port + * refers to the Sorrento external FPGA port. + */ +#define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x3 /***********************************/ @@ -5195,7 +5393,7 @@ #define MC_CMD_SET_MAC 0x2c #undef MC_CMD_0x2c_PRIVILEGE_CTG -#define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_LINK +#define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL /* MC_CMD_SET_MAC_IN msgrequest */ #define MC_CMD_SET_MAC_IN_LEN 28 @@ -5230,6 +5428,55 @@ #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_WIDTH 1 +/* MC_CMD_SET_MAC_EXT_IN msgrequest */ +#define MC_CMD_SET_MAC_EXT_IN_LEN 32 +/* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of + * EtherII, VLAN, bug16011 padding). + */ +#define MC_CMD_SET_MAC_EXT_IN_MTU_OFST 0 +#define MC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 4 +#define MC_CMD_SET_MAC_EXT_IN_ADDR_OFST 8 +#define MC_CMD_SET_MAC_EXT_IN_ADDR_LEN 8 +#define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_OFST 8 +#define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_OFST 12 +#define MC_CMD_SET_MAC_EXT_IN_REJECT_OFST 16 +#define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0 +#define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_WIDTH 1 +#define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_LBN 1 +#define MC_CMD_SET_MAC_EXT_IN_REJECT_BRDCST_WIDTH 1 +#define MC_CMD_SET_MAC_EXT_IN_FCNTL_OFST 20 +/* enum: Flow control is off. */ +/* MC_CMD_FCNTL_OFF 0x0 */ +/* enum: Respond to flow control. */ +/* MC_CMD_FCNTL_RESPOND 0x1 */ +/* enum: Respond to and Issue flow control. */ +/* MC_CMD_FCNTL_BIDIR 0x2 */ +/* enum: Auto neg flow control. */ +/* MC_CMD_FCNTL_AUTO 0x3 */ +/* enum: Priority flow control (eftest builds only). */ +/* MC_CMD_FCNTL_QBB 0x4 */ +/* enum: Issue flow control. */ +/* MC_CMD_FCNTL_GENERATE 0x5 */ +#define MC_CMD_SET_MAC_EXT_IN_FLAGS_OFST 24 +#define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0 +#define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_WIDTH 1 +/* Select which parameters to configure. A parameter will only be modified if + * the corresponding control flag is set. If SET_MAC_ENHANCED is not set in + * capabilities then this field is ignored (and all flags are assumed to be + * set). + */ +#define MC_CMD_SET_MAC_EXT_IN_CONTROL_OFST 28 +#define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0 +#define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_WIDTH 1 +#define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_LBN 1 +#define MC_CMD_SET_MAC_EXT_IN_CFG_DRAIN_WIDTH 1 +#define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_LBN 2 +#define MC_CMD_SET_MAC_EXT_IN_CFG_REJECT_WIDTH 1 +#define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_LBN 3 +#define MC_CMD_SET_MAC_EXT_IN_CFG_FCNTL_WIDTH 1 +#define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4 +#define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_WIDTH 1 + /* MC_CMD_SET_MAC_OUT msgresponse */ #define MC_CMD_SET_MAC_OUT_LEN 0 @@ -5831,6 +6078,26 @@ #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20 +/* MC_CMD_NVRAM_INFO_V2_OUT msgresponse */ +#define MC_CMD_NVRAM_INFO_V2_OUT_LEN 28 +#define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_OFST 0 +/* Enum values, see field(s): */ +/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ +#define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_OFST 4 +#define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_OFST 8 +#define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_OFST 12 +#define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 0 +#define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_WIDTH 1 +#define MC_CMD_NVRAM_INFO_V2_OUT_TLV_LBN 1 +#define MC_CMD_NVRAM_INFO_V2_OUT_TLV_WIDTH 1 +#define MC_CMD_NVRAM_INFO_V2_OUT_A_B_LBN 7 +#define MC_CMD_NVRAM_INFO_V2_OUT_A_B_WIDTH 1 +#define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_OFST 16 +#define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_OFST 20 +/* Writes must be multiples of this size. Added to support the MUM on Sorrento. + */ +#define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_OFST 24 + /***********************************/ /* MC_CMD_NVRAM_UPDATE_START @@ -5873,6 +6140,37 @@ /* amount to read in bytes */ #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8 +/* MC_CMD_NVRAM_READ_IN_V2 msgrequest */ +#define MC_CMD_NVRAM_READ_IN_V2_LEN 16 +#define MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0 +/* Enum values, see field(s): */ +/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ +#define MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4 +/* amount to read in bytes */ +#define MC_CMD_NVRAM_READ_IN_V2_LENGTH_OFST 8 +/* Optional control info. If a partition is stored with an A/B versioning + * scheme (i.e. in more than one physical partition in NVRAM) the host can set + * this to control which underlying physical partition is used to read data + * from. This allows it to perform a read-modify-write-verify with the write + * lock continuously held by calling NVRAM_UPDATE_START, reading the old + * contents using MODE=TARGET_CURRENT, overwriting the old partition and then + * verifying by reading with MODE=TARGET_BACKUP. + */ +#define MC_CMD_NVRAM_READ_IN_V2_MODE_OFST 12 +/* enum: Same as omitting MODE: caller sees data in current partition unless it + * holds the write lock in which case it sees data in the partition it is + * updating. + */ +#define MC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x0 +/* enum: Read from the current partition of an A/B pair, even if holding the + * write lock. + */ +#define MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x1 +/* enum: Read from the non-current (i.e. to be updated) partition of an A/B + * pair + */ +#define MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x2 + /* MC_CMD_NVRAM_READ_OUT msgresponse */ #define MC_CMD_NVRAM_READ_OUT_LENMIN 1 #define MC_CMD_NVRAM_READ_OUT_LENMAX 252 @@ -6214,6 +6512,8 @@ #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39 /* enum: CCOM AVREG 1v8 supply (external ADC): mV */ #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a +/* enum: CCOM RTS temperature: degC */ +#define MC_CMD_SENSOR_CONTROLLER_RTS 0x3b /* enum: Not a sensor: reserved for the next page flag */ #define MC_CMD_SENSOR_PAGE1_NEXT 0x3f /* enum: controller internal temperature sensor voltage on master core @@ -6250,6 +6550,8 @@ #define MC_CMD_SENSOR_PHY0_VCC 0x4c /* enum: Voltage supplied to the QSFP #1 from their power supply: mV */ #define MC_CMD_SENSOR_PHY1_VCC 0x4d +/* enum: Controller die temperature (TDIODE): degC */ +#define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ #define MC_CMD_SENSOR_ENTRY_OFST 4 #define MC_CMD_SENSOR_ENTRY_LEN 8 @@ -6327,7 +6629,7 @@ /* MC_CMD_READ_SENSORS_EXT_IN msgrequest */ #define MC_CMD_READ_SENSORS_EXT_IN_LEN 12 -/* DMA address of host buffer for sensor readings */ +/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0 @@ -6942,6 +7244,10 @@ * operations */ #define MC_CMD_MUM_OP_QSFP 0xc +/* enum: Request discrete and SODIMM DDR info (type, size, speed grade, voltage + * level) from MUM + */ +#define MC_CMD_MUM_OP_READ_DDR_INFO 0xd /* MC_CMD_MUM_IN_NULL msgrequest */ #define MC_CMD_MUM_IN_NULL_LEN 4 @@ -7127,6 +7433,10 @@ #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_OFST 8 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_WIDTH 1 +#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_LBN 1 +#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_NIC_FROM_FPGA_WIDTH 1 +#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_LBN 2 +#define MC_CMD_MUM_IN_PROGRAM_CLOCKS_CLOCK_REF_FROM_XO_WIDTH 1 /* MC_CMD_MUM_IN_FPGA_LOAD msgrequest */ #define MC_CMD_MUM_IN_FPGA_LOAD_LEN 8 @@ -7196,6 +7506,11 @@ #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 4 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_OFST 8 +/* MC_CMD_MUM_IN_READ_DDR_INFO msgrequest */ +#define MC_CMD_MUM_IN_READ_DDR_INFO_LEN 4 +/* MUM cmd header */ +/* MC_CMD_MUM_IN_CMD_OFST 0 */ + /* MC_CMD_MUM_OUT msgresponse */ #define MC_CMD_MUM_OUT_LEN 0 @@ -7338,6 +7653,69 @@ #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 4 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 0 +/* MC_CMD_MUM_OUT_READ_DDR_INFO msgresponse */ +#define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMIN 24 +#define MC_CMD_MUM_OUT_READ_DDR_INFO_LENMAX 248 +#define MC_CMD_MUM_OUT_READ_DDR_INFO_LEN(num) (8+8*(num)) +/* Discrete (soldered) DDR resistor strap info */ +#define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0 +#define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 0 +#define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_WIDTH 16 +#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_LBN 16 +#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_WIDTH 16 +/* Number of SODIMM info records */ +#define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_OFST 4 +/* Array of SODIMM info records */ +#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_OFST 8 +#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LEN 8 +#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_OFST 8 +#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_OFST 12 +#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MINNUM 2 +#define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_MAXNUM 30 +#define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 0 +#define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_WIDTH 8 +/* enum: SODIMM bank 1 (Top SODIMM for Sorrento) */ +#define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK1 0x0 +/* enum: SODIMM bank 2 (Bottom SODDIMM for Sorrento) */ +#define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x1 +/* enum: Total number of SODIMM banks */ +#define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x2 +#define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_LBN 8 +#define MC_CMD_MUM_OUT_READ_DDR_INFO_TYPE_WIDTH 8 +#define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_LBN 16 +#define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 4 +#define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_LBN 20 +#define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 4 +#define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */ +#define MC_CMD_MUM_OUT_READ_DDR_INFO_1V25 0x1 /* enum */ +#define MC_CMD_MUM_OUT_READ_DDR_INFO_1V35 0x2 /* enum */ +#define MC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */ +/* enum: Values 5-15 are reserved for future usage */ +#define MC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x4 +#define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_LBN 24 +#define MC_CMD_MUM_OUT_READ_DDR_INFO_SIZE_WIDTH 8 +#define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_LBN 32 +#define MC_CMD_MUM_OUT_READ_DDR_INFO_SPEED_WIDTH 16 +#define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_LBN 48 +#define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 4 +/* enum: No module present */ +#define MC_CMD_MUM_OUT_READ_DDR_INFO_ABSENT 0x0 +/* enum: Module present supported and powered on */ +#define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_POWERED 0x1 +/* enum: Module present but bad type */ +#define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_TYPE 0x2 +/* enum: Module present but incompatible voltage */ +#define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_VOLTAGE 0x3 +/* enum: Module present but unknown SPD */ +#define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SPD 0x4 +/* enum: Module present but slot cannot support it */ +#define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SLOT 0x5 +/* enum: Modules may or may not be present, but cannot establish contact by I2C + */ +#define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x6 +#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_LBN 52 +#define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED2_WIDTH 12 + /* MC_CMD_RESOURCE_SPECIFIER enum */ /* enum: Any */ #define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff @@ -7410,6 +7788,8 @@ #define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500 /* enum: Expansion ROM configuration data for port 0 */ #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600 +/* enum: Synonym for EXPROM_CONFIG_PORT0 as used in pmap files */ +#define NVRAM_PARTITION_TYPE_EXPROM_CONFIG 0x600 /* enum: Expansion ROM configuration data for port 1 */ #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601 /* enum: Expansion ROM configuration data for port 2 */ @@ -7418,6 +7798,8 @@ #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603 /* enum: Non-volatile log output partition */ #define NVRAM_PARTITION_TYPE_LOG 0x700 +/* enum: Non-volatile log output of second core on dual-core device */ +#define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701 /* enum: Device state dump output partition */ #define NVRAM_PARTITION_TYPE_DUMP 0x800 /* enum: Application license key storage partition */ @@ -7450,6 +7832,20 @@ #define NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05 /* enum: MUM fuses and lockbits partition. */ #define NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06 +/* enum: UEFI expansion ROM if separate from PXE */ +#define NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00 +/* enum: Spare partition 0 */ +#define NVRAM_PARTITION_TYPE_SPARE_0 0x1000 +/* enum: Spare partition 1 */ +#define NVRAM_PARTITION_TYPE_SPARE_1 0x1100 +/* enum: Spare partition 2 */ +#define NVRAM_PARTITION_TYPE_SPARE_2 0x1200 +/* enum: Spare partition 3 */ +#define NVRAM_PARTITION_TYPE_SPARE_3 0x1300 +/* enum: Spare partition 4 */ +#define NVRAM_PARTITION_TYPE_SPARE_4 0x1400 +/* enum: Spare partition 5 */ +#define NVRAM_PARTITION_TYPE_SPARE_5 0x1500 /* enum: Start of reserved value range (firmware may use for any purpose) */ #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00 /* enum: End of reserved value range (firmware may use for any purpose) */ @@ -7483,6 +7879,88 @@ #define LICENSED_APP_ID_ID_LBN 0 #define LICENSED_APP_ID_ID_WIDTH 32 +/* LICENSED_FEATURES structuredef */ +#define LICENSED_FEATURES_LEN 8 +/* Bitmask of licensed firmware features */ +#define LICENSED_FEATURES_MASK_OFST 0 +#define LICENSED_FEATURES_MASK_LEN 8 +#define LICENSED_FEATURES_MASK_LO_OFST 0 +#define LICENSED_FEATURES_MASK_HI_OFST 4 +#define LICENSED_FEATURES_RX_CUT_THROUGH_LBN 0 +#define LICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1 +#define LICENSED_FEATURES_PIO_LBN 1 +#define LICENSED_FEATURES_PIO_WIDTH 1 +#define LICENSED_FEATURES_EVQ_TIMER_LBN 2 +#define LICENSED_FEATURES_EVQ_TIMER_WIDTH 1 +#define LICENSED_FEATURES_CLOCK_LBN 3 +#define LICENSED_FEATURES_CLOCK_WIDTH 1 +#define LICENSED_FEATURES_RX_TIMESTAMPS_LBN 4 +#define LICENSED_FEATURES_RX_TIMESTAMPS_WIDTH 1 +#define LICENSED_FEATURES_TX_TIMESTAMPS_LBN 5 +#define LICENSED_FEATURES_TX_TIMESTAMPS_WIDTH 1 +#define LICENSED_FEATURES_RX_SNIFF_LBN 6 +#define LICENSED_FEATURES_RX_SNIFF_WIDTH 1 +#define LICENSED_FEATURES_TX_SNIFF_LBN 7 +#define LICENSED_FEATURES_TX_SNIFF_WIDTH 1 +#define LICENSED_FEATURES_PROXY_FILTER_OPS_LBN 8 +#define LICENSED_FEATURES_PROXY_FILTER_OPS_WIDTH 1 +#define LICENSED_FEATURES_MASK_LBN 0 +#define LICENSED_FEATURES_MASK_WIDTH 64 + +/* LICENSED_V3_APPS structuredef */ +#define LICENSED_V3_APPS_LEN 8 +/* Bitmask of licensed applications */ +#define LICENSED_V3_APPS_MASK_OFST 0 +#define LICENSED_V3_APPS_MASK_LEN 8 +#define LICENSED_V3_APPS_MASK_LO_OFST 0 +#define LICENSED_V3_APPS_MASK_HI_OFST 4 +#define LICENSED_V3_APPS_ONLOAD_LBN 0 +#define LICENSED_V3_APPS_ONLOAD_WIDTH 1 +#define LICENSED_V3_APPS_PTP_LBN 1 +#define LICENSED_V3_APPS_PTP_WIDTH 1 +#define LICENSED_V3_APPS_SOLARCAPTURE_PRO_LBN 2 +#define LICENSED_V3_APPS_SOLARCAPTURE_PRO_WIDTH 1 +#define LICENSED_V3_APPS_SOLARSECURE_LBN 3 +#define LICENSED_V3_APPS_SOLARSECURE_WIDTH 1 +#define LICENSED_V3_APPS_PERF_MONITOR_LBN 4 +#define LICENSED_V3_APPS_PERF_MONITOR_WIDTH 1 +#define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_LBN 5 +#define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_WIDTH 1 +#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_LBN 6 +#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_WIDTH 1 +#define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_LBN 7 +#define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_WIDTH 1 +#define LICENSED_V3_APPS_MASK_LBN 0 +#define LICENSED_V3_APPS_MASK_WIDTH 64 + +/* LICENSED_V3_FEATURES structuredef */ +#define LICENSED_V3_FEATURES_LEN 8 +/* Bitmask of licensed firmware features */ +#define LICENSED_V3_FEATURES_MASK_OFST 0 +#define LICENSED_V3_FEATURES_MASK_LEN 8 +#define LICENSED_V3_FEATURES_MASK_LO_OFST 0 +#define LICENSED_V3_FEATURES_MASK_HI_OFST 4 +#define LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0 +#define LICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1 +#define LICENSED_V3_FEATURES_PIO_LBN 1 +#define LICENSED_V3_FEATURES_PIO_WIDTH 1 +#define LICENSED_V3_FEATURES_EVQ_TIMER_LBN 2 +#define LICENSED_V3_FEATURES_EVQ_TIMER_WIDTH 1 +#define LICENSED_V3_FEATURES_CLOCK_LBN 3 +#define LICENSED_V3_FEATURES_CLOCK_WIDTH 1 +#define LICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 4 +#define LICENSED_V3_FEATURES_RX_TIMESTAMPS_WIDTH 1 +#define LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN 5 +#define LICENSED_V3_FEATURES_TX_TIMESTAMPS_WIDTH 1 +#define LICENSED_V3_FEATURES_RX_SNIFF_LBN 6 +#define LICENSED_V3_FEATURES_RX_SNIFF_WIDTH 1 +#define LICENSED_V3_FEATURES_TX_SNIFF_LBN 7 +#define LICENSED_V3_FEATURES_TX_SNIFF_WIDTH 1 +#define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_LBN 8 +#define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_WIDTH 1 +#define LICENSED_V3_FEATURES_MASK_LBN 0 +#define LICENSED_V3_FEATURES_MASK_WIDTH 64 + /* TX_TIMESTAMP_EVENT structuredef */ #define TX_TIMESTAMP_EVENT_LEN 6 /* lower 16 bits of timestamp data */ @@ -7699,6 +8177,8 @@ #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_LBN 9 #define MC_CMD_INIT_RXQ_IN_FLAG_DISABLE_SCATTER_WIDTH 1 +#define MC_CMD_INIT_RXQ_IN_FLAG_FORCE_EV_MERGING_LBN 10 +#define MC_CMD_INIT_RXQ_IN_FLAG_FORCE_EV_MERGING_WIDTH 1 /* Owner ID to use if in buffer mode (zero if physical) */ #define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ @@ -7759,6 +8239,8 @@ #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */ #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_LBN 18 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES_WIDTH 1 +#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_LBN 19 +#define MC_CMD_INIT_RXQ_EXT_IN_FLAG_FORCE_EV_MERGING_WIDTH 1 /* Owner ID to use if in buffer mode (zero if physical) */ #define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_OFST 20 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ @@ -7873,6 +8355,8 @@ #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 +#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_LBN 12 +#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_WIDTH 1 /* Owner ID to use if in buffer mode (zero if physical) */ #define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 20 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ @@ -8091,6 +8575,46 @@ #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_OFST 44 #define MC_CMD_PROXY_CONFIGURE_IN_ALLOWED_MCDI_MASK_LEN 64 +/* MC_CMD_PROXY_CONFIGURE_EXT_IN msgrequest */ +#define MC_CMD_PROXY_CONFIGURE_EXT_IN_LEN 112 +#define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_OFST 0 +#define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_LBN 0 +#define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_WIDTH 1 +/* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS + * of blocks, each of the size REQUEST_BLOCK_SIZE. + */ +#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_OFST 4 +#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LEN 8 +#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_OFST 4 +#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_OFST 8 +/* Must be a power of 2 */ +#define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_OFST 12 +/* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS + * of blocks, each of the size REPLY_BLOCK_SIZE. + */ +#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_OFST 16 +#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LEN 8 +#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_OFST 16 +#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_OFST 20 +/* Must be a power of 2 */ +#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_OFST 24 +/* Host provides a contiguous memory buffer that contains at least NUM_BLOCKS + * of blocks, each of the size STATUS_BLOCK_SIZE. This buffer is only needed if + * host intends to complete proxied operations by using MC_CMD_PROXY_CMD. + */ +#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_OFST 28 +#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LEN 8 +#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_OFST 28 +#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_OFST 32 +/* Must be a power of 2, or zero if this buffer is not provided */ +#define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_OFST 36 +/* Applies to all three buffers */ +#define MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_OFST 40 +/* A bit mask defining which MCDI operations may be proxied */ +#define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_OFST 44 +#define MC_CMD_PROXY_CONFIGURE_EXT_IN_ALLOWED_MCDI_MASK_LEN 64 +#define MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_OFST 108 + /* MC_CMD_PROXY_CONFIGURE_OUT msgresponse */ #define MC_CMD_PROXY_CONFIGURE_OUT_LEN 0 @@ -8706,7 +9230,10 @@ /***********************************/ /* MC_CMD_PARSER_DISP_RW - * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging + * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging. + * Please note that this interface is only of use to debug tools which have + * knowledge of firmware and hardware data structures; nothing here is intended + * for use by normal driver code. */ #define MC_CMD_PARSER_DISP_RW 0xe5 #undef MC_CMD_0xe5_PRIVILEGE_CTG @@ -8725,6 +9252,12 @@ #define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2 /* enum: Lookup engine (with requested metadata format) */ #define MC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA 0x3 +/* enum: RX0 dispatcher CPU (alias for RX_DICPU; Medford has 2 RX DICPUs) */ +#define MC_CMD_PARSER_DISP_RW_IN_RX0_DICPU 0x0 +/* enum: RX1 dispatcher CPU (only valid for Medford) */ +#define MC_CMD_PARSER_DISP_RW_IN_RX1_DICPU 0x4 +/* enum: Miscellaneous other state (only valid for Medford) */ +#define MC_CMD_PARSER_DISP_RW_IN_MISC_STATE 0x5 /* identifies the type of operation requested */ #define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4 /* enum: read a word of DICPU DMEM or a LUE entry */ @@ -8733,8 +9266,12 @@ #define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1 /* enum: read-modify-write a word of DICPU DMEM (not valid for LUE) */ #define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2 -/* data memory address or LUE index */ +/* data memory address (DICPU targets) or LUE index (LUE targets) */ #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8 +/* selector (for MISC_STATE target) */ +#define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_OFST 8 +/* enum: Port to datapath mapping */ +#define MC_CMD_PARSER_DISP_RW_IN_PORT_DP_MAPPING 0x1 /* value to write (for DMEM writes) */ #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12 /* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */ @@ -8759,6 +9296,12 @@ */ #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 20 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 32 +/* datapath(s) used for each port (for MISC_STATE PORT_DP_MAPPING selector) */ +#define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_OFST 0 +#define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_LEN 4 +#define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_NUM 4 +#define MC_CMD_PARSER_DISP_RW_OUT_DP0 0x1 /* enum */ +#define MC_CMD_PARSER_DISP_RW_OUT_DP1 0x2 /* enum */ /***********************************/ @@ -9439,6 +9982,24 @@ #define MC_CMD_GET_CAPABILITIES_OUT_LEN 20 /* First word of flags. */ #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0 +#define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_LBN 3 +#define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 4 +#define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN 5 +#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 +#define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_LBN 7 +#define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_LBN 8 +#define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_LBN 9 +#define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 +#define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 +#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN 13 @@ -9506,6 +10067,8 @@ #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 /* enum: RXDP Test firmware image 8 */ #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 +/* enum: RXDP Test firmware image 9 */ +#define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b /* TxDPCPU firmware id. */ #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2 @@ -9595,6 +10158,200 @@ /* Licensed capabilities */ #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16 +/* MC_CMD_GET_CAPABILITIES_V2_IN msgrequest */ +#define MC_CMD_GET_CAPABILITIES_V2_IN_LEN 0 + +/* MC_CMD_GET_CAPABILITIES_V2_OUT msgresponse */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_LEN 26 +/* First word of flags. */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 0 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_LBN 3 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 4 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_LBN 5 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_LBN 7 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_LBN 8 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_LBN 9 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_LBN 13 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_LBN 14 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_LBN 16 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_LBN 17 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_LBN 18 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_LBN 19 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_LBN 20 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_LBN 21 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_LBN 22 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_LBN 23 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_LBN 24 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_LBN 25 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_LBN 26 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_LBN 27 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_LBN 28 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_LBN 30 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_LBN 31 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_WIDTH 1 +/* RxDPCPU firmware id. */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_OFST 4 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_LEN 2 +/* enum: Standard RXDP firmware */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP 0x0 +/* enum: Low latency RXDP firmware */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY 0x1 +/* enum: Packed stream RXDP firmware */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x2 +/* enum: BIST RXDP firmware */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a +/* enum: RXDP Test firmware image 1 */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 +/* enum: RXDP Test firmware image 2 */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 +/* enum: RXDP Test firmware image 3 */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 +/* enum: RXDP Test firmware image 4 */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 +/* enum: RXDP Test firmware image 5 */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE 0x105 +/* enum: RXDP Test firmware image 6 */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 +/* enum: RXDP Test firmware image 7 */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 +/* enum: RXDP Test firmware image 8 */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 +/* enum: RXDP Test firmware image 9 */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b +/* TxDPCPU firmware id. */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_OFST 6 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_LEN 2 +/* enum: Standard TXDP firmware */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP 0x0 +/* enum: Low latency TXDP firmware */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY 0x1 +/* enum: High packet rate TXDP firmware */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x3 +/* enum: BIST TXDP firmware */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d +/* enum: TXDP Test firmware image 1 */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 +/* enum: TXDP Test firmware image 2 */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_OFST 8 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_LEN 2 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 0 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_WIDTH 12 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_LBN 12 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 +/* enum: reserved value - do not use (may indicate alternative interpretation + * of REV field in future) + */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED 0x0 +/* enum: Trivial RX PD firmware for early Huntington development (Huntington + * development only) + */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 +/* enum: RX PD firmware with approximately Siena-compatible behaviour + * (Huntington development only) + */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 +/* enum: Virtual switching (full feature) RX PD production firmware */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH 0x3 +/* enum: siena_compat variant RX PD firmware using PM rather than MAC + * (Huntington development only) + */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 +/* enum: Low latency RX PD production firmware */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 +/* enum: Packed stream RX PD production firmware */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 +/* enum: RX PD firmware handling layer 2 only for high packet rate performance + * tests (Medford development only) + */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 +/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe +/* enum: RX PD firmware parsing but not filtering network overlay tunnel + * encapsulations (Medford development only) + */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_OFST 10 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_LEN 2 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 0 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_WIDTH 12 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_LBN 12 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 +/* enum: reserved value - do not use (may indicate alternative interpretation + * of REV field in future) + */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED 0x0 +/* enum: Trivial TX PD firmware for early Huntington development (Huntington + * development only) + */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 +/* enum: TX PD firmware with approximately Siena-compatible behaviour + * (Huntington development only) + */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 +/* enum: Virtual switching (full feature) TX PD production firmware */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH 0x3 +/* enum: siena_compat variant TX PD firmware using PM rather than MAC + * (Huntington development only) + */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ +/* enum: TX PD firmware handling layer 2 only for high packet rate performance + * tests (Medford development only) + */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 +/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe +/* Hardware capabilities of NIC */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_OFST 12 +/* Licensed capabilities */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_OFST 16 +/* Second word of flags. Not present on older firmware (check the length). */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_OFST 20 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 0 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_LBN 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_WIDTH 1 +/* Number of FATSOv2 contexts per datapath supported by this NIC. Not present + * on older firmware (check the length). + */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 + /***********************************/ /* MC_CMD_V2_EXTN @@ -9851,6 +10608,26 @@ /***********************************/ +/* MC_CMD_VSWITCH_QUERY + * read some config of v-switch. For now this command is an empty placeholder. + * It may be used to check if a v-switch is connected to a given EVB port (if + * not, then the command returns ENOENT). + */ +#define MC_CMD_VSWITCH_QUERY 0x63 +#undef MC_CMD_0x63_PRIVILEGE_CTG + +#define MC_CMD_0x63_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_VSWITCH_QUERY_IN msgrequest */ +#define MC_CMD_VSWITCH_QUERY_IN_LEN 4 +/* The port to which the v-switch is connected. */ +#define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_OFST 0 + +/* MC_CMD_VSWITCH_QUERY_OUT msgresponse */ +#define MC_CMD_VSWITCH_QUERY_OUT_LEN 0 + + +/***********************************/ /* MC_CMD_VPORT_ALLOC * allocate a v-port. */ @@ -9887,6 +10664,8 @@ #define MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1 +#define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_LBN 1 +#define MC_CMD_VPORT_ALLOC_IN_FLAG_VLAN_RESTRICT_WIDTH 1 /* The number of VLAN tags to insert/remove. An error will be returned if * incompatible with the number of VLAN tags specified for the upstream * v-switch. @@ -9940,6 +10719,8 @@ #define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1 +#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 1 +#define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 /* The number of VLAN tags to strip on receive */ #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12 /* The number of VLAN tags to transparently insert/remove. */ @@ -10021,6 +10802,30 @@ /***********************************/ +/* MC_CMD_VADAPTOR_QUERY + * read some config of v-adaptor. + */ +#define MC_CMD_VADAPTOR_QUERY 0x61 +#undef MC_CMD_0x61_PRIVILEGE_CTG + +#define MC_CMD_0x61_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_VADAPTOR_QUERY_IN msgrequest */ +#define MC_CMD_VADAPTOR_QUERY_IN_LEN 4 +/* The port to which the v-adaptor is connected. */ +#define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_OFST 0 + +/* MC_CMD_VADAPTOR_QUERY_OUT msgresponse */ +#define MC_CMD_VADAPTOR_QUERY_OUT_LEN 12 +/* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */ +#define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_OFST 0 +/* The v-adaptor flags as defined at MC_CMD_VADAPTOR_ALLOC. */ +#define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_OFST 4 +/* The number of VLAN tags that may still be added */ +#define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 8 + + +/***********************************/ /* MC_CMD_EVB_PORT_ASSIGN * assign a port to a PCI function. */ @@ -10268,10 +11073,17 @@ #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8 /* The handle of the RSS context */ #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 -/* Hash control flags. The _EN bits are always supported. The _MODE bits only - * work when the firmware reports ADDITIONAL_RSS_MODES in - * MC_CMD_GET_CAPABILITIES and override the _EN bits if any of them are not 0. - * See the RSS_MODE structure for the meaning of the mode bits. +/* Hash control flags. The _EN bits are always supported, but new modes are + * available when ADDITIONAL_RSS_MODES is reported by MC_CMD_GET_CAPABILITIES: + * in this case, the MODE fields may be set to non-zero values, and will take + * effect regardless of the settings of the _EN flags. See the RSS_MODE + * structure for the meaning of the mode bits. Drivers must check the + * capability before trying to set any _MODE fields, as older firmware will + * reject any attempt to set the FLAGS field to a value > 0xff with EINVAL. In + * the case where all the _MODE flags are zero, the _EN flags take effect, + * providing backward compatibility for existing drivers. (Setting all _MODE + * *and* all _EN flags to zero is valid, to disable RSS spreading for that + * particular packet type.) */ #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0 @@ -10317,11 +11129,18 @@ /* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */ #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8 -/* Hash control flags. If any _MODE bits are non-zero (which will only be true - * when the firmware reports ADDITIONAL_RSS_MODES) then the _EN bits should be - * disregarded (but are guaranteed to be consistent with the _MODE bits if - * RSS_CONTEXT_SET_FLAGS has never been called for this context since it was - * allocated). +/* Hash control flags. If all _MODE bits are zero (which will always be true + * for older firmware which does not report the ADDITIONAL_RSS_MODES + * capability), the _EN bits report the state. If any _MODE bits are non-zero + * (which will only be true when the firmware reports ADDITIONAL_RSS_MODES) + * then the _EN bits should be disregarded, although the _MODE flags are + * guaranteed to be consistent with the _EN flags for a freshly-allocated RSS + * context and in the case where the _EN flags were used in the SET. This + * provides backward compatibility: old drivers will not be attempting to + * derive any meaning from the _MODE bits (and can never set them to any value + * not representable by the _EN bits); new drivers can always determine the + * mode by looking only at the _MODE bits; the value returned by a GET can + * always be used for a SET regardless of old/new driver vs. old/new firmware. */ #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0 @@ -10558,6 +11377,76 @@ /***********************************/ +/* MC_CMD_VPORT_RECONFIGURE + * Replace VLAN tags and/or MAC addresses of an existing v-port. If the v-port + * has already been passed to another function (v-port's user), then that + * function will be reset before applying the changes. + */ +#define MC_CMD_VPORT_RECONFIGURE 0xeb +#undef MC_CMD_0xeb_PRIVILEGE_CTG + +#define MC_CMD_0xeb_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_VPORT_RECONFIGURE_IN msgrequest */ +#define MC_CMD_VPORT_RECONFIGURE_IN_LEN 44 +/* The handle of the v-port */ +#define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_OFST 0 +/* Flags requesting what should be changed. */ +#define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_OFST 4 +#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_LBN 0 +#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_WIDTH 1 +#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_LBN 1 +#define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_WIDTH 1 +/* The number of VLAN tags to insert/remove. An error will be returned if + * incompatible with the number of VLAN tags specified for the upstream + * v-switch. + */ +#define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_OFST 8 +/* The actual VLAN tags to insert/remove */ +#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_OFST 12 +#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_LBN 0 +#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_WIDTH 16 +#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_LBN 16 +#define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_1_WIDTH 16 +/* The number of MAC addresses to add */ +#define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_OFST 16 +/* MAC addresses to add */ +#define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_OFST 20 +#define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_LEN 6 +#define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_NUM 4 + +/* MC_CMD_VPORT_RECONFIGURE_OUT msgresponse */ +#define MC_CMD_VPORT_RECONFIGURE_OUT_LEN 4 +#define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_OFST 0 +#define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 0 +#define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_WIDTH 1 + + +/***********************************/ +/* MC_CMD_EVB_PORT_QUERY + * read some config of v-port. + */ +#define MC_CMD_EVB_PORT_QUERY 0x62 +#undef MC_CMD_0x62_PRIVILEGE_CTG + +#define MC_CMD_0x62_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_EVB_PORT_QUERY_IN msgrequest */ +#define MC_CMD_EVB_PORT_QUERY_IN_LEN 4 +/* The handle of the v-port */ +#define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_OFST 0 + +/* MC_CMD_EVB_PORT_QUERY_OUT msgresponse */ +#define MC_CMD_EVB_PORT_QUERY_OUT_LEN 8 +/* The EVB port flags as defined at MC_CMD_VPORT_ALLOC. */ +#define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_OFST 0 +/* The number of VLAN tags that may be used on a v-adaptor connected to this + * EVB port. + */ +#define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 4 + + +/***********************************/ /* MC_CMD_DUMP_BUFTBL_ENTRIES * Dump buffer table entries, mainly for command client debug use. Dumps * absolute entries, and does not use chunk handles. All entries must be in @@ -10601,6 +11490,14 @@ #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1 +#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_LBN 1 +#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_WIDTH 2 +/* enum: pad to 64 bytes */ +#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64 0x0 +/* enum: pad to 128 bytes (Medford only) */ +#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128 0x1 +/* enum: pad to 256 bytes (Medford only) */ +#define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256 0x2 /* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */ #define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0 @@ -10623,6 +11520,10 @@ #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1 +#define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_LBN 1 +#define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_WIDTH 2 +/* Enum values, see field(s): */ +/* MC_CMD_SET_RXDP_CONFIG/MC_CMD_SET_RXDP_CONFIG_IN/PAD_HOST_LEN */ /***********************************/ @@ -11209,32 +12110,38 @@ #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 -/* enum: Attenuation (0-15, TBD for Medford) */ +/* enum: Attenuation (0-15, Huntington) */ #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0 -/* enum: CTLE Boost (0-15, TBD for Medford) */ +/* enum: CTLE Boost (0-15, Huntington) */ #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1 -/* enum: Edge DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive, TBD - * for Medford) +/* enum: Edge DFE Tap1 (Huntington - 0 - max negative, 64 - zero, 127 - max + * positive, Medford - 0-31) */ #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2 -/* enum: Edge DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive, TBD for - * Medford) +/* enum: Edge DFE Tap2 (Huntington - 0 - max negative, 32 - zero, 63 - max + * positive, Medford - 0-31) */ #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3 -/* enum: Edge DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive, TBD for - * Medford) +/* enum: Edge DFE Tap3 (Huntington - 0 - max negative, 32 - zero, 63 - max + * positive, Medford - 0-16) */ #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4 -/* enum: Edge DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive, TBD for - * Medford) +/* enum: Edge DFE Tap4 (Huntington - 0 - max negative, 32 - zero, 63 - max + * positive, Medford - 0-16) */ #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5 -/* enum: Edge DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive, TBD for - * Medford) +/* enum: Edge DFE Tap5 (Huntington - 0 - max negative, 32 - zero, 63 - max + * positive, Medford - 0-16) */ #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6 -/* enum: Edge DFE DLEV (TBD for Medford) */ +/* enum: Edge DFE DLEV (0-128 for Medford) */ #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_DLEV 0x7 +/* enum: Variable Gain Amplifier (0-15, Medford) */ +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_VGA 0x8 +/* enum: CTLE EQ Capacitor (0-15, Medford) */ +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9 +/* enum: CTLE EQ Resistor (0-7, Medford) */ +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ @@ -11306,26 +12213,32 @@ #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 -/* enum: TX Amplitude */ +/* enum: TX Amplitude (Huntington, Medford) */ #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0 -/* enum: De-Emphasis Tap1 Magnitude (0-7) */ +/* enum: De-Emphasis Tap1 Magnitude (0-7) (Huntington) */ #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1 /* enum: De-Emphasis Tap1 Fine */ #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2 -/* enum: De-Emphasis Tap2 Magnitude (0-6) */ +/* enum: De-Emphasis Tap2 Magnitude (0-6) (Huntington) */ #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3 -/* enum: De-Emphasis Tap2 Fine */ +/* enum: De-Emphasis Tap2 Fine (Huntington) */ #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4 -/* enum: Pre-Emphasis Magnitude */ +/* enum: Pre-Emphasis Magnitude (Huntington) */ #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5 -/* enum: Pre-Emphasis Fine */ +/* enum: Pre-Emphasis Fine (Huntington) */ #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6 -/* enum: TX Slew Rate Coarse control */ +/* enum: TX Slew Rate Coarse control (Huntington) */ #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7 -/* enum: TX Slew Rate Fine control */ +/* enum: TX Slew Rate Fine control (Huntington) */ #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8 -/* enum: TX Termination Impedance control */ +/* enum: TX Termination Impedance control (Huntington) */ #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET 0x9 +/* enum: TX Amplitude Fine control (Medford) */ +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_FINE 0xa +/* enum: Pre-shoot Tap (Medford) */ +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV 0xb +/* enum: De-emphasis Tap (Medford) */ +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY 0xc #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */ @@ -11508,8 +12421,16 @@ #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5 /* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */ #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6 +/* enum: DFE DLev */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_DLEV 0x7 +/* enum: Figure of Merit */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_FOM 0x8 +/* enum: CTLE EQ Capacitor (HF Gain) */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9 +/* enum: CTLE EQ Resistor (DC Gain) */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 -#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 4 +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 5 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ @@ -11518,12 +12439,57 @@ #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */ #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */ #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */ -#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x8 /* enum */ -#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12 -#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 12 +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_8 0x8 /* enum */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_9 0x9 /* enum */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_10 0xa /* enum */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_11 0xb /* enum */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_12 0xc /* enum */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_13 0xd /* enum */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_14 0xe /* enum */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_15 0xf /* enum */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x10 /* enum */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 13 +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 14 +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 10 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 +/* MC_CMD_PCIE_TUNE_RXEQ_SET_IN msgrequest */ +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMIN 8 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMAX 252 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) +/* Requested operation */ +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_OFST 0 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_LEN 1 +/* Align the arguments to 32 bits */ +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_OFST 1 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_LEN 3 +/* RXEQ Parameter */ +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_OFST 4 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LEN 4 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 +/* Enum values, see field(s): */ +/* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_ID */ +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 5 +/* Enum values, see field(s): */ +/* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 13 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_LBN 14 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 2 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 + +/* MC_CMD_PCIE_TUNE_RXEQ_SET_OUT msgresponse */ +#define MC_CMD_PCIE_TUNE_RXEQ_SET_OUT_LEN 0 + /* MC_CMD_PCIE_TUNE_TXEQ_GET_IN msgrequest */ #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4 /* Requested operation */ @@ -11598,6 +12564,7 @@ /***********************************/ /* MC_CMD_LICENSING * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition + * - not used for V3 licensing */ #define MC_CMD_LICENSING 0xf3 #undef MC_CMD_0xf3_PRIVILEGE_CTG @@ -11643,6 +12610,95 @@ /***********************************/ +/* MC_CMD_LICENSING_V3 + * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition + * - V3 licensing (Medford) + */ +#define MC_CMD_LICENSING_V3 0xd0 +#undef MC_CMD_0xd0_PRIVILEGE_CTG + +#define MC_CMD_0xd0_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_LICENSING_V3_IN msgrequest */ +#define MC_CMD_LICENSING_V3_IN_LEN 4 +/* identifies the type of operation requested */ +#define MC_CMD_LICENSING_V3_IN_OP_OFST 0 +/* enum: re-read and apply licenses after a license key partition update; note + * that this operation returns a zero-length response + */ +#define MC_CMD_LICENSING_V3_IN_OP_UPDATE_LICENSE 0x0 +/* enum: report counts of installed licenses */ +#define MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE 0x1 + +/* MC_CMD_LICENSING_V3_OUT msgresponse */ +#define MC_CMD_LICENSING_V3_OUT_LEN 88 +/* count of keys which are valid */ +#define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_OFST 0 +/* sum of UNVERIFIABLE_KEYS + WRONG_NODE_KEYS (for compatibility with + * MC_CMD_FC_OP_LICENSE) + */ +#define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_OFST 4 +/* count of keys which are invalid due to being unverifiable */ +#define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_OFST 8 +/* count of keys which are invalid due to being for the wrong node */ +#define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_OFST 12 +/* licensing state (for diagnostics; the exact meaning of the bits in this + * field are private to the firmware) + */ +#define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_OFST 16 +/* licensing subsystem self-test report (for manftest) */ +#define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_OFST 20 +/* enum: licensing subsystem self-test failed */ +#define MC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL 0x0 +/* enum: licensing subsystem self-test passed */ +#define MC_CMD_LICENSING_V3_OUT_SELF_TEST_PASS 0x1 +/* bitmask of licensed applications */ +#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_OFST 24 +#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LEN 8 +#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_OFST 24 +#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_OFST 28 +/* reserved for future use */ +#define MC_CMD_LICENSING_V3_OUT_RESERVED_0_OFST 32 +#define MC_CMD_LICENSING_V3_OUT_RESERVED_0_LEN 24 +/* bitmask of licensed features */ +#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_OFST 56 +#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LEN 8 +#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_OFST 56 +#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_OFST 60 +/* reserved for future use */ +#define MC_CMD_LICENSING_V3_OUT_RESERVED_1_OFST 64 +#define MC_CMD_LICENSING_V3_OUT_RESERVED_1_LEN 24 + + +/***********************************/ +/* MC_CMD_LICENSING_GET_ID_V3 + * Get ID and type from the NVRAM_PARTITION_TYPE_LICENSE application license + * partition - V3 licensing (Medford) + */ +#define MC_CMD_LICENSING_GET_ID_V3 0xd1 +#undef MC_CMD_0xd1_PRIVILEGE_CTG + +#define MC_CMD_0xd1_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_LICENSING_GET_ID_V3_IN msgrequest */ +#define MC_CMD_LICENSING_GET_ID_V3_IN_LEN 0 + +/* MC_CMD_LICENSING_GET_ID_V3_OUT msgresponse */ +#define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMIN 8 +#define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX 252 +#define MC_CMD_LICENSING_GET_ID_V3_OUT_LEN(num) (8+1*(num)) +/* type of license (eg 3) */ +#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_OFST 0 +/* length of the license ID (in bytes) */ +#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_OFST 4 +/* the unique license ID of the adapter */ +#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_OFST 8 +#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LEN 1 +#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MINNUM 0 +#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM 244 + + +/***********************************/ /* MC_CMD_MC2MC_PROXY * Execute an arbitrary MCDI command on the slave MC of a dual-core device. * This will fail on a single-core system. @@ -11663,7 +12719,7 @@ /* MC_CMD_GET_LICENSED_APP_STATE * Query the state of an individual licensed application. (Note that the actual * state may be invalidated by the MC_CMD_LICENSING OP_UPDATE_LICENSE operation - * or a reboot of the MC.) + * or a reboot of the MC.) Not used for V3 licensing */ #define MC_CMD_GET_LICENSED_APP_STATE 0xf5 #undef MC_CMD_0xf5_PRIVILEGE_CTG @@ -11686,8 +12742,70 @@ /***********************************/ +/* MC_CMD_GET_LICENSED_V3_APP_STATE + * Query the state of an individual licensed application. (Note that the actual + * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE + * operation or a reboot of the MC.) Used for V3 licensing (Medford) + */ +#define MC_CMD_GET_LICENSED_V3_APP_STATE 0xd2 +#undef MC_CMD_0xd2_PRIVILEGE_CTG + +#define MC_CMD_0xd2_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_GET_LICENSED_V3_APP_STATE_IN msgrequest */ +#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_LEN 8 +/* application ID to query (LICENSED_V3_APPS_xxx) expressed as a single bit + * mask + */ +#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 0 +#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LEN 8 +#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 0 +#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 4 + +/* MC_CMD_GET_LICENSED_V3_APP_STATE_OUT msgresponse */ +#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4 +/* state of this application */ +#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_OFST 0 +/* enum: no (or invalid) license is present for the application */ +#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_NOT_LICENSED 0x0 +/* enum: a valid license is present for the application */ +#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LICENSED 0x1 + + +/***********************************/ +/* MC_CMD_GET_LICENSED_V3_FEATURE_STATES + * Query the state of an one or more licensed features. (Note that the actual + * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE + * operation or a reboot of the MC.) Used for V3 licensing (Medford) + */ +#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3 +#undef MC_CMD_0xd3_PRIVILEGE_CTG + +#define MC_CMD_0xd3_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN msgrequest */ +#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_LEN 8 +/* features to query (LICENSED_V3_FEATURES_xxx) expressed as a mask with one or + * more bits set + */ +#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 0 +#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LEN 8 +#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 0 +#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 4 + +/* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT msgresponse */ +#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_LEN 8 +/* states of these features - bit set for licensed, clear for not licensed */ +#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 0 +#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LEN 8 +#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0 +#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4 + + +/***********************************/ /* MC_CMD_LICENSED_APP_OP - * Perform an action for an individual licensed application. + * Perform an action for an individual licensed application - not used for V3 + * licensing. */ #define MC_CMD_LICENSED_APP_OP 0xf6 #undef MC_CMD_0xf6_PRIVILEGE_CTG @@ -11754,6 +12872,69 @@ /***********************************/ +/* MC_CMD_LICENSED_V3_VALIDATE_APP + * Perform validation for an individual licensed application - V3 licensing + * (Medford) + */ +#define MC_CMD_LICENSED_V3_VALIDATE_APP 0xd4 +#undef MC_CMD_0xd4_PRIVILEGE_CTG + +#define MC_CMD_0xd4_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_LICENSED_V3_VALIDATE_APP_IN msgrequest */ +#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_LEN 72 +/* application ID expressed as a single bit mask */ +#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_OFST 0 +#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LEN 8 +#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_OFST 0 +#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_OFST 4 +/* challenge for validation */ +#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_OFST 8 +#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_LEN 64 + +/* MC_CMD_LICENSED_V3_VALIDATE_APP_OUT msgresponse */ +#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_LEN 72 +/* application expiry time */ +#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_OFST 0 +/* application expiry units */ +#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_OFST 4 +/* enum: expiry units are accounting units */ +#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_ACC 0x0 +/* enum: expiry units are calendar days */ +#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_DAYS 0x1 +/* validation response to challenge */ +#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_OFST 8 +#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_LEN 64 + + +/***********************************/ +/* MC_CMD_LICENSED_V3_MASK_FEATURES + * Mask features - V3 licensing (Medford) + */ +#define MC_CMD_LICENSED_V3_MASK_FEATURES 0xd5 +#undef MC_CMD_0xd5_PRIVILEGE_CTG + +#define MC_CMD_0xd5_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_LICENSED_V3_MASK_FEATURES_IN msgrequest */ +#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_LEN 12 +/* mask to be applied to features to be changed */ +#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 0 +#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LEN 8 +#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 0 +#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4 +/* whether to turn on or turn off the masked features */ +#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_OFST 8 +/* enum: turn the features off */ +#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_OFF 0x0 +/* enum: turn the features back on */ +#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_ON 0x1 + +/* MC_CMD_LICENSED_V3_MASK_FEATURES_OUT msgresponse */ +#define MC_CMD_LICENSED_V3_MASK_FEATURES_OUT_LEN 0 + + +/***********************************/ /* MC_CMD_SET_PORT_SNIFF_CONFIG * Configure RX port sniffing for the physical port associated with the calling * function. Only a privileged function may change the port sniffing @@ -12133,12 +13314,27 @@ #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */ #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */ #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */ -#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20 /* enum */ +/* enum: Deprecated. Equivalent to MAC_SPOOFING_TX combined with CHANGE_MAC. */ +#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */ #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */ #define MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */ #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */ #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */ +/* enum: Allows to set the TX packets' source MAC address to any arbitrary MAC + * adress. + */ +#define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING_TX 0x800 +/* enum: Privilege that allows a Function to change the MAC address configured + * in its associated vAdapter/vPort. + */ +#define MC_CMD_PRIVILEGE_MASK_IN_GRP_CHANGE_MAC 0x1000 +/* enum: Privilege that allows a Function to install filters that specify VLANs + * that are not in the permit list for the associated vPort. This privilege is + * primarily to support ESX where vPorts are created that restrict traffic to + * only a set of permitted VLANs. See the vPort flag FLAG_VLAN_RESTRICT. + */ +#define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNRESTRICTED_VLAN 0x2000 /* enum: Set this bit to indicate that a new privilege mask is to be set, * otherwise the command will only read the existing mask. */ @@ -12396,7 +13592,7 @@ /* Sector type */ #define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_OFST 4 /* Enum values, see field(s): */ -/* MC_CMD_XPM_READ_SECTOR_OUT/TYPE */ +/* MC_CMD_XPM_READ_SECTOR/MC_CMD_XPM_READ_SECTOR_OUT/TYPE */ /* Sector size */ #define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_OFST 8 /* Sector data */ @@ -12516,4 +13712,54 @@ /* MC_CMD_XPM_WRITE_TEST_OUT msgresponse */ #define MC_CMD_XPM_WRITE_TEST_OUT_LEN 0 + +/***********************************/ +/* MC_CMD_EXEC_SIGNED + * Check the CMAC of the contents of IMEM and DMEM against the value supplied + * and if correct begin execution from the start of IMEM. The caller supplies a + * key ID, the length of IMEM and DMEM to validate and the expected CMAC. CMAC + * computation runs from the start of IMEM, and from the start of DMEM + 16k, + * to match flash booting. The command will respond with EINVAL if the CMAC + * does match, otherwise it will respond with success before it jumps to IMEM. + */ +#define MC_CMD_EXEC_SIGNED 0x10c +#undef MC_CMD_0x10c_PRIVILEGE_CTG + +#define MC_CMD_0x10c_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_EXEC_SIGNED_IN msgrequest */ +#define MC_CMD_EXEC_SIGNED_IN_LEN 28 +/* the length of code to include in the CMAC */ +#define MC_CMD_EXEC_SIGNED_IN_CODELEN_OFST 0 +/* the length of date to include in the CMAC */ +#define MC_CMD_EXEC_SIGNED_IN_DATALEN_OFST 4 +/* the XPM sector containing the key to use */ +#define MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_OFST 8 +/* the expected CMAC value */ +#define MC_CMD_EXEC_SIGNED_IN_CMAC_OFST 12 +#define MC_CMD_EXEC_SIGNED_IN_CMAC_LEN 16 + +/* MC_CMD_EXEC_SIGNED_OUT msgresponse */ +#define MC_CMD_EXEC_SIGNED_OUT_LEN 0 + + +/***********************************/ +/* MC_CMD_PREPARE_SIGNED + * Prepare to upload a signed image. This will scrub the specified length of + * the data region, which must be at least as large as the DATALEN supplied to + * MC_CMD_EXEC_SIGNED. + */ +#define MC_CMD_PREPARE_SIGNED 0x10d +#undef MC_CMD_0x10d_PRIVILEGE_CTG + +#define MC_CMD_0x10d_PRIVILEGE_CTG SRIOV_CTG_ADMIN + +/* MC_CMD_PREPARE_SIGNED_IN msgrequest */ +#define MC_CMD_PREPARE_SIGNED_IN_LEN 4 +/* the length of data area to clear */ +#define MC_CMD_PREPARE_SIGNED_IN_DATALEN_OFST 0 + +/* MC_CMD_PREPARE_SIGNED_OUT msgresponse */ +#define MC_CMD_PREPARE_SIGNED_OUT_LEN 0 + #endif /* _SIENA_MC_DRIVER_PCOL_H */ diff --git a/sys/dev/sfxge/common/efx_rx.c b/sys/dev/sfxge/common/efx_rx.c index 3501d6e..a0b143f 100644 --- a/sys/dev/sfxge/common/efx_rx.c +++ b/sys/dev/sfxge/common/efx_rx.c @@ -31,16 +31,13 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" -#include "efx_types.h" -#include "efx_regs.h" #include "efx_impl.h" #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_rx_init( __in efx_nic_t *enp); @@ -48,41 +45,45 @@ static void falconsiena_rx_fini( __in efx_nic_t *enp); -#if EFSYS_OPT_RX_HDR_SPLIT -static __checkReturn int -falconsiena_rx_hdr_split_enable( - __in efx_nic_t *enp, - __in unsigned int hdr_buf_size, - __in unsigned int pld_buf_size); -#endif /* EFSYS_OPT_RX_HDR_SPLIT */ - #if EFSYS_OPT_RX_SCATTER -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_rx_scatter_enable( __in efx_nic_t *enp, __in unsigned int buf_size); #endif /* EFSYS_OPT_RX_SCATTER */ #if EFSYS_OPT_RX_SCALE -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_rx_scale_mode_set( __in efx_nic_t *enp, __in efx_rx_hash_alg_t alg, __in efx_rx_hash_type_t type, __in boolean_t insert); -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_rx_scale_key_set( __in efx_nic_t *enp, __in_ecount(n) uint8_t *key, __in size_t n); -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_rx_scale_tbl_set( __in efx_nic_t *enp, __in_ecount(n) unsigned int *table, __in size_t n); +static __checkReturn uint32_t +falconsiena_rx_prefix_hash( + __in efx_nic_t *enp, + __in efx_rx_hash_alg_t func, + __in uint8_t *buffer); + +static __checkReturn efx_rc_t +falconsiena_rx_prefix_pktlen( + __in efx_nic_t *enp, + __in uint8_t *buffer, + __out uint16_t *lengthp); + #endif /* EFSYS_OPT_RX_SCALE */ static void @@ -100,7 +101,7 @@ falconsiena_rx_qpush( __in unsigned int added, __inout unsigned int *pushedp); -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_rx_qflush( __in efx_rxq_t *erp); @@ -108,7 +109,7 @@ static void falconsiena_rx_qenable( __in efx_rxq_t *erp); -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_rx_qcreate( __in efx_nic_t *enp, __in unsigned int index, @@ -131,9 +132,6 @@ falconsiena_rx_qdestroy( static efx_rx_ops_t __efx_rx_falcon_ops = { falconsiena_rx_init, /* erxo_init */ falconsiena_rx_fini, /* erxo_fini */ -#if EFSYS_OPT_RX_HDR_SPLIT - falconsiena_rx_hdr_split_enable, /* erxo_hdr_split_enable */ -#endif #if EFSYS_OPT_RX_SCATTER falconsiena_rx_scatter_enable, /* erxo_scatter_enable */ #endif @@ -141,7 +139,9 @@ static efx_rx_ops_t __efx_rx_falcon_ops = { falconsiena_rx_scale_mode_set, /* erxo_scale_mode_set */ falconsiena_rx_scale_key_set, /* erxo_scale_key_set */ falconsiena_rx_scale_tbl_set, /* erxo_scale_tbl_set */ + falconsiena_rx_prefix_hash, /* erxo_prefix_hash */ #endif + falconsiena_rx_prefix_pktlen, /* erxo_prefix_pktlen */ falconsiena_rx_qpost, /* erxo_qpost */ falconsiena_rx_qpush, /* erxo_qpush */ falconsiena_rx_qflush, /* erxo_qflush */ @@ -155,9 +155,6 @@ static efx_rx_ops_t __efx_rx_falcon_ops = { static efx_rx_ops_t __efx_rx_siena_ops = { falconsiena_rx_init, /* erxo_init */ falconsiena_rx_fini, /* erxo_fini */ -#if EFSYS_OPT_RX_HDR_SPLIT - falconsiena_rx_hdr_split_enable, /* erxo_hdr_split_enable */ -#endif #if EFSYS_OPT_RX_SCATTER falconsiena_rx_scatter_enable, /* erxo_scatter_enable */ #endif @@ -165,7 +162,9 @@ static efx_rx_ops_t __efx_rx_siena_ops = { falconsiena_rx_scale_mode_set, /* erxo_scale_mode_set */ falconsiena_rx_scale_key_set, /* erxo_scale_key_set */ falconsiena_rx_scale_tbl_set, /* erxo_scale_tbl_set */ + falconsiena_rx_prefix_hash, /* erxo_prefix_hash */ #endif + falconsiena_rx_prefix_pktlen, /* erxo_prefix_pktlen */ falconsiena_rx_qpost, /* erxo_qpost */ falconsiena_rx_qpush, /* erxo_qpush */ falconsiena_rx_qflush, /* erxo_qflush */ @@ -175,37 +174,36 @@ static efx_rx_ops_t __efx_rx_siena_ops = { }; #endif /* EFSYS_OPT_SIENA */ -#if EFSYS_OPT_HUNTINGTON -static efx_rx_ops_t __efx_rx_hunt_ops = { - hunt_rx_init, /* erxo_init */ - hunt_rx_fini, /* erxo_fini */ -#if EFSYS_OPT_RX_HDR_SPLIT - hunt_rx_hdr_split_enable, /* erxo_hdr_split_enable */ -#endif +#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD +static efx_rx_ops_t __efx_rx_ef10_ops = { + ef10_rx_init, /* erxo_init */ + ef10_rx_fini, /* erxo_fini */ #if EFSYS_OPT_RX_SCATTER - hunt_rx_scatter_enable, /* erxo_scatter_enable */ + ef10_rx_scatter_enable, /* erxo_scatter_enable */ #endif #if EFSYS_OPT_RX_SCALE - hunt_rx_scale_mode_set, /* erxo_scale_mode_set */ - hunt_rx_scale_key_set, /* erxo_scale_key_set */ - hunt_rx_scale_tbl_set, /* erxo_scale_tbl_set */ + ef10_rx_scale_mode_set, /* erxo_scale_mode_set */ + ef10_rx_scale_key_set, /* erxo_scale_key_set */ + ef10_rx_scale_tbl_set, /* erxo_scale_tbl_set */ + ef10_rx_prefix_hash, /* erxo_prefix_hash */ #endif - hunt_rx_qpost, /* erxo_qpost */ - hunt_rx_qpush, /* erxo_qpush */ - hunt_rx_qflush, /* erxo_qflush */ - hunt_rx_qenable, /* erxo_qenable */ - hunt_rx_qcreate, /* erxo_qcreate */ - hunt_rx_qdestroy, /* erxo_qdestroy */ + ef10_rx_prefix_pktlen, /* erxo_prefix_pktlen */ + ef10_rx_qpost, /* erxo_qpost */ + ef10_rx_qpush, /* erxo_qpush */ + ef10_rx_qflush, /* erxo_qflush */ + ef10_rx_qenable, /* erxo_qenable */ + ef10_rx_qcreate, /* erxo_qcreate */ + ef10_rx_qdestroy, /* erxo_qdestroy */ }; -#endif /* EFSYS_OPT_HUNTINGTON */ +#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ - __checkReturn int + __checkReturn efx_rc_t efx_rx_init( __inout efx_nic_t *enp) { efx_rx_ops_t *erxop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); @@ -235,10 +233,16 @@ efx_rx_init( #if EFSYS_OPT_HUNTINGTON case EFX_FAMILY_HUNTINGTON: - erxop = (efx_rx_ops_t *)&__efx_rx_hunt_ops; + erxop = (efx_rx_ops_t *)&__efx_rx_ef10_ops; break; #endif /* EFSYS_OPT_HUNTINGTON */ +#if EFSYS_OPT_MEDFORD + case EFX_FAMILY_MEDFORD: + erxop = (efx_rx_ops_t *)&__efx_rx_ef10_ops; + break; +#endif /* EFSYS_OPT_MEDFORD */ + default: EFSYS_ASSERT(0); rc = ENOTSUP; @@ -259,7 +263,7 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); enp->en_erxop = NULL; enp->en_mod_flags &= ~EFX_MOD_RX; @@ -283,40 +287,14 @@ efx_rx_fini( enp->en_mod_flags &= ~EFX_MOD_RX; } -#if EFSYS_OPT_RX_HDR_SPLIT - __checkReturn int -efx_rx_hdr_split_enable( - __in efx_nic_t *enp, - __in unsigned int hdr_buf_size, - __in unsigned int pld_buf_size) -{ - efx_rx_ops_t *erxop = enp->en_erxop; - int rc; - - EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); - EFSYS_ASSERT3U(enp->en_family, >=, EFX_FAMILY_SIENA); - - if ((rc = erxop->erxo_hdr_split_enable(enp, hdr_buf_size, - pld_buf_size)) != 0) - goto fail1; - - return (0); - -fail1: - EFSYS_PROBE1(fail1, int, rc); - return (rc); -} -#endif /* EFSYS_OPT_RX_HDR_SPLIT */ - #if EFSYS_OPT_RX_SCATTER - __checkReturn int + __checkReturn efx_rc_t efx_rx_scatter_enable( __in efx_nic_t *enp, __in unsigned int buf_size) { efx_rx_ops_t *erxop = enp->en_erxop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); @@ -327,18 +305,18 @@ efx_rx_scatter_enable( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } #endif /* EFSYS_OPT_RX_SCATTER */ #if EFSYS_OPT_RX_SCALE - __checkReturn int + __checkReturn efx_rc_t efx_rx_hash_support_get( __in efx_nic_t *enp, __out efx_rx_hash_support_t *supportp) { - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); @@ -354,17 +332,17 @@ efx_rx_hash_support_get( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_rx_scale_support_get( __in efx_nic_t *enp, __out efx_rx_scale_support_t *supportp) { - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); @@ -380,12 +358,12 @@ efx_rx_scale_support_get( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_rx_scale_mode_set( __in efx_nic_t *enp, __in efx_rx_hash_alg_t alg, @@ -393,7 +371,7 @@ efx_rx_scale_mode_set( __in boolean_t insert) { efx_rx_ops_t *erxop = enp->en_erxop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); @@ -407,20 +385,20 @@ efx_rx_scale_mode_set( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } #endif /* EFSYS_OPT_RX_SCALE */ #if EFSYS_OPT_RX_SCALE - __checkReturn int + __checkReturn efx_rc_t efx_rx_scale_key_set( __in efx_nic_t *enp, __in_ecount(n) uint8_t *key, __in size_t n) { efx_rx_ops_t *erxop = enp->en_erxop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); @@ -431,21 +409,21 @@ efx_rx_scale_key_set( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } #endif /* EFSYS_OPT_RX_SCALE */ #if EFSYS_OPT_RX_SCALE - __checkReturn int + __checkReturn efx_rc_t efx_rx_scale_tbl_set( __in efx_nic_t *enp, __in_ecount(n) unsigned int *table, __in size_t n) { efx_rx_ops_t *erxop = enp->en_erxop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); @@ -456,7 +434,7 @@ efx_rx_scale_tbl_set( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -493,13 +471,13 @@ efx_rx_qpush( erxop->erxo_qpush(erp, added, pushedp); } - __checkReturn int + __checkReturn efx_rc_t efx_rx_qflush( __in efx_rxq_t *erp) { efx_nic_t *enp = erp->er_enp; efx_rx_ops_t *erxop = enp->en_erxop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC); @@ -509,7 +487,7 @@ efx_rx_qflush( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -526,7 +504,7 @@ efx_rx_qenable( erxop->erxo_qenable(erp); } - __checkReturn int + __checkReturn efx_rc_t efx_rx_qcreate( __in efx_nic_t *enp, __in unsigned int index, @@ -540,7 +518,7 @@ efx_rx_qcreate( { efx_rx_ops_t *erxop = enp->en_erxop; efx_rxq_t *erp; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX); @@ -573,7 +551,7 @@ fail2: EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -590,95 +568,34 @@ efx_rx_qdestroy( erxop->erxo_qdestroy(erp); } -/* - * Psuedo-header info for Siena/Falcon. - * - * The psuedo-header is a byte array of one of the forms: - * - * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - * XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.TT.TT.TT.TT - * XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.LL.LL - * - * where: - * - * TT.TT.TT.TT is a 32-bit Toeplitz hash - * LL.LL is a 16-bit LFSR hash - * - * Hash values are in network (big-endian) byte order. - * - * - * On Huntington the pseudo-header is laid out as: - * (See also SF-109306-TC section 9) - * - * Toeplitz hash (32 bits, little-endian) - * Out-of-band outer VLAN tag - * (16 bits, big-endian, 0 if the packet did not have an outer VLAN tag) - * Out-of-band inner VLAN tag - * (16 bits, big-endian, 0 if the packet did not have an inner VLAN tag) - * Packet length (16 bits, little-endian, may be 0) - * MAC timestamp (32 bits, little-endian, may be 0) - * VLAN tag - * (16 bits, big-endian, 0 if the packet did not have an outer VLAN tag) - * VLAN tag - * (16 bits, big-endian, 0 if the packet did not have an inner VLAN tag) - */ - - __checkReturn int + __checkReturn efx_rc_t efx_psuedo_hdr_pkt_length_get( __in efx_nic_t *enp, __in uint8_t *buffer, - __out uint16_t *pkt_lengthp) + __out uint16_t *lengthp) { - if (enp->en_family != EFX_FAMILY_HUNTINGTON) { - EFSYS_ASSERT(0); - return (ENOTSUP); - } - - *pkt_lengthp = buffer[8] | (buffer[9] << 8); + efx_rx_ops_t *erxop = enp->en_erxop; - return (0); + return (erxop->erxo_prefix_pktlen(enp, buffer, lengthp)); } #if EFSYS_OPT_RX_SCALE - -uint32_t + __checkReturn uint32_t efx_psuedo_hdr_hash_get( __in efx_nic_t *enp, __in efx_rx_hash_alg_t func, __in uint8_t *buffer) { - if (func == EFX_RX_HASHALG_TOEPLITZ) { - switch (enp->en_family) { - case EFX_FAMILY_FALCON: - case EFX_FAMILY_SIENA: - return ((buffer[12] << 24) | - (buffer[13] << 16) | - (buffer[14] << 8) | - buffer[15]); - case EFX_FAMILY_HUNTINGTON: - return (buffer[0] | - (buffer[1] << 8) | - (buffer[2] << 16) | - (buffer[3] << 24)); - default: - EFSYS_ASSERT(0); - return (0); - } - } else if (func == EFX_RX_HASHALG_LFSR) { - EFSYS_ASSERT(enp->en_family == EFX_FAMILY_FALCON || - enp->en_family == EFX_FAMILY_SIENA); - return ((buffer[14] << 8) | buffer[15]); - } else { - EFSYS_ASSERT(0); - return (0); - } -} + efx_rx_ops_t *erxop = enp->en_erxop; + EFSYS_ASSERT3U(enp->en_hash_support, ==, EFX_RX_HASH_AVAILABLE); + return (erxop->erxo_prefix_hash(enp, func, buffer)); +} #endif /* EFSYS_OPT_RX_SCALE */ #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_rx_init( __in efx_nic_t *enp) { @@ -714,69 +631,15 @@ falconsiena_rx_init( return (0); } -#if EFSYS_OPT_RX_HDR_SPLIT -static __checkReturn int -falconsiena_rx_hdr_split_enable( - __in efx_nic_t *enp, - __in unsigned int hdr_buf_size, - __in unsigned int pld_buf_size) -{ - unsigned int nhdr32; - unsigned int npld32; - efx_oword_t oword; - int rc; - - nhdr32 = hdr_buf_size / 32; - if ((nhdr32 == 0) || - (nhdr32 >= (1 << FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_WIDTH)) || - ((hdr_buf_size % 32) != 0)) { - rc = EINVAL; - goto fail1; - } - - npld32 = pld_buf_size / 32; - if ((npld32 == 0) || - (npld32 >= (1 << FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_WIDTH)) || - ((pld_buf_size % 32) != 0)) { - rc = EINVAL; - goto fail2; - } - - if (enp->en_rx_qcount > 0) { - rc = EBUSY; - goto fail3; - } - - EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword); - - EFX_SET_OWORD_FIELD(oword, FRF_CZ_RX_HDR_SPLIT_EN, 1); - EFX_SET_OWORD_FIELD(oword, FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE, nhdr32); - EFX_SET_OWORD_FIELD(oword, FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE, npld32); - - EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword); - - return (0); - -fail3: - EFSYS_PROBE(fail3); -fail2: - EFSYS_PROBE(fail2); -fail1: - EFSYS_PROBE1(fail1, int, rc); - - return (rc); -} -#endif /* EFSYS_OPT_RX_HDR_SPLIT */ - #if EFSYS_OPT_RX_SCATTER -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_rx_scatter_enable( __in efx_nic_t *enp, __in unsigned int buf_size) { unsigned int nbuf32; efx_oword_t oword; - int rc; + efx_rc_t rc; nbuf32 = buf_size / 32; if ((nbuf32 == 0) || @@ -806,7 +669,7 @@ falconsiena_rx_scatter_enable( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -880,14 +743,14 @@ fail1: #if EFSYS_OPT_RX_SCALE -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_rx_scale_mode_set( __in efx_nic_t *enp, __in efx_rx_hash_alg_t alg, __in efx_rx_hash_type_t type, __in boolean_t insert) { - int rc; + efx_rc_t rc; switch (alg) { case EFX_RX_HASHALG_LFSR: @@ -918,7 +781,7 @@ falconsiena_rx_scale_mode_set( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); EFX_RX_LFSR_HASH(enp, B_FALSE); @@ -927,7 +790,7 @@ fail1: #endif #if EFSYS_OPT_RX_SCALE -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_rx_scale_key_set( __in efx_nic_t *enp, __in_ecount(n) uint8_t *key, @@ -936,7 +799,7 @@ falconsiena_rx_scale_key_set( efx_oword_t oword; unsigned int byte; unsigned int offset; - int rc; + efx_rc_t rc; byte = 0; @@ -1047,14 +910,14 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } #endif #if EFSYS_OPT_RX_SCALE -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_rx_scale_tbl_set( __in efx_nic_t *enp, __in_ecount(n) unsigned int *table, @@ -1062,7 +925,7 @@ falconsiena_rx_scale_tbl_set( { efx_oword_t oword; int index; - int rc; + efx_rc_t rc; EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE == FR_BZ_RX_INDIRECTION_TBL_ROWS); EFX_STATIC_ASSERT(EFX_MAXRSS == (1 << FRF_BZ_IT_QUEUE_WIDTH)); @@ -1109,12 +972,64 @@ falconsiena_rx_scale_tbl_set( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } #endif +/* + * Falcon/Siena psuedo-header + * -------------------------- + * + * Receive packets are prefixed by an optional 16 byte pseudo-header. + * The psuedo-header is a byte array of one of the forms: + * + * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.TT.TT.TT.TT + * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.LL.LL + * + * where: + * TT.TT.TT.TT Toeplitz hash (32-bit big-endian) + * LL.LL LFSR hash (16-bit big-endian) + */ + +#if EFSYS_OPT_RX_SCALE +static __checkReturn uint32_t +falconsiena_rx_prefix_hash( + __in efx_nic_t *enp, + __in efx_rx_hash_alg_t func, + __in uint8_t *buffer) +{ + switch (func) { + case EFX_RX_HASHALG_TOEPLITZ: + return ((buffer[12] << 24) | + (buffer[13] << 16) | + (buffer[14] << 8) | + buffer[15]); + + case EFX_RX_HASHALG_LFSR: + return ((buffer[14] << 8) | buffer[15]); + + default: + EFSYS_ASSERT(0); + return (0); + } +} +#endif /* EFSYS_OPT_RX_SCALE */ + +static __checkReturn efx_rc_t +falconsiena_rx_prefix_pktlen( + __in efx_nic_t *enp, + __in uint8_t *buffer, + __out uint16_t *lengthp) +{ + /* Not supported by Falcon/Siena hardware */ + EFSYS_ASSERT(0); + return (ENOTSUP); +} + + static void falconsiena_rx_qpost( __in efx_rxq_t *erp, @@ -1185,7 +1100,7 @@ falconsiena_rx_qpush( erp->er_index, &dword, B_FALSE); } -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_rx_qflush( __in efx_rxq_t *erp) { @@ -1223,7 +1138,7 @@ falconsiena_rx_qenable( erp->er_index, &oword, B_TRUE); } -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_rx_qcreate( __in efx_nic_t *enp, __in unsigned int index, @@ -1238,9 +1153,8 @@ falconsiena_rx_qcreate( efx_nic_cfg_t *encp = &(enp->en_nic_cfg); efx_oword_t oword; uint32_t size; - boolean_t split; boolean_t jumbo; - int rc; + efx_rc_t rc; EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS == (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH)); @@ -1269,37 +1183,15 @@ falconsiena_rx_qcreate( switch (type) { case EFX_RXQ_TYPE_DEFAULT: - split = B_FALSE; jumbo = B_FALSE; break; -#if EFSYS_OPT_RX_HDR_SPLIT - case EFX_RXQ_TYPE_SPLIT_HEADER: - if ((enp->en_family < EFX_FAMILY_SIENA) || ((index & 1) != 0)) { - rc = EINVAL; - goto fail4; - } - split = B_TRUE; - jumbo = B_TRUE; - break; - - case EFX_RXQ_TYPE_SPLIT_PAYLOAD: - if ((enp->en_family < EFX_FAMILY_SIENA) || ((index & 1) == 0)) { - rc = EINVAL; - goto fail4; - } - split = B_FALSE; - jumbo = B_TRUE; - break; -#endif /* EFSYS_OPT_RX_HDR_SPLIT */ - #if EFSYS_OPT_RX_SCATTER case EFX_RXQ_TYPE_SCATTER: if (enp->en_family < EFX_FAMILY_SIENA) { rc = EINVAL; goto fail4; } - split = B_FALSE; jumbo = B_TRUE; break; #endif /* EFSYS_OPT_RX_SCATTER */ @@ -1310,10 +1202,7 @@ falconsiena_rx_qcreate( } /* Set up the new descriptor queue */ - EFX_POPULATE_OWORD_10(oword, - FRF_CZ_RX_HDR_SPLIT, split, - FRF_AZ_RX_ISCSI_DDIG_EN, 0, - FRF_AZ_RX_ISCSI_HDIG_EN, 0, + EFX_POPULATE_OWORD_7(oword, FRF_AZ_RX_DESCQ_BUF_BASE_ID, id, FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index, FRF_AZ_RX_DESCQ_OWNER_ID, 0, @@ -1334,7 +1223,7 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } diff --git a/sys/dev/sfxge/common/efx_sram.c b/sys/dev/sfxge/common/efx_sram.c index 4bd951b..f2a7b78 100644 --- a/sys/dev/sfxge/common/efx_sram.c +++ b/sys/dev/sfxge/common/efx_sram.c @@ -31,13 +31,10 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" -#include "efx_types.h" -#include "efx_regs.h" #include "efx_impl.h" - __checkReturn int + __checkReturn efx_rc_t efx_sram_buf_tbl_set( __in efx_nic_t *enp, __in uint32_t id, @@ -50,25 +47,26 @@ efx_sram_buf_tbl_set( efsys_dma_addr_t addr; efx_oword_t oword; unsigned int count; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); -#if EFSYS_OPT_HUNTINGTON - if (enp->en_family == EFX_FAMILY_HUNTINGTON) { +#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD + if (enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD) { /* * FIXME: the efx_sram_buf_tbl_*() functionality needs to be * pulled inside the Falcon/Siena queue create/destroy code, * and then the original functions can be removed (see bug30834 * comment #1). But, for now, we just ensure that they are - * no-ops for Huntington, to allow bringing up existing drivers + * no-ops for EF10, to allow bringing up existing drivers * without modification. */ return (0); } -#endif /* EFSYS_OPT_HUNTINGTON */ +#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ if (stop >= EFX_BUF_TBL_SIZE) { rc = EFBIG; @@ -158,7 +156,7 @@ fail2: EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_UPD_REG, &oword); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -176,20 +174,21 @@ efx_sram_buf_tbl_clear( EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); -#if EFSYS_OPT_HUNTINGTON - if (enp->en_family == EFX_FAMILY_HUNTINGTON) { +#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD + if (enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD) { /* * FIXME: the efx_sram_buf_tbl_*() functionality needs to be * pulled inside the Falcon/Siena queue create/destroy code, * and then the original functions can be removed (see bug30834 * comment #1). But, for now, we just ensure that they are - * no-ops for Huntington, to allow bringing up existing drivers + * no-ops for EF10, to allow bringing up existing drivers * without modification. */ return; } -#endif /* EFSYS_OPT_HUNTINGTON */ +#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ EFSYS_ASSERT3U(stop, <, EFX_BUF_TBL_SIZE); @@ -306,7 +305,7 @@ efx_sram_pattern_fn_t __efx_sram_pattern_fns[] = { efx_sram_bit_sweep_set }; - __checkReturn int + __checkReturn efx_rc_t efx_sram_test( __in efx_nic_t *enp, __in efx_pattern_type_t type) diff --git a/sys/dev/sfxge/common/efx_tx.c b/sys/dev/sfxge/common/efx_tx.c index a2e8769..cff7742 100644 --- a/sys/dev/sfxge/common/efx_tx.c +++ b/sys/dev/sfxge/common/efx_tx.c @@ -31,10 +31,7 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" -#include "efx_types.h" -#include "efx_regs.h" #include "efx_impl.h" #if EFSYS_OPT_QSTATS @@ -49,7 +46,7 @@ __FBSDID("$FreeBSD$"); #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_tx_init( __in efx_nic_t *enp); @@ -57,7 +54,7 @@ static void falconsiena_tx_fini( __in efx_nic_t *enp); -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_tx_qcreate( __in efx_nic_t *enp, __in unsigned int index, @@ -74,7 +71,7 @@ static void falconsiena_tx_qdestroy( __in efx_txq_t *etp); -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_tx_qpost( __in efx_txq_t *etp, __in_ecount(n) efx_buffer_t *eb, @@ -88,12 +85,12 @@ falconsiena_tx_qpush( __in unsigned int added, __in unsigned int pushed); -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_tx_qpace( __in efx_txq_t *etp, __in unsigned int ns); -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_tx_qflush( __in efx_txq_t *etp); @@ -101,7 +98,7 @@ static void falconsiena_tx_qenable( __in efx_txq_t *etp); - __checkReturn int + __checkReturn efx_rc_t falconsiena_tx_qdesc_post( __in efx_txq_t *etp, __in_ecount(n) efx_desc_t *ed, @@ -179,35 +176,60 @@ static efx_tx_ops_t __efx_tx_siena_ops = { #if EFSYS_OPT_HUNTINGTON static efx_tx_ops_t __efx_tx_hunt_ops = { - hunt_tx_init, /* etxo_init */ - hunt_tx_fini, /* etxo_fini */ - hunt_tx_qcreate, /* etxo_qcreate */ - hunt_tx_qdestroy, /* etxo_qdestroy */ - hunt_tx_qpost, /* etxo_qpost */ - hunt_tx_qpush, /* etxo_qpush */ - hunt_tx_qpace, /* etxo_qpace */ - hunt_tx_qflush, /* etxo_qflush */ - hunt_tx_qenable, /* etxo_qenable */ - hunt_tx_qpio_enable, /* etxo_qpio_enable */ - hunt_tx_qpio_disable, /* etxo_qpio_disable */ - hunt_tx_qpio_write, /* etxo_qpio_write */ - hunt_tx_qpio_post, /* etxo_qpio_post */ - hunt_tx_qdesc_post, /* etxo_qdesc_post */ - hunt_tx_qdesc_dma_create, /* etxo_qdesc_dma_create */ + ef10_tx_init, /* etxo_init */ + ef10_tx_fini, /* etxo_fini */ + ef10_tx_qcreate, /* etxo_qcreate */ + ef10_tx_qdestroy, /* etxo_qdestroy */ + ef10_tx_qpost, /* etxo_qpost */ + ef10_tx_qpush, /* etxo_qpush */ + ef10_tx_qpace, /* etxo_qpace */ + ef10_tx_qflush, /* etxo_qflush */ + ef10_tx_qenable, /* etxo_qenable */ + ef10_tx_qpio_enable, /* etxo_qpio_enable */ + ef10_tx_qpio_disable, /* etxo_qpio_disable */ + ef10_tx_qpio_write, /* etxo_qpio_write */ + ef10_tx_qpio_post, /* etxo_qpio_post */ + ef10_tx_qdesc_post, /* etxo_qdesc_post */ + ef10_tx_qdesc_dma_create, /* etxo_qdesc_dma_create */ hunt_tx_qdesc_tso_create, /* etxo_qdesc_tso_create */ - hunt_tx_qdesc_vlantci_create, /* etxo_qdesc_vlantci_create */ + ef10_tx_qdesc_vlantci_create, /* etxo_qdesc_vlantci_create */ #if EFSYS_OPT_QSTATS - hunt_tx_qstats_update, /* etxo_qstats_update */ + ef10_tx_qstats_update, /* etxo_qstats_update */ #endif }; #endif /* EFSYS_OPT_HUNTINGTON */ - __checkReturn int +#if EFSYS_OPT_MEDFORD +static efx_tx_ops_t __efx_tx_medford_ops = { + ef10_tx_init, /* etxo_init */ + ef10_tx_fini, /* etxo_fini */ + ef10_tx_qcreate, /* etxo_qcreate */ + ef10_tx_qdestroy, /* etxo_qdestroy */ + ef10_tx_qpost, /* etxo_qpost */ + ef10_tx_qpush, /* etxo_qpush */ + ef10_tx_qpace, /* etxo_qpace */ + ef10_tx_qflush, /* etxo_qflush */ + ef10_tx_qenable, /* etxo_qenable */ + ef10_tx_qpio_enable, /* etxo_qpio_enable */ + ef10_tx_qpio_disable, /* etxo_qpio_disable */ + ef10_tx_qpio_write, /* etxo_qpio_write */ + ef10_tx_qpio_post, /* etxo_qpio_post */ + ef10_tx_qdesc_post, /* etxo_qdesc_post */ + ef10_tx_qdesc_dma_create, /* etxo_qdesc_dma_create */ + NULL, /* etxo_qdesc_tso_create */ + ef10_tx_qdesc_vlantci_create, /* etxo_qdesc_vlantci_create */ +#if EFSYS_OPT_QSTATS + ef10_tx_qstats_update, /* etxo_qstats_update */ +#endif +}; +#endif /* EFSYS_OPT_MEDFORD */ + + __checkReturn efx_rc_t efx_tx_init( __in efx_nic_t *enp) { efx_tx_ops_t *etxop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC); @@ -241,6 +263,12 @@ efx_tx_init( break; #endif /* EFSYS_OPT_HUNTINGTON */ +#if EFSYS_OPT_MEDFORD + case EFX_FAMILY_MEDFORD: + etxop = (efx_tx_ops_t *)&__efx_tx_medford_ops; + break; +#endif /* EFSYS_OPT_MEDFORD */ + default: EFSYS_ASSERT(0); rc = ENOTSUP; @@ -263,7 +291,7 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); enp->en_etxop = NULL; enp->en_mod_flags &= ~EFX_MOD_TX; @@ -287,7 +315,7 @@ efx_tx_fini( enp->en_mod_flags &= ~EFX_MOD_TX; } - __checkReturn int + __checkReturn efx_rc_t efx_tx_qcreate( __in efx_nic_t *enp, __in unsigned int index, @@ -303,7 +331,7 @@ efx_tx_qcreate( efx_tx_ops_t *etxop = enp->en_etxop; efx_nic_cfg_t *encp = &(enp->en_nic_cfg); efx_txq_t *etp; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_TX); @@ -340,7 +368,7 @@ fail2: EFSYS_PROBE(fail2); EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_txq_t), etp); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -362,7 +390,7 @@ efx_tx_qdestroy( EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_txq_t), etp); } - __checkReturn int + __checkReturn efx_rc_t efx_tx_qpost( __in efx_txq_t *etp, __in_ecount(n) efx_buffer_t *eb, @@ -372,7 +400,7 @@ efx_tx_qpost( { efx_nic_t *enp = etp->et_enp; efx_tx_ops_t *etxop = enp->en_etxop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); @@ -383,7 +411,7 @@ efx_tx_qpost( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -401,14 +429,14 @@ efx_tx_qpush( etxop->etxo_qpush(etp, added, pushed); } - __checkReturn int + __checkReturn efx_rc_t efx_tx_qpace( __in efx_txq_t *etp, __in unsigned int ns) { efx_nic_t *enp = etp->et_enp; efx_tx_ops_t *etxop = enp->en_etxop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); @@ -418,17 +446,17 @@ efx_tx_qpace( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_tx_qflush( __in efx_txq_t *etp) { efx_nic_t *enp = etp->et_enp; efx_tx_ops_t *etxop = enp->en_etxop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); @@ -438,7 +466,7 @@ efx_tx_qflush( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -454,13 +482,13 @@ efx_tx_qenable( etxop->etxo_qenable(etp); } - __checkReturn int + __checkReturn efx_rc_t efx_tx_qpio_enable( __in efx_txq_t *etp) { efx_nic_t *enp = etp->et_enp; efx_tx_ops_t *etxop = enp->en_etxop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); @@ -482,7 +510,7 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -499,7 +527,7 @@ efx_tx_qpio_disable( etxop->etxo_qpio_disable(etp); } - __checkReturn int + __checkReturn efx_rc_t efx_tx_qpio_write( __in efx_txq_t *etp, __in_ecount(buf_length) uint8_t *buffer, @@ -508,7 +536,7 @@ efx_tx_qpio_write( { efx_nic_t *enp = etp->et_enp; efx_tx_ops_t *etxop = enp->en_etxop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); @@ -522,11 +550,11 @@ efx_tx_qpio_write( return (ENOTSUP); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_tx_qpio_post( __in efx_txq_t *etp, __in size_t pkt_length, @@ -535,7 +563,7 @@ efx_tx_qpio_post( { efx_nic_t *enp = etp->et_enp; efx_tx_ops_t *etxop = enp->en_etxop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); @@ -549,11 +577,11 @@ efx_tx_qpio_post( return (ENOTSUP); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_tx_qdesc_post( __in efx_txq_t *etp, __in_ecount(n) efx_desc_t *ed, @@ -563,7 +591,7 @@ efx_tx_qdesc_post( { efx_nic_t *enp = etp->et_enp; efx_tx_ops_t *etxop = enp->en_etxop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC); @@ -574,7 +602,7 @@ efx_tx_qdesc_post( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -646,7 +674,7 @@ efx_tx_qstats_update( #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_tx_init( __in efx_nic_t *enp) { @@ -709,7 +737,7 @@ falconsiena_tx_init( _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_tx_qpost( __in efx_txq_t *etp, __in_ecount(n) efx_buffer_t *eb, @@ -742,7 +770,7 @@ falconsiena_tx_qpost( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -778,7 +806,7 @@ falconsiena_tx_qpush( #define EFX_MAX_PACE_VALUE 20 #define EFX_TX_PACE_CLOCK_BASE 104 -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_tx_qpace( __in efx_txq_t *etp, __in unsigned int ns) @@ -788,7 +816,7 @@ falconsiena_tx_qpace( efx_oword_t oword; unsigned int pace_val; unsigned int timer_period; - int rc; + efx_rc_t rc; if (ns == 0) { pace_val = 0; @@ -816,12 +844,12 @@ falconsiena_tx_qpace( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_tx_qflush( __in efx_txq_t *etp) { @@ -865,7 +893,7 @@ falconsiena_tx_qenable( etp->et_index, &oword, B_TRUE); } -static __checkReturn int +static __checkReturn efx_rc_t falconsiena_tx_qcreate( __in efx_nic_t *enp, __in unsigned int index, @@ -881,7 +909,7 @@ falconsiena_tx_qcreate( efx_nic_cfg_t *encp = &(enp->en_nic_cfg); efx_oword_t oword; uint32_t size; - int rc; + efx_rc_t rc; EFX_STATIC_ASSERT(EFX_EV_TX_NLABELS == (1 << FRF_AZ_TX_DESCQ_LABEL_WIDTH)); @@ -909,6 +937,8 @@ falconsiena_tx_qcreate( } /* Set up the new descriptor queue */ + *addedp = 0; + EFX_POPULATE_OWORD_6(oword, FRF_AZ_TX_DESCQ_BUF_BASE_ID, id, FRF_AZ_TX_DESCQ_EVQ_ID, eep->ee_index, @@ -919,9 +949,9 @@ falconsiena_tx_qcreate( EFX_SET_OWORD_FIELD(oword, FRF_BZ_TX_NON_IP_DROP_DIS, 1); EFX_SET_OWORD_FIELD(oword, FRF_BZ_TX_IP_CHKSM_DIS, - (flags & EFX_CKSUM_IPV4) ? 0 : 1); + (flags & EFX_TXQ_CKSUM_IPV4) ? 0 : 1); EFX_SET_OWORD_FIELD(oword, FRF_BZ_TX_TCP_CHKSM_DIS, - (flags & EFX_CKSUM_TCPUDP) ? 0 : 1); + (flags & EFX_TXQ_CKSUM_TCPUDP) ? 0 : 1); EFX_BAR_TBL_WRITEO(enp, FR_AZ_TX_DESC_PTR_TBL, etp->et_index, &oword, B_TRUE); @@ -933,12 +963,12 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t falconsiena_tx_qdesc_post( __in efx_txq_t *etp, __in_ecount(n) efx_desc_t *ed, @@ -948,7 +978,7 @@ falconsiena_tx_qdesc_post( { unsigned int added = *addedp; unsigned int i; - int rc; + efx_rc_t rc; if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) { rc = ENOSPC; @@ -975,7 +1005,7 @@ falconsiena_tx_qdesc_post( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } diff --git a/sys/dev/sfxge/common/efx_types.h b/sys/dev/sfxge/common/efx_types.h index ee357b1..ae4c6d9 100644 --- a/sys/dev/sfxge/common/efx_types.h +++ b/sys/dev/sfxge/common/efx_types.h @@ -536,7 +536,7 @@ extern int fix_lint; (_oword).eo_u32[3]) == ~((uint32_t)0)) #define EFX_QWORD_IS_SET64(_qword) \ - (((_qword).eq_u64[0]) == ~((uint32_t)0)) + (((_qword).eq_u64[0]) == ~((uint64_t)0)) #define EFX_QWORD_IS_SET32(_qword) \ (((_qword).eq_u32[0] & \ @@ -1584,7 +1584,7 @@ extern int fix_lint; #define EFX_OR_BYTE(_byte1, _byte2) \ do { \ - (_byte1).eb_u8[0] &= (_byte2).eb_u8[0]; \ + (_byte1).eb_u8[0] |= (_byte2).eb_u8[0]; \ _NOTE(CONSTANTCONDITION) \ } while (B_FALSE) diff --git a/sys/dev/sfxge/common/efx_vpd.c b/sys/dev/sfxge/common/efx_vpd.c index 812070a..c1762e6 100644 --- a/sys/dev/sfxge/common/efx_vpd.c +++ b/sys/dev/sfxge/common/efx_vpd.c @@ -31,10 +31,7 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" -#include "efx_types.h" -#include "efx_regs.h" #include "efx_impl.h" #if EFSYS_OPT_VPD @@ -91,29 +88,29 @@ static efx_vpd_ops_t __efx_vpd_siena_ops = { #endif /* EFSYS_OPT_SIENA */ -#if EFSYS_OPT_HUNTINGTON - -static efx_vpd_ops_t __efx_vpd_hunt_ops = { - hunt_vpd_init, /* evpdo_init */ - hunt_vpd_size, /* evpdo_size */ - hunt_vpd_read, /* evpdo_read */ - hunt_vpd_verify, /* evpdo_verify */ - hunt_vpd_reinit, /* evpdo_reinit */ - hunt_vpd_get, /* evpdo_get */ - hunt_vpd_set, /* evpdo_set */ - hunt_vpd_next, /* evpdo_next */ - hunt_vpd_write, /* evpdo_write */ - hunt_vpd_fini, /* evpdo_fini */ +#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD + +static efx_vpd_ops_t __efx_vpd_ef10_ops = { + ef10_vpd_init, /* evpdo_init */ + ef10_vpd_size, /* evpdo_size */ + ef10_vpd_read, /* evpdo_read */ + ef10_vpd_verify, /* evpdo_verify */ + ef10_vpd_reinit, /* evpdo_reinit */ + ef10_vpd_get, /* evpdo_get */ + ef10_vpd_set, /* evpdo_set */ + ef10_vpd_next, /* evpdo_next */ + ef10_vpd_write, /* evpdo_write */ + ef10_vpd_fini, /* evpdo_fini */ }; -#endif /* EFSYS_OPT_HUNTINGTON */ +#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ - __checkReturn int + __checkReturn efx_rc_t efx_vpd_init( __in efx_nic_t *enp) { efx_vpd_ops_t *evpdop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); @@ -134,10 +131,16 @@ efx_vpd_init( #if EFSYS_OPT_HUNTINGTON case EFX_FAMILY_HUNTINGTON: - evpdop = (efx_vpd_ops_t *)&__efx_vpd_hunt_ops; + evpdop = (efx_vpd_ops_t *)&__efx_vpd_ef10_ops; break; #endif /* EFSYS_OPT_HUNTINGTON */ +#if EFSYS_OPT_MEDFORD + case EFX_FAMILY_MEDFORD: + evpdop = (efx_vpd_ops_t *)&__efx_vpd_ef10_ops; + break; +#endif /* EFSYS_OPT_MEDFORD */ + default: EFSYS_ASSERT(0); rc = ENOTSUP; @@ -157,18 +160,18 @@ efx_vpd_init( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_vpd_size( __in efx_nic_t *enp, __out size_t *sizep) { efx_vpd_ops_t *evpdop = enp->en_evpdop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_VPD); @@ -179,19 +182,19 @@ efx_vpd_size( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_vpd_read( __in efx_nic_t *enp, __out_bcount(size) caddr_t data, __in size_t size) { efx_vpd_ops_t *evpdop = enp->en_evpdop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_VPD); @@ -202,19 +205,19 @@ efx_vpd_read( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_vpd_verify( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size) { efx_vpd_ops_t *evpdop = enp->en_evpdop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_VPD); @@ -225,19 +228,19 @@ efx_vpd_verify( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_vpd_reinit( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size) { efx_vpd_ops_t *evpdop = enp->en_evpdop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_VPD); @@ -255,12 +258,12 @@ efx_vpd_reinit( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_vpd_get( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, @@ -268,7 +271,7 @@ efx_vpd_get( __inout efx_vpd_value_t *evvp) { efx_vpd_ops_t *evpdop = enp->en_evpdop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_VPD); @@ -279,12 +282,12 @@ efx_vpd_get( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_vpd_set( __in efx_nic_t *enp, __inout_bcount(size) caddr_t data, @@ -292,7 +295,7 @@ efx_vpd_set( __in efx_vpd_value_t *evvp) { efx_vpd_ops_t *evpdop = enp->en_evpdop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_VPD); @@ -303,12 +306,12 @@ efx_vpd_set( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_vpd_next( __in efx_nic_t *enp, __inout_bcount(size) caddr_t data, @@ -317,7 +320,7 @@ efx_vpd_next( __inout unsigned int *contp) { efx_vpd_ops_t *evpdop = enp->en_evpdop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_VPD); @@ -328,19 +331,19 @@ efx_vpd_next( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_vpd_write( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size) { efx_vpd_ops_t *evpdop = enp->en_evpdop; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_VPD); @@ -351,12 +354,12 @@ efx_vpd_write( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t efx_vpd_next_tag( __in caddr_t data, __in size_t size, @@ -369,7 +372,7 @@ efx_vpd_next_tag( uint8_t name; uint16_t length; size_t headlen; - int rc; + efx_rc_t rc; if (*offsetp >= size) { rc = EFAULT; @@ -436,12 +439,12 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t efx_vpd_next_keyword( __in_bcount(size) caddr_t tag, __in size_t size, @@ -451,7 +454,7 @@ efx_vpd_next_keyword( { efx_vpd_keyword_t keyword; uint8_t length; - int rc; + efx_rc_t rc; if (pos + 3U > size) { rc = EFAULT; @@ -474,12 +477,12 @@ efx_vpd_next_keyword( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_vpd_hunk_length( __in_bcount(size) caddr_t data, __in size_t size, @@ -488,7 +491,7 @@ efx_vpd_hunk_length( efx_vpd_tag_t tag; unsigned int offset; uint16_t taglen; - int rc; + efx_rc_t rc; offset = 0; _NOTE(CONSTANTCONDITION) @@ -506,12 +509,12 @@ efx_vpd_hunk_length( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_vpd_hunk_verify( __in_bcount(size) caddr_t data, __in size_t size, @@ -526,7 +529,7 @@ efx_vpd_hunk_verify( uint8_t keylen; uint8_t cksum; boolean_t cksummed = B_FALSE; - int rc; + efx_rc_t rc; /* * Parse every tag,keyword in the existing VPD. If the csum is present, @@ -545,8 +548,10 @@ efx_vpd_hunk_verify( for (pos = 0; pos != taglen; pos += 3 + keylen) { /* RV keyword must be the last in the block */ - if (cksummed) + if (cksummed) { + rc = EFAULT; goto fail2; + } if ((rc = efx_vpd_next_keyword(data + offset, taglen, pos, &keyword, &keylen)) != 0) @@ -589,7 +594,7 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -610,7 +615,7 @@ static uint8_t __efx_vpd_blank_r[] = { 0x00, }; - __checkReturn int + __checkReturn efx_rc_t efx_vpd_hunk_reinit( __in_bcount(size) caddr_t data, __in size_t size, @@ -620,7 +625,7 @@ efx_vpd_hunk_reinit( unsigned int pos; efx_byte_t byte; uint8_t cksum; - int rc; + efx_rc_t rc; if (size < 0x100) { rc = ENOSPC; @@ -653,12 +658,12 @@ efx_vpd_hunk_reinit( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_vpd_hunk_next( __in_bcount(size) caddr_t data, __in size_t size, @@ -676,7 +681,7 @@ efx_vpd_hunk_next( uint16_t taglen; uint8_t keylen; uint8_t paylen; - int rc; + efx_rc_t rc; offset = index = 0; _NOTE(CONSTANTCONDITION) @@ -729,12 +734,12 @@ done: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_vpd_hunk_get( __in_bcount(size) caddr_t data, __in size_t size, @@ -749,7 +754,7 @@ efx_vpd_hunk_get( unsigned int pos; uint16_t taglen; uint8_t keylen; - int rc; + efx_rc_t rc; offset = 0; _NOTE(CONSTANTCONDITION) @@ -791,12 +796,12 @@ efx_vpd_hunk_get( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_vpd_hunk_set( __in_bcount(size) caddr_t data, __in size_t size, @@ -815,7 +820,7 @@ efx_vpd_hunk_set( uint8_t keylen; uint8_t cksum; size_t used; - int rc; + efx_rc_t rc; switch (evvp->evv_tag) { case EFX_VPD_ID: @@ -1005,7 +1010,7 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } diff --git a/sys/dev/sfxge/common/efx_wol.c b/sys/dev/sfxge/common/efx_wol.c index 2e1b4a1..aea3c55 100644 --- a/sys/dev/sfxge/common/efx_wol.c +++ b/sys/dev/sfxge/common/efx_wol.c @@ -31,19 +31,17 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" -#include "efx_types.h" #include "efx_impl.h" #if EFSYS_OPT_WOL - __checkReturn int + __checkReturn efx_rc_t efx_wol_init( __in efx_nic_t *enp) { efx_nic_cfg_t *encp = &(enp->en_nic_cfg); - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); @@ -62,19 +60,19 @@ efx_wol_init( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_wol_filter_clear( __in efx_nic_t *enp) { efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_WOL_FILTER_RESET_IN_LEN, MC_CMD_WOL_FILTER_RESET_OUT_LEN)]; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_WOL); @@ -100,12 +98,12 @@ efx_wol_filter_clear( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_wol_filter_add( __in efx_nic_t *enp, __in efx_wol_type_t type, @@ -116,7 +114,7 @@ efx_wol_filter_add( uint8_t payload[MAX(MC_CMD_WOL_FILTER_SET_IN_LEN, MC_CMD_WOL_FILTER_SET_OUT_LEN)]; efx_byte_t link_mask; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_WOL); @@ -222,12 +220,12 @@ efx_wol_filter_add( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_wol_filter_remove( __in efx_nic_t *enp, __in uint32_t filter_id) @@ -235,7 +233,7 @@ efx_wol_filter_remove( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_WOL_FILTER_REMOVE_IN_LEN, MC_CMD_WOL_FILTER_REMOVE_OUT_LEN)]; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_WOL); @@ -259,13 +257,13 @@ efx_wol_filter_remove( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_lightsout_offload_add( __in efx_nic_t *enp, __in efx_lightsout_offload_type_t type, @@ -276,7 +274,7 @@ efx_lightsout_offload_add( uint8_t payload[MAX(MAX(MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN, MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN), MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN)]; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_WOL); @@ -341,13 +339,13 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t efx_lightsout_offload_remove( __in efx_nic_t *enp, __in efx_lightsout_offload_type_t type, @@ -356,7 +354,7 @@ efx_lightsout_offload_remove( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN, MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN)]; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_WOL); @@ -397,7 +395,7 @@ efx_lightsout_offload_remove( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } diff --git a/sys/dev/sfxge/common/hunt_ev.c b/sys/dev/sfxge/common/hunt_ev.c index 8e5cf89..2cea2e0 100644 --- a/sys/dev/sfxge/common/hunt_ev.c +++ b/sys/dev/sfxge/common/hunt_ev.c @@ -31,10 +31,7 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" -#include "efx_types.h" -#include "efx_regs.h" #include "efx_impl.h" #if EFSYS_OPT_MON_STATS #include "mcdi_mon.h" @@ -54,42 +51,42 @@ __FBSDID("$FreeBSD$"); static __checkReturn boolean_t -hunt_ev_rx( +ef10_ev_rx( __in efx_evq_t *eep, __in efx_qword_t *eqp, __in const efx_ev_callbacks_t *eecp, __in_opt void *arg); static __checkReturn boolean_t -hunt_ev_tx( +ef10_ev_tx( __in efx_evq_t *eep, __in efx_qword_t *eqp, __in const efx_ev_callbacks_t *eecp, __in_opt void *arg); static __checkReturn boolean_t -hunt_ev_driver( +ef10_ev_driver( __in efx_evq_t *eep, __in efx_qword_t *eqp, __in const efx_ev_callbacks_t *eecp, __in_opt void *arg); static __checkReturn boolean_t -hunt_ev_drv_gen( +ef10_ev_drv_gen( __in efx_evq_t *eep, __in efx_qword_t *eqp, __in const efx_ev_callbacks_t *eecp, __in_opt void *arg); static __checkReturn boolean_t -hunt_ev_mcdi( +ef10_ev_mcdi( __in efx_evq_t *eep, __in efx_qword_t *eqp, __in const efx_ev_callbacks_t *eecp, __in_opt void *arg); -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_init_evq( __in efx_nic_t *enp, __in unsigned int instance, @@ -107,7 +104,7 @@ efx_mcdi_init_evq( int npages; int i; int supports_rx_batching; - int rc; + efx_rc_t rc; npages = EFX_EVQ_NBUFS(nevs); if (MC_CMD_INIT_EVQ_IN_LEN(npages) > MC_CMD_INIT_EVQ_IN_LENMAX) { @@ -188,12 +185,12 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_fini_evq( __in efx_nic_t *enp, __in uint32_t instance) @@ -201,7 +198,7 @@ efx_mcdi_fini_evq( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_FINI_EVQ_IN_LEN, MC_CMD_FINI_EVQ_OUT_LEN)]; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_FINI_EVQ; @@ -222,15 +219,15 @@ efx_mcdi_fini_evq( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_ev_init( + __checkReturn efx_rc_t +ef10_ev_init( __in efx_nic_t *enp) { _NOTE(ARGUNUSED(enp)) @@ -238,14 +235,14 @@ hunt_ev_init( } void -hunt_ev_fini( +ef10_ev_fini( __in efx_nic_t *enp) { _NOTE(ARGUNUSED(enp)) } - __checkReturn int -hunt_ev_qcreate( + __checkReturn efx_rc_t +ef10_ev_qcreate( __in efx_nic_t *enp, __in unsigned int index, __in efsys_mem_t *esmp, @@ -255,7 +252,7 @@ hunt_ev_qcreate( { efx_nic_cfg_t *encp = &(enp->en_nic_cfg); uint32_t irq; - int rc; + efx_rc_t rc; _NOTE(ARGUNUSED(id)) /* buftbl id managed by MC */ EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS)); @@ -272,11 +269,11 @@ hunt_ev_qcreate( } /* Set up the handler table */ - eep->ee_rx = hunt_ev_rx; - eep->ee_tx = hunt_ev_tx; - eep->ee_driver = hunt_ev_driver; - eep->ee_drv_gen = hunt_ev_drv_gen; - eep->ee_mcdi = hunt_ev_mcdi; + eep->ee_rx = ef10_ev_rx; + eep->ee_tx = ef10_ev_tx; + eep->ee_driver = ef10_ev_driver; + eep->ee_drv_gen = ef10_ev_drv_gen; + eep->ee_mcdi = ef10_ev_mcdi; /* * Set up the event queue @@ -293,24 +290,25 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } void -hunt_ev_qdestroy( +ef10_ev_qdestroy( __in efx_evq_t *eep) { efx_nic_t *enp = eep->ee_enp; - EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); (void) efx_mcdi_fini_evq(eep->ee_enp, eep->ee_index); } - __checkReturn int -hunt_ev_qprime( + __checkReturn efx_rc_t +ef10_ev_qprime( __in efx_evq_t *eep, __in unsigned int count) { @@ -350,7 +348,7 @@ hunt_ev_qprime( return (0); } -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_driver_event( __in efx_nic_t *enp, __in uint32_t evq, @@ -359,7 +357,7 @@ efx_mcdi_driver_event( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_DRIVER_EVENT_IN_LEN, MC_CMD_DRIVER_EVENT_OUT_LEN)]; - int rc; + efx_rc_t rc; req.emr_cmd = MC_CMD_DRIVER_EVENT; req.emr_in_buf = payload; @@ -384,13 +382,13 @@ efx_mcdi_driver_event( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } void -hunt_ev_qpost( +ef10_ev_qpost( __in efx_evq_t *eep, __in uint16_t data) { @@ -405,8 +403,8 @@ hunt_ev_qpost( (void) efx_mcdi_driver_event(enp, eep->ee_index, event); } - __checkReturn int -hunt_ev_qmoderate( + __checkReturn efx_rc_t +ef10_ev_qmoderate( __in efx_evq_t *eep, __in unsigned int us) { @@ -414,7 +412,7 @@ hunt_ev_qmoderate( efx_nic_cfg_t *encp = &(enp->en_nic_cfg); efx_dword_t dword; uint32_t timer_val, mode; - int rc; + efx_rc_t rc; if (us > encp->enc_evq_timer_max_us) { rc = EINVAL; @@ -455,7 +453,7 @@ hunt_ev_qmoderate( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -463,14 +461,10 @@ fail1: #if EFSYS_OPT_QSTATS void -hunt_ev_qstats_update( +ef10_ev_qstats_update( __in efx_evq_t *eep, __inout_ecount(EV_NQSTATS) efsys_stat_t *stat) { - /* - * TBD: Consider a common Siena/Huntington function. The code is - * essentially identical. - */ unsigned int id; for (id = 0; id < EV_NQSTATS; id++) { @@ -484,7 +478,7 @@ hunt_ev_qstats_update( static __checkReturn boolean_t -hunt_ev_rx( +ef10_ev_rx( __in efx_evq_t *eep, __in efx_qword_t *eqp, __in const efx_ev_callbacks_t *eecp, @@ -492,7 +486,9 @@ hunt_ev_rx( { efx_nic_t *enp = eep->ee_enp; uint32_t size; +#if 0 boolean_t parse_err; +#endif uint32_t label; uint32_t mcast; uint32_t eth_base_class; @@ -500,7 +496,6 @@ hunt_ev_rx( uint32_t l3_class; uint32_t l4_class; uint32_t next_read_lbits; - boolean_t soft1, soft2; uint16_t flags; boolean_t should_abort; efx_evq_rxq_state_t *eersp; @@ -528,14 +523,21 @@ hunt_ev_rx( if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_CONT) != 0) { /* + * This may be part of a scattered frame, or it may be a + * truncated frame if scatter is disabled on this RXQ. + * Overlength frames can be received if e.g. a VF is configured + * for 1500 MTU but connected to a port set to 9000 MTU + * (see bug56567). * FIXME: There is not yet any driver that supports scatter on * Huntington. Scatter support is required for OSX. */ - EFSYS_ASSERT(0); flags |= EFX_PKT_CONT; } +#if 0 + /* TODO What to do if the packet is flagged with parsing error */ parse_err = (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_PARSE_INCOMPLETE) != 0); +#endif label = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_QLABEL); if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECRC_ERR) != 0) { @@ -555,10 +557,6 @@ hunt_ev_rx( flags |= EFX_DISCARD; } - /* FIXME: do we need soft bits from RXDP firmware ? */ - soft1 = (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_EV_SOFT1) != 0); - soft2 = (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_EV_SOFT2) != 0); - mcast = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_MAC_CLASS); if (mcast == ESE_DZ_MAC_CLASS_UCAST) flags |= EFX_PKT_UNICAST; @@ -619,7 +617,9 @@ hunt_ev_rx( switch (l3_class) { case ESE_DZ_L3_CLASS_RSVD7: /* Used by firmware for packet overrun */ +#if 0 parse_err = B_TRUE; +#endif flags |= EFX_DISCARD; break; @@ -680,7 +680,7 @@ hunt_ev_rx( } static __checkReturn boolean_t -hunt_ev_tx( +ef10_ev_tx( __in efx_evq_t *eep, __in efx_qword_t *eqp, __in const efx_ev_callbacks_t *eecp, @@ -715,7 +715,7 @@ hunt_ev_tx( } static __checkReturn boolean_t -hunt_ev_driver( +ef10_ev_driver( __in efx_evq_t *eep, __in efx_qword_t *eqp, __in const efx_ev_callbacks_t *eecp, @@ -765,7 +765,7 @@ hunt_ev_driver( } static __checkReturn boolean_t -hunt_ev_drv_gen( +ef10_ev_drv_gen( __in efx_evq_t *eep, __in efx_qword_t *eqp, __in const efx_ev_callbacks_t *eecp, @@ -793,7 +793,7 @@ hunt_ev_drv_gen( } static __checkReturn boolean_t -hunt_ev_mcdi( +ef10_ev_mcdi( __in efx_evq_t *eep, __in efx_qword_t *eqp, __in const efx_ev_callbacks_t *eecp, @@ -818,6 +818,20 @@ hunt_ev_mcdi( MCDI_EV_FIELD(eqp, CMDDONE_ERRNO)); break; +#if EFSYS_OPT_MCDI_PROXY_AUTH + case MCDI_EVENT_CODE_PROXY_RESPONSE: + /* + * This event notifies a function that an authorization request + * has been processed. If the request was authorized then the + * function can now re-send the original MCDI request. + * See SF-113652-SW "SR-IOV Proxied Network Access Control". + */ + efx_mcdi_ev_proxy_response(enp, + MCDI_EV_FIELD(eqp, PROXY_RESPONSE_HANDLE), + MCDI_EV_FIELD(eqp, PROXY_RESPONSE_RC)); + break; +#endif /* EFSYS_OPT_MCDI_PROXY_AUTH */ + case MCDI_EVENT_CODE_LINKCHANGE: { efx_link_mode_t link_mode; @@ -830,7 +844,7 @@ hunt_ev_mcdi( #if EFSYS_OPT_MON_STATS efx_mon_stat_t id; efx_mon_stat_value_t value; - int rc; + efx_rc_t rc; /* Decode monitor stat for MCDI sensor (if supported) */ if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0) { @@ -975,7 +989,7 @@ hunt_ev_mcdi( } void -hunt_ev_rxlabel_init( +ef10_ev_rxlabel_init( __in efx_evq_t *eep, __in efx_rxq_t *erp, __in unsigned int label) @@ -992,7 +1006,7 @@ hunt_ev_rxlabel_init( } void -hunt_ev_rxlabel_fini( +ef10_ev_rxlabel_fini( __in efx_evq_t *eep, __in unsigned int label) { diff --git a/sys/dev/sfxge/common/hunt_filter.c b/sys/dev/sfxge/common/hunt_filter.c index 27af7c3..eaa0720 100644 --- a/sys/dev/sfxge/common/hunt_filter.c +++ b/sys/dev/sfxge/common/hunt_filter.c @@ -31,100 +31,98 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" -#include "efx_types.h" -#include "efx_regs_mcdi.h" #include "efx_impl.h" #if EFSYS_OPT_HUNTINGTON #if EFSYS_OPT_FILTER -#define HFE_SPEC(hftp, index) ((hftp)->hft_entry[(index)].hfe_spec) +#define EFE_SPEC(eftp, index) ((eftp)->eft_entry[(index)].efe_spec) static efx_filter_spec_t * -hunt_filter_entry_spec( - __in const hunt_filter_table_t *hftp, +ef10_filter_entry_spec( + __in const ef10_filter_table_t *eftp, __in unsigned int index) { - return ((efx_filter_spec_t *)(HFE_SPEC(hftp, index) & - ~(uintptr_t)EFX_HUNT_FILTER_FLAGS)); + return ((efx_filter_spec_t *)(EFE_SPEC(eftp, index) & + ~(uintptr_t)EFX_EF10_FILTER_FLAGS)); } static boolean_t -hunt_filter_entry_is_busy( - __in const hunt_filter_table_t *hftp, +ef10_filter_entry_is_busy( + __in const ef10_filter_table_t *eftp, __in unsigned int index) { - if (HFE_SPEC(hftp, index) & EFX_HUNT_FILTER_FLAG_BUSY) + if (EFE_SPEC(eftp, index) & EFX_EF10_FILTER_FLAG_BUSY) return (B_TRUE); else return (B_FALSE); } static boolean_t -hunt_filter_entry_is_auto_old( - __in const hunt_filter_table_t *hftp, +ef10_filter_entry_is_auto_old( + __in const ef10_filter_table_t *eftp, __in unsigned int index) { - if (HFE_SPEC(hftp, index) & EFX_HUNT_FILTER_FLAG_AUTO_OLD) + if (EFE_SPEC(eftp, index) & EFX_EF10_FILTER_FLAG_AUTO_OLD) return (B_TRUE); else return (B_FALSE); } static void -hunt_filter_set_entry( - __inout hunt_filter_table_t *hftp, +ef10_filter_set_entry( + __inout ef10_filter_table_t *eftp, __in unsigned int index, __in_opt const efx_filter_spec_t *efsp) { - HFE_SPEC(hftp, index) = (uintptr_t)efsp; + EFE_SPEC(eftp, index) = (uintptr_t)efsp; } static void -hunt_filter_set_entry_busy( - __inout hunt_filter_table_t *hftp, +ef10_filter_set_entry_busy( + __inout ef10_filter_table_t *eftp, __in unsigned int index) { - HFE_SPEC(hftp, index) |= (uintptr_t)EFX_HUNT_FILTER_FLAG_BUSY; + EFE_SPEC(eftp, index) |= (uintptr_t)EFX_EF10_FILTER_FLAG_BUSY; } static void -hunt_filter_set_entry_not_busy( - __inout hunt_filter_table_t *hftp, +ef10_filter_set_entry_not_busy( + __inout ef10_filter_table_t *eftp, __in unsigned int index) { - HFE_SPEC(hftp, index) &= ~(uintptr_t)EFX_HUNT_FILTER_FLAG_BUSY; + EFE_SPEC(eftp, index) &= ~(uintptr_t)EFX_EF10_FILTER_FLAG_BUSY; } static void -hunt_filter_set_entry_auto_old( - __inout hunt_filter_table_t *hftp, +ef10_filter_set_entry_auto_old( + __inout ef10_filter_table_t *eftp, __in unsigned int index) { - EFSYS_ASSERT(hunt_filter_entry_spec(hftp, index) != NULL); - HFE_SPEC(hftp, index) |= (uintptr_t)EFX_HUNT_FILTER_FLAG_AUTO_OLD; + EFSYS_ASSERT(ef10_filter_entry_spec(eftp, index) != NULL); + EFE_SPEC(eftp, index) |= (uintptr_t)EFX_EF10_FILTER_FLAG_AUTO_OLD; } static void -hunt_filter_set_entry_not_auto_old( - __inout hunt_filter_table_t *hftp, +ef10_filter_set_entry_not_auto_old( + __inout ef10_filter_table_t *eftp, __in unsigned int index) { - HFE_SPEC(hftp, index) &= ~(uintptr_t)EFX_HUNT_FILTER_FLAG_AUTO_OLD; - EFSYS_ASSERT(hunt_filter_entry_spec(hftp, index) != NULL); + EFE_SPEC(eftp, index) &= ~(uintptr_t)EFX_EF10_FILTER_FLAG_AUTO_OLD; + EFSYS_ASSERT(ef10_filter_entry_spec(eftp, index) != NULL); } - __checkReturn int -hunt_filter_init( + __checkReturn efx_rc_t +ef10_filter_init( __in efx_nic_t *enp) { - int rc; - hunt_filter_table_t *hftp; + efx_rc_t rc; + ef10_filter_table_t *eftp; - EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); #define MATCH_MASK(match) (EFX_MASK32(match) << EFX_LOW_BIT(match)) EFX_STATIC_ASSERT(EFX_FILTER_MATCH_REM_HOST == @@ -149,47 +147,48 @@ hunt_filter_init( MATCH_MASK(MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO)); #undef MATCH_MASK - EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (hunt_filter_table_t), hftp); + EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (ef10_filter_table_t), eftp); - if (!hftp) { + if (!eftp) { rc = ENOMEM; goto fail1; } - enp->en_filter.ef_hunt_filter_table = hftp; + enp->en_filter.ef_ef10_filter_table = eftp; return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } void -hunt_filter_fini( +ef10_filter_fini( __in efx_nic_t *enp) { - EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); - if (enp->en_filter.ef_hunt_filter_table != NULL) { - EFSYS_KMEM_FREE(enp->en_esip, sizeof (hunt_filter_table_t), - enp->en_filter.ef_hunt_filter_table); + if (enp->en_filter.ef_ef10_filter_table != NULL) { + EFSYS_KMEM_FREE(enp->en_esip, sizeof (ef10_filter_table_t), + enp->en_filter.ef_ef10_filter_table); } } -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_filter_op_add( __in efx_nic_t *enp, __in efx_filter_spec_t *spec, __in unsigned int filter_op, - __inout hunt_filter_handle_t *handle) + __inout ef10_filter_handle_t *handle) { efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_FILTER_OP_IN_LEN, MC_CMD_FILTER_OP_OUT_LEN)]; uint32_t match_fields = 0; - int rc; + efx_rc_t rc; memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_FILTER_OP; @@ -201,9 +200,9 @@ efx_mcdi_filter_op_add( switch (filter_op) { case MC_CMD_FILTER_OP_IN_OP_REPLACE: MCDI_IN_SET_DWORD(req, FILTER_OP_IN_HANDLE_LO, - handle->hfh_lo); + handle->efh_lo); MCDI_IN_SET_DWORD(req, FILTER_OP_IN_HANDLE_HI, - handle->hfh_hi); + handle->efh_hi); /* Fall through */ case MC_CMD_FILTER_OP_IN_OP_INSERT: case MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE: @@ -302,8 +301,8 @@ efx_mcdi_filter_op_add( goto fail3; } - handle->hfh_lo = MCDI_OUT_DWORD(req, FILTER_OP_OUT_HANDLE_LO); - handle->hfh_hi = MCDI_OUT_DWORD(req, FILTER_OP_OUT_HANDLE_HI); + handle->efh_lo = MCDI_OUT_DWORD(req, FILTER_OP_OUT_HANDLE_LO); + handle->efh_hi = MCDI_OUT_DWORD(req, FILTER_OP_OUT_HANDLE_HI); return (0); @@ -312,22 +311,22 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_filter_op_delete( __in efx_nic_t *enp, __in unsigned int filter_op, - __inout hunt_filter_handle_t *handle) + __inout ef10_filter_handle_t *handle) { efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_FILTER_OP_IN_LEN, MC_CMD_FILTER_OP_OUT_LEN)]; - int rc; + efx_rc_t rc; memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_FILTER_OP; @@ -351,8 +350,8 @@ efx_mcdi_filter_op_delete( goto fail1; } - MCDI_IN_SET_DWORD(req, FILTER_OP_IN_HANDLE_LO, handle->hfh_lo); - MCDI_IN_SET_DWORD(req, FILTER_OP_IN_HANDLE_HI, handle->hfh_hi); + MCDI_IN_SET_DWORD(req, FILTER_OP_IN_HANDLE_LO, handle->efh_lo); + MCDI_IN_SET_DWORD(req, FILTER_OP_IN_HANDLE_HI, handle->efh_hi); efx_mcdi_execute(enp, &req); @@ -374,13 +373,13 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } static __checkReturn boolean_t -hunt_filter_equal( +ef10_filter_equal( __in const efx_filter_spec_t *left, __in const efx_filter_spec_t *right) { @@ -413,7 +412,7 @@ hunt_filter_equal( } static __checkReturn boolean_t -hunt_filter_same_dest( +ef10_filter_same_dest( __in const efx_filter_spec_t *left, __in const efx_filter_spec_t *right) { @@ -430,7 +429,7 @@ hunt_filter_same_dest( } static __checkReturn uint32_t -hunt_filter_hash( +ef10_filter_hash( __in efx_filter_spec_t *spec) { EFX_STATIC_ASSERT((sizeof (efx_filter_spec_t) % sizeof (uint32_t)) @@ -456,7 +455,7 @@ hunt_filter_hash( * exclusive. */ static __checkReturn boolean_t -hunt_filter_is_exclusive( +ef10_filter_is_exclusive( __in efx_filter_spec_t *spec) { if ((spec->efs_match_flags & EFX_FILTER_MATCH_LOC_MAC) && @@ -477,31 +476,32 @@ hunt_filter_is_exclusive( return (B_FALSE); } - __checkReturn int -hunt_filter_restore( + __checkReturn efx_rc_t +ef10_filter_restore( __in efx_nic_t *enp) { int tbl_id; efx_filter_spec_t *spec; - hunt_filter_table_t *hftp = enp->en_filter.ef_hunt_filter_table; + ef10_filter_table_t *eftp = enp->en_filter.ef_ef10_filter_table; boolean_t restoring; int state; - int rc; + efx_rc_t rc; - EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); - for (tbl_id = 0; tbl_id < EFX_HUNT_FILTER_TBL_ROWS; tbl_id++) { + for (tbl_id = 0; tbl_id < EFX_EF10_FILTER_TBL_ROWS; tbl_id++) { EFSYS_LOCK(enp->en_eslp, state); - spec = hunt_filter_entry_spec(hftp, tbl_id); + spec = ef10_filter_entry_spec(eftp, tbl_id); if (spec == NULL) { restoring = B_FALSE; - } else if (hunt_filter_entry_is_busy(hftp, tbl_id)) { + } else if (ef10_filter_entry_is_busy(eftp, tbl_id)) { /* Ignore busy entries. */ restoring = B_FALSE; } else { - hunt_filter_set_entry_busy(hftp, tbl_id); + ef10_filter_set_entry_busy(eftp, tbl_id); restoring = B_TRUE; } @@ -510,14 +510,14 @@ hunt_filter_restore( if (restoring == B_FALSE) continue; - if (hunt_filter_is_exclusive(spec)) { + if (ef10_filter_is_exclusive(spec)) { rc = efx_mcdi_filter_op_add(enp, spec, MC_CMD_FILTER_OP_IN_OP_INSERT, - &hftp->hft_entry[tbl_id].hfe_handle); + &eftp->eft_entry[tbl_id].efe_handle); } else { rc = efx_mcdi_filter_op_add(enp, spec, MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE, - &hftp->hft_entry[tbl_id].hfe_handle); + &eftp->eft_entry[tbl_id].efe_handle); } if (rc != 0) @@ -525,7 +525,7 @@ hunt_filter_restore( EFSYS_LOCK(enp->en_eslp, state); - hunt_filter_set_entry_not_busy(hftp, tbl_id); + ef10_filter_set_entry_not_busy(eftp, tbl_id); EFSYS_UNLOCK(enp->en_eslp, state); } @@ -533,7 +533,7 @@ hunt_filter_restore( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -542,17 +542,17 @@ fail1: * An arbitrary search limit for the software hash table. As per the linux net * driver. */ -#define EFX_HUNT_FILTER_SEARCH_LIMIT 200 +#define EF10_FILTER_SEARCH_LIMIT 200 -static __checkReturn int -hunt_filter_add_internal( +static __checkReturn efx_rc_t +ef10_filter_add_internal( __in efx_nic_t *enp, __inout efx_filter_spec_t *spec, __in boolean_t may_replace, __out_opt uint32_t *filter_id) { - int rc; - hunt_filter_table_t *hftp = enp->en_filter.ef_hunt_filter_table; + efx_rc_t rc; + ef10_filter_table_t *eftp = enp->en_filter.ef_ef10_filter_table; efx_filter_spec_t *saved_spec; uint32_t hash; unsigned int depth; @@ -562,13 +562,14 @@ hunt_filter_add_internal( int state; boolean_t locked = B_FALSE; - EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); #if EFSYS_OPT_RX_SCALE spec->efs_rss_context = enp->en_rss_context; #endif - hash = hunt_filter_hash(spec); + hash = ef10_filter_hash(spec); /* * FIXME: Add support for inserting filters of different priorities @@ -587,21 +588,21 @@ hunt_filter_add_internal( locked = B_TRUE; for (;;) { - i = (hash + depth) & (EFX_HUNT_FILTER_TBL_ROWS - 1); - saved_spec = hunt_filter_entry_spec(hftp, i); + i = (hash + depth) & (EFX_EF10_FILTER_TBL_ROWS - 1); + saved_spec = ef10_filter_entry_spec(eftp, i); if (!saved_spec) { if (ins_index < 0) { ins_index = i; } - } else if (hunt_filter_equal(spec, saved_spec)) { - if (hunt_filter_entry_is_busy(hftp, i)) + } else if (ef10_filter_equal(spec, saved_spec)) { + if (ef10_filter_entry_is_busy(eftp, i)) break; if (saved_spec->efs_priority == EFX_FILTER_PRI_AUTO) { ins_index = i; goto found; - } else if (hunt_filter_is_exclusive(spec)) { + } else if (ef10_filter_is_exclusive(spec)) { if (may_replace) { ins_index = i; goto found; @@ -619,7 +620,7 @@ hunt_filter_add_internal( * the first suitable slot or return EBUSY if * there was none. */ - if (depth == EFX_HUNT_FILTER_SEARCH_LIMIT) { + if (depth == EF10_FILTER_SEARCH_LIMIT) { if (ins_index < 0) { rc = EBUSY; goto fail2; @@ -639,11 +640,11 @@ found: * insert a conflicting filter while we're waiting for the * firmware must find the busy entry. */ - saved_spec = hunt_filter_entry_spec(hftp, ins_index); + saved_spec = ef10_filter_entry_spec(eftp, ins_index); if (saved_spec) { if (saved_spec->efs_priority == EFX_FILTER_PRI_AUTO) { /* This is a filter we are refreshing */ - hunt_filter_set_entry_not_auto_old(hftp, ins_index); + ef10_filter_set_entry_not_auto_old(eftp, ins_index); goto out_unlock; } @@ -655,9 +656,9 @@ found: goto fail3; } *saved_spec = *spec; - hunt_filter_set_entry(hftp, ins_index, saved_spec); + ef10_filter_set_entry(eftp, ins_index, saved_spec); } - hunt_filter_set_entry_busy(hftp, ins_index); + ef10_filter_set_entry_busy(eftp, ins_index); EFSYS_UNLOCK(enp->en_eslp, state); locked = B_FALSE; @@ -669,15 +670,15 @@ found: if (replacing) { rc = efx_mcdi_filter_op_add(enp, spec, MC_CMD_FILTER_OP_IN_OP_REPLACE, - &hftp->hft_entry[ins_index].hfe_handle); - } else if (hunt_filter_is_exclusive(spec)) { + &eftp->eft_entry[ins_index].efe_handle); + } else if (ef10_filter_is_exclusive(spec)) { rc = efx_mcdi_filter_op_add(enp, spec, MC_CMD_FILTER_OP_IN_OP_INSERT, - &hftp->hft_entry[ins_index].hfe_handle); + &eftp->eft_entry[ins_index].efe_handle); } else { rc = efx_mcdi_filter_op_add(enp, spec, MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE, - &hftp->hft_entry[ins_index].hfe_handle); + &eftp->eft_entry[ins_index].efe_handle); } if (rc != 0) @@ -694,7 +695,7 @@ found: saved_spec->efs_dmaq_id = spec->efs_dmaq_id; } - hunt_filter_set_entry_not_busy(hftp, ins_index); + ef10_filter_set_entry_not_busy(eftp, ins_index); out_unlock: @@ -713,8 +714,8 @@ fail4: EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), saved_spec); saved_spec = NULL; } - hunt_filter_set_entry_not_busy(hftp, ins_index); - hunt_filter_set_entry(hftp, ins_index, NULL); + ef10_filter_set_entry_not_busy(eftp, ins_index); + ef10_filter_set_entry(eftp, ins_index, NULL); fail3: EFSYS_PROBE(fail3); @@ -723,7 +724,7 @@ fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); if (locked) EFSYS_UNLOCK(enp->en_eslp, state); @@ -731,37 +732,37 @@ fail1: return (rc); } - __checkReturn int -hunt_filter_add( + __checkReturn efx_rc_t +ef10_filter_add( __in efx_nic_t *enp, __inout efx_filter_spec_t *spec, __in boolean_t may_replace) { - int rc; + efx_rc_t rc; - rc = hunt_filter_add_internal(enp, spec, may_replace, NULL); + rc = ef10_filter_add_internal(enp, spec, may_replace, NULL); if (rc != 0) goto fail1; return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int -hunt_filter_delete_internal( +static __checkReturn efx_rc_t +ef10_filter_delete_internal( __in efx_nic_t *enp, __in uint32_t filter_id) { - int rc; - hunt_filter_table_t *table = enp->en_filter.ef_hunt_filter_table; + efx_rc_t rc; + ef10_filter_table_t *table = enp->en_filter.ef_ef10_filter_table; efx_filter_spec_t *spec; int state; - uint32_t filter_idx = filter_id % EFX_HUNT_FILTER_TBL_ROWS; + uint32_t filter_idx = filter_id % EFX_EF10_FILTER_TBL_ROWS; /* * Find the software table entry and mark it busy. Don't @@ -771,13 +772,13 @@ hunt_filter_delete_internal( * FIXME: What if the busy flag is never cleared? */ EFSYS_LOCK(enp->en_eslp, state); - while (hunt_filter_entry_is_busy(table, filter_idx)) { + while (ef10_filter_entry_is_busy(table, filter_idx)) { EFSYS_UNLOCK(enp->en_eslp, state); EFSYS_SPIN(1); EFSYS_LOCK(enp->en_eslp, state); } - if ((spec = hunt_filter_entry_spec(table, filter_idx)) != NULL) { - hunt_filter_set_entry_busy(table, filter_idx); + if ((spec = ef10_filter_entry_spec(table, filter_idx)) != NULL) { + ef10_filter_set_entry_busy(table, filter_idx); } EFSYS_UNLOCK(enp->en_eslp, state); @@ -790,20 +791,20 @@ hunt_filter_delete_internal( * Try to remove the hardware filter. This may fail if the MC has * rebooted (which frees all hardware filter resources). */ - if (hunt_filter_is_exclusive(spec)) { + if (ef10_filter_is_exclusive(spec)) { rc = efx_mcdi_filter_op_delete(enp, MC_CMD_FILTER_OP_IN_OP_REMOVE, - &table->hft_entry[filter_idx].hfe_handle); + &table->eft_entry[filter_idx].efe_handle); } else { rc = efx_mcdi_filter_op_delete(enp, MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE, - &table->hft_entry[filter_idx].hfe_handle); + &table->eft_entry[filter_idx].efe_handle); } /* Free the software table entry */ EFSYS_LOCK(enp->en_eslp, state); - hunt_filter_set_entry_not_busy(table, filter_idx); - hunt_filter_set_entry(table, filter_idx, NULL); + ef10_filter_set_entry_not_busy(table, filter_idx); + ef10_filter_set_entry(table, filter_idx, NULL); EFSYS_UNLOCK(enp->en_eslp, state); EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec); @@ -818,18 +819,18 @@ fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_filter_delete( + __checkReturn efx_rc_t +ef10_filter_delete( __in efx_nic_t *enp, __inout efx_filter_spec_t *spec) { - int rc; - hunt_filter_table_t *table = enp->en_filter.ef_hunt_filter_table; + efx_rc_t rc; + ef10_filter_table_t *table = enp->en_filter.ef_ef10_filter_table; efx_filter_spec_t *saved_spec; unsigned int hash; unsigned int depth; @@ -837,22 +838,23 @@ hunt_filter_delete( int state; boolean_t locked = B_FALSE; - EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); - hash = hunt_filter_hash(spec); + hash = ef10_filter_hash(spec); EFSYS_LOCK(enp->en_eslp, state); locked = B_TRUE; depth = 1; for (;;) { - i = (hash + depth) & (EFX_HUNT_FILTER_TBL_ROWS - 1); - saved_spec = hunt_filter_entry_spec(table, i); - if (saved_spec && hunt_filter_equal(spec, saved_spec) && - hunt_filter_same_dest(spec, saved_spec)) { + i = (hash + depth) & (EFX_EF10_FILTER_TBL_ROWS - 1); + saved_spec = ef10_filter_entry_spec(table, i); + if (saved_spec && ef10_filter_equal(spec, saved_spec) && + ef10_filter_same_dest(spec, saved_spec)) { break; } - if (depth == EFX_HUNT_FILTER_SEARCH_LIMIT) { + if (depth == EF10_FILTER_SEARCH_LIMIT) { rc = ENOENT; goto fail1; } @@ -862,7 +864,7 @@ hunt_filter_delete( EFSYS_UNLOCK(enp->en_eslp, state); locked = B_FALSE; - rc = hunt_filter_delete_internal(enp, i); + rc = ef10_filter_delete_internal(enp, i); if (rc != 0) goto fail2; @@ -872,7 +874,7 @@ fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); if (locked) EFSYS_UNLOCK(enp->en_eslp, state); @@ -880,7 +882,7 @@ fail1: return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_get_parser_disp_info( __in efx_nic_t *enp, __out uint32_t *list, @@ -889,7 +891,7 @@ efx_mcdi_get_parser_disp_info( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_GET_PARSER_DISP_INFO_IN_LEN, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX)]; - int rc; + efx_rc_t rc; uint32_t i; boolean_t support_unknown_ucast = B_FALSE; boolean_t support_unknown_mcast = B_FALSE; @@ -955,18 +957,18 @@ efx_mcdi_get_parser_disp_info( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_filter_supported_filters( + __checkReturn efx_rc_t +ef10_filter_supported_filters( __in efx_nic_t *enp, __out uint32_t *list, __out size_t *length) { - int rc; + efx_rc_t rc; if ((rc = efx_mcdi_get_parser_disp_info(enp, list, length) != 0)) goto fail1; @@ -974,21 +976,21 @@ hunt_filter_supported_filters( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int -hunt_filter_unicast_refresh( +static __checkReturn efx_rc_t +ef10_filter_unicast_refresh( __in efx_nic_t *enp, __in_ecount(6) uint8_t const *addr, __in boolean_t all_unicst, __in efx_filter_flag_t filter_flags) { - hunt_filter_table_t *hftp = enp->en_filter.ef_hunt_filter_table; + ef10_filter_table_t *eftp = enp->en_filter.ef_ef10_filter_table; efx_filter_spec_t spec; - int rc; + efx_rc_t rc; if (all_unicst == B_TRUE) goto use_uc_def; @@ -996,11 +998,11 @@ hunt_filter_unicast_refresh( /* Insert the filter for the local station address */ efx_filter_spec_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, - hftp->hft_default_rxq); + eftp->eft_default_rxq); efx_filter_spec_set_eth_local(&spec, EFX_FILTER_SPEC_VID_UNSPEC, addr); - rc = hunt_filter_add_internal(enp, &spec, B_TRUE, - &hftp->hft_unicst_filter_index); + rc = ef10_filter_add_internal(enp, &spec, B_TRUE, + &eftp->eft_unicst_filter_index); if (rc != 0) { /* * Fall back to an unknown filter. We may be able to subscribe @@ -1008,7 +1010,7 @@ hunt_filter_unicast_refresh( */ goto use_uc_def; } - hftp->hft_unicst_filter_set = B_TRUE; + eftp->eft_unicst_filter_set = B_TRUE; return (0); @@ -1016,32 +1018,32 @@ use_uc_def: /* Insert the unknown unicast filter */ efx_filter_spec_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, - hftp->hft_default_rxq); + eftp->eft_default_rxq); efx_filter_spec_set_uc_def(&spec); - rc = hunt_filter_add_internal(enp, &spec, B_TRUE, - &hftp->hft_unicst_filter_index); + rc = ef10_filter_add_internal(enp, &spec, B_TRUE, + &eftp->eft_unicst_filter_index); if (rc != 0) goto fail1; - hftp->hft_unicst_filter_set = B_TRUE; + eftp->eft_unicst_filter_set = B_TRUE; return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); - if (hftp->hft_unicst_filter_set != B_FALSE) { - (void) hunt_filter_delete_internal(enp, - hftp->hft_unicst_filter_index); + if (eftp->eft_unicst_filter_set != B_FALSE) { + (void) ef10_filter_delete_internal(enp, + eftp->eft_unicst_filter_index); - hftp->hft_unicst_filter_set = B_FALSE; + eftp->eft_unicst_filter_set = B_FALSE; } return (rc); } -static __checkReturn int -hunt_filter_multicast_refresh( +static __checkReturn efx_rc_t +ef10_filter_multicast_refresh( __in efx_nic_t *enp, __in boolean_t mulcst, __in boolean_t all_mulcst, @@ -1050,11 +1052,11 @@ hunt_filter_multicast_refresh( __in int count, __in efx_filter_flag_t filter_flags) { - hunt_filter_table_t *hftp = enp->en_filter.ef_hunt_filter_table; + ef10_filter_table_t *eftp = enp->en_filter.ef_ef10_filter_table; efx_filter_spec_t spec; uint8_t addr[6]; unsigned i; - int rc; + efx_rc_t rc; if (all_mulcst == B_TRUE) goto use_mc_def; @@ -1063,25 +1065,25 @@ hunt_filter_multicast_refresh( count = 0; if (count + (brdcst ? 1 : 0) > - EFX_ARRAY_SIZE(hftp->hft_mulcst_filter_indexes)) { + EFX_ARRAY_SIZE(eftp->eft_mulcst_filter_indexes)) { /* Too many MAC addresses; use unknown multicast filter */ goto use_mc_def; } /* Insert/renew multicast address list filters */ - hftp->hft_mulcst_filter_count = count; - for (i = 0; i < hftp->hft_mulcst_filter_count; i++) { + eftp->eft_mulcst_filter_count = count; + for (i = 0; i < eftp->eft_mulcst_filter_count; i++) { efx_filter_spec_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, - hftp->hft_default_rxq); + eftp->eft_default_rxq); efx_filter_spec_set_eth_local(&spec, EFX_FILTER_SPEC_VID_UNSPEC, &addrs[i * EFX_MAC_ADDR_LEN]); - rc = hunt_filter_add_internal(enp, &spec, B_TRUE, - &hftp->hft_mulcst_filter_indexes[i]); + rc = ef10_filter_add_internal(enp, &spec, B_TRUE, + &eftp->eft_mulcst_filter_indexes[i]); if (rc != 0) { /* Rollback, then use unknown multicast filter */ goto rollback; @@ -1090,18 +1092,18 @@ hunt_filter_multicast_refresh( if (brdcst == B_TRUE) { /* Insert/renew broadcast address filter */ - hftp->hft_mulcst_filter_count++; + eftp->eft_mulcst_filter_count++; efx_filter_spec_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, - hftp->hft_default_rxq); + eftp->eft_default_rxq); EFX_MAC_BROADCAST_ADDR_SET(addr); efx_filter_spec_set_eth_local(&spec, EFX_FILTER_SPEC_VID_UNSPEC, addr); - rc = hunt_filter_add_internal(enp, &spec, B_TRUE, - &hftp->hft_mulcst_filter_indexes[ - hftp->hft_mulcst_filter_count - 1]); + rc = ef10_filter_add_internal(enp, &spec, B_TRUE, + &eftp->eft_mulcst_filter_indexes[ + eftp->eft_mulcst_filter_count - 1]); if (rc != 0) { /* Rollback, then use unknown multicast filter */ goto rollback; @@ -1116,24 +1118,24 @@ rollback: * before inserting the unknown multicast filter. */ while (i--) { - (void) hunt_filter_delete_internal(enp, - hftp->hft_mulcst_filter_indexes[i]); + (void) ef10_filter_delete_internal(enp, + eftp->eft_mulcst_filter_indexes[i]); } - hftp->hft_mulcst_filter_count = 0; + eftp->eft_mulcst_filter_count = 0; use_mc_def: /* Insert the unknown multicast filter */ efx_filter_spec_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, - hftp->hft_default_rxq); + eftp->eft_default_rxq); efx_filter_spec_set_mc_def(&spec); - rc = hunt_filter_add_internal(enp, &spec, B_TRUE, - &hftp->hft_mulcst_filter_indexes[0]); + rc = ef10_filter_add_internal(enp, &spec, B_TRUE, + &eftp->eft_mulcst_filter_indexes[0]); if (rc != 0) goto fail1; - hftp->hft_mulcst_filter_count = 1; + eftp->eft_mulcst_filter_count = 1; /* * FIXME: If brdcst == B_FALSE, add a filter to drop broadcast traffic. @@ -1142,21 +1144,21 @@ use_mc_def: return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t hunt_filter_get_workarounds( __in efx_nic_t *enp) { efx_nic_cfg_t *encp = &enp->en_nic_cfg; uint32_t implemented = 0; uint32_t enabled = 0; - int rc; + efx_rc_t rc; rc = efx_mcdi_get_workarounds(enp, &implemented, &enabled); if (rc == 0) { @@ -1178,7 +1180,7 @@ hunt_filter_get_workarounds( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); @@ -1191,8 +1193,8 @@ fail1: * return ENOTSUP (Note the filters for the specified addresses are * still applied in this case). */ - __checkReturn int -hunt_filter_reconfigure( + __checkReturn efx_rc_t +ef10_filter_reconfigure( __in efx_nic_t *enp, __in_ecount(6) uint8_t const *mac_addr, __in boolean_t all_unicst, @@ -1202,58 +1204,58 @@ hunt_filter_reconfigure( __in_ecount(6*count) uint8_t const *addrs, __in int count) { - hunt_filter_table_t *table = enp->en_filter.ef_hunt_filter_table; + ef10_filter_table_t *table = enp->en_filter.ef_ef10_filter_table; efx_filter_flag_t filter_flags; unsigned i; int all_unicst_rc; int all_mulcst_rc; - int rc; + efx_rc_t rc; - if (table->hft_default_rxq == NULL) { + if (table->eft_default_rxq == NULL) { /* * Filters direct traffic to the default RXQ, and so cannot be * inserted until it is available. Any currently configured * filters must be removed (ignore errors in case the MC * has rebooted, which removes hardware filters). */ - if (table->hft_unicst_filter_set != B_FALSE) { - (void) hunt_filter_delete_internal(enp, - table->hft_unicst_filter_index); - table->hft_unicst_filter_set = B_FALSE; + if (table->eft_unicst_filter_set != B_FALSE) { + (void) ef10_filter_delete_internal(enp, + table->eft_unicst_filter_index); + table->eft_unicst_filter_set = B_FALSE; } - for (i = 0; i < table->hft_mulcst_filter_count; i++) { - (void) hunt_filter_delete_internal(enp, - table->hft_mulcst_filter_indexes[i]); + for (i = 0; i < table->eft_mulcst_filter_count; i++) { + (void) ef10_filter_delete_internal(enp, + table->eft_mulcst_filter_indexes[i]); } - table->hft_mulcst_filter_count = 0; + table->eft_mulcst_filter_count = 0; return (0); } - if (table->hft_using_rss) + if (table->eft_using_rss) filter_flags = EFX_FILTER_FLAG_RX_RSS; else filter_flags = 0; /* Mark old filters which may need to be removed */ - if (table->hft_unicst_filter_set != B_FALSE) { - hunt_filter_set_entry_auto_old(table, - table->hft_unicst_filter_index); + if (table->eft_unicst_filter_set != B_FALSE) { + ef10_filter_set_entry_auto_old(table, + table->eft_unicst_filter_index); } - for (i = 0; i < table->hft_mulcst_filter_count; i++) { - hunt_filter_set_entry_auto_old(table, - table->hft_mulcst_filter_indexes[i]); + for (i = 0; i < table->eft_mulcst_filter_count; i++) { + ef10_filter_set_entry_auto_old(table, + table->eft_mulcst_filter_indexes[i]); } /* Insert or renew unicast filters */ - if ((all_unicst_rc = hunt_filter_unicast_refresh(enp, mac_addr, + if ((all_unicst_rc = ef10_filter_unicast_refresh(enp, mac_addr, all_unicst, filter_flags)) != 0) { if (all_unicst == B_FALSE) { rc = all_unicst_rc; goto fail1; } /* Retry without all_unicast flag */ - rc = hunt_filter_unicast_refresh(enp, mac_addr, + rc = ef10_filter_unicast_refresh(enp, mac_addr, B_FALSE, filter_flags); if (rc != 0) goto fail2; @@ -1272,12 +1274,14 @@ hunt_filter_reconfigure( * filters. This ensures that encp->enc_workaround_bug26807 matches the * firmware state, and that later changes to enable/disable the * workaround will result in this function seeing a reset (FLR). + * + * FIXME: On Medford mulicast chaining should always be on. */ if ((rc = hunt_filter_get_workarounds(enp)) != 0) goto fail3; /* Insert or renew multicast filters */ - if ((all_mulcst_rc = hunt_filter_multicast_refresh(enp, mulcst, + if ((all_mulcst_rc = ef10_filter_multicast_refresh(enp, mulcst, all_mulcst, brdcst, addrs, count, filter_flags)) != 0) { if (all_mulcst == B_FALSE) { @@ -1285,7 +1289,7 @@ hunt_filter_reconfigure( goto fail4; } /* Retry without all_mulcast flag */ - rc = hunt_filter_multicast_refresh(enp, mulcst, + rc = ef10_filter_multicast_refresh(enp, mulcst, B_FALSE, brdcst, addrs, count, filter_flags); if (rc != 0) @@ -1293,9 +1297,9 @@ hunt_filter_reconfigure( } /* Remove old filters which were not renewed */ - for (i = 0; i < EFX_ARRAY_SIZE(table->hft_entry); i++) { - if (hunt_filter_entry_is_auto_old(table, i)) { - (void) hunt_filter_delete_internal(enp, i); + for (i = 0; i < EFX_ARRAY_SIZE(table->eft_entry); i++) { + if (ef10_filter_entry_is_auto_old(table, i)) { + (void) ef10_filter_delete_internal(enp, i); } } @@ -1316,12 +1320,12 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); /* Clear auto old flags */ - for (i = 0; i < EFX_ARRAY_SIZE(table->hft_entry); i++) { - if (hunt_filter_entry_is_auto_old(table, i)) { - hunt_filter_set_entry_not_auto_old(table, i); + for (i = 0; i < EFX_ARRAY_SIZE(table->eft_entry); i++) { + if (ef10_filter_entry_is_auto_old(table, i)) { + ef10_filter_set_entry_not_auto_old(table, i); } } @@ -1329,45 +1333,45 @@ fail1: } void -hunt_filter_get_default_rxq( +ef10_filter_get_default_rxq( __in efx_nic_t *enp, __out efx_rxq_t **erpp, __out boolean_t *using_rss) { - hunt_filter_table_t *table = enp->en_filter.ef_hunt_filter_table; + ef10_filter_table_t *table = enp->en_filter.ef_ef10_filter_table; - *erpp = table->hft_default_rxq; - *using_rss = table->hft_using_rss; + *erpp = table->eft_default_rxq; + *using_rss = table->eft_using_rss; } void -hunt_filter_default_rxq_set( +ef10_filter_default_rxq_set( __in efx_nic_t *enp, __in efx_rxq_t *erp, __in boolean_t using_rss) { - hunt_filter_table_t *table = enp->en_filter.ef_hunt_filter_table; + ef10_filter_table_t *table = enp->en_filter.ef_ef10_filter_table; #if EFSYS_OPT_RX_SCALE EFSYS_ASSERT((using_rss == B_FALSE) || - (enp->en_rss_context != HUNTINGTON_RSS_CONTEXT_INVALID)); - table->hft_using_rss = using_rss; + (enp->en_rss_context != EF10_RSS_CONTEXT_INVALID)); + table->eft_using_rss = using_rss; #else EFSYS_ASSERT(using_rss == B_FALSE); - table->hft_using_rss = B_FALSE; + table->eft_using_rss = B_FALSE; #endif - table->hft_default_rxq = erp; + table->eft_default_rxq = erp; } void -hunt_filter_default_rxq_clear( +ef10_filter_default_rxq_clear( __in efx_nic_t *enp) { - hunt_filter_table_t *table = enp->en_filter.ef_hunt_filter_table; + ef10_filter_table_t *table = enp->en_filter.ef_ef10_filter_table; - table->hft_default_rxq = NULL; - table->hft_using_rss = B_FALSE; + table->eft_default_rxq = NULL; + table->eft_using_rss = B_FALSE; } diff --git a/sys/dev/sfxge/common/hunt_impl.h b/sys/dev/sfxge/common/hunt_impl.h index 0aa4ae5..f8c3b5e 100644 --- a/sys/dev/sfxge/common/hunt_impl.h +++ b/sys/dev/sfxge/common/hunt_impl.h @@ -42,29 +42,34 @@ extern "C" { #endif -#define HUNTINGTON_NVRAM_CHUNK 0x80 +/* + * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could + * possibly be increased, or the write size reported by newer firmware used + * instead. + */ +#define EF10_NVRAM_CHUNK 0x80 /* Alignment requirement for value written to RX WPTR: * the WPTR must be aligned to an 8 descriptor boundary */ -#define HUNTINGTON_RX_WPTR_ALIGN 8 +#define EF10_RX_WPTR_ALIGN 8 /* Invalid RSS context handle */ -#define HUNTINGTON_RSS_CONTEXT_INVALID (0xffffffff) +#define EF10_RSS_CONTEXT_INVALID (0xffffffff) /* EV */ - __checkReturn int -hunt_ev_init( + __checkReturn efx_rc_t +ef10_ev_init( __in efx_nic_t *enp); void -hunt_ev_fini( +ef10_ev_fini( __in efx_nic_t *enp); - __checkReturn int -hunt_ev_qcreate( + __checkReturn efx_rc_t +ef10_ev_qcreate( __in efx_nic_t *enp, __in unsigned int index, __in efsys_mem_t *esmp, @@ -73,144 +78,159 @@ hunt_ev_qcreate( __in efx_evq_t *eep); void -hunt_ev_qdestroy( +ef10_ev_qdestroy( __in efx_evq_t *eep); - __checkReturn int -hunt_ev_qprime( + __checkReturn efx_rc_t +ef10_ev_qprime( __in efx_evq_t *eep, __in unsigned int count); void -hunt_ev_qpost( +ef10_ev_qpost( __in efx_evq_t *eep, __in uint16_t data); - __checkReturn int -hunt_ev_qmoderate( + __checkReturn efx_rc_t +ef10_ev_qmoderate( __in efx_evq_t *eep, __in unsigned int us); #if EFSYS_OPT_QSTATS void -hunt_ev_qstats_update( +ef10_ev_qstats_update( __in efx_evq_t *eep, __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); #endif /* EFSYS_OPT_QSTATS */ void -hunt_ev_rxlabel_init( +ef10_ev_rxlabel_init( __in efx_evq_t *eep, __in efx_rxq_t *erp, __in unsigned int label); void -hunt_ev_rxlabel_fini( +ef10_ev_rxlabel_fini( __in efx_evq_t *eep, __in unsigned int label); /* INTR */ - __checkReturn int -hunt_intr_init( + __checkReturn efx_rc_t +ef10_intr_init( __in efx_nic_t *enp, __in efx_intr_type_t type, __in efsys_mem_t *esmp); void -hunt_intr_enable( +ef10_intr_enable( __in efx_nic_t *enp); void -hunt_intr_disable( +ef10_intr_disable( __in efx_nic_t *enp); void -hunt_intr_disable_unlocked( +ef10_intr_disable_unlocked( __in efx_nic_t *enp); - __checkReturn int -hunt_intr_trigger( + __checkReturn efx_rc_t +ef10_intr_trigger( __in efx_nic_t *enp, __in unsigned int level); void -hunt_intr_fini( +ef10_intr_status_line( + __in efx_nic_t *enp, + __out boolean_t *fatalp, + __out uint32_t *qmaskp); + + void +ef10_intr_status_message( + __in efx_nic_t *enp, + __in unsigned int message, + __out boolean_t *fatalp); + + void +ef10_intr_fatal( + __in efx_nic_t *enp); + void +ef10_intr_fini( __in efx_nic_t *enp); /* NIC */ -extern __checkReturn int -hunt_nic_probe( +extern __checkReturn efx_rc_t +ef10_nic_probe( __in efx_nic_t *enp); -extern __checkReturn int -hunt_nic_set_drv_limits( +extern __checkReturn efx_rc_t +ef10_nic_set_drv_limits( __inout efx_nic_t *enp, __in efx_drv_limits_t *edlp); -extern __checkReturn int -hunt_nic_get_vi_pool( +extern __checkReturn efx_rc_t +ef10_nic_get_vi_pool( __in efx_nic_t *enp, __out uint32_t *vi_countp); -extern __checkReturn int -hunt_nic_get_bar_region( +extern __checkReturn efx_rc_t +ef10_nic_get_bar_region( __in efx_nic_t *enp, __in efx_nic_region_t region, __out uint32_t *offsetp, __out size_t *sizep); -extern __checkReturn int -hunt_nic_reset( +extern __checkReturn efx_rc_t +ef10_nic_reset( __in efx_nic_t *enp); -extern __checkReturn int -hunt_nic_init( +extern __checkReturn efx_rc_t +ef10_nic_init( __in efx_nic_t *enp); #if EFSYS_OPT_DIAG -extern __checkReturn int -hunt_nic_register_test( +extern __checkReturn efx_rc_t +ef10_nic_register_test( __in efx_nic_t *enp); #endif /* EFSYS_OPT_DIAG */ extern void -hunt_nic_fini( +ef10_nic_fini( __in efx_nic_t *enp); extern void -hunt_nic_unprobe( +ef10_nic_unprobe( __in efx_nic_t *enp); /* MAC */ -extern __checkReturn int +extern __checkReturn efx_rc_t hunt_mac_poll( __in efx_nic_t *enp, __out efx_link_mode_t *link_modep); -extern __checkReturn int +extern __checkReturn efx_rc_t hunt_mac_up( __in efx_nic_t *enp, __out boolean_t *mac_upp); -extern __checkReturn int +extern __checkReturn efx_rc_t hunt_mac_addr_set( __in efx_nic_t *enp); -extern __checkReturn int +extern __checkReturn efx_rc_t hunt_mac_reconfigure( __in efx_nic_t *enp); -extern __checkReturn int +extern __checkReturn efx_rc_t hunt_mac_multicast_list_set( __in efx_nic_t *enp); -extern __checkReturn int +extern __checkReturn efx_rc_t hunt_mac_filter_default_rxq_set( __in efx_nic_t *enp, __in efx_rxq_t *erp, @@ -222,7 +242,7 @@ hunt_mac_filter_default_rxq_clear( #if EFSYS_OPT_LOOPBACK -extern __checkReturn int +extern __checkReturn efx_rc_t hunt_mac_loopback_set( __in efx_nic_t *enp, __in efx_link_mode_t link_mode, @@ -232,12 +252,12 @@ hunt_mac_loopback_set( #if EFSYS_OPT_MAC_STATS -extern __checkReturn int +extern __checkReturn efx_rc_t hunt_mac_stats_update( __in efx_nic_t *enp, __in efsys_mem_t *esmp, - __out_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, - __out_opt uint32_t *generationp); + __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, + __inout_opt uint32_t *generationp); #endif /* EFSYS_OPT_MAC_STATS */ @@ -246,17 +266,17 @@ hunt_mac_stats_update( #if EFSYS_OPT_MCDI -extern __checkReturn int -hunt_mcdi_init( +extern __checkReturn efx_rc_t +ef10_mcdi_init( __in efx_nic_t *enp, __in const efx_mcdi_transport_t *mtp); extern void -hunt_mcdi_fini( +ef10_mcdi_fini( __in efx_nic_t *enp); extern void -hunt_mcdi_request_copyin( +ef10_mcdi_request_copyin( __in efx_nic_t *enp, __in efx_mcdi_req_t *emrp, __in unsigned int seq, @@ -264,26 +284,29 @@ hunt_mcdi_request_copyin( __in boolean_t new_epoch); extern __checkReturn boolean_t -hunt_mcdi_request_poll( +ef10_mcdi_poll_response( __in efx_nic_t *enp); extern void -hunt_mcdi_request_copyout( +ef10_mcdi_read_response( + __in efx_nic_t *enp, + __out_bcount(length) void *bufferp, + __in size_t offset, + __in size_t length); + +extern void +ef10_mcdi_request_copyout( __in efx_nic_t *enp, __in efx_mcdi_req_t *emrp); -extern int -hunt_mcdi_poll_reboot( +extern efx_rc_t +ef10_mcdi_poll_reboot( __in efx_nic_t *enp); -extern __checkReturn int -hunt_mcdi_fw_update_supported( - __in efx_nic_t *enp, - __out boolean_t *supportedp); - -extern __checkReturn int -hunt_mcdi_macaddr_change_supported( +extern __checkReturn efx_rc_t +ef10_mcdi_feature_supported( __in efx_nic_t *enp, + __in efx_mcdi_feature_id_t id, __out boolean_t *supportedp); #endif /* EFSYS_OPT_MCDI */ @@ -292,17 +315,17 @@ hunt_mcdi_macaddr_change_supported( #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD -extern __checkReturn int -hunt_nvram_buf_read_tlv( +extern __checkReturn efx_rc_t +ef10_nvram_buf_read_tlv( __in efx_nic_t *enp, - __in_bcount(partn_size) caddr_t partn_data, - __in size_t partn_size, + __in_bcount(max_seg_size) caddr_t seg_data, + __in size_t max_seg_size, __in uint32_t tag, __deref_out_bcount_opt(*sizep) caddr_t *datap, __out size_t *sizep); -extern __checkReturn int -hunt_nvram_buf_write_tlv( +extern __checkReturn efx_rc_t +ef10_nvram_buf_write_tlv( __inout_bcount(partn_size) caddr_t partn_data, __in size_t partn_size, __in uint32_t tag, @@ -310,60 +333,69 @@ hunt_nvram_buf_write_tlv( __in size_t tag_size, __out size_t *total_lengthp); -extern __checkReturn int -hunt_nvram_partn_read_tlv( +extern __checkReturn efx_rc_t +ef10_nvram_partn_read_tlv( __in efx_nic_t *enp, __in uint32_t partn, __in uint32_t tag, __deref_out_bcount_opt(*sizep) caddr_t *datap, __out size_t *sizep); -extern __checkReturn int -hunt_nvram_partn_write_tlv( +extern __checkReturn efx_rc_t +ef10_nvram_partn_write_tlv( __in efx_nic_t *enp, __in uint32_t partn, __in uint32_t tag, __in_bcount(size) caddr_t data, __in size_t size); -extern __checkReturn int -hunt_nvram_partn_size( +extern __checkReturn efx_rc_t +ef10_nvram_partn_write_segment_tlv( + __in efx_nic_t *enp, + __in uint32_t partn, + __in uint32_t tag, + __in_bcount(size) caddr_t data, + __in size_t size, + __in boolean_t all_segments); + +extern __checkReturn efx_rc_t +ef10_nvram_partn_size( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __out size_t *sizep); -extern __checkReturn int -hunt_nvram_partn_lock( +extern __checkReturn efx_rc_t +ef10_nvram_partn_lock( __in efx_nic_t *enp, - __in unsigned int partn); + __in uint32_t partn); -extern __checkReturn int -hunt_nvram_partn_read( +extern __checkReturn efx_rc_t +ef10_nvram_partn_read( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __in unsigned int offset, __out_bcount(size) caddr_t data, __in size_t size); -extern __checkReturn int -hunt_nvram_partn_erase( +extern __checkReturn efx_rc_t +ef10_nvram_partn_erase( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __in unsigned int offset, __in size_t size); -extern __checkReturn int -hunt_nvram_partn_write( +extern __checkReturn efx_rc_t +ef10_nvram_partn_write( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __in unsigned int offset, __out_bcount(size) caddr_t data, __in size_t size); extern void -hunt_nvram_partn_unlock( +ef10_nvram_partn_unlock( __in efx_nic_t *enp, - __in unsigned int partn); + __in uint32_t partn); #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ @@ -371,46 +403,46 @@ hunt_nvram_partn_unlock( #if EFSYS_OPT_DIAG -extern __checkReturn int -hunt_nvram_test( +extern __checkReturn efx_rc_t +ef10_nvram_test( __in efx_nic_t *enp); #endif /* EFSYS_OPT_DIAG */ -extern __checkReturn int -hunt_nvram_size( +extern __checkReturn efx_rc_t +ef10_nvram_size( __in efx_nic_t *enp, __in efx_nvram_type_t type, __out size_t *sizep); -extern __checkReturn int -hunt_nvram_get_version( +extern __checkReturn efx_rc_t +ef10_nvram_get_version( __in efx_nic_t *enp, __in efx_nvram_type_t type, __out uint32_t *subtypep, __out_ecount(4) uint16_t version[4]); -extern __checkReturn int -hunt_nvram_rw_start( +extern __checkReturn efx_rc_t +ef10_nvram_rw_start( __in efx_nic_t *enp, __in efx_nvram_type_t type, __out size_t *pref_chunkp); -extern __checkReturn int -hunt_nvram_read_chunk( +extern __checkReturn efx_rc_t +ef10_nvram_read_chunk( __in efx_nic_t *enp, __in efx_nvram_type_t type, __in unsigned int offset, __out_bcount(size) caddr_t data, __in size_t size); -extern __checkReturn int -hunt_nvram_erase( +extern __checkReturn efx_rc_t +ef10_nvram_erase( __in efx_nic_t *enp, __in efx_nvram_type_t type); -extern __checkReturn int -hunt_nvram_write_chunk( +extern __checkReturn efx_rc_t +ef10_nvram_write_chunk( __in efx_nic_t *enp, __in efx_nvram_type_t type, __in unsigned int offset, @@ -418,22 +450,28 @@ hunt_nvram_write_chunk( __in size_t size); extern void -hunt_nvram_rw_finish( +ef10_nvram_rw_finish( __in efx_nic_t *enp, __in efx_nvram_type_t type); -extern __checkReturn int -hunt_nvram_partn_set_version( +extern __checkReturn efx_rc_t +ef10_nvram_partn_set_version( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __in_ecount(4) uint16_t version[4]); -extern __checkReturn int -hunt_nvram_set_version( +extern __checkReturn efx_rc_t +ef10_nvram_set_version( __in efx_nic_t *enp, __in efx_nvram_type_t type, __in_ecount(4) uint16_t version[4]); +extern __checkReturn efx_rc_t +ef10_nvram_type_to_partn( + __in efx_nic_t *enp, + __in efx_nvram_type_t type, + __out uint32_t *partnp); + #endif /* EFSYS_OPT_NVRAM */ @@ -456,36 +494,36 @@ hunt_phy_link_ev( __in efx_qword_t *eqp, __out efx_link_mode_t *link_modep); -extern __checkReturn int +extern __checkReturn efx_rc_t hunt_phy_get_link( __in efx_nic_t *enp, __out hunt_link_state_t *hlsp); -extern __checkReturn int +extern __checkReturn efx_rc_t hunt_phy_power( __in efx_nic_t *enp, __in boolean_t on); -extern __checkReturn int +extern __checkReturn efx_rc_t hunt_phy_reconfigure( __in efx_nic_t *enp); -extern __checkReturn int +extern __checkReturn efx_rc_t hunt_phy_verify( __in efx_nic_t *enp); -extern __checkReturn int +extern __checkReturn efx_rc_t hunt_phy_oui_get( __in efx_nic_t *enp, __out uint32_t *ouip); #if EFSYS_OPT_PHY_STATS -extern __checkReturn int +extern __checkReturn efx_rc_t hunt_phy_stats_update( __in efx_nic_t *enp, __in efsys_mem_t *esmp, - __out_ecount(EFX_PHY_NSTATS) uint32_t *stat); + __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); #endif /* EFSYS_OPT_PHY_STATS */ @@ -500,14 +538,14 @@ hunt_phy_prop_name( #endif /* EFSYS_OPT_NAMES */ -extern __checkReturn int +extern __checkReturn efx_rc_t hunt_phy_prop_get( __in efx_nic_t *enp, __in unsigned int id, __in uint32_t flags, __out uint32_t *valp); -extern __checkReturn int +extern __checkReturn efx_rc_t hunt_phy_prop_set( __in efx_nic_t *enp, __in unsigned int id, @@ -517,16 +555,16 @@ hunt_phy_prop_set( #if EFSYS_OPT_BIST -extern __checkReturn int +extern __checkReturn efx_rc_t hunt_bist_enable_offline( __in efx_nic_t *enp); -extern __checkReturn int +extern __checkReturn efx_rc_t hunt_bist_start( __in efx_nic_t *enp, __in efx_bist_type_t type); -extern __checkReturn int +extern __checkReturn efx_rc_t hunt_bist_poll( __in efx_nic_t *enp, __in efx_bist_type_t type, @@ -549,8 +587,8 @@ hunt_bist_stop( #if EFSYS_OPT_DIAG -extern __checkReturn int -hunt_sram_test( +extern __checkReturn efx_rc_t +ef10_sram_test( __in efx_nic_t *enp, __in efx_sram_pattern_fn_t func); @@ -559,16 +597,16 @@ hunt_sram_test( /* TX */ -extern __checkReturn int -hunt_tx_init( +extern __checkReturn efx_rc_t +ef10_tx_init( __in efx_nic_t *enp); extern void -hunt_tx_fini( +ef10_tx_fini( __in efx_nic_t *enp); -extern __checkReturn int -hunt_tx_qcreate( +extern __checkReturn efx_rc_t +ef10_tx_qcreate( __in efx_nic_t *enp, __in unsigned int index, __in unsigned int label, @@ -581,11 +619,11 @@ hunt_tx_qcreate( __out unsigned int *addedp); extern void -hunt_tx_qdestroy( +ef10_tx_qdestroy( __in efx_txq_t *etp); -extern __checkReturn int -hunt_tx_qpost( +extern __checkReturn efx_rc_t +ef10_tx_qpost( __in efx_txq_t *etp, __in_ecount(n) efx_buffer_t *eb, __in unsigned int n, @@ -593,48 +631,48 @@ hunt_tx_qpost( __inout unsigned int *addedp); extern void -hunt_tx_qpush( +ef10_tx_qpush( __in efx_txq_t *etp, __in unsigned int added, __in unsigned int pushed); -extern __checkReturn int -hunt_tx_qpace( +extern __checkReturn efx_rc_t +ef10_tx_qpace( __in efx_txq_t *etp, __in unsigned int ns); -extern __checkReturn int -hunt_tx_qflush( +extern __checkReturn efx_rc_t +ef10_tx_qflush( __in efx_txq_t *etp); extern void -hunt_tx_qenable( +ef10_tx_qenable( __in efx_txq_t *etp); -extern __checkReturn int -hunt_tx_qpio_enable( +extern __checkReturn efx_rc_t +ef10_tx_qpio_enable( __in efx_txq_t *etp); extern void -hunt_tx_qpio_disable( +ef10_tx_qpio_disable( __in efx_txq_t *etp); -extern __checkReturn int -hunt_tx_qpio_write( +extern __checkReturn efx_rc_t +ef10_tx_qpio_write( __in efx_txq_t *etp, __in_ecount(buf_length) uint8_t *buffer, __in size_t buf_length, __in size_t pio_buf_offset); -extern __checkReturn int -hunt_tx_qpio_post( +extern __checkReturn efx_rc_t +ef10_tx_qpio_post( __in efx_txq_t *etp, __in size_t pkt_length, __in unsigned int completed, __inout unsigned int *addedp); -extern __checkReturn int -hunt_tx_qdesc_post( +extern __checkReturn efx_rc_t +ef10_tx_qdesc_post( __in efx_txq_t *etp, __in_ecount(n) efx_desc_t *ed, __in unsigned int n, @@ -642,7 +680,7 @@ hunt_tx_qdesc_post( __inout unsigned int *addedp); extern void -hunt_tx_qdesc_dma_create( +ef10_tx_qdesc_dma_create( __in efx_txq_t *etp, __in efsys_dma_addr_t addr, __in size_t size, @@ -658,7 +696,7 @@ hunt_tx_qdesc_tso_create( __out efx_desc_t *edp); extern void -hunt_tx_qdesc_vlantci_create( +ef10_tx_qdesc_vlantci_create( __in efx_txq_t *etp, __in uint16_t vlan_tci, __out efx_desc_t *edp); @@ -667,7 +705,7 @@ hunt_tx_qdesc_vlantci_create( #if EFSYS_OPT_QSTATS extern void -hunt_tx_qstats_update( +ef10_tx_qstats_update( __in efx_txq_t *etp, __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); @@ -695,7 +733,7 @@ hunt_tx_qstats_update( #define HUNT_MIN_PIO_ALLOC_SIZE (HUNT_PIOBUF_SIZE / 32) -#define HUNT_LEGACY_PF_PRIVILEGE_MASK \ +#define HUNT_LEGACY_PF_PRIVILEGE_MASK \ (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \ MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \ MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD | \ @@ -708,14 +746,14 @@ hunt_tx_qstats_update( MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST | \ MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS) -#define HUNT_LEGACY_VF_PRIVILEGE_MASK 0 +#define HUNT_LEGACY_VF_PRIVILEGE_MASK 0 typedef uint32_t efx_piobuf_handle_t; #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t) -1) -extern __checkReturn int -hunt_nic_pio_alloc( +extern __checkReturn efx_rc_t +ef10_nic_pio_alloc( __inout efx_nic_t *enp, __out uint32_t *bufnump, __out efx_piobuf_handle_t *handlep, @@ -723,20 +761,20 @@ hunt_nic_pio_alloc( __out uint32_t *offsetp, __out size_t *sizep); -extern __checkReturn int -hunt_nic_pio_free( +extern __checkReturn efx_rc_t +ef10_nic_pio_free( __inout efx_nic_t *enp, __in uint32_t bufnum, __in uint32_t blknum); -extern __checkReturn int -hunt_nic_pio_link( +extern __checkReturn efx_rc_t +ef10_nic_pio_link( __inout efx_nic_t *enp, __in uint32_t vi_index, __in efx_piobuf_handle_t handle); -extern __checkReturn int -hunt_nic_pio_unlink( +extern __checkReturn efx_rc_t +ef10_nic_pio_unlink( __inout efx_nic_t *enp, __in uint32_t vi_index); @@ -745,63 +783,63 @@ hunt_nic_pio_unlink( #if EFSYS_OPT_VPD -extern __checkReturn int -hunt_vpd_init( +extern __checkReturn efx_rc_t +ef10_vpd_init( __in efx_nic_t *enp); -extern __checkReturn int -hunt_vpd_size( +extern __checkReturn efx_rc_t +ef10_vpd_size( __in efx_nic_t *enp, __out size_t *sizep); -extern __checkReturn int -hunt_vpd_read( +extern __checkReturn efx_rc_t +ef10_vpd_read( __in efx_nic_t *enp, __out_bcount(size) caddr_t data, __in size_t size); -extern __checkReturn int -hunt_vpd_verify( +extern __checkReturn efx_rc_t +ef10_vpd_verify( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size); -extern __checkReturn int -hunt_vpd_reinit( +extern __checkReturn efx_rc_t +ef10_vpd_reinit( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size); -extern __checkReturn int -hunt_vpd_get( +extern __checkReturn efx_rc_t +ef10_vpd_get( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size, __inout efx_vpd_value_t *evvp); -extern __checkReturn int -hunt_vpd_set( +extern __checkReturn efx_rc_t +ef10_vpd_set( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size, __in efx_vpd_value_t *evvp); -extern __checkReturn int -hunt_vpd_next( +extern __checkReturn efx_rc_t +ef10_vpd_next( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size, __out efx_vpd_value_t *evvp, __inout unsigned int *contp); -extern __checkReturn int -hunt_vpd_write( +extern __checkReturn efx_rc_t +ef10_vpd_write( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size); extern void -hunt_vpd_fini( +ef10_vpd_fini( __in efx_nic_t *enp); #endif /* EFSYS_OPT_VPD */ @@ -809,21 +847,13 @@ hunt_vpd_fini( /* RX */ -extern __checkReturn int -hunt_rx_init( +extern __checkReturn efx_rc_t +ef10_rx_init( __in efx_nic_t *enp); -#if EFSYS_OPT_RX_HDR_SPLIT -extern __checkReturn int -hunt_rx_hdr_split_enable( - __in efx_nic_t *enp, - __in unsigned int hdr_buf_size, - __in unsigned int pld_buf_size); -#endif /* EFSYS_OPT_RX_HDR_SPLIT */ - #if EFSYS_OPT_RX_SCATTER -extern __checkReturn int -hunt_rx_scatter_enable( +extern __checkReturn efx_rc_t +ef10_rx_scatter_enable( __in efx_nic_t *enp, __in unsigned int buf_size); #endif /* EFSYS_OPT_RX_SCATTER */ @@ -831,29 +861,41 @@ hunt_rx_scatter_enable( #if EFSYS_OPT_RX_SCALE -extern __checkReturn int -hunt_rx_scale_mode_set( +extern __checkReturn efx_rc_t +ef10_rx_scale_mode_set( __in efx_nic_t *enp, __in efx_rx_hash_alg_t alg, __in efx_rx_hash_type_t type, __in boolean_t insert); -extern __checkReturn int -hunt_rx_scale_key_set( +extern __checkReturn efx_rc_t +ef10_rx_scale_key_set( __in efx_nic_t *enp, __in_ecount(n) uint8_t *key, __in size_t n); -extern __checkReturn int -hunt_rx_scale_tbl_set( +extern __checkReturn efx_rc_t +ef10_rx_scale_tbl_set( __in efx_nic_t *enp, __in_ecount(n) unsigned int *table, __in size_t n); +extern __checkReturn uint32_t +ef10_rx_prefix_hash( + __in efx_nic_t *enp, + __in efx_rx_hash_alg_t func, + __in uint8_t *buffer); + +extern __checkReturn efx_rc_t +ef10_rx_prefix_pktlen( + __in efx_nic_t *enp, + __in uint8_t *buffer, + __out uint16_t *lengthp); + #endif /* EFSYS_OPT_RX_SCALE */ extern void -hunt_rx_qpost( +ef10_rx_qpost( __in efx_rxq_t *erp, __in_ecount(n) efsys_dma_addr_t *addrp, __in size_t size, @@ -862,21 +904,21 @@ hunt_rx_qpost( __in unsigned int added); extern void -hunt_rx_qpush( +ef10_rx_qpush( __in efx_rxq_t *erp, __in unsigned int added, __inout unsigned int *pushedp); -extern __checkReturn int -hunt_rx_qflush( +extern __checkReturn efx_rc_t +ef10_rx_qflush( __in efx_rxq_t *erp); extern void -hunt_rx_qenable( +ef10_rx_qenable( __in efx_rxq_t *erp); -extern __checkReturn int -hunt_rx_qcreate( +extern __checkReturn efx_rc_t +ef10_rx_qcreate( __in efx_nic_t *enp, __in unsigned int index, __in unsigned int label, @@ -888,80 +930,84 @@ hunt_rx_qcreate( __in efx_rxq_t *erp); extern void -hunt_rx_qdestroy( +ef10_rx_qdestroy( __in efx_rxq_t *erp); extern void -hunt_rx_fini( +ef10_rx_fini( __in efx_nic_t *enp); #if EFSYS_OPT_FILTER -typedef struct hunt_filter_handle_s { - uint32_t hfh_lo; - uint32_t hfh_hi; -} hunt_filter_handle_t; +typedef struct ef10_filter_handle_s { + uint32_t efh_lo; + uint32_t efh_hi; +} ef10_filter_handle_t; -typedef struct hunt_filter_entry_s { - uintptr_t hfe_spec; /* pointer to filter spec plus busy bit */ - hunt_filter_handle_t hfe_handle; -} hunt_filter_entry_t; +typedef struct ef10_filter_entry_s { + uintptr_t efe_spec; /* pointer to filter spec plus busy bit */ + ef10_filter_handle_t efe_handle; +} ef10_filter_entry_t; /* * BUSY flag indicates that an update is in progress. * AUTO_OLD flag is used to mark and sweep MAC packet filters. */ -#define EFX_HUNT_FILTER_FLAG_BUSY 1U -#define EFX_HUNT_FILTER_FLAG_AUTO_OLD 2U -#define EFX_HUNT_FILTER_FLAGS 3U +#define EFX_EF10_FILTER_FLAG_BUSY 1U +#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U +#define EFX_EF10_FILTER_FLAGS 3U -#define EFX_HUNT_FILTER_TBL_ROWS 8192 +/* + * Size of the hash table used by the driver. Doesn't need to be the + * same size as the hardware's table. + */ +#define EFX_EF10_FILTER_TBL_ROWS 8192 /* Allow for the broadcast address to be added to the multicast list */ -#define EFX_HUNT_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1) - -typedef struct hunt_filter_table_s { - hunt_filter_entry_t hft_entry[EFX_HUNT_FILTER_TBL_ROWS]; - efx_rxq_t * hft_default_rxq; - boolean_t hft_using_rss; - uint32_t hft_unicst_filter_index; - boolean_t hft_unicst_filter_set; - uint32_t hft_mulcst_filter_indexes[ - EFX_HUNT_FILTER_MULTICAST_FILTERS_MAX]; - uint32_t hft_mulcst_filter_count; -} hunt_filter_table_t; - - __checkReturn int -hunt_filter_init( +#define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1) + +typedef struct ef10_filter_table_s { + ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS]; + efx_rxq_t * eft_default_rxq; + boolean_t eft_using_rss; + uint32_t eft_unicst_filter_index; + boolean_t eft_unicst_filter_set; + uint32_t eft_mulcst_filter_indexes[ + EFX_EF10_FILTER_MULTICAST_FILTERS_MAX]; + uint32_t eft_mulcst_filter_count; +} ef10_filter_table_t; + + __checkReturn efx_rc_t +ef10_filter_init( __in efx_nic_t *enp); void -hunt_filter_fini( +ef10_filter_fini( __in efx_nic_t *enp); - __checkReturn int -hunt_filter_restore( + __checkReturn efx_rc_t +ef10_filter_restore( __in efx_nic_t *enp); - __checkReturn int -hunt_filter_add( + __checkReturn efx_rc_t +ef10_filter_add( __in efx_nic_t *enp, __inout efx_filter_spec_t *spec, __in boolean_t may_replace); - __checkReturn int -hunt_filter_delete( + __checkReturn efx_rc_t +ef10_filter_delete( __in efx_nic_t *enp, __inout efx_filter_spec_t *spec); -extern __checkReturn int -hunt_filter_supported_filters( +extern __checkReturn efx_rc_t +ef10_filter_supported_filters( __in efx_nic_t *enp, __out uint32_t *list, __out size_t *length); -extern __checkReturn int -hunt_filter_reconfigure( +extern __checkReturn efx_rc_t +ef10_filter_reconfigure( __in efx_nic_t *enp, __in_ecount(6) uint8_t const *mac_addr, __in boolean_t all_unicst, @@ -972,51 +1018,31 @@ hunt_filter_reconfigure( __in int count); extern void -hunt_filter_get_default_rxq( +ef10_filter_get_default_rxq( __in efx_nic_t *enp, __out efx_rxq_t **erpp, __out boolean_t *using_rss); extern void -hunt_filter_default_rxq_set( +ef10_filter_default_rxq_set( __in efx_nic_t *enp, __in efx_rxq_t *erp, __in boolean_t using_rss); extern void -hunt_filter_default_rxq_clear( +ef10_filter_default_rxq_clear( __in efx_nic_t *enp); #endif /* EFSYS_OPT_FILTER */ -extern __checkReturn int -hunt_pktfilter_set( - __in efx_nic_t *enp, - __in boolean_t unicst, - __in boolean_t brdcst); - -#if EFSYS_OPT_MCAST_FILTER_LIST - -extern __checkReturn int -hunt_pktfilter_mcast_set( - __in efx_nic_t *enp, - __in uint8_t const *addrs, - __in int count); - -#endif /* EFSYS_OPT_MCAST_FILTER_LIST */ - -extern __checkReturn int -hunt_pktfilter_mcast_all( - __in efx_nic_t *enp); - -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mcdi_get_function_info( __in efx_nic_t *enp, __out uint32_t *pfp, __out_opt uint32_t *vfp); -extern __checkReturn int +extern __checkReturn efx_rc_t efx_mcdi_privilege_mask( __in efx_nic_t *enp, __in uint32_t pf, diff --git a/sys/dev/sfxge/common/hunt_intr.c b/sys/dev/sfxge/common/hunt_intr.c index b68135c..7a4293c 100644 --- a/sys/dev/sfxge/common/hunt_intr.c +++ b/sys/dev/sfxge/common/hunt_intr.c @@ -31,15 +31,14 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" #include "efx_impl.h" #if EFSYS_OPT_HUNTINGTON - __checkReturn int -hunt_intr_init( + __checkReturn efx_rc_t +ef10_intr_init( __in efx_nic_t *enp, __in efx_intr_type_t type, __in efsys_mem_t *esmp) @@ -50,7 +49,7 @@ hunt_intr_init( void -hunt_intr_enable( +ef10_intr_enable( __in efx_nic_t *enp) { _NOTE(ARGUNUSED(enp)) @@ -58,7 +57,7 @@ hunt_intr_enable( void -hunt_intr_disable( +ef10_intr_disable( __in efx_nic_t *enp) { _NOTE(ARGUNUSED(enp)) @@ -66,14 +65,14 @@ hunt_intr_disable( void -hunt_intr_disable_unlocked( +ef10_intr_disable_unlocked( __in efx_nic_t *enp) { _NOTE(ARGUNUSED(enp)) } -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_trigger_interrupt( __in efx_nic_t *enp, __in unsigned int level) @@ -81,9 +80,10 @@ efx_mcdi_trigger_interrupt( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_TRIGGER_INTERRUPT_IN_LEN, MC_CMD_TRIGGER_INTERRUPT_OUT_LEN)]; - int rc; + efx_rc_t rc; - EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); if (level >= enp->en_nic_cfg.enc_intr_limit) { rc = EINVAL; @@ -112,21 +112,24 @@ fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_intr_trigger( + __checkReturn efx_rc_t +ef10_intr_trigger( __in efx_nic_t *enp, __in unsigned int level) { efx_nic_cfg_t *encp = &(enp->en_nic_cfg); - int rc; + efx_rc_t rc; if (encp->enc_bug41750_workaround) { - /* bug 41750: Test interrupts don't work on Greenport */ + /* + * bug 41750: Test interrupts don't work on Greenport + * bug 50084: Test interrupts don't work on VFs + */ rc = ENOTSUP; goto fail1; } @@ -139,14 +142,56 @@ hunt_intr_trigger( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } + void +ef10_intr_status_line( + __in efx_nic_t *enp, + __out boolean_t *fatalp, + __out uint32_t *qmaskp) +{ + efx_dword_t dword; + + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); + + /* Read the queue mask and implicitly acknowledge the interrupt. */ + EFX_BAR_READD(enp, ER_DZ_BIU_INT_ISR_REG, &dword, B_FALSE); + *qmaskp = EFX_DWORD_FIELD(dword, EFX_DWORD_0); + + EFSYS_PROBE1(qmask, uint32_t, *qmaskp); + + *fatalp = B_FALSE; +} + + void +ef10_intr_status_message( + __in efx_nic_t *enp, + __in unsigned int message, + __out boolean_t *fatalp) +{ + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); + + _NOTE(ARGUNUSED(enp, message)) + + /* EF10 fatal errors are reported via events */ + *fatalp = B_FALSE; +} + + void +ef10_intr_fatal( + __in efx_nic_t *enp) +{ + /* EF10 fatal errors are reported via events */ + _NOTE(ARGUNUSED(enp)) +} void -hunt_intr_fini( +ef10_intr_fini( __in efx_nic_t *enp) { _NOTE(ARGUNUSED(enp)) diff --git a/sys/dev/sfxge/common/hunt_mac.c b/sys/dev/sfxge/common/hunt_mac.c index be9eb37..358c4d9 100644 --- a/sys/dev/sfxge/common/hunt_mac.c +++ b/sys/dev/sfxge/common/hunt_mac.c @@ -31,14 +31,13 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" #include "efx_impl.h" #if EFSYS_OPT_HUNTINGTON - __checkReturn int + __checkReturn efx_rc_t hunt_mac_poll( __in efx_nic_t *enp, __out efx_link_mode_t *link_modep) @@ -50,7 +49,7 @@ hunt_mac_poll( efx_port_t *epp = &(enp->en_port); hunt_link_state_t hls; - int rc; + efx_rc_t rc; if ((rc = hunt_phy_get_link(enp, &hls)) != 0) goto fail1; @@ -63,14 +62,14 @@ hunt_mac_poll( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); *link_modep = EFX_LINK_UNKNOWN; return (rc); } - __checkReturn int + __checkReturn efx_rc_t hunt_mac_up( __in efx_nic_t *enp, __out boolean_t *mac_upp) @@ -81,7 +80,7 @@ hunt_mac_up( */ hunt_link_state_t hls; - int rc; + efx_rc_t rc; /* * Because Huntington doesn't *require* polling, we can't rely on @@ -95,7 +94,7 @@ hunt_mac_up( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -107,7 +106,7 @@ fail1: * MC_CMD_VADAPTOR_SET_MAC requires mac-spoofing privilege and * the port to have no filters or queues active. */ -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_vadapter_set_mac( __in efx_nic_t *enp) { @@ -115,7 +114,7 @@ efx_mcdi_vadapter_set_mac( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_VADAPTOR_SET_MAC_IN_LEN, MC_CMD_VADAPTOR_SET_MAC_OUT_LEN)]; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_VADAPTOR_SET_MAC; @@ -139,16 +138,16 @@ efx_mcdi_vadapter_set_mac( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t hunt_mac_addr_set( __in efx_nic_t *enp) { - int rc; + efx_rc_t rc; if ((rc = efx_mcdi_vadapter_set_mac(enp)) != 0) { if (rc != ENOTSUP) @@ -165,12 +164,12 @@ fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -__checkReturn int +__checkReturn efx_rc_t hunt_mac_reconfigure( __in efx_nic_t *enp) { @@ -178,7 +177,7 @@ hunt_mac_reconfigure( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_SET_MAC_IN_LEN, MC_CMD_SET_MAC_OUT_LEN)]; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_SET_MAC; @@ -242,18 +241,18 @@ hunt_mac_reconfigure( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t hunt_mac_multicast_list_set( __in efx_nic_t *enp) { efx_port_t *epp = &(enp->en_port); efx_mac_ops_t *emop = epp->ep_emop; - int rc; + efx_rc_t rc; EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); @@ -265,12 +264,12 @@ hunt_mac_multicast_list_set( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t hunt_mac_filter_default_rxq_set( __in efx_nic_t *enp, __in efx_rxq_t *erp, @@ -279,11 +278,11 @@ hunt_mac_filter_default_rxq_set( efx_port_t *epp = &(enp->en_port); efx_rxq_t *old_rxq; boolean_t old_using_rss; - int rc; + efx_rc_t rc; - hunt_filter_get_default_rxq(enp, &old_rxq, &old_using_rss); + ef10_filter_get_default_rxq(enp, &old_rxq, &old_using_rss); - hunt_filter_default_rxq_set(enp, erp, using_rss); + ef10_filter_default_rxq_set(enp, erp, using_rss); rc = efx_filter_reconfigure(enp, epp->ep_mac_addr, epp->ep_all_unicst, epp->ep_mulcst, @@ -297,9 +296,9 @@ hunt_mac_filter_default_rxq_set( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); - hunt_filter_default_rxq_set(enp, old_rxq, old_using_rss); + ef10_filter_default_rxq_set(enp, old_rxq, old_using_rss); return (rc); } @@ -310,7 +309,7 @@ hunt_mac_filter_default_rxq_clear( { efx_port_t *epp = &(enp->en_port); - hunt_filter_default_rxq_clear(enp); + ef10_filter_default_rxq_clear(enp); efx_filter_reconfigure(enp, epp->ep_mac_addr, epp->ep_all_unicst, epp->ep_mulcst, @@ -322,7 +321,7 @@ hunt_mac_filter_default_rxq_clear( #if EFSYS_OPT_LOOPBACK - __checkReturn int + __checkReturn efx_rc_t hunt_mac_loopback_set( __in efx_nic_t *enp, __in efx_link_mode_t link_mode, @@ -337,7 +336,7 @@ hunt_mac_loopback_set( efx_phy_ops_t *epop = epp->ep_epop; efx_loopback_type_t old_loopback_type; efx_link_mode_t old_loopback_link_mode; - int rc; + efx_rc_t rc; /* The PHY object handles this on Huntington */ old_loopback_type = epp->ep_loopback_type; @@ -351,7 +350,7 @@ hunt_mac_loopback_set( return (0); fail1: - EFSYS_PROBE(fail2); + EFSYS_PROBE1(fail1, efx_rc_t, rc); epp->ep_loopback_type = old_loopback_type; epp->ep_loopback_link_mode = old_loopback_link_mode; @@ -367,12 +366,12 @@ fail1: EFSYS_MEM_READQ((_esmp), (_field) * sizeof (efx_qword_t), _eqp) - __checkReturn int + __checkReturn efx_rc_t hunt_mac_stats_update( __in efx_nic_t *enp, __in efsys_mem_t *esmp, - __out_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, - __out_opt uint32_t *generationp) + __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, + __inout_opt uint32_t *generationp) { efx_qword_t value; efx_qword_t generation_start; diff --git a/sys/dev/sfxge/common/hunt_mcdi.c b/sys/dev/sfxge/common/hunt_mcdi.c index 8782bcc..1cccb23 100644 --- a/sys/dev/sfxge/common/hunt_mcdi.c +++ b/sys/dev/sfxge/common/hunt_mcdi.c @@ -31,17 +31,16 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" #include "efx_impl.h" -#if EFSYS_OPT_HUNTINGTON +#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD #if EFSYS_OPT_MCDI #ifndef WITH_MCDI_V2 -#error "WITH_MCDI_V2 required for Huntington MCDIv2 commands." +#error "WITH_MCDI_V2 required for EF10 MCDIv2 commands." #endif typedef enum efx_mcdi_header_type_e { @@ -76,19 +75,28 @@ typedef enum efx_mcdi_header_type_e { */ - __checkReturn int -hunt_mcdi_init( + __checkReturn efx_rc_t +ef10_mcdi_init( __in efx_nic_t *enp, __in const efx_mcdi_transport_t *emtp) { + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); efsys_mem_t *esmp = emtp->emt_dma_mem; efx_dword_t dword; - int rc; + efx_rc_t rc; - EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); EFSYS_ASSERT(enp->en_features & EFX_FEATURE_MCDI_DMA); - /* A host DMA buffer is required for Huntington MCDI */ + /* + * All EF10 firmware supports MCDIv2 and MCDIv1. + * Medford BootROM supports MCDIv2 and MCDIv1. + * Huntington BootROM supports MCDIv1 only. + */ + emip->emi_max_version = 2; + + /* A host DMA buffer is required for EF10 MCDI */ if (esmp == NULL) { rc = EINVAL; goto fail1; @@ -107,7 +115,7 @@ hunt_mcdi_init( EFX_BAR_WRITED(enp, ER_DZ_MC_DB_HWRD_REG, &dword, B_FALSE); /* Save initial MC reboot status */ - (void) hunt_mcdi_poll_reboot(enp); + (void) ef10_mcdi_poll_reboot(enp); /* Start a new epoch (allow fresh MCDI requests to succeed) */ efx_mcdi_new_epoch(enp); @@ -117,13 +125,13 @@ hunt_mcdi_init( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } void -hunt_mcdi_fini( +ef10_mcdi_fini( __in efx_nic_t *enp) { efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); @@ -131,36 +139,78 @@ hunt_mcdi_fini( emip->emi_new_epoch = B_FALSE; } +static void +ef10_mcdi_send_request( + __in efx_nic_t *enp, + __in void *hdrp, + __in size_t hdr_len, + __in void *sdup, + __in size_t sdu_len) +{ + const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp; + efsys_mem_t *esmp = emtp->emt_dma_mem; + efx_dword_t dword; + unsigned int pos; + + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); + + /* Write the header */ + for (pos = 0; pos < hdr_len; pos += sizeof (efx_dword_t)) { + dword = *(efx_dword_t *)((uint8_t *)hdrp + pos); + EFSYS_MEM_WRITED(esmp, pos, &dword); + } + + /* Write the payload */ + for (pos = 0; pos < sdu_len; pos += sizeof (efx_dword_t)) { + dword = *(efx_dword_t *)((uint8_t *)sdup + pos); + EFSYS_MEM_WRITED(esmp, hdr_len + pos, &dword); + } + + /* Guarantee ordering of memory (MCDI request) and PIO (MC doorbell) */ + EFSYS_DMA_SYNC_FOR_DEVICE(esmp, 0, hdr_len + sdu_len); + EFSYS_PIO_WRITE_BARRIER(); + + /* Ring the doorbell to post the command DMA address to the MC */ + EFX_POPULATE_DWORD_1(dword, EFX_DWORD_0, + EFSYS_MEM_ADDR(esmp) >> 32); + EFX_BAR_WRITED(enp, ER_DZ_MC_DB_LWRD_REG, &dword, B_FALSE); + + EFX_POPULATE_DWORD_1(dword, EFX_DWORD_0, + EFSYS_MEM_ADDR(esmp) & 0xffffffff); + EFX_BAR_WRITED(enp, ER_DZ_MC_DB_HWRD_REG, &dword, B_FALSE); +} + void -hunt_mcdi_request_copyin( +ef10_mcdi_request_copyin( __in efx_nic_t *enp, __in efx_mcdi_req_t *emrp, __in unsigned int seq, __in boolean_t ev_cpl, __in boolean_t new_epoch) { +#if EFSYS_OPT_MCDI_LOGGING const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp; - efsys_mem_t *esmp = emtp->emt_dma_mem; +#endif /* EFSYS_OPT_MCDI_LOGGING */ efx_mcdi_header_type_t hdr_type; - efx_dword_t dword; + efx_dword_t hdr[2]; + size_t hdr_len; unsigned int xflags; - unsigned int pos; - size_t offset; - EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); xflags = 0; if (ev_cpl) xflags |= MCDI_HEADER_XFLAGS_EVREQ; - offset = 0; - hdr_type = EFX_MCDI_HEADER_TYPE(emrp->emr_cmd, MAX(emrp->emr_in_length, emrp->emr_out_length)); if (hdr_type == EFX_MCDI_HEADER_TYPE_V2) { /* Construct MCDI v2 header */ - EFX_POPULATE_DWORD_8(dword, + hdr_len = sizeof (hdr); + EFX_POPULATE_DWORD_8(hdr[0], MCDI_HEADER_CODE, MC_CMD_V2_EXTN, MCDI_HEADER_RESYNC, 1, MCDI_HEADER_DATALEN, 0, @@ -169,17 +219,14 @@ hunt_mcdi_request_copyin( MCDI_HEADER_ERROR, 0, MCDI_HEADER_RESPONSE, 0, MCDI_HEADER_XFLAGS, xflags); - EFSYS_MEM_WRITED(esmp, offset, &dword); - offset += sizeof (dword); - EFX_POPULATE_DWORD_2(dword, + EFX_POPULATE_DWORD_2(hdr[1], MC_CMD_V2_EXTN_IN_EXTENDED_CMD, emrp->emr_cmd, MC_CMD_V2_EXTN_IN_ACTUAL_LEN, emrp->emr_in_length); - EFSYS_MEM_WRITED(esmp, offset, &dword); - offset += sizeof (dword); } else { /* Construct MCDI v1 header */ - EFX_POPULATE_DWORD_8(dword, + hdr_len = sizeof (hdr[0]); + EFX_POPULATE_DWORD_8(hdr[0], MCDI_HEADER_CODE, emrp->emr_cmd, MCDI_HEADER_RESYNC, 1, MCDI_HEADER_DATALEN, emrp->emr_in_length, @@ -188,207 +235,104 @@ hunt_mcdi_request_copyin( MCDI_HEADER_ERROR, 0, MCDI_HEADER_RESPONSE, 0, MCDI_HEADER_XFLAGS, xflags); - EFSYS_MEM_WRITED(esmp, offset, &dword); - offset += sizeof (dword); } - /* Construct the payload */ - for (pos = 0; pos < emrp->emr_in_length; pos += sizeof (efx_dword_t)) { - memcpy(&dword, MCDI_IN(*emrp, efx_dword_t, pos), - MIN(sizeof (dword), emrp->emr_in_length - pos)); - EFSYS_MEM_WRITED(esmp, offset + pos, &dword); +#if EFSYS_OPT_MCDI_LOGGING + if (emtp->emt_logger != NULL) { + emtp->emt_logger(emtp->emt_context, EFX_LOG_MCDI_REQUEST, + &hdr, hdr_len, + emrp->emr_in_buf, emrp->emr_in_length); } +#endif /* EFSYS_OPT_MCDI_LOGGING */ - /* Ring the doorbell to post the command DMA address to the MC */ - EFSYS_ASSERT((EFSYS_MEM_ADDR(esmp) & 0xFF) == 0); - - /* Guarantee ordering of memory (MCDI request) and PIO (MC doorbell) */ - EFSYS_DMA_SYNC_FOR_DEVICE(esmp, 0, offset + emrp->emr_in_length); - EFSYS_PIO_WRITE_BARRIER(); - - EFX_POPULATE_DWORD_1(dword, - EFX_DWORD_0, EFSYS_MEM_ADDR(esmp) >> 32); - EFX_BAR_WRITED(enp, ER_DZ_MC_DB_LWRD_REG, &dword, B_FALSE); - - EFX_POPULATE_DWORD_1(dword, - EFX_DWORD_0, EFSYS_MEM_ADDR(esmp) & 0xffffffff); - EFX_BAR_WRITED(enp, ER_DZ_MC_DB_HWRD_REG, &dword, B_FALSE); + ef10_mcdi_send_request(enp, &hdr[0], hdr_len, + emrp->emr_in_buf, emrp->emr_in_length); } void -hunt_mcdi_request_copyout( +ef10_mcdi_request_copyout( __in efx_nic_t *enp, __in efx_mcdi_req_t *emrp) { +#if EFSYS_OPT_MCDI_LOGGING const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp; - efsys_mem_t *esmp = emtp->emt_dma_mem; - unsigned int pos; - unsigned int offset; - efx_dword_t hdr; - efx_dword_t hdr2; - efx_dword_t data; +#endif /* EFSYS_OPT_MCDI_LOGGING */ + efx_dword_t hdr[2]; + unsigned int hdr_len; size_t bytes; if (emrp->emr_out_buf == NULL) return; /* Read the command header to detect MCDI response format */ - EFSYS_MEM_READD(esmp, 0, &hdr); - if (EFX_DWORD_FIELD(hdr, MCDI_HEADER_CODE) == MC_CMD_V2_EXTN) { - offset = 2 * sizeof (efx_dword_t); - + hdr_len = sizeof (hdr[0]); + ef10_mcdi_read_response(enp, &hdr[0], 0, hdr_len); + if (EFX_DWORD_FIELD(hdr[0], MCDI_HEADER_CODE) == MC_CMD_V2_EXTN) { /* * Read the actual payload length. The length given in the event * is only correct for responses with the V1 format. */ - EFSYS_MEM_READD(esmp, sizeof (efx_dword_t), &hdr2); - emrp->emr_out_length_used = EFX_DWORD_FIELD(hdr2, + ef10_mcdi_read_response(enp, &hdr[1], hdr_len, sizeof (hdr[1])); + hdr_len += sizeof (hdr[1]); + + emrp->emr_out_length_used = EFX_DWORD_FIELD(hdr[1], MC_CMD_V2_EXTN_IN_ACTUAL_LEN); - } else { - offset = sizeof (efx_dword_t); } /* Copy payload out into caller supplied buffer */ bytes = MIN(emrp->emr_out_length_used, emrp->emr_out_length); - for (pos = 0; pos < bytes; pos += sizeof (efx_dword_t)) { - EFSYS_MEM_READD(esmp, offset + pos, &data); - memcpy(MCDI_OUT(*emrp, efx_dword_t, pos), &data, - MIN(sizeof (data), bytes - pos)); + ef10_mcdi_read_response(enp, emrp->emr_out_buf, hdr_len, bytes); + +#if EFSYS_OPT_MCDI_LOGGING + if (emtp->emt_logger != NULL) { + emtp->emt_logger(emtp->emt_context, + EFX_LOG_MCDI_RESPONSE, + &hdr, hdr_len, + emrp->emr_out_buf, bytes); } +#endif /* EFSYS_OPT_MCDI_LOGGING */ } __checkReturn boolean_t -hunt_mcdi_request_poll( +ef10_mcdi_poll_response( __in efx_nic_t *enp) { - efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp; efsys_mem_t *esmp = emtp->emt_dma_mem; - efx_mcdi_req_t *emrp; - efx_dword_t dword; - unsigned int seq; - unsigned int cmd; - unsigned int length; - size_t offset; - int state; - int rc; - - EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_HUNTINGTON); - - /* Serialise against post-watchdog efx_mcdi_ev* */ - EFSYS_LOCK(enp->en_eslp, state); - - EFSYS_ASSERT(emip->emi_pending_req != NULL); - EFSYS_ASSERT(!emip->emi_ev_cpl); - emrp = emip->emi_pending_req; - - offset = 0; - - /* Read the command header */ - EFSYS_MEM_READD(esmp, offset, &dword); - offset += sizeof (efx_dword_t); - if (EFX_DWORD_FIELD(dword, MCDI_HEADER_RESPONSE) == 0) { - EFSYS_UNLOCK(enp->en_eslp, state); - return (B_FALSE); - } - if (EFX_DWORD_FIELD(dword, MCDI_HEADER_CODE) == MC_CMD_V2_EXTN) { - efx_dword_t dword2; - - EFSYS_MEM_READD(esmp, offset, &dword2); - offset += sizeof (efx_dword_t); - - cmd = EFX_DWORD_FIELD(dword2, MC_CMD_V2_EXTN_IN_EXTENDED_CMD); - length = EFX_DWORD_FIELD(dword2, MC_CMD_V2_EXTN_IN_ACTUAL_LEN); - } else { - cmd = EFX_DWORD_FIELD(dword, MCDI_HEADER_CODE); - length = EFX_DWORD_FIELD(dword, MCDI_HEADER_DATALEN); - } - - /* Request complete */ - emip->emi_pending_req = NULL; - seq = (emip->emi_seq - 1) & EFX_MASK32(MCDI_HEADER_SEQ); - - /* Check for synchronous reboot */ - if (EFX_DWORD_FIELD(dword, MCDI_HEADER_ERROR) != 0 && length == 0) { - /* The MC has rebooted since the request was sent. */ - EFSYS_SPIN(EFX_MCDI_STATUS_SLEEP_US); - hunt_mcdi_poll_reboot(enp); - - EFSYS_UNLOCK(enp->en_eslp, state); - rc = EIO; - goto fail1; - } - - /* Ensure stale MCDI requests fail after an MC reboot. */ - emip->emi_new_epoch = B_FALSE; + efx_dword_t hdr; - EFSYS_UNLOCK(enp->en_eslp, state); + EFSYS_MEM_READD(esmp, 0, &hdr); + return (EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE) ? B_TRUE : B_FALSE); +} - /* Check that the returned data is consistent */ - if (cmd != emrp->emr_cmd || - EFX_DWORD_FIELD(dword, MCDI_HEADER_SEQ) != seq) { - /* Response is for a different request */ - rc = EIO; - goto fail2; - } - if (EFX_DWORD_FIELD(dword, MCDI_HEADER_ERROR)) { - efx_dword_t errdword; - int errcode; - int argnum; - - /* Read error code (and arg num for MCDI v2 commands) */ - EFSYS_MEM_READD(esmp, offset + MC_CMD_ERR_CODE_OFST, &errdword); - errcode = EFX_DWORD_FIELD(errdword, EFX_DWORD_0); - - EFSYS_MEM_READD(esmp, offset + MC_CMD_ERR_ARG_OFST, &errdword); - argnum = EFX_DWORD_FIELD(errdword, EFX_DWORD_0); - - rc = efx_mcdi_request_errcode(errcode); - if (!emrp->emr_quiet) { - EFSYS_PROBE3(mcdi_err_arg, int, emrp->emr_cmd, - int, errcode, int, argnum); - } - goto fail3; + void +ef10_mcdi_read_response( + __in efx_nic_t *enp, + __out_bcount(length) void *bufferp, + __in size_t offset, + __in size_t length) +{ + const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp; + efsys_mem_t *esmp = emtp->emt_dma_mem; + unsigned int pos; + efx_dword_t data; - } else { - emrp->emr_out_length_used = length; - emrp->emr_rc = 0; - hunt_mcdi_request_copyout(enp, emrp); + for (pos = 0; pos < length; pos += sizeof (efx_dword_t)) { + EFSYS_MEM_READD(esmp, offset + pos, &data); + memcpy((uint8_t *)bufferp + pos, &data, + MIN(sizeof (data), length - pos)); } - - goto out; - -fail3: - if (!emrp->emr_quiet) - EFSYS_PROBE(fail3); -fail2: - if (!emrp->emr_quiet) - EFSYS_PROBE(fail2); -fail1: - if (!emrp->emr_quiet) - EFSYS_PROBE1(fail1, int, rc); - - /* Fill out error state */ - emrp->emr_rc = rc; - emrp->emr_out_length_used = 0; - - /* Reboot/Assertion */ - if (rc == EIO || rc == EINTR) - efx_mcdi_raise_exception(enp, emrp, rc); - -out: - return (B_TRUE); } - int -hunt_mcdi_poll_reboot( + efx_rc_t +ef10_mcdi_poll_reboot( __in efx_nic_t *enp) { efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); efx_dword_t dword; uint32_t old_status; uint32_t new_status; - int rc; + efx_rc_t rc; old_status = emip->emi_mc_reboot_status; @@ -405,7 +349,7 @@ hunt_mcdi_poll_reboot( * * The Siena support for checking for MC reboot from status * flags is broken - see comments in siena_mcdi_poll_reboot(). - * As the generic MCDI code is shared the Huntington reboot + * As the generic MCDI code is shared the EF10 reboot * detection suffers similar problems. * * Do not report an error when the boot status changes until @@ -421,45 +365,82 @@ hunt_mcdi_poll_reboot( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_mcdi_fw_update_supported( + __checkReturn efx_rc_t +ef10_mcdi_feature_supported( __in efx_nic_t *enp, + __in efx_mcdi_feature_id_t id, __out boolean_t *supportedp) { efx_nic_cfg_t *encp = &(enp->en_nic_cfg); + uint32_t privilege_mask = encp->enc_privilege_mask; + efx_rc_t rc; - EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_HUNTINGTON); - - /* use privilege mask state at MCDI attach */ - *supportedp = (encp->enc_privilege_mask & - MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN) - == MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN; + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); - return (0); -} + /* + * Use privilege mask state at MCDI attach. + */ - __checkReturn int -hunt_mcdi_macaddr_change_supported( - __in efx_nic_t *enp, - __out boolean_t *supportedp) -{ - efx_nic_cfg_t *encp = &(enp->en_nic_cfg); + switch (id) { + case EFX_MCDI_FEATURE_FW_UPDATE: + /* + * Admin privilege must be used prior to introduction of + * specific flag. + */ + *supportedp = + EFX_MCDI_HAVE_PRIVILEGE(privilege_mask, ADMIN); + break; + case EFX_MCDI_FEATURE_LINK_CONTROL: + /* + * Admin privilege used prior to introduction of + * specific flag. + */ + *supportedp = + EFX_MCDI_HAVE_PRIVILEGE(privilege_mask, LINK) || + EFX_MCDI_HAVE_PRIVILEGE(privilege_mask, ADMIN); + break; + case EFX_MCDI_FEATURE_MACADDR_CHANGE: + /* + * Admin privilege must be used prior to introduction of + * mac spoofing privilege (at v4.6), which is used up to + * introduction of change mac spoofing privilege (at v4.7) + */ + *supportedp = + EFX_MCDI_HAVE_PRIVILEGE(privilege_mask, CHANGE_MAC) || + EFX_MCDI_HAVE_PRIVILEGE(privilege_mask, MAC_SPOOFING) || + EFX_MCDI_HAVE_PRIVILEGE(privilege_mask, ADMIN); + break; + case EFX_MCDI_FEATURE_MAC_SPOOFING: + /* + * Admin privilege must be used prior to introduction of + * mac spoofing privilege (at v4.6), which is used up to + * introduction of mac spoofing TX privilege (at v4.7) + */ + *supportedp = + EFX_MCDI_HAVE_PRIVILEGE(privilege_mask, MAC_SPOOFING_TX) || + EFX_MCDI_HAVE_PRIVILEGE(privilege_mask, MAC_SPOOFING) || + EFX_MCDI_HAVE_PRIVILEGE(privilege_mask, ADMIN); + break; + default: + rc = ENOTSUP; + goto fail1; + break; + } - EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_HUNTINGTON); + return (0); - /* use privilege mask state at MCDI attach */ - *supportedp = (encp->enc_privilege_mask & - MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING) - == MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING; +fail1: + EFSYS_PROBE1(fail1, efx_rc_t, rc); - return (0); + return (rc); } #endif /* EFSYS_OPT_MCDI */ -#endif /* EFSYS_OPT_HUNTINGTON */ +#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ diff --git a/sys/dev/sfxge/common/hunt_nic.c b/sys/dev/sfxge/common/hunt_nic.c index 3a7204e..d87f3cd 100644 --- a/sys/dev/sfxge/common/hunt_nic.c +++ b/sys/dev/sfxge/common/hunt_nic.c @@ -31,16 +31,17 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" #include "efx_impl.h" +#if EFSYS_OPT_MON_MCDI #include "mcdi_mon.h" +#endif #if EFSYS_OPT_HUNTINGTON #include "ef10_tlv_layout.h" -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_get_port_assignment( __in efx_nic_t *enp, __out uint32_t *portp) @@ -48,9 +49,10 @@ efx_mcdi_get_port_assignment( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN, MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN)]; - int rc; + efx_rc_t rc; - EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT; @@ -78,12 +80,12 @@ efx_mcdi_get_port_assignment( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_get_port_modes( __in efx_nic_t *enp, __out uint32_t *modesp) @@ -91,9 +93,10 @@ efx_mcdi_get_port_modes( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_GET_PORT_MODES_IN_LEN, MC_CMD_GET_PORT_MODES_OUT_LEN)]; - int rc; + efx_rc_t rc; - EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_GET_PORT_MODES; @@ -123,13 +126,13 @@ efx_mcdi_get_port_modes( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_vadaptor_alloc( __in efx_nic_t *enp, __in uint32_t port_id) @@ -137,7 +140,7 @@ efx_mcdi_vadaptor_alloc( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_VADAPTOR_ALLOC_IN_LEN, MC_CMD_VADAPTOR_ALLOC_OUT_LEN)]; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_vport_id, ==, EVB_PORT_ID_NULL); @@ -149,6 +152,9 @@ efx_mcdi_vadaptor_alloc( req.emr_out_length = MC_CMD_VADAPTOR_ALLOC_OUT_LEN; MCDI_IN_SET_DWORD(req, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id); + MCDI_IN_POPULATE_DWORD_1(req, VADAPTOR_ALLOC_IN_FLAGS, + VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED, + enp->en_nic_cfg.enc_allow_set_mac_with_installed_filters ? 1 : 0); efx_mcdi_execute(enp, &req); @@ -160,12 +166,12 @@ efx_mcdi_vadaptor_alloc( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_vadaptor_free( __in efx_nic_t *enp, __in uint32_t port_id) @@ -173,7 +179,7 @@ efx_mcdi_vadaptor_free( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_VADAPTOR_FREE_IN_LEN, MC_CMD_VADAPTOR_FREE_OUT_LEN)]; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_VADAPTOR_FREE; @@ -194,12 +200,12 @@ efx_mcdi_vadaptor_free( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_get_mac_address_pf( __in efx_nic_t *enp, __out_ecount_opt(6) uint8_t mac_addrp[6]) @@ -207,9 +213,10 @@ efx_mcdi_get_mac_address_pf( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_GET_MAC_ADDRESSES_IN_LEN, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)]; - int rc; + efx_rc_t rc; - EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES; @@ -251,12 +258,12 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_get_mac_address_vf( __in efx_nic_t *enp, __out_ecount_opt(6) uint8_t mac_addrp[6]) @@ -264,9 +271,10 @@ efx_mcdi_get_mac_address_vf( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX)]; - int rc; + efx_rc_t rc; - EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES; @@ -313,12 +321,12 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_get_clock( __in efx_nic_t *enp, __out uint32_t *sys_freqp) @@ -326,9 +334,10 @@ efx_mcdi_get_clock( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_GET_CLOCK_IN_LEN, MC_CMD_GET_CLOCK_OUT_LEN)]; - int rc; + efx_rc_t rc; - EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_GET_CLOCK; @@ -362,12 +371,12 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_get_vector_cfg( __in efx_nic_t *enp, __out_opt uint32_t *vec_basep, @@ -377,7 +386,7 @@ efx_mcdi_get_vector_cfg( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_GET_VECTOR_CFG_IN_LEN, MC_CMD_GET_VECTOR_CFG_OUT_LEN)]; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_GET_VECTOR_CFG; @@ -410,27 +419,28 @@ efx_mcdi_get_vector_cfg( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_get_capabilities( __in efx_nic_t *enp, - __out efx_dword_t *flagsp) + __out efx_dword_t *flagsp, + __out efx_dword_t *flags2p) { efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_GET_CAPABILITIES_IN_LEN, - MC_CMD_GET_CAPABILITIES_OUT_LEN)]; - int rc; + MC_CMD_GET_CAPABILITIES_V2_OUT_LEN)]; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_GET_CAPABILITIES; req.emr_in_buf = payload; req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN; req.emr_out_buf = payload; - req.emr_out_length = MC_CMD_GET_CAPABILITIES_OUT_LEN; + req.emr_out_length = MC_CMD_GET_CAPABILITIES_V2_OUT_LEN; efx_mcdi_execute(enp, &req); @@ -446,30 +456,36 @@ efx_mcdi_get_capabilities( *flagsp = *MCDI_OUT2(req, efx_dword_t, GET_CAPABILITIES_OUT_FLAGS1); + if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_V2_OUT_LEN) + EFX_ZERO_DWORD(*flags2p); + else + *flags2p = *MCDI_OUT2(req, efx_dword_t, + GET_CAPABILITIES_V2_OUT_FLAGS2); + return (0); fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_alloc_vis( __in efx_nic_t *enp, __in uint32_t min_vi_count, __in uint32_t max_vi_count, - __out_opt uint32_t *vi_basep, - __out uint32_t *vi_countp) - + __out uint32_t *vi_basep, + __out uint32_t *vi_countp, + __out uint32_t *vi_shiftp) { efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_ALLOC_VIS_IN_LEN, MC_CMD_ALLOC_VIS_OUT_LEN)]; - int rc; + efx_rc_t rc; if (vi_countp == NULL) { rc = EINVAL; @@ -498,11 +514,14 @@ efx_mcdi_alloc_vis( goto fail3; } - if (vi_basep != NULL) - *vi_basep = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_BASE); + *vi_basep = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_BASE); + *vi_countp = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_COUNT); - if (vi_countp != NULL) - *vi_countp = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_COUNT); + /* Report VI_SHIFT if available (always zero for Huntington) */ + if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_EXT_OUT_LEN) + *vi_shiftp = 0; + else + *vi_shiftp = MCDI_OUT_DWORD(req, ALLOC_VIS_EXT_OUT_VI_SHIFT); return (0); @@ -511,18 +530,18 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_free_vis( __in efx_nic_t *enp) { efx_mcdi_req_t req; - int rc; + efx_rc_t rc; EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0); EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0); @@ -544,13 +563,13 @@ efx_mcdi_free_vis( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_alloc_piobuf( __in efx_nic_t *enp, __out efx_piobuf_handle_t *handlep) @@ -558,7 +577,7 @@ efx_mcdi_alloc_piobuf( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_ALLOC_PIOBUF_IN_LEN, MC_CMD_ALLOC_PIOBUF_OUT_LEN)]; - int rc; + efx_rc_t rc; if (handlep == NULL) { rc = EINVAL; @@ -593,20 +612,20 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_free_piobuf( __in efx_nic_t *enp, - __out efx_piobuf_handle_t handle) + __in efx_piobuf_handle_t handle) { efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_FREE_PIOBUF_IN_LEN, MC_CMD_FREE_PIOBUF_OUT_LEN)]; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_FREE_PIOBUF; @@ -627,12 +646,12 @@ efx_mcdi_free_piobuf( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_link_piobuf( __in efx_nic_t *enp, __in uint32_t vi_index, @@ -641,7 +660,7 @@ efx_mcdi_link_piobuf( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_LINK_PIOBUF_IN_LEN, MC_CMD_LINK_PIOBUF_OUT_LEN)]; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_LINK_PIOBUF; @@ -663,12 +682,12 @@ efx_mcdi_link_piobuf( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_unlink_piobuf( __in efx_nic_t *enp, __in uint32_t vi_index) @@ -676,7 +695,7 @@ efx_mcdi_unlink_piobuf( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_UNLINK_PIOBUF_IN_LEN, MC_CMD_UNLINK_PIOBUF_OUT_LEN)]; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_UNLINK_PIOBUF; @@ -697,67 +716,67 @@ efx_mcdi_unlink_piobuf( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } static void -hunt_nic_alloc_piobufs( +ef10_nic_alloc_piobufs( __in efx_nic_t *enp, __in uint32_t max_piobuf_count) { efx_piobuf_handle_t *handlep; unsigned int i; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(max_piobuf_count, <=, - EFX_ARRAY_SIZE(enp->en_u.hunt.enu_piobuf_handle)); + EFX_ARRAY_SIZE(enp->en_arch.ef10.ena_piobuf_handle)); - enp->en_u.hunt.enu_piobuf_count = 0; + enp->en_arch.ef10.ena_piobuf_count = 0; for (i = 0; i < max_piobuf_count; i++) { - handlep = &enp->en_u.hunt.enu_piobuf_handle[i]; + handlep = &enp->en_arch.ef10.ena_piobuf_handle[i]; if ((rc = efx_mcdi_alloc_piobuf(enp, handlep)) != 0) goto fail1; - enp->en_u.hunt.enu_pio_alloc_map[i] = 0; - enp->en_u.hunt.enu_piobuf_count++; + enp->en_arch.ef10.ena_pio_alloc_map[i] = 0; + enp->en_arch.ef10.ena_piobuf_count++; } return; fail1: - for (i = 0; i < enp->en_u.hunt.enu_piobuf_count; i++) { - handlep = &enp->en_u.hunt.enu_piobuf_handle[i]; + for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) { + handlep = &enp->en_arch.ef10.ena_piobuf_handle[i]; efx_mcdi_free_piobuf(enp, *handlep); *handlep = EFX_PIOBUF_HANDLE_INVALID; } - enp->en_u.hunt.enu_piobuf_count = 0; + enp->en_arch.ef10.ena_piobuf_count = 0; } static void -hunt_nic_free_piobufs( +ef10_nic_free_piobufs( __in efx_nic_t *enp) { efx_piobuf_handle_t *handlep; unsigned int i; - for (i = 0; i < enp->en_u.hunt.enu_piobuf_count; i++) { - handlep = &enp->en_u.hunt.enu_piobuf_handle[i]; + for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) { + handlep = &enp->en_arch.ef10.ena_piobuf_handle[i]; efx_mcdi_free_piobuf(enp, *handlep); *handlep = EFX_PIOBUF_HANDLE_INVALID; } - enp->en_u.hunt.enu_piobuf_count = 0; + enp->en_arch.ef10.ena_piobuf_count = 0; } /* Sub-allocate a block from a piobuf */ - __checkReturn int -hunt_nic_pio_alloc( + __checkReturn efx_rc_t +ef10_nic_pio_alloc( __inout efx_nic_t *enp, __out uint32_t *bufnump, __out efx_piobuf_handle_t *handlep, @@ -765,12 +784,14 @@ hunt_nic_pio_alloc( __out uint32_t *offsetp, __out size_t *sizep) { + efx_nic_cfg_t *encp = &enp->en_nic_cfg; efx_drv_cfg_t *edcp = &enp->en_drv_cfg; uint32_t blk_per_buf; uint32_t buf, blk; - int rc; + efx_rc_t rc; - EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); EFSYS_ASSERT(bufnump); EFSYS_ASSERT(handlep); EFSYS_ASSERT(blknump); @@ -778,14 +799,14 @@ hunt_nic_pio_alloc( EFSYS_ASSERT(sizep); if ((edcp->edc_pio_alloc_size == 0) || - (enp->en_u.hunt.enu_piobuf_count == 0)) { + (enp->en_arch.ef10.ena_piobuf_count == 0)) { rc = ENOMEM; goto fail1; } - blk_per_buf = HUNT_PIOBUF_SIZE / edcp->edc_pio_alloc_size; + blk_per_buf = encp->enc_piobuf_size / edcp->edc_pio_alloc_size; - for (buf = 0; buf < enp->en_u.hunt.enu_piobuf_count; buf++) { - uint32_t *map = &enp->en_u.hunt.enu_pio_alloc_map[buf]; + for (buf = 0; buf < enp->en_arch.ef10.ena_piobuf_count; buf++) { + uint32_t *map = &enp->en_arch.ef10.ena_pio_alloc_map[buf]; if (~(*map) == 0) continue; @@ -802,7 +823,7 @@ hunt_nic_pio_alloc( goto fail2; done: - *handlep = enp->en_u.hunt.enu_piobuf_handle[buf]; + *handlep = enp->en_arch.ef10.ena_piobuf_handle[buf]; *bufnump = buf; *blknump = blk; *sizep = edcp->edc_pio_alloc_size; @@ -813,28 +834,28 @@ done: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } /* Free a piobuf sub-allocated block */ - __checkReturn int -hunt_nic_pio_free( + __checkReturn efx_rc_t +ef10_nic_pio_free( __inout efx_nic_t *enp, __in uint32_t bufnum, __in uint32_t blknum) { uint32_t *map; - int rc; + efx_rc_t rc; - if ((bufnum >= enp->en_u.hunt.enu_piobuf_count) || + if ((bufnum >= enp->en_arch.ef10.ena_piobuf_count) || (blknum >= (8 * sizeof (*map)))) { rc = EINVAL; goto fail1; } - map = &enp->en_u.hunt.enu_pio_alloc_map[bufnum]; + map = &enp->en_arch.ef10.ena_pio_alloc_map[bufnum]; if ((*map & (1u << blknum)) == 0) { rc = ENOENT; goto fail2; @@ -846,13 +867,13 @@ hunt_nic_pio_free( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_nic_pio_link( + __checkReturn efx_rc_t +ef10_nic_pio_link( __inout efx_nic_t *enp, __in uint32_t vi_index, __in efx_piobuf_handle_t handle) @@ -860,23 +881,25 @@ hunt_nic_pio_link( return (efx_mcdi_link_piobuf(enp, vi_index, handle)); } - __checkReturn int -hunt_nic_pio_unlink( + __checkReturn efx_rc_t +ef10_nic_pio_unlink( __inout efx_nic_t *enp, __in uint32_t vi_index) { return (efx_mcdi_unlink_piobuf(enp, vi_index)); } -static __checkReturn int -hunt_get_datapath_caps( +static __checkReturn efx_rc_t +ef10_get_datapath_caps( __in efx_nic_t *enp) { efx_nic_cfg_t *encp = &(enp->en_nic_cfg); efx_dword_t datapath_capabilities; - int rc; + efx_dword_t datapath_capabilities_v2; + efx_rc_t rc; - if ((rc = efx_mcdi_get_capabilities(enp, &datapath_capabilities)) != 0) + if ((rc = efx_mcdi_get_capabilities(enp, &datapath_capabilities, + &datapath_capabilities_v2)) != 0) goto fail1; /* @@ -920,12 +943,29 @@ hunt_get_datapath_caps( encp->enc_rx_batching_enabled = B_FALSE; } + /* Check if the firmware supports disabling scatter on RXQs */ + if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities, + GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER) == 1) { + encp->enc_rx_disable_scatter_supported = B_TRUE; + } else { + encp->enc_rx_disable_scatter_supported = B_FALSE; + } + + /* Check if the firmware supports set mac with running filters */ + if (MCDI_CMD_DWORD_FIELD(&datapath_capabilities, + GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED) + == 1) { + encp->enc_allow_set_mac_with_installed_filters = B_TRUE; + } else { + encp->enc_allow_set_mac_with_installed_filters = B_FALSE; + } + return (0); fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -943,33 +983,41 @@ static struct { efx_family_t family; uint32_t modes_mask; uint32_t stride; -} __hunt_external_port_mappings[] = { +} __ef10_external_port_mappings[] = { /* Supported modes requiring 1 output per port */ { EFX_FAMILY_HUNTINGTON, (1 << TLV_PORT_MODE_10G) | - (1 << TLV_PORT_MODE_40G) | (1 << TLV_PORT_MODE_10G_10G) | - (1 << TLV_PORT_MODE_40G_40G), + (1 << TLV_PORT_MODE_10G_10G_10G_10G), 1 }, /* Supported modes requiring 2 outputs per port */ { EFX_FAMILY_HUNTINGTON, - (1 << TLV_PORT_MODE_10G_10G_10G_10G) | + (1 << TLV_PORT_MODE_40G) | + (1 << TLV_PORT_MODE_40G_40G) | (1 << TLV_PORT_MODE_40G_10G_10G) | (1 << TLV_PORT_MODE_10G_10G_40G), 2 } + /* + * NOTE: Medford modes will require 4 outputs per port: + * TLV_PORT_MODE_10G_10G_10G_10G_Q + * TLV_PORT_MODE_10G_10G_10G_10G_Q2 + * The Q2 mode routes outputs to external port 2. Support for this + * will require a new field specifying the number to add after + * scaling by stride. This is fixed at 1 currently. + */ }; -static __checkReturn int -hunt_external_port_mapping( +static __checkReturn efx_rc_t +ef10_external_port_mapping( __in efx_nic_t *enp, __in uint32_t port, __out uint8_t *external_portp) { - int rc; + efx_rc_t rc; int i; uint32_t port_modes; uint32_t matches; @@ -984,14 +1032,14 @@ hunt_external_port_mapping( * Infer the internal port -> external port mapping from * the possible port modes for this NIC. */ - for (i = 0; i < EFX_ARRAY_SIZE(__hunt_external_port_mappings); ++i) { - if (__hunt_external_port_mappings[i].family != + for (i = 0; i < EFX_ARRAY_SIZE(__ef10_external_port_mappings); ++i) { + if (__ef10_external_port_mappings[i].family != enp->en_family) continue; - matches = (__hunt_external_port_mappings[i].modes_mask & + matches = (__ef10_external_port_mappings[i].modes_mask & port_modes); if (matches != 0) { - stride = __hunt_external_port_mappings[i].stride; + stride = __ef10_external_port_mappings[i].stride; port_modes &= ~matches; } } @@ -1011,12 +1059,12 @@ out: return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t hunt_board_cfg( __in efx_nic_t *enp) { @@ -1033,7 +1081,7 @@ hunt_board_cfg( uint32_t flags; uint32_t sysclk; uint32_t base, nvec; - int rc; + efx_rc_t rc; if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0) goto fail1; @@ -1044,7 +1092,7 @@ hunt_board_cfg( */ emip->emi_port = port + 1; - if ((rc = hunt_external_port_mapping(enp, port, + if ((rc = ef10_external_port_mapping(enp, port, &encp->enc_external_port)) != 0) goto fail2; @@ -1063,18 +1111,18 @@ hunt_board_cfg( /* MAC address for this function */ if (EFX_PCI_FUNCTION_IS_PF(encp)) { rc = efx_mcdi_get_mac_address_pf(enp, mac_addr); + if ((rc == 0) && (mac_addr[0] & 0x02)) { + /* + * If the static config does not include a global MAC + * address pool then the board may return a locally + * administered MAC address (this should only happen on + * incorrectly programmed boards). + */ + rc = EINVAL; + } } else { rc = efx_mcdi_get_mac_address_vf(enp, mac_addr); } - if ((rc == 0) && (mac_addr[0] & 0x02)) { - /* - * If the static config does not include a global MAC address - * pool then the board may return a locally administered MAC - * address (this should only happen on incorrectly programmed - * boards). - */ - rc = EINVAL; - } if (rc != 0) goto fail4; @@ -1208,7 +1256,7 @@ hunt_board_cfg( } /* Check capabilities of running datapath firmware */ - if ((rc = hunt_get_datapath_caps(enp)) != 0) + if ((rc = ef10_get_datapath_caps(enp)) != 0) goto fail12; /* Alignment for receive packet DMA buffers */ @@ -1216,7 +1264,7 @@ hunt_board_cfg( encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */ /* Alignment for WPTR updates */ - encp->enc_rx_push_align = HUNTINGTON_RX_WPTR_ALIGN; + encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN; /* * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use @@ -1232,6 +1280,7 @@ hunt_board_cfg( encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS; encp->enc_piobuf_size = HUNT_PIOBUF_SIZE; + encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE; /* * Get the current privilege mask. Note that this may be modified @@ -1302,21 +1351,22 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_nic_probe( + __checkReturn efx_rc_t +ef10_nic_probe( __in efx_nic_t *enp) { efx_nic_cfg_t *encp = &(enp->en_nic_cfg); efx_drv_cfg_t *edcp = &(enp->en_drv_cfg); - int rc; + efx_rc_t rc; - EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); /* Read and clear any assertion state */ if ((rc = efx_mcdi_read_assertion(enp)) != 0) @@ -1390,13 +1440,13 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_nic_set_drv_limits( + __checkReturn efx_rc_t +ef10_nic_set_drv_limits( __inout efx_nic_t *enp, __in efx_drv_limits_t *edlp) { @@ -1405,7 +1455,7 @@ hunt_nic_set_drv_limits( uint32_t min_evq_count, max_evq_count; uint32_t min_rxq_count, max_rxq_count; uint32_t min_txq_count, max_txq_count; - int rc; + efx_rc_t rc; if (edlp == NULL) { rc = EINVAL; @@ -1442,7 +1492,8 @@ hunt_nic_set_drv_limits( uint32_t blk_size, blk_count, blks_per_piobuf; blk_size = - MAX(edlp->edl_min_pio_alloc_size, HUNT_MIN_PIO_ALLOC_SIZE); + MAX(edlp->edl_min_pio_alloc_size, + encp->enc_piobuf_min_alloc_size); blks_per_piobuf = encp->enc_piobuf_size / blk_size; EFSYS_ASSERT3U(blks_per_piobuf, <=, 32); @@ -1463,22 +1514,22 @@ hunt_nic_set_drv_limits( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_nic_reset( + __checkReturn efx_rc_t +ef10_nic_reset( __in efx_nic_t *enp) { efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_ENTITY_RESET_IN_LEN, MC_CMD_ENTITY_RESET_OUT_LEN)]; - int rc; + efx_rc_t rc; - /* hunt_nic_reset() is called to recover from BADASSERT failures. */ + /* ef10_nic_reset() is called to recover from BADASSERT failures. */ if ((rc = efx_mcdi_read_assertion(enp)) != 0) goto fail1; if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0) @@ -1511,29 +1562,32 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_nic_init( + __checkReturn efx_rc_t +ef10_nic_init( __in efx_nic_t *enp) { efx_drv_cfg_t *edcp = &(enp->en_drv_cfg); uint32_t min_vi_count, max_vi_count; - uint32_t vi_count, vi_base; + uint32_t vi_count, vi_base, vi_shift; uint32_t i; - int rc; + uint32_t retry; + uint32_t delay_us; + efx_rc_t rc; - EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); /* Enable reporting of some events (e.g. link change) */ if ((rc = efx_mcdi_log_ctrl(enp)) != 0) goto fail1; /* Allocate (optional) on-chip PIO buffers */ - hunt_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count); + ef10_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count); /* * For best performance, PIO writes should use a write-combined @@ -1549,7 +1603,8 @@ hunt_nic_init( * each VI that is using a sub-allocated block from the piobuf. */ min_vi_count = edcp->edc_min_vi_count; - max_vi_count = edcp->edc_max_vi_count + enp->en_u.hunt.enu_piobuf_count; + max_vi_count = + edcp->edc_max_vi_count + enp->en_arch.ef10.ena_piobuf_count; /* Ensure that the previously attached driver's VIs are freed */ if ((rc = efx_mcdi_free_vis(enp)) != 0) @@ -1561,7 +1616,7 @@ hunt_nic_init( */ vi_count = 0; if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count, - &vi_base, &vi_count)) != 0) + &vi_base, &vi_count, &vi_shift)) != 0) goto fail3; EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count); @@ -1571,57 +1626,93 @@ hunt_nic_init( goto fail4; } - enp->en_u.hunt.enu_vi_base = vi_base; - enp->en_u.hunt.enu_vi_count = vi_count; + enp->en_arch.ef10.ena_vi_base = vi_base; + enp->en_arch.ef10.ena_vi_count = vi_count; + enp->en_arch.ef10.ena_vi_shift = vi_shift; - if (vi_count < min_vi_count + enp->en_u.hunt.enu_piobuf_count) { + if (vi_count < min_vi_count + enp->en_arch.ef10.ena_piobuf_count) { /* Not enough extra VIs to map piobufs */ - hunt_nic_free_piobufs(enp); + ef10_nic_free_piobufs(enp); } - enp->en_u.hunt.enu_pio_write_vi_base = - vi_count - enp->en_u.hunt.enu_piobuf_count; + enp->en_arch.ef10.ena_pio_write_vi_base = + vi_count - enp->en_arch.ef10.ena_piobuf_count; /* Save UC memory mapping details */ - enp->en_u.hunt.enu_uc_mem_map_offset = 0; - if (enp->en_u.hunt.enu_piobuf_count > 0) { - enp->en_u.hunt.enu_uc_mem_map_size = + enp->en_arch.ef10.ena_uc_mem_map_offset = 0; + if (enp->en_arch.ef10.ena_piobuf_count > 0) { + enp->en_arch.ef10.ena_uc_mem_map_size = (ER_DZ_TX_PIOBUF_STEP * - enp->en_u.hunt.enu_pio_write_vi_base); + enp->en_arch.ef10.ena_pio_write_vi_base); } else { - enp->en_u.hunt.enu_uc_mem_map_size = + enp->en_arch.ef10.ena_uc_mem_map_size = (ER_DZ_TX_PIOBUF_STEP * - enp->en_u.hunt.enu_vi_count); + enp->en_arch.ef10.ena_vi_count); } /* Save WC memory mapping details */ - enp->en_u.hunt.enu_wc_mem_map_offset = - enp->en_u.hunt.enu_uc_mem_map_offset + - enp->en_u.hunt.enu_uc_mem_map_size; + enp->en_arch.ef10.ena_wc_mem_map_offset = + enp->en_arch.ef10.ena_uc_mem_map_offset + + enp->en_arch.ef10.ena_uc_mem_map_size; - enp->en_u.hunt.enu_wc_mem_map_size = + enp->en_arch.ef10.ena_wc_mem_map_size = (ER_DZ_TX_PIOBUF_STEP * - enp->en_u.hunt.enu_piobuf_count); + enp->en_arch.ef10.ena_piobuf_count); /* Link piobufs to extra VIs in WC mapping */ - if (enp->en_u.hunt.enu_piobuf_count > 0) { - for (i = 0; i < enp->en_u.hunt.enu_piobuf_count; i++) { + if (enp->en_arch.ef10.ena_piobuf_count > 0) { + for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) { rc = efx_mcdi_link_piobuf(enp, - enp->en_u.hunt.enu_pio_write_vi_base + i, - enp->en_u.hunt.enu_piobuf_handle[i]); + enp->en_arch.ef10.ena_pio_write_vi_base + i, + enp->en_arch.ef10.ena_piobuf_handle[i]); if (rc != 0) break; } } - /* Allocate a vAdapter attached to our upstream vPort/pPort */ - if ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) - goto fail5; + /* + * Allocate a vAdaptor attached to our upstream vPort/pPort. + * + * On a VF, this may fail with MC_CMD_ERR_NO_EVB_PORT (ENOENT) if the PF + * driver has yet to bring up the EVB port. See bug 56147. In this case, + * retry the request several times after waiting a while. The wait time + * between retries starts small (10ms) and exponentially increases. + * Total wait time is a little over two seconds. Retry logic in the + * client driver may mean this whole loop is repeated if it continues to + * fail. + */ + retry = 0; + delay_us = 10000; + while ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) { + if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) || + (rc != ENOENT)) { + /* + * Do not retry alloc for PF, or for other errors on + * a VF. + */ + goto fail5; + } + + /* VF startup before PF is ready. Retry allocation. */ + if (retry > 5) { + /* Too many attempts */ + rc = EINVAL; + goto fail6; + } + EFSYS_PROBE1(mcdi_no_evb_port_retry, int, retry); + EFSYS_SLEEP(delay_us); + retry++; + if (delay_us < 500000) + delay_us <<= 2; + } enp->en_vport_id = EVB_PORT_ID_ASSIGNED; + enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2; return (0); +fail6: + EFSYS_PROBE(fail6); fail5: EFSYS_PROBE(fail5); fail4: @@ -1631,40 +1722,42 @@ fail3: fail2: EFSYS_PROBE(fail2); - hunt_nic_free_piobufs(enp); + ef10_nic_free_piobufs(enp); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_nic_get_vi_pool( + __checkReturn efx_rc_t +ef10_nic_get_vi_pool( __in efx_nic_t *enp, __out uint32_t *vi_countp) { - EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); /* * Report VIs that the client driver can use. * Do not include VIs used for PIO buffer writes. */ - *vi_countp = enp->en_u.hunt.enu_pio_write_vi_base; + *vi_countp = enp->en_arch.ef10.ena_pio_write_vi_base; return (0); } - __checkReturn int -hunt_nic_get_bar_region( + __checkReturn efx_rc_t +ef10_nic_get_bar_region( __in efx_nic_t *enp, __in efx_nic_region_t region, __out uint32_t *offsetp, __out size_t *sizep) { - int rc; + efx_rc_t rc; - EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); /* * TODO: Specify host memory mapping alignment and granularity @@ -1674,14 +1767,14 @@ hunt_nic_get_bar_region( switch (region) { case EFX_REGION_VI: /* UC mapped memory BAR region for VI registers */ - *offsetp = enp->en_u.hunt.enu_uc_mem_map_offset; - *sizep = enp->en_u.hunt.enu_uc_mem_map_size; + *offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset; + *sizep = enp->en_arch.ef10.ena_uc_mem_map_size; break; case EFX_REGION_PIO_WRITE_VI: /* WC mapped memory BAR region for piobuf writes */ - *offsetp = enp->en_u.hunt.enu_wc_mem_map_offset; - *sizep = enp->en_u.hunt.enu_wc_mem_map_size; + *offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset; + *sizep = enp->en_arch.ef10.ena_wc_mem_map_size; break; default: @@ -1692,27 +1785,39 @@ hunt_nic_get_bar_region( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } void -hunt_nic_fini( +ef10_nic_fini( __in efx_nic_t *enp) { + uint32_t i; + efx_rc_t rc; + (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id); enp->en_vport_id = 0; - /* FIXME: do we need to unlink piobufs ? */ - hunt_nic_free_piobufs(enp); + /* Unlink piobufs from extra VIs in WC mapping */ + if (enp->en_arch.ef10.ena_piobuf_count > 0) { + for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) { + rc = efx_mcdi_unlink_piobuf(enp, + enp->en_arch.ef10.ena_pio_write_vi_base + i); + if (rc != 0) + break; + } + } + + ef10_nic_free_piobufs(enp); (void) efx_mcdi_free_vis(enp); - enp->en_u.hunt.enu_vi_count = 0; + enp->en_arch.ef10.ena_vi_count = 0; } void -hunt_nic_unprobe( +ef10_nic_unprobe( __in efx_nic_t *enp) { #if EFSYS_OPT_MON_STATS @@ -1723,11 +1828,11 @@ hunt_nic_unprobe( #if EFSYS_OPT_DIAG - __checkReturn int -hunt_nic_register_test( + __checkReturn efx_rc_t +ef10_nic_register_test( __in efx_nic_t *enp) { - int rc; + efx_rc_t rc; /* FIXME */ _NOTE(ARGUNUSED(enp)) @@ -1740,7 +1845,7 @@ hunt_nic_register_test( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } diff --git a/sys/dev/sfxge/common/hunt_nvram.c b/sys/dev/sfxge/common/hunt_nvram.c index 3e130f4..35c5ddd 100644 --- a/sys/dev/sfxge/common/hunt_nvram.c +++ b/sys/dev/sfxge/common/hunt_nvram.c @@ -31,10 +31,7 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" -#include "efx_types.h" -#include "efx_regs.h" #include "efx_impl.h" #if EFSYS_OPT_HUNTINGTON @@ -51,7 +48,7 @@ typedef struct tlv_cursor_s { uint32_t *limit; /* Last dword of data block */ } tlv_cursor_t; -static __checkReturn int +static __checkReturn efx_rc_t tlv_validate_state( __in tlv_cursor_t *cursor); @@ -125,11 +122,11 @@ tlv_next_item_ptr( return (cursor->current + TLV_DWORD_COUNT(length)); } -static int +static efx_rc_t tlv_advance( __in tlv_cursor_t *cursor) { - int rc; + efx_rc_t rc; if ((rc = tlv_validate_state(cursor)) != 0) goto fail1; @@ -154,16 +151,16 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static int +static efx_rc_t tlv_rewind( __in tlv_cursor_t *cursor) { - int rc; + efx_rc_t rc; cursor->current = cursor->block; @@ -173,17 +170,17 @@ tlv_rewind( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static int +static efx_rc_t tlv_find( __in tlv_cursor_t *cursor, __in uint32_t tag) { - int rc; + efx_rc_t rc; rc = tlv_rewind(cursor); while (rc == 0) { @@ -195,11 +192,11 @@ tlv_find( return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t tlv_validate_state( __in tlv_cursor_t *cursor) { - int rc; + efx_rc_t rc; /* Check cursor position */ if (cursor->current < cursor->block) { @@ -236,14 +233,14 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static int +static efx_rc_t tlv_init_cursor( - __in tlv_cursor_t *cursor, + __out tlv_cursor_t *cursor, __in uint32_t *block, __in uint32_t *limit) { @@ -256,9 +253,9 @@ tlv_init_cursor( return (tlv_validate_state(cursor)); } -static int +static efx_rc_t tlv_init_cursor_from_size( - __in tlv_cursor_t *cursor, + __out tlv_cursor_t *cursor, __in uint8_t *block, __in size_t size) { @@ -267,12 +264,12 @@ tlv_init_cursor_from_size( return (tlv_init_cursor(cursor, (uint32_t *)block, limit)); } -static int +static efx_rc_t tlv_require_end( __in tlv_cursor_t *cursor) { uint32_t *pos; - int rc; + efx_rc_t rc; if (cursor->end == NULL) { pos = cursor->current; @@ -286,7 +283,7 @@ tlv_require_end( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -295,7 +292,7 @@ static size_t tlv_block_length_used( __in tlv_cursor_t *cursor) { - int rc; + efx_rc_t rc; if ((rc = tlv_validate_state(cursor)) != 0) goto fail1; @@ -309,7 +306,7 @@ tlv_block_length_used( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (0); } @@ -339,7 +336,7 @@ tlv_write( return (ptr); } -static __checkReturn int +static __checkReturn efx_rc_t tlv_insert( __in tlv_cursor_t *cursor, __in uint32_t tag, @@ -347,7 +344,7 @@ tlv_insert( __in size_t size) { unsigned int delta; - int rc; + efx_rc_t rc; if ((rc = tlv_validate_state(cursor)) != 0) goto fail1; @@ -385,12 +382,12 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t tlv_modify( __in tlv_cursor_t *cursor, __in uint32_t tag, @@ -401,7 +398,7 @@ tlv_modify( unsigned int old_ndwords; unsigned int new_ndwords; unsigned int delta; - int rc; + efx_rc_t rc; if ((rc = tlv_validate_state(cursor)) != 0) goto fail1; @@ -468,13 +465,13 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } /* Validate TLV formatted partition contents (before writing to flash) */ - __checkReturn int + __checkReturn efx_rc_t efx_nvram_tlv_validate( __in efx_nic_t *enp, __in uint32_t partn, @@ -487,9 +484,9 @@ efx_nvram_tlv_validate( size_t total_length; uint32_t cksum; int pos; - int rc; + efx_rc_t rc; - EFX_STATIC_ASSERT(sizeof (*header) <= HUNTINGTON_NVRAM_CHUNK); + EFX_STATIC_ASSERT(sizeof (*header) <= EF10_NVRAM_CHUNK); if ((partn_data == NULL) || (partn_size == 0)) { rc = EINVAL; @@ -497,7 +494,7 @@ efx_nvram_tlv_validate( } /* The partition header must be the first item (at offset zero) */ - if ((rc = tlv_init_cursor_from_size(&cursor, partn_data, + if ((rc = tlv_init_cursor_from_size(&cursor, (uint8_t *)partn_data, partn_size)) != 0) { rc = EFAULT; goto fail2; @@ -566,18 +563,24 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -/* Read and validate an entire TLV formatted partition */ -static __checkReturn int -hunt_nvram_read_tlv_partition( - __in efx_nic_t *enp, - __in uint32_t partn, - __in_bcount(partn_size) caddr_t partn_data, - __in size_t partn_size) +/* + * Read and validate a segment from a partition. A segment is a complete + * tlv chain between PARTITION_HEADER and PARTITION_END tags. There may + * be multiple segments in a partition, so seg_offset allows segments + * beyond the first to be read. + */ +static __checkReturn efx_rc_t +ef10_nvram_read_tlv_segment( + __in efx_nic_t *enp, + __in uint32_t partn, + __in size_t seg_offset, + __in_bcount(max_seg_size) caddr_t seg_data, + __in size_t max_seg_size) { tlv_cursor_t cursor; struct tlv_partition_header *header; @@ -585,24 +588,24 @@ hunt_nvram_read_tlv_partition( size_t total_length; uint32_t cksum; int pos; - int rc; + efx_rc_t rc; - EFX_STATIC_ASSERT(sizeof (*header) <= HUNTINGTON_NVRAM_CHUNK); + EFX_STATIC_ASSERT(sizeof (*header) <= EF10_NVRAM_CHUNK); - if ((partn_data == NULL) || (partn_size == 0)) { + if ((seg_data == NULL) || (max_seg_size == 0)) { rc = EINVAL; goto fail1; } - /* Read initial chunk of partition */ - if ((rc = hunt_nvram_partn_read(enp, partn, 0, partn_data, - HUNTINGTON_NVRAM_CHUNK)) != 0) { + /* Read initial chunk of the segment, starting at offset */ + if ((rc = ef10_nvram_partn_read(enp, partn, seg_offset, seg_data, + EF10_NVRAM_CHUNK)) != 0) { goto fail2; } - /* The partition header must be the first item (at offset zero) */ - if ((rc = tlv_init_cursor_from_size(&cursor, partn_data, - partn_size)) != 0) { + /* A PARTITION_HEADER tag must be the first item at the given offset */ + if ((rc = tlv_init_cursor_from_size(&cursor, (uint8_t *)seg_data, + max_seg_size)) != 0) { rc = EFAULT; goto fail3; } @@ -612,23 +615,23 @@ hunt_nvram_read_tlv_partition( } header = (struct tlv_partition_header *)tlv_item(&cursor); - /* Check TLV partition length (includes the END tag) */ + /* Check TLV segment length (includes the END tag) */ total_length = __LE_TO_CPU_32(header->total_length); - if (total_length > partn_size) { + if (total_length > max_seg_size) { rc = EFBIG; goto fail5; } - /* Read the remaining partition content */ - if (total_length > HUNTINGTON_NVRAM_CHUNK) { - if ((rc = hunt_nvram_partn_read(enp, partn, - HUNTINGTON_NVRAM_CHUNK, - partn_data + HUNTINGTON_NVRAM_CHUNK, - total_length - HUNTINGTON_NVRAM_CHUNK)) != 0) + /* Read the remaining segment content */ + if (total_length > EF10_NVRAM_CHUNK) { + if ((rc = ef10_nvram_partn_read(enp, partn, + seg_offset + EF10_NVRAM_CHUNK, + seg_data + EF10_NVRAM_CHUNK, + total_length - EF10_NVRAM_CHUNK)) != 0) goto fail6; } - /* Check partition ends with PARTITION_TRAILER and END tags */ + /* Check segment ends with PARTITION_TRAILER and END tags */ if ((rc = tlv_find(&cursor, TLV_TAG_PARTITION_TRAILER)) != 0) { rc = EINVAL; goto fail7; @@ -644,7 +647,7 @@ hunt_nvram_read_tlv_partition( goto fail9; } - /* Check data read from partition is consistent */ + /* Check data read from segment is consistent */ if (trailer->generation != header->generation) { /* * The partition data may have been modified between successive @@ -656,10 +659,10 @@ hunt_nvram_read_tlv_partition( goto fail10; } - /* Verify partition checksum */ + /* Verify segment checksum */ cksum = 0; for (pos = 0; (size_t)pos < total_length; pos += sizeof (uint32_t)) { - cksum += *((uint32_t *)(partn_data + pos)); + cksum += *((uint32_t *)(seg_data + pos)); } if (cksum != 0) { rc = EINVAL; @@ -689,20 +692,20 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } /* * Read a single TLV item from a host memory - * buffer containing a TLV formatted partition. + * buffer containing a TLV formatted segment. */ - __checkReturn int -hunt_nvram_buf_read_tlv( + __checkReturn efx_rc_t +ef10_nvram_buf_read_tlv( __in efx_nic_t *enp, - __in_bcount(partn_size) caddr_t partn_data, - __in size_t partn_size, + __in_bcount(max_seg_size) caddr_t seg_data, + __in size_t max_seg_size, __in uint32_t tag, __deref_out_bcount_opt(*sizep) caddr_t *datap, __out size_t *sizep) @@ -711,16 +714,16 @@ hunt_nvram_buf_read_tlv( caddr_t data; size_t length; caddr_t value; - int rc; + efx_rc_t rc; - if ((partn_data == NULL) || (partn_size == 0)) { + if ((seg_data == NULL) || (max_seg_size == 0)) { rc = EINVAL; goto fail1; } - /* Find requested TLV tag in partition data */ - if ((rc = tlv_init_cursor_from_size(&cursor, partn_data, - partn_size)) != 0) { + /* Find requested TLV tag in segment data */ + if ((rc = tlv_init_cursor_from_size(&cursor, (uint8_t *)seg_data, + max_seg_size)) != 0) { rc = EFAULT; goto fail2; } @@ -728,7 +731,7 @@ hunt_nvram_buf_read_tlv( rc = ENOENT; goto fail3; } - value = tlv_value(&cursor); + value = (caddr_t)tlv_value(&cursor); length = tlv_length(&cursor); if (length == 0) @@ -755,31 +758,29 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - - -/* Read a single TLV item from a TLV formatted partition */ - __checkReturn int -hunt_nvram_partn_read_tlv( - __in efx_nic_t *enp, - __in uint32_t partn, - __in uint32_t tag, - __deref_out_bcount_opt(*sizep) caddr_t *datap, - __out size_t *sizep) +/* Read a single TLV item from the first segment in a TLV formatted partition */ + __checkReturn efx_rc_t +ef10_nvram_partn_read_tlv( + __in efx_nic_t *enp, + __in uint32_t partn, + __in uint32_t tag, + __deref_out_bcount_opt(*seg_sizep) caddr_t *seg_datap, + __out size_t *seg_sizep) { - caddr_t partn_data = NULL; + caddr_t seg_data = NULL; size_t partn_size = 0; size_t length; caddr_t data; int retry; - int rc; + efx_rc_t rc; /* Allocate sufficient memory for the entire partition */ - if ((rc = hunt_nvram_partn_size(enp, partn, &partn_size)) != 0) + if ((rc = ef10_nvram_partn_size(enp, partn, &partn_size)) != 0) goto fail1; if (partn_size == 0) { @@ -787,39 +788,39 @@ hunt_nvram_partn_read_tlv( goto fail2; } - EFSYS_KMEM_ALLOC(enp->en_esip, partn_size, partn_data); - if (partn_data == NULL) { + EFSYS_KMEM_ALLOC(enp->en_esip, partn_size, seg_data); + if (seg_data == NULL) { rc = ENOMEM; goto fail3; } /* - * Read the entire TLV partition. Retry until consistent partition - * contents are returned. Inconsistent data may be read if: - * a) the partition contents are invalid + * Read the first segment in a TLV partition. Retry until consistent + * segment contents are returned. Inconsistent data may be read if: + * a) the segment contents are invalid * b) the MC has rebooted while we were reading the partition * c) the partition has been modified while we were reading it * Limit retry attempts to ensure forward progress. */ retry = 10; do { - rc = hunt_nvram_read_tlv_partition(enp, partn, - partn_data, partn_size); + rc = ef10_nvram_read_tlv_segment(enp, partn, 0, + seg_data, partn_size); } while ((rc == EAGAIN) && (--retry > 0)); if (rc != 0) { - /* Failed to obtain consistent partition data */ + /* Failed to obtain consistent segment data */ goto fail4; } - if ((rc = hunt_nvram_buf_read_tlv(enp, partn_data, partn_size, + if ((rc = ef10_nvram_buf_read_tlv(enp, seg_data, partn_size, tag, &data, &length)) != 0) goto fail5; - EFSYS_KMEM_FREE(enp->en_esip, partn_size, partn_data); + EFSYS_KMEM_FREE(enp->en_esip, partn_size, seg_data); - *datap = data; - *sizep = length; + *seg_datap = data; + *seg_sizep = length; return (0); @@ -828,25 +829,153 @@ fail5: fail4: EFSYS_PROBE(fail4); - EFSYS_KMEM_FREE(enp->en_esip, partn_size, partn_data); + EFSYS_KMEM_FREE(enp->en_esip, partn_size, seg_data); fail3: EFSYS_PROBE(fail3); fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); + + return (rc); +} + +/* Compute the size of a segment. */ + static __checkReturn efx_rc_t +ef10_nvram_buf_segment_size( + __in caddr_t seg_data, + __in size_t max_seg_size, + __out size_t *seg_sizep) +{ + efx_rc_t rc; + tlv_cursor_t cursor; + struct tlv_partition_header *header; + uint32_t cksum; + int pos; + uint32_t *end_tag_position; + uint32_t segment_length; + + /* A PARTITION_HEADER tag must be the first item at the given offset */ + if ((rc = tlv_init_cursor_from_size(&cursor, (uint8_t *)seg_data, + max_seg_size)) != 0) { + rc = EFAULT; + goto fail1; + } + if (tlv_tag(&cursor) != TLV_TAG_PARTITION_HEADER) { + rc = EINVAL; + goto fail2; + } + header = (struct tlv_partition_header *)tlv_item(&cursor); + + /* Check TLV segment length (includes the END tag) */ + *seg_sizep = __LE_TO_CPU_32(header->total_length); + if (*seg_sizep > max_seg_size) { + rc = EFBIG; + goto fail3; + } + + /* Check segment ends with PARTITION_TRAILER and END tags */ + if ((rc = tlv_find(&cursor, TLV_TAG_PARTITION_TRAILER)) != 0) { + rc = EINVAL; + goto fail4; + } + + if ((rc = tlv_advance(&cursor)) != 0) { + rc = EINVAL; + goto fail5; + } + if (tlv_tag(&cursor) != TLV_TAG_END) { + rc = EINVAL; + goto fail6; + } + end_tag_position = cursor.current; + + /* Verify segment checksum */ + cksum = 0; + for (pos = 0; (size_t)pos < *seg_sizep; pos += sizeof (uint32_t)) { + cksum += *((uint32_t *)(seg_data + pos)); + } + if (cksum != 0) { + rc = EINVAL; + goto fail7; + } + + /* + * Calculate total length from HEADER to END tags and compare to + * max_seg_size and the total_length field in the HEADER tag. + */ + segment_length = tlv_block_length_used(&cursor); + + if (segment_length > max_seg_size) { + rc = EINVAL; + goto fail8; + } + + if (segment_length != *seg_sizep) { + rc = EINVAL; + goto fail9; + } + + /* Skip over the first HEADER tag. */ + rc = tlv_rewind(&cursor); + rc = tlv_advance(&cursor); + + while (rc == 0) { + if (tlv_tag(&cursor) == TLV_TAG_END) { + /* Check that the END tag is the one found earlier. */ + if (cursor.current != end_tag_position) + goto fail10; + break; + } + /* Check for duplicate HEADER tags before the END tag. */ + if (tlv_tag(&cursor) == TLV_TAG_PARTITION_HEADER) { + rc = EINVAL; + goto fail11; + } + + rc = tlv_advance(&cursor); + } + if (rc != 0) + goto fail12; + + return (0); + +fail12: + EFSYS_PROBE(fail12); +fail11: + EFSYS_PROBE(fail11); +fail10: + EFSYS_PROBE(fail10); +fail9: + EFSYS_PROBE(fail9); +fail8: + EFSYS_PROBE(fail8); +fail7: + EFSYS_PROBE(fail7); +fail6: + EFSYS_PROBE(fail6); +fail5: + EFSYS_PROBE(fail5); +fail4: + EFSYS_PROBE(fail4); +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); +fail1: + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } /* * Add or update a single TLV item in a host memory buffer containing a TLV - * formatted partition. + * formatted segment. Historically partitions consisted of only one segment. */ - __checkReturn int -hunt_nvram_buf_write_tlv( - __inout_bcount(partn_size) caddr_t partn_data, - __in size_t partn_size, + __checkReturn efx_rc_t +ef10_nvram_buf_write_tlv( + __inout_bcount(max_seg_size) caddr_t seg_data, + __in size_t max_seg_size, __in uint32_t tag, __in_bcount(tag_size) caddr_t tag_data, __in size_t tag_size, @@ -858,11 +987,11 @@ hunt_nvram_buf_write_tlv( uint32_t generation; uint32_t cksum; int pos; - int rc; + efx_rc_t rc; - /* The partition header must be the first item (at offset zero) */ - if ((rc = tlv_init_cursor_from_size(&cursor, partn_data, - partn_size)) != 0) { + /* A PARTITION_HEADER tag must be the first item (at offset zero) */ + if ((rc = tlv_init_cursor_from_size(&cursor, (uint8_t *)seg_data, + max_seg_size)) != 0) { rc = EFAULT; goto fail1; } @@ -876,7 +1005,7 @@ hunt_nvram_buf_write_tlv( if ((rc = tlv_find(&cursor, tag)) == 0) { /* Modify existing TLV item */ if ((rc = tlv_modify(&cursor, tag, - tag_data, tag_size)) != 0) + (uint8_t *)tag_data, tag_size)) != 0) goto fail3; } else { /* Insert a new TLV item before the PARTITION_TRAILER */ @@ -886,7 +1015,7 @@ hunt_nvram_buf_write_tlv( goto fail4; } if ((rc = tlv_insert(&cursor, tag, - tag_data, tag_size)) != 0) { + (uint8_t *)tag_data, tag_size)) != 0) { rc = EINVAL; goto fail5; } @@ -901,7 +1030,10 @@ hunt_nvram_buf_write_tlv( /* Update PARTITION_HEADER and PARTITION_TRAILER fields */ *total_lengthp = tlv_block_length_used(&cursor); - EFSYS_ASSERT3U(*total_lengthp, <=, partn_size); + if (*total_lengthp > max_seg_size) { + rc = ENOSPC; + goto fail7; + } generation = __LE_TO_CPU_32(header->generation) + 1; header->total_length = __CPU_TO_LE_32(*total_lengthp); @@ -912,12 +1044,14 @@ hunt_nvram_buf_write_tlv( trailer->checksum = 0; cksum = 0; for (pos = 0; (size_t)pos < *total_lengthp; pos += sizeof (uint32_t)) { - cksum += *((uint32_t *)(partn_data + pos)); + cksum += *((uint32_t *)(seg_data + pos)); } trailer->checksum = ~cksum + 1; return (0); +fail7: + EFSYS_PROBE(fail7); fail6: EFSYS_PROBE(fail6); fail5: @@ -929,29 +1063,137 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -/* Add or update a single TLV item in a TLV formatted partition */ - __checkReturn int -hunt_nvram_partn_write_tlv( +/* + * Add or update a single TLV item in the first segment of a TLV formatted + * dynamic config partition. The first segment is the current active + * configuration. + */ + __checkReturn efx_rc_t +ef10_nvram_partn_write_tlv( __in efx_nic_t *enp, __in uint32_t partn, __in uint32_t tag, __in_bcount(size) caddr_t data, __in size_t size) { - size_t partn_size; + return ef10_nvram_partn_write_segment_tlv(enp, partn, tag, data, + size, B_FALSE); +} + +/* + * Read a segment from nvram at the given offset into a buffer (segment_data) + * and optionally write a new tag to it. + */ + static __checkReturn efx_rc_t +ef10_nvram_segment_write_tlv( + __in efx_nic_t *enp, + __in uint32_t partn, + __in uint32_t tag, + __in_bcount(size) caddr_t data, + __in size_t size, + __inout caddr_t *seg_datap, + __inout size_t *partn_offsetp, + __inout size_t *src_remain_lenp, + __inout size_t *dest_remain_lenp, + __in boolean_t write) +{ + efx_rc_t rc; + efx_rc_t status; + size_t original_segment_size; + size_t modified_segment_size; + + /* + * Read the segment from NVRAM into the segment_data buffer and validate + * it, returning if it does not validate. This is not a failure unless + * this is the first segment in a partition. In this case the caller + * must propogate the error. + */ + status = ef10_nvram_read_tlv_segment(enp, partn, *partn_offsetp, + *seg_datap, *src_remain_lenp); + if (status != 0) + return (EINVAL); + + status = ef10_nvram_buf_segment_size(*seg_datap, + *src_remain_lenp, &original_segment_size); + if (status != 0) + return (EINVAL); + + if (write) { + /* Update the contents of the segment in the buffer */ + if ((rc = ef10_nvram_buf_write_tlv(*seg_datap, + *dest_remain_lenp, tag, data, size, + &modified_segment_size)) != 0) + goto fail1; + *dest_remain_lenp -= modified_segment_size; + *seg_datap += modified_segment_size; + } else { + /* + * We won't modify this segment, but still need to update the + * remaining lengths and pointers. + */ + *dest_remain_lenp -= original_segment_size; + *seg_datap += original_segment_size; + } + + *partn_offsetp += original_segment_size; + *src_remain_lenp -= original_segment_size; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, efx_rc_t, rc); + + return (rc); +} + +/* + * Add or update a single TLV item in either the first segment or in all + * segments in a TLV formatted dynamic config partition. Dynamic config + * partitions on boards that support RFID are divided into a number of segments, + * each formatted like a partition, with header, trailer and end tags. The first + * segment is the current active configuration. + * + * The segments are initialised by manftest and each contain a different + * configuration e.g. firmware variant. The firmware can be instructed + * via RFID to copy a segment to replace the first segment, hence changing the + * active configuration. This allows ops to change the configuration of a board + * prior to shipment using RFID. + * + * Changes to the dynamic config may need to be written to all segments (e.g. + * firmware versions) or just the first segment (changes to the active + * configuration). See SF-111324-SW "The use of RFID in Solarflare Products". + * If only the first segment is written the code still needs to be aware of the + * possible presence of subsequent segments as writing to a segment may cause + * its size to increase, which would overwrite the subsequent segments and + * invalidate them. + */ + __checkReturn efx_rc_t +ef10_nvram_partn_write_segment_tlv( + __in efx_nic_t *enp, + __in uint32_t partn, + __in uint32_t tag, + __in_bcount(size) caddr_t data, + __in size_t size, + __in boolean_t all_segments) +{ + size_t partn_size = 0; caddr_t partn_data; - size_t total_length; - int rc; + size_t total_length = 0; + efx_rc_t rc; + size_t current_offset = 0; + size_t remaining_original_length; + size_t remaining_modified_length; + caddr_t segment_data; EFSYS_ASSERT3U(partn, ==, NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG); /* Allocate sufficient memory for the entire partition */ - if ((rc = hunt_nvram_partn_size(enp, partn, &partn_size)) != 0) + if ((rc = ef10_nvram_partn_size(enp, partn, &partn_size)) != 0) goto fail1; EFSYS_KMEM_ALLOC(enp->en_esip, partn_size, partn_data); @@ -960,33 +1202,55 @@ hunt_nvram_partn_write_tlv( goto fail2; } + remaining_original_length = partn_size; + remaining_modified_length = partn_size; + segment_data = partn_data; + /* Lock the partition */ - if ((rc = hunt_nvram_partn_lock(enp, partn)) != 0) + if ((rc = ef10_nvram_partn_lock(enp, partn)) != 0) goto fail3; - /* Read the partition contents (no need to retry when locked). */ - if ((rc = hunt_nvram_read_tlv_partition(enp, partn, - partn_data, partn_size)) != 0) { - /* Failed to obtain consistent partition data */ - goto fail4; - } + /* Iterate over each (potential) segment to update it. */ + do { + boolean_t write = all_segments || current_offset == 0; + + rc = ef10_nvram_segment_write_tlv(enp, partn, tag, data, size, + &segment_data, ¤t_offset, &remaining_original_length, + &remaining_modified_length, write); + if (rc != 0) { + if (current_offset == 0) { + /* + * If no data has been read then the first + * segment is invalid, which is an error. + */ + goto fail4; + } + break; + } + } while (current_offset < partn_size); + + total_length = segment_data - partn_data; - /* Update the contents in memory */ - if ((rc = hunt_nvram_buf_write_tlv(partn_data, partn_size, - tag, data, size, &total_length)) != 0) + /* + * We've run out of space. This should actually be dealt with by + * ef10_nvram_buf_write_tlv returning ENOSPC. + */ + if (total_length > partn_size) { + rc = ENOSPC; goto fail5; + } - /* Erase the whole partition */ - if ((rc = hunt_nvram_partn_erase(enp, partn, 0, partn_size)) != 0) + /* Erase the whole partition in NVRAM */ + if ((rc = ef10_nvram_partn_erase(enp, partn, 0, partn_size)) != 0) goto fail6; - /* Write new partition contents to NVRAM */ - if ((rc = hunt_nvram_partn_write(enp, partn, 0, partn_data, + /* Write new partition contents from the buffer to NVRAM */ + if ((rc = ef10_nvram_partn_write(enp, partn, 0, partn_data, total_length)) != 0) goto fail7; /* Unlock the partition */ - hunt_nvram_partn_unlock(enp, partn); + ef10_nvram_partn_unlock(enp, partn); EFSYS_KMEM_FREE(enp->en_esip, partn_size, partn_data); @@ -1001,7 +1265,7 @@ fail5: fail4: EFSYS_PROBE(fail4); - hunt_nvram_partn_unlock(enp, partn); + ef10_nvram_partn_unlock(enp, partn); fail3: EFSYS_PROBE(fail3); @@ -1009,36 +1273,41 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_nvram_partn_size( +/* + * Get the size of a NVRAM partition. This is the total size allocated in nvram, + * not the data used by the segments in the partition. + */ + __checkReturn efx_rc_t +ef10_nvram_partn_size( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __out size_t *sizep) { - int rc; + efx_rc_t rc; - if ((rc = efx_mcdi_nvram_info(enp, partn, sizep, NULL, NULL)) != 0) + if ((rc = efx_mcdi_nvram_info(enp, partn, sizep, + NULL, NULL, NULL)) != 0) goto fail1; return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_nvram_partn_lock( + __checkReturn efx_rc_t +ef10_nvram_partn_lock( __in efx_nic_t *enp, - __in unsigned int partn) + __in uint32_t partn) { - int rc; + efx_rc_t rc; if ((rc = efx_mcdi_nvram_update_start(enp, partn)) != 0) goto fail1; @@ -1046,24 +1315,24 @@ hunt_nvram_partn_lock( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_nvram_partn_read( + __checkReturn efx_rc_t +ef10_nvram_partn_read( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __in unsigned int offset, __out_bcount(size) caddr_t data, __in size_t size) { size_t chunk; - int rc; + efx_rc_t rc; while (size > 0) { - chunk = MIN(size, HUNTINGTON_NVRAM_CHUNK); + chunk = MIN(size, EF10_NVRAM_CHUNK); if ((rc = efx_mcdi_nvram_read(enp, partn, offset, data, chunk)) != 0) { @@ -1078,48 +1347,91 @@ hunt_nvram_partn_read( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_nvram_partn_erase( + __checkReturn efx_rc_t +ef10_nvram_partn_erase( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __in unsigned int offset, __in size_t size) { - int rc; + efx_rc_t rc; + uint32_t erase_size; - if ((rc = efx_mcdi_nvram_erase(enp, partn, offset, size)) != 0) + if ((rc = efx_mcdi_nvram_info(enp, partn, NULL, NULL, + &erase_size, NULL)) != 0) goto fail1; + if (erase_size == 0) { + if ((rc = efx_mcdi_nvram_erase(enp, partn, offset, size)) != 0) + goto fail2; + } else { + if (size % erase_size != 0) { + rc = EINVAL; + goto fail3; + } + while (size > 0) { + if ((rc = efx_mcdi_nvram_erase(enp, partn, offset, + erase_size)) != 0) + goto fail4; + offset += erase_size; + size -= erase_size; + } + } + return (0); +fail4: + EFSYS_PROBE(fail4); +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_nvram_partn_write( + __checkReturn efx_rc_t +ef10_nvram_partn_write( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __in unsigned int offset, __out_bcount(size) caddr_t data, __in size_t size) { size_t chunk; - int rc; + uint32_t write_size; + efx_rc_t rc; + + if ((rc = efx_mcdi_nvram_info(enp, partn, NULL, NULL, + NULL, &write_size)) != 0) + goto fail1; + + if (write_size != 0) { + /* + * Check that the size is a multiple of the write chunk size if + * the write chunk size is available. + */ + if (size % write_size != 0) { + rc = EINVAL; + goto fail2; + } + } else { + write_size = EF10_NVRAM_CHUNK; + } while (size > 0) { - chunk = MIN(size, HUNTINGTON_NVRAM_CHUNK); + chunk = MIN(size, write_size); if ((rc = efx_mcdi_nvram_write(enp, partn, offset, data, chunk)) != 0) { - goto fail1; + goto fail3; } size -= chunk; @@ -1129,19 +1441,23 @@ hunt_nvram_partn_write( return (0); +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } void -hunt_nvram_partn_unlock( +ef10_nvram_partn_unlock( __in efx_nic_t *enp, - __in unsigned int partn) + __in uint32_t partn) { boolean_t reboot; - int rc; + efx_rc_t rc; reboot = B_FALSE; if ((rc = efx_mcdi_nvram_update_finish(enp, partn, reboot)) != 0) @@ -1150,18 +1466,18 @@ hunt_nvram_partn_unlock( return; fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); } - __checkReturn int -hunt_nvram_partn_set_version( + __checkReturn efx_rc_t +ef10_nvram_partn_set_version( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __in_ecount(4) uint16_t version[4]) { struct tlv_partition_version partn_version; size_t size; - int rc; + efx_rc_t rc; /* Add or modify partition version TLV item */ partn_version.version_w = __CPU_TO_LE_16(version[0]); @@ -1171,16 +1487,17 @@ hunt_nvram_partn_set_version( size = sizeof (partn_version) - (2 * sizeof (uint32_t)); - if ((rc = hunt_nvram_partn_write_tlv(enp, + /* Write the version number to all segments in the partition */ + if ((rc = ef10_nvram_partn_write_segment_tlv(enp, NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, TLV_TAG_PARTITION_VERSION(partn), - (caddr_t)&partn_version.version_w, size)) != 0) + (caddr_t)&partn_version.version_w, size, B_TRUE)) != 0) goto fail1; return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -1189,14 +1506,14 @@ fail1: #if EFSYS_OPT_NVRAM -typedef struct hunt_parttbl_entry_s { +typedef struct ef10_parttbl_entry_s { unsigned int partn; unsigned int port; efx_nvram_type_t nvtype; -} hunt_parttbl_entry_t; +} ef10_parttbl_entry_t; /* Translate EFX NVRAM types to firmware partition types */ -static hunt_parttbl_entry_t hunt_parttbl[] = { +static ef10_parttbl_entry_t hunt_parttbl[] = { {NVRAM_PARTITION_TYPE_MC_FIRMWARE, 1, EFX_NVRAM_MC_FIRMWARE}, {NVRAM_PARTITION_TYPE_MC_FIRMWARE, 2, EFX_NVRAM_MC_FIRMWARE}, {NVRAM_PARTITION_TYPE_MC_FIRMWARE, 3, EFX_NVRAM_MC_FIRMWARE}, @@ -1216,47 +1533,143 @@ static hunt_parttbl_entry_t hunt_parttbl[] = { {NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 1, EFX_NVRAM_DYNAMIC_CFG}, {NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 2, EFX_NVRAM_DYNAMIC_CFG}, {NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 3, EFX_NVRAM_DYNAMIC_CFG}, - {NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 4, EFX_NVRAM_DYNAMIC_CFG} + {NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 4, EFX_NVRAM_DYNAMIC_CFG}, + {NVRAM_PARTITION_TYPE_FPGA, 1, EFX_NVRAM_FPGA}, + {NVRAM_PARTITION_TYPE_FPGA, 2, EFX_NVRAM_FPGA}, + {NVRAM_PARTITION_TYPE_FPGA, 3, EFX_NVRAM_FPGA}, + {NVRAM_PARTITION_TYPE_FPGA, 4, EFX_NVRAM_FPGA}, + {NVRAM_PARTITION_TYPE_FPGA_BACKUP, 1, EFX_NVRAM_FPGA_BACKUP}, + {NVRAM_PARTITION_TYPE_FPGA_BACKUP, 2, EFX_NVRAM_FPGA_BACKUP}, + {NVRAM_PARTITION_TYPE_FPGA_BACKUP, 3, EFX_NVRAM_FPGA_BACKUP}, + {NVRAM_PARTITION_TYPE_FPGA_BACKUP, 4, EFX_NVRAM_FPGA_BACKUP} }; -static __checkReturn hunt_parttbl_entry_t * -hunt_parttbl_entry( +static ef10_parttbl_entry_t medford_parttbl[] = { + {NVRAM_PARTITION_TYPE_MC_FIRMWARE, 1, EFX_NVRAM_MC_FIRMWARE}, + {NVRAM_PARTITION_TYPE_MC_FIRMWARE, 2, EFX_NVRAM_MC_FIRMWARE}, + {NVRAM_PARTITION_TYPE_MC_FIRMWARE, 3, EFX_NVRAM_MC_FIRMWARE}, + {NVRAM_PARTITION_TYPE_MC_FIRMWARE, 4, EFX_NVRAM_MC_FIRMWARE}, + {NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 1, EFX_NVRAM_MC_GOLDEN}, + {NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 2, EFX_NVRAM_MC_GOLDEN}, + {NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 3, EFX_NVRAM_MC_GOLDEN}, + {NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 4, EFX_NVRAM_MC_GOLDEN}, + {NVRAM_PARTITION_TYPE_EXPANSION_ROM, 1, EFX_NVRAM_BOOTROM}, + {NVRAM_PARTITION_TYPE_EXPANSION_ROM, 2, EFX_NVRAM_BOOTROM}, + {NVRAM_PARTITION_TYPE_EXPANSION_ROM, 3, EFX_NVRAM_BOOTROM}, + {NVRAM_PARTITION_TYPE_EXPANSION_ROM, 4, EFX_NVRAM_BOOTROM}, + {NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 1, EFX_NVRAM_BOOTROM_CFG}, + {NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 2, EFX_NVRAM_BOOTROM_CFG}, + {NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 3, EFX_NVRAM_BOOTROM_CFG}, + {NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 4, EFX_NVRAM_BOOTROM_CFG}, + {NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 1, EFX_NVRAM_DYNAMIC_CFG}, + {NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 2, EFX_NVRAM_DYNAMIC_CFG}, + {NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 3, EFX_NVRAM_DYNAMIC_CFG}, + {NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 4, EFX_NVRAM_DYNAMIC_CFG}, + {NVRAM_PARTITION_TYPE_FPGA, 1, EFX_NVRAM_FPGA}, + {NVRAM_PARTITION_TYPE_FPGA, 2, EFX_NVRAM_FPGA}, + {NVRAM_PARTITION_TYPE_FPGA, 3, EFX_NVRAM_FPGA}, + {NVRAM_PARTITION_TYPE_FPGA, 4, EFX_NVRAM_FPGA}, + {NVRAM_PARTITION_TYPE_FPGA_BACKUP, 1, EFX_NVRAM_FPGA_BACKUP}, + {NVRAM_PARTITION_TYPE_FPGA_BACKUP, 2, EFX_NVRAM_FPGA_BACKUP}, + {NVRAM_PARTITION_TYPE_FPGA_BACKUP, 3, EFX_NVRAM_FPGA_BACKUP}, + {NVRAM_PARTITION_TYPE_FPGA_BACKUP, 4, EFX_NVRAM_FPGA_BACKUP} +}; + +static __checkReturn efx_rc_t +ef10_parttbl_get( __in efx_nic_t *enp, - __in efx_nvram_type_t type) + __out ef10_parttbl_entry_t **parttblp, + __out size_t *parttbl_rowsp) +{ + switch (enp->en_family) { + case EFX_FAMILY_HUNTINGTON: + *parttblp = hunt_parttbl; + *parttbl_rowsp = EFX_ARRAY_SIZE(hunt_parttbl); + break; + + case EFX_FAMILY_MEDFORD: + *parttblp = medford_parttbl; + *parttbl_rowsp = EFX_ARRAY_SIZE(medford_parttbl); + break; + + default: + EFSYS_ASSERT(B_FALSE); + return (EINVAL); + } + return (0); +} + + __checkReturn efx_rc_t +ef10_nvram_type_to_partn( + __in efx_nic_t *enp, + __in efx_nvram_type_t type, + __out uint32_t *partnp) { efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); - hunt_parttbl_entry_t *entry; - int i; + ef10_parttbl_entry_t *parttbl = NULL; + size_t parttbl_rows = 0; + unsigned int i; EFSYS_ASSERT3U(type, <, EFX_NVRAM_NTYPES); + EFSYS_ASSERT(partnp != NULL); - for (i = 0; i < EFX_ARRAY_SIZE(hunt_parttbl); i++) { - entry = &hunt_parttbl[i]; + if (ef10_parttbl_get(enp, &parttbl, &parttbl_rows) == 0) { + for (i = 0; i < parttbl_rows; i++) { + ef10_parttbl_entry_t *entry = &parttbl[i]; - if (entry->port == emip->emi_port && entry->nvtype == type) - return (entry); + if (entry->nvtype == type && + entry->port == emip->emi_port) { + *partnp = entry->partn; + return (0); + } + } } - return (NULL); + return (ENOTSUP); } - #if EFSYS_OPT_DIAG - __checkReturn int -hunt_nvram_test( - __in efx_nic_t *enp) +static __checkReturn efx_rc_t +ef10_nvram_partn_to_type( + __in efx_nic_t *enp, + __in uint32_t partn, + __out efx_nvram_type_t *typep) { efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); - hunt_parttbl_entry_t *entry; + ef10_parttbl_entry_t *parttbl = NULL; + size_t parttbl_rows = 0; + unsigned int i; + + EFSYS_ASSERT(typep != NULL); + + if (ef10_parttbl_get(enp, &parttbl, &parttbl_rows) == 0) { + for (i = 0; i < parttbl_rows; i++) { + ef10_parttbl_entry_t *entry = &parttbl[i]; + + if (entry->partn == partn && + entry->port == emip->emi_port) { + *typep = entry->nvtype; + return (0); + } + } + } + + return (ENOTSUP); +} + + __checkReturn efx_rc_t +ef10_nvram_test( + __in efx_nic_t *enp) +{ + efx_nvram_type_t type; unsigned int npartns = 0; uint32_t *partns = NULL; size_t size; - int i; - unsigned int j; - int rc; + unsigned int i; + efx_rc_t rc; - /* Find supported partitions */ + /* Read available partitions from NVRAM partition map */ size = MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM * sizeof (uint32_t); EFSYS_KMEM_ALLOC(enp->en_esip, size, partns); if (partns == NULL) { @@ -1269,23 +1682,13 @@ hunt_nvram_test( goto fail2; } - /* - * Iterate over the list of supported partition types - * applicable to *this* port - */ - for (i = 0; i < EFX_ARRAY_SIZE(hunt_parttbl); i++) { - entry = &hunt_parttbl[i]; - - if (entry->port != emip->emi_port) + for (i = 0; i < npartns; i++) { + /* Check if the partition is supported for this port */ + if ((rc = ef10_nvram_partn_to_type(enp, partns[i], &type)) != 0) continue; - for (j = 0; j < npartns; j++) { - if (entry->partn == partns[j]) { - rc = efx_mcdi_nvram_test(enp, entry->partn); - if (rc != 0) - goto fail3; - } - } + if ((rc = efx_mcdi_nvram_test(enp, partns[i])) != 0) + goto fail3; } EFSYS_KMEM_FREE(enp->en_esip, size, partns); @@ -1297,29 +1700,25 @@ fail2: EFSYS_PROBE(fail2); EFSYS_KMEM_FREE(enp->en_esip, size, partns); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } #endif /* EFSYS_OPT_DIAG */ - __checkReturn int -hunt_nvram_size( + __checkReturn efx_rc_t +ef10_nvram_size( __in efx_nic_t *enp, __in efx_nvram_type_t type, __out size_t *sizep) { - hunt_parttbl_entry_t *entry; uint32_t partn; - int rc; + efx_rc_t rc; - if ((entry = hunt_parttbl_entry(enp, type)) == NULL) { - rc = ENOTSUP; + if ((rc = ef10_nvram_type_to_partn(enp, type, &partn)) != 0) goto fail1; - } - partn = entry->partn; - if ((rc = hunt_nvram_partn_size(enp, partn, sizep)) != 0) + if ((rc = ef10_nvram_partn_size(enp, partn, sizep)) != 0) goto fail2; return (0); @@ -1327,29 +1726,25 @@ hunt_nvram_size( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); *sizep = 0; return (rc); } - __checkReturn int -hunt_nvram_get_version( + __checkReturn efx_rc_t +ef10_nvram_get_version( __in efx_nic_t *enp, __in efx_nvram_type_t type, __out uint32_t *subtypep, __out_ecount(4) uint16_t version[4]) { - hunt_parttbl_entry_t *entry; uint32_t partn; - int rc; + efx_rc_t rc; - if ((entry = hunt_parttbl_entry(enp, type)) == NULL) { - rc = ENOTSUP; + if ((rc = ef10_nvram_type_to_partn(enp, type, &partn)) != 0) goto fail1; - } - partn = entry->partn; /* FIXME: get highest partn version from all ports */ /* FIXME: return partn description if available */ @@ -1363,61 +1758,54 @@ hunt_nvram_get_version( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_nvram_rw_start( + __checkReturn efx_rc_t +ef10_nvram_rw_start( __in efx_nic_t *enp, __in efx_nvram_type_t type, __out size_t *chunk_sizep) { - hunt_parttbl_entry_t *entry; uint32_t partn; - int rc; + efx_rc_t rc; - if ((entry = hunt_parttbl_entry(enp, type)) == NULL) { - rc = ENOTSUP; + if ((rc = ef10_nvram_type_to_partn(enp, type, &partn)) != 0) goto fail1; - } - partn = entry->partn; - if ((rc = hunt_nvram_partn_lock(enp, partn)) != 0) + if ((rc = ef10_nvram_partn_lock(enp, partn)) != 0) goto fail2; if (chunk_sizep != NULL) - *chunk_sizep = HUNTINGTON_NVRAM_CHUNK; + *chunk_sizep = EF10_NVRAM_CHUNK; return (0); fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_nvram_read_chunk( + __checkReturn efx_rc_t +ef10_nvram_read_chunk( __in efx_nic_t *enp, __in efx_nvram_type_t type, __in unsigned int offset, __out_bcount(size) caddr_t data, __in size_t size) { - hunt_parttbl_entry_t *entry; - int rc; + uint32_t partn; + efx_rc_t rc; - if ((entry = hunt_parttbl_entry(enp, type)) == NULL) { - rc = ENOTSUP; + if ((rc = ef10_nvram_type_to_partn(enp, type, &partn)) != 0) goto fail1; - } - if ((rc = hunt_nvram_partn_read(enp, entry->partn, - offset, data, size)) != 0) + if ((rc = ef10_nvram_partn_read(enp, partn, offset, data, size)) != 0) goto fail2; return (0); @@ -1425,29 +1813,27 @@ hunt_nvram_read_chunk( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_nvram_erase( + __checkReturn efx_rc_t +ef10_nvram_erase( __in efx_nic_t *enp, __in efx_nvram_type_t type) { - hunt_parttbl_entry_t *entry; + uint32_t partn; size_t size; - int rc; + efx_rc_t rc; - if ((entry = hunt_parttbl_entry(enp, type)) == NULL) { - rc = ENOTSUP; + if ((rc = ef10_nvram_type_to_partn(enp, type, &partn)) != 0) goto fail1; - } - if ((rc = hunt_nvram_partn_size(enp, entry->partn, &size)) != 0) + if ((rc = ef10_nvram_partn_size(enp, partn, &size)) != 0) goto fail2; - if ((rc = hunt_nvram_partn_erase(enp, entry->partn, 0, size)) != 0) + if ((rc = ef10_nvram_partn_erase(enp, partn, 0, size)) != 0) goto fail3; return (0); @@ -1457,29 +1843,26 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_nvram_write_chunk( + __checkReturn efx_rc_t +ef10_nvram_write_chunk( __in efx_nic_t *enp, __in efx_nvram_type_t type, __in unsigned int offset, __in_bcount(size) caddr_t data, __in size_t size) { - hunt_parttbl_entry_t *entry; - int rc; + uint32_t partn; + efx_rc_t rc; - if ((entry = hunt_parttbl_entry(enp, type)) == NULL) { - rc = ENOTSUP; + if ((rc = ef10_nvram_type_to_partn(enp, type, &partn)) != 0) goto fail1; - } - if ((rc = hunt_nvram_partn_write(enp, entry->partn, - offset, data, size)) != 0) + if ((rc = ef10_nvram_partn_write(enp, partn, offset, data, size)) != 0) goto fail2; return (0); @@ -1487,48 +1870,44 @@ hunt_nvram_write_chunk( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } void -hunt_nvram_rw_finish( +ef10_nvram_rw_finish( __in efx_nic_t *enp, __in efx_nvram_type_t type) { - hunt_parttbl_entry_t *entry; + uint32_t partn; + efx_rc_t rc; - if ((entry = hunt_parttbl_entry(enp, type)) != NULL) - hunt_nvram_partn_unlock(enp, entry->partn); + if ((rc = ef10_nvram_type_to_partn(enp, type, &partn)) == 0) + ef10_nvram_partn_unlock(enp, partn); } - __checkReturn int -hunt_nvram_set_version( + __checkReturn efx_rc_t +ef10_nvram_set_version( __in efx_nic_t *enp, __in efx_nvram_type_t type, __in_ecount(4) uint16_t version[4]) { - hunt_parttbl_entry_t *entry; - unsigned int partn; - int rc; + uint32_t partn; + efx_rc_t rc; - if ((entry = hunt_parttbl_entry(enp, type)) == NULL) { - rc = ENOTSUP; + if ((rc = ef10_nvram_type_to_partn(enp, type, &partn)) != 0) goto fail1; - } - partn = entry->partn; - if ((rc = hunt_nvram_partn_set_version(enp, partn, version)) != 0) + if ((rc = ef10_nvram_partn_set_version(enp, partn, version)) != 0) goto fail2; return (0); fail2: EFSYS_PROBE(fail2); - fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } diff --git a/sys/dev/sfxge/common/hunt_phy.c b/sys/dev/sfxge/common/hunt_phy.c index 1cffea2..c25e820 100644 --- a/sys/dev/sfxge/common/hunt_phy.c +++ b/sys/dev/sfxge/common/hunt_phy.c @@ -31,7 +31,6 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" #include "efx_impl.h" @@ -191,14 +190,14 @@ hunt_phy_link_ev( *link_modep = link_mode; } - __checkReturn int + __checkReturn efx_rc_t hunt_phy_power( __in efx_nic_t *enp, __in boolean_t power) { /* TBD: consider common Siena/Hunt function: essentially identical */ - int rc; + efx_rc_t rc; if (!power) return (0); @@ -212,12 +211,12 @@ hunt_phy_power( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t hunt_phy_get_link( __in efx_nic_t *enp, __out hunt_link_state_t *hlsp) @@ -231,7 +230,7 @@ hunt_phy_get_link( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_GET_LINK_IN_LEN, MC_CMD_GET_LINK_OUT_LEN)]; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_GET_LINK; @@ -293,12 +292,12 @@ hunt_phy_get_link( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t hunt_phy_reconfigure( __in efx_nic_t *enp) { @@ -316,7 +315,7 @@ hunt_phy_reconfigure( uint32_t cap_mask; unsigned int led_mode; unsigned int speed; - int rc; + efx_rc_t rc; if (~encp->enc_func_flags & EFX_NIC_FUNC_LINKCTRL) goto out; @@ -423,12 +422,12 @@ out: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t hunt_phy_verify( __in efx_nic_t *enp) { @@ -438,7 +437,7 @@ hunt_phy_verify( uint8_t payload[MAX(MC_CMD_GET_PHY_STATE_IN_LEN, MC_CMD_GET_PHY_STATE_OUT_LEN)]; uint32_t state; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_GET_PHY_STATE; @@ -474,12 +473,12 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t hunt_phy_oui_get( __in efx_nic_t *enp, __out uint32_t *ouip) @@ -491,11 +490,11 @@ hunt_phy_oui_get( #if EFSYS_OPT_PHY_STATS - __checkReturn int + __checkReturn efx_rc_t hunt_phy_stats_update( __in efx_nic_t *enp, __in efsys_mem_t *esmp, - __out_ecount(EFX_PHY_NSTATS) uint32_t *stat) + __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat) { /* TBD: no stats support in firmware yet */ _NOTE(ARGUNUSED(enp, esmp)) @@ -522,7 +521,7 @@ hunt_phy_prop_name( #endif /* EFSYS_OPT_NAMES */ -extern __checkReturn int +extern __checkReturn efx_rc_t hunt_phy_prop_get( __in efx_nic_t *enp, __in unsigned int id, @@ -534,7 +533,7 @@ hunt_phy_prop_get( return (ENOTSUP); } -extern __checkReturn int +extern __checkReturn efx_rc_t hunt_phy_prop_set( __in efx_nic_t *enp, __in unsigned int id, @@ -549,11 +548,11 @@ hunt_phy_prop_set( #if EFSYS_OPT_BIST - __checkReturn int + __checkReturn efx_rc_t hunt_bist_enable_offline( __in efx_nic_t *enp) { - int rc; + efx_rc_t rc; if ((rc = efx_mcdi_bist_enable_offline(enp)) != 0) goto fail1; @@ -561,17 +560,17 @@ hunt_bist_enable_offline( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t hunt_bist_start( __in efx_nic_t *enp, __in efx_bist_type_t type) { - int rc; + efx_rc_t rc; if ((rc = efx_mcdi_bist_start(enp, type)) != 0) goto fail1; @@ -579,12 +578,12 @@ hunt_bist_start( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t hunt_bist_poll( __in efx_nic_t *enp, __in efx_bist_type_t type, @@ -601,7 +600,7 @@ hunt_bist_poll( MCDI_CTL_SDU_LEN_MAX)]; uint32_t value_mask = 0; uint32_t result; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_POLL_BIST; @@ -682,7 +681,7 @@ hunt_bist_poll( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } diff --git a/sys/dev/sfxge/common/hunt_rx.c b/sys/dev/sfxge/common/hunt_rx.c index 991f293..984d48d 100644 --- a/sys/dev/sfxge/common/hunt_rx.c +++ b/sys/dev/sfxge/common/hunt_rx.c @@ -31,7 +31,6 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" #include "efx_impl.h" @@ -39,14 +38,15 @@ __FBSDID("$FreeBSD$"); #if EFSYS_OPT_HUNTINGTON -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_init_rxq( __in efx_nic_t *enp, __in uint32_t size, __in uint32_t target_evq, __in uint32_t label, __in uint32_t instance, - __in efsys_mem_t *esmp) + __in efsys_mem_t *esmp, + __in boolean_t disable_scatter) { efx_mcdi_req_t req; uint8_t payload[ @@ -56,7 +56,7 @@ efx_mcdi_init_rxq( int i; efx_qword_t *dma_addr; uint64_t addr; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(size, <=, EFX_RXQ_MAXNDESCS); @@ -71,12 +71,13 @@ efx_mcdi_init_rxq( MCDI_IN_SET_DWORD(req, INIT_RXQ_IN_TARGET_EVQ, target_evq); MCDI_IN_SET_DWORD(req, INIT_RXQ_IN_LABEL, label); MCDI_IN_SET_DWORD(req, INIT_RXQ_IN_INSTANCE, instance); - MCDI_IN_POPULATE_DWORD_5(req, INIT_RXQ_IN_FLAGS, - INIT_RXQ_IN_FLAG_BUFF_MODE, 0, - INIT_RXQ_IN_FLAG_HDR_SPLIT, 0, - INIT_RXQ_IN_FLAG_TIMESTAMP, 0, - INIT_RXQ_IN_CRC_MODE, 0, - INIT_RXQ_IN_FLAG_PREFIX, 1); + MCDI_IN_POPULATE_DWORD_6(req, INIT_RXQ_IN_FLAGS, + INIT_RXQ_IN_FLAG_BUFF_MODE, 0, + INIT_RXQ_IN_FLAG_HDR_SPLIT, 0, + INIT_RXQ_IN_FLAG_TIMESTAMP, 0, + INIT_RXQ_IN_CRC_MODE, 0, + INIT_RXQ_IN_FLAG_PREFIX, 1, + INIT_RXQ_IN_FLAG_DISABLE_SCATTER, disable_scatter); MCDI_IN_SET_DWORD(req, INIT_RXQ_IN_OWNER_ID, 0); MCDI_IN_SET_DWORD(req, INIT_RXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED); @@ -102,12 +103,12 @@ efx_mcdi_init_rxq( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_fini_rxq( __in efx_nic_t *enp, __in uint32_t instance) @@ -115,7 +116,7 @@ efx_mcdi_fini_rxq( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_FINI_RXQ_IN_LEN, MC_CMD_FINI_RXQ_OUT_LEN)]; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_FINI_RXQ; @@ -136,22 +137,42 @@ efx_mcdi_fini_rxq( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } #if EFSYS_OPT_RX_SCALE -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_rss_context_alloc( __in efx_nic_t *enp, + __in efx_rx_scale_support_t scale_support, + __in uint32_t num_queues, __out uint32_t *rss_contextp) { efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)]; uint32_t rss_context; - int rc; + uint32_t context_type; + efx_rc_t rc; + + if (num_queues > EFX_MAXRSS) { + rc = EINVAL; + goto fail1; + } + + switch (scale_support) { + case EFX_RX_SCALE_EXCLUSIVE: + context_type = MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE; + break; + case EFX_RX_SCALE_SHARED: + context_type = MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED; + break; + default: + rc = EINVAL; + goto fail2; + } (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_RSS_CONTEXT_ALLOC; @@ -162,46 +183,49 @@ efx_mcdi_rss_context_alloc( MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID, EVB_PORT_ID_ASSIGNED); - MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_TYPE, - MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE); + MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_TYPE, context_type); /* NUM_QUEUES is only used to validate indirection table offsets */ - MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, 64); + MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, num_queues); efx_mcdi_execute(enp, &req); if (req.emr_rc != 0) { rc = req.emr_rc; - goto fail1; + goto fail3; } if (req.emr_out_length_used < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN) { rc = EMSGSIZE; - goto fail2; + goto fail4; } rss_context = MCDI_OUT_DWORD(req, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID); - if (rss_context == HUNTINGTON_RSS_CONTEXT_INVALID) { + if (rss_context == EF10_RSS_CONTEXT_INVALID) { rc = ENOENT; - goto fail3; + goto fail5; } *rss_contextp = rss_context; return (0); +fail5: + EFSYS_PROBE(fail5); +fail4: + EFSYS_PROBE(fail4); fail3: EFSYS_PROBE(fail3); fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } #endif /* EFSYS_OPT_RX_SCALE */ #if EFSYS_OPT_RX_SCALE -static int +static efx_rc_t efx_mcdi_rss_context_free( __in efx_nic_t *enp, __in uint32_t rss_context) @@ -209,9 +233,9 @@ efx_mcdi_rss_context_free( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_RSS_CONTEXT_FREE_IN_LEN, MC_CMD_RSS_CONTEXT_FREE_OUT_LEN)]; - int rc; + efx_rc_t rc; - if (rss_context == HUNTINGTON_RSS_CONTEXT_INVALID) { + if (rss_context == EF10_RSS_CONTEXT_INVALID) { rc = EINVAL; goto fail1; } @@ -237,14 +261,14 @@ efx_mcdi_rss_context_free( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } #endif /* EFSYS_OPT_RX_SCALE */ #if EFSYS_OPT_RX_SCALE -static int +static efx_rc_t efx_mcdi_rss_context_set_flags( __in efx_nic_t *enp, __in uint32_t rss_context, @@ -253,9 +277,9 @@ efx_mcdi_rss_context_set_flags( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN, MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN)]; - int rc; + efx_rc_t rc; - if (rss_context == HUNTINGTON_RSS_CONTEXT_INVALID) { + if (rss_context == EF10_RSS_CONTEXT_INVALID) { rc = EINVAL; goto fail1; } @@ -292,14 +316,14 @@ efx_mcdi_rss_context_set_flags( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } #endif /* EFSYS_OPT_RX_SCALE */ #if EFSYS_OPT_RX_SCALE -static int +static efx_rc_t efx_mcdi_rss_context_set_key( __in efx_nic_t *enp, __in uint32_t rss_context, @@ -309,9 +333,9 @@ efx_mcdi_rss_context_set_key( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN, MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN)]; - int rc; + efx_rc_t rc; - if (rss_context == HUNTINGTON_RSS_CONTEXT_INVALID) { + if (rss_context == EF10_RSS_CONTEXT_INVALID) { rc = EINVAL; goto fail1; } @@ -349,14 +373,14 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } #endif /* EFSYS_OPT_RX_SCALE */ #if EFSYS_OPT_RX_SCALE -static int +static efx_rc_t efx_mcdi_rss_context_set_table( __in efx_nic_t *enp, __in uint32_t rss_context, @@ -369,7 +393,7 @@ efx_mcdi_rss_context_set_table( uint8_t *req_table; int i, rc; - if (rss_context == HUNTINGTON_RSS_CONTEXT_INVALID) { + if (rss_context == EF10_RSS_CONTEXT_INVALID) { rc = EINVAL; goto fail1; } @@ -405,20 +429,21 @@ efx_mcdi_rss_context_set_table( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } #endif /* EFSYS_OPT_RX_SCALE */ - __checkReturn int -hunt_rx_init( + __checkReturn efx_rc_t +ef10_rx_init( __in efx_nic_t *enp) { #if EFSYS_OPT_RX_SCALE - if (efx_mcdi_rss_context_alloc(enp, &enp->en_rss_context) == 0) { + if (efx_mcdi_rss_context_alloc(enp, EFX_RX_SCALE_EXCLUSIVE, EFX_MAXRSS, + &enp->en_rss_context) == 0) { /* * Allocated an exclusive RSS context, which allows both the * indirection table and key to be modified. @@ -440,35 +465,9 @@ hunt_rx_init( return (0); } -#if EFSYS_OPT_RX_HDR_SPLIT - __checkReturn int -hunt_rx_hdr_split_enable( - __in efx_nic_t *enp, - __in unsigned int hdr_buf_size, - __in unsigned int pld_buf_size) -{ - int rc; - - /* FIXME */ - _NOTE(ARGUNUSED(enp, hdr_buf_size, pld_buf_size)) - if (B_FALSE) { - rc = ENOTSUP; - goto fail1; - } - /* FIXME */ - - return (0); - -fail1: - EFSYS_PROBE1(fail1, int, rc); - - return (rc); -} -#endif /* EFSYS_OPT_RX_HDR_SPLIT */ - #if EFSYS_OPT_RX_SCATTER - __checkReturn int -hunt_rx_scatter_enable( + __checkReturn efx_rc_t +ef10_rx_scatter_enable( __in efx_nic_t *enp, __in unsigned int buf_size) { @@ -478,14 +477,14 @@ hunt_rx_scatter_enable( #endif /* EFSYS_OPT_RX_SCATTER */ #if EFSYS_OPT_RX_SCALE - __checkReturn int -hunt_rx_scale_mode_set( + __checkReturn efx_rc_t +ef10_rx_scale_mode_set( __in efx_nic_t *enp, __in efx_rx_hash_alg_t alg, __in efx_rx_hash_type_t type, __in boolean_t insert) { - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(alg, ==, EFX_RX_HASHALG_TOEPLITZ); EFSYS_ASSERT3U(insert, ==, B_TRUE); @@ -511,20 +510,20 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } #endif /* EFSYS_OPT_RX_SCALE */ #if EFSYS_OPT_RX_SCALE - __checkReturn int -hunt_rx_scale_key_set( + __checkReturn efx_rc_t +ef10_rx_scale_key_set( __in efx_nic_t *enp, __in_ecount(n) uint8_t *key, __in size_t n) { - int rc; + efx_rc_t rc; if (enp->en_rss_support == EFX_RX_SCALE_UNAVAILABLE) { rc = ENOTSUP; @@ -540,20 +539,20 @@ hunt_rx_scale_key_set( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } #endif /* EFSYS_OPT_RX_SCALE */ #if EFSYS_OPT_RX_SCALE - __checkReturn int -hunt_rx_scale_tbl_set( + __checkReturn efx_rc_t +ef10_rx_scale_tbl_set( __in efx_nic_t *enp, __in_ecount(n) unsigned int *table, __in size_t n) { - int rc; + efx_rc_t rc; if (enp->en_rss_support == EFX_RX_SCALE_UNAVAILABLE) { rc = ENOTSUP; @@ -569,14 +568,73 @@ hunt_rx_scale_tbl_set( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } #endif /* EFSYS_OPT_RX_SCALE */ + +/* + * EF10 RX pseudo-header + * --------------------- + * + * Receive packets are prefixed by an (optional) 14 byte pseudo-header: + * + * +00: Toeplitz hash value. + * (32bit little-endian) + * +04: Outer VLAN tag. Zero if the packet did not have an outer VLAN tag. + * (16bit big-endian) + * +06: Inner VLAN tag. Zero if the packet did not have an inner VLAN tag. + * (16bit big-endian) + * +08: Packet Length. Zero if the RX datapath was in cut-through mode. + * (16bit little-endian) + * +10: MAC timestamp. Zero if timestamping is not enabled. + * (32bit little-endian) + * + * See "The RX Pseudo-header" in SF-109306-TC. + */ + + __checkReturn efx_rc_t +ef10_rx_prefix_pktlen( + __in efx_nic_t *enp, + __in uint8_t *buffer, + __out uint16_t *lengthp) +{ + /* + * The RX pseudo-header contains the packet length, excluding the + * pseudo-header. If the hardware receive datapath was operating in + * cut-through mode then the length in the RX pseudo-header will be + * zero, and the packet length must be obtained from the DMA length + * reported in the RX event. + */ + *lengthp = buffer[8] | (buffer[9] << 8); + return (0); +} + +#if EFSYS_OPT_RX_SCALE + __checkReturn uint32_t +ef10_rx_prefix_hash( + __in efx_nic_t *enp, + __in efx_rx_hash_alg_t func, + __in uint8_t *buffer) +{ + switch (func) { + case EFX_RX_HASHALG_TOEPLITZ: + return (buffer[0] | + (buffer[1] << 8) | + (buffer[2] << 16) | + (buffer[3] << 24)); + + default: + EFSYS_ASSERT(0); + return (0); + } +} +#endif /* EFSYS_OPT_RX_SCALE */ + void -hunt_rx_qpost( +ef10_rx_qpost( __in efx_rxq_t *erp, __in_ecount(n) efsys_dma_addr_t *addrp, __in size_t size, @@ -614,7 +672,7 @@ hunt_rx_qpost( } void -hunt_rx_qpush( +ef10_rx_qpush( __in efx_rxq_t *erp, __in unsigned int added, __inout unsigned int *pushedp) @@ -625,7 +683,7 @@ hunt_rx_qpush( efx_dword_t dword; /* Hardware has alignment restriction for WPTR */ - wptr = P2ALIGN(added, HUNTINGTON_RX_WPTR_ALIGN); + wptr = P2ALIGN(added, EF10_RX_WPTR_ALIGN); if (pushed == wptr) return; @@ -644,12 +702,12 @@ hunt_rx_qpush( erp->er_index, &dword, B_FALSE); } - __checkReturn int -hunt_rx_qflush( + __checkReturn efx_rc_t +ef10_rx_qflush( __in efx_rxq_t *erp) { efx_nic_t *enp = erp->er_enp; - int rc; + efx_rc_t rc; if ((rc = efx_mcdi_fini_rxq(enp, erp->er_index)) != 0) goto fail1; @@ -657,13 +715,13 @@ hunt_rx_qflush( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } void -hunt_rx_qenable( +ef10_rx_qenable( __in efx_rxq_t *erp) { /* FIXME */ @@ -671,8 +729,8 @@ hunt_rx_qenable( /* FIXME */ } - __checkReturn int -hunt_rx_qcreate( + __checkReturn efx_rc_t +ef10_rx_qcreate( __in efx_nic_t *enp, __in unsigned int index, __in unsigned int label, @@ -684,7 +742,8 @@ hunt_rx_qcreate( __in efx_rxq_t *erp) { efx_nic_cfg_t *encp = &(enp->en_nic_cfg); - int rc; + efx_rc_t rc; + boolean_t disable_scatter; _NOTE(ARGUNUSED(erp)) @@ -704,20 +763,22 @@ hunt_rx_qcreate( goto fail2; } - /* - * FIXME: Siena code handles different queue types (default, header - * split, scatter); we'll need to do something more here later, but - * all that stuff is TBD for now. - */ + /* Scatter can only be disabled if the firmware supports doing so */ + if ((type != EFX_RXQ_TYPE_SCATTER) && + enp->en_nic_cfg.enc_rx_disable_scatter_supported) { + disable_scatter = B_TRUE; + } else { + disable_scatter = B_FALSE; + } if ((rc = efx_mcdi_init_rxq(enp, n, eep->ee_index, label, index, - esmp)) != 0) + esmp, disable_scatter)) != 0) goto fail3; erp->er_eep = eep; erp->er_label = label; - hunt_ev_rxlabel_init(eep, erp, label); + ef10_ev_rxlabel_init(eep, erp, label); return (0); @@ -726,20 +787,20 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } void -hunt_rx_qdestroy( +ef10_rx_qdestroy( __in efx_rxq_t *erp) { efx_nic_t *enp = erp->er_enp; efx_evq_t *eep = erp->er_eep; unsigned int label = erp->er_label; - hunt_ev_rxlabel_fini(eep, label); + ef10_ev_rxlabel_fini(eep, label); EFSYS_ASSERT(enp->en_rx_qcount != 0); --enp->en_rx_qcount; @@ -748,7 +809,7 @@ hunt_rx_qdestroy( } void -hunt_rx_fini( +ef10_rx_fini( __in efx_nic_t *enp) { #if EFSYS_OPT_RX_SCALE diff --git a/sys/dev/sfxge/common/hunt_sram.c b/sys/dev/sfxge/common/hunt_sram.c index 947e033..1e35991 100644 --- a/sys/dev/sfxge/common/hunt_sram.c +++ b/sys/dev/sfxge/common/hunt_sram.c @@ -31,7 +31,6 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" #include "efx_impl.h" @@ -40,12 +39,12 @@ __FBSDID("$FreeBSD$"); #if EFSYS_OPT_DIAG - __checkReturn int -hunt_sram_test( + __checkReturn efx_rc_t +ef10_sram_test( __in efx_nic_t *enp, __in efx_sram_pattern_fn_t func) { - int rc; + efx_rc_t rc; /* FIXME */ _NOTE(ARGUNUSED(enp)) @@ -59,7 +58,7 @@ hunt_sram_test( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } diff --git a/sys/dev/sfxge/common/hunt_tx.c b/sys/dev/sfxge/common/hunt_tx.c index ee5691a..593db88 100755 --- a/sys/dev/sfxge/common/hunt_tx.c +++ b/sys/dev/sfxge/common/hunt_tx.c @@ -31,7 +31,6 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" #include "efx_impl.h" @@ -48,7 +47,7 @@ __FBSDID("$FreeBSD$"); #define EFX_TX_QSTAT_INCR(_etp, _stat) #endif -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_init_txq( __in efx_nic_t *enp, __in uint32_t size, @@ -65,7 +64,7 @@ efx_mcdi_init_txq( uint64_t addr; int npages; int i; - int rc; + efx_rc_t rc; EFSYS_ASSERT(EFX_TXQ_MAX_BUFS >= EFX_TXQ_NBUFS(EFX_TXQ_MAXNDESCS(&enp->en_nic_cfg))); @@ -90,8 +89,10 @@ efx_mcdi_init_txq( MCDI_IN_POPULATE_DWORD_6(req, INIT_TXQ_IN_FLAGS, INIT_TXQ_IN_FLAG_BUFF_MODE, 0, - INIT_TXQ_IN_FLAG_IP_CSUM_DIS, (flags & EFX_CKSUM_IPV4) ? 0 : 1, - INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, (flags & EFX_CKSUM_TCPUDP) ? 0 : 1, + INIT_TXQ_IN_FLAG_IP_CSUM_DIS, + (flags & EFX_TXQ_CKSUM_IPV4) ? 0 : 1, + INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, + (flags & EFX_TXQ_CKSUM_TCPUDP) ? 0 : 1, INIT_TXQ_IN_FLAG_TCP_UDP_ONLY, 0, INIT_TXQ_IN_CRC_MODE, 0, INIT_TXQ_IN_FLAG_TIMESTAMP, 0); @@ -123,12 +124,12 @@ efx_mcdi_init_txq( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_fini_txq( __in efx_nic_t *enp, __in uint32_t instance) @@ -136,7 +137,7 @@ efx_mcdi_fini_txq( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_FINI_TXQ_IN_LEN, MC_CMD_FINI_TXQ_OUT_LEN)]; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_FINI_TXQ; @@ -157,13 +158,13 @@ efx_mcdi_fini_txq( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_tx_init( + __checkReturn efx_rc_t +ef10_tx_init( __in efx_nic_t *enp) { _NOTE(ARGUNUSED(enp)) @@ -171,14 +172,14 @@ hunt_tx_init( } void -hunt_tx_fini( +ef10_tx_fini( __in efx_nic_t *enp) { _NOTE(ARGUNUSED(enp)) } - __checkReturn int -hunt_tx_qcreate( + __checkReturn efx_rc_t +ef10_tx_qcreate( __in efx_nic_t *enp, __in unsigned int index, __in unsigned int label, @@ -191,7 +192,7 @@ hunt_tx_qcreate( __out unsigned int *addedp) { efx_qword_t desc; - int rc; + efx_rc_t rc; if ((rc = efx_mcdi_init_txq(enp, n, eep->ee_index, label, index, flags, @@ -210,22 +211,24 @@ hunt_tx_qcreate( EFX_POPULATE_QWORD_4(desc, ESF_DZ_TX_DESC_IS_OPT, 1, ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_CRC_CSUM, - ESF_DZ_TX_OPTION_UDP_TCP_CSUM, (flags & EFX_CKSUM_TCPUDP) ? 1 : 0, - ESF_DZ_TX_OPTION_IP_CSUM, (flags & EFX_CKSUM_IPV4) ? 1 : 0); + ESF_DZ_TX_OPTION_UDP_TCP_CSUM, + (flags & EFX_TXQ_CKSUM_TCPUDP) ? 1 : 0, + ESF_DZ_TX_OPTION_IP_CSUM, + (flags & EFX_TXQ_CKSUM_IPV4) ? 1 : 0); EFSYS_MEM_WRITEQ(etp->et_esmp, 0, &desc); - hunt_tx_qpush(etp, *addedp, 0); + ef10_tx_qpush(etp, *addedp, 0); return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } void -hunt_tx_qdestroy( +ef10_tx_qdestroy( __in efx_txq_t *etp) { /* FIXME */ @@ -233,13 +236,13 @@ hunt_tx_qdestroy( /* FIXME */ } - __checkReturn int -hunt_tx_qpio_enable( + __checkReturn efx_rc_t +ef10_tx_qpio_enable( __in efx_txq_t *etp) { efx_nic_t *enp = etp->et_enp; efx_piobuf_handle_t handle; - int rc; + efx_rc_t rc; if (etp->et_pio_size != 0) { rc = EALREADY; @@ -247,7 +250,7 @@ hunt_tx_qpio_enable( } /* Sub-allocate a PIO block from a piobuf */ - if ((rc = hunt_nic_pio_alloc(enp, + if ((rc = ef10_nic_pio_alloc(enp, &etp->et_pio_bufnum, &handle, &etp->et_pio_blknum, @@ -258,7 +261,7 @@ hunt_tx_qpio_enable( EFSYS_ASSERT3U(etp->et_pio_size, !=, 0); /* Link the piobuf to this TXQ */ - if ((rc = hunt_nic_pio_link(enp, etp->et_index, handle)) != 0) { + if ((rc = ef10_nic_pio_link(enp, etp->et_index, handle)) != 0) { goto fail3; } @@ -279,35 +282,35 @@ hunt_tx_qpio_enable( fail3: EFSYS_PROBE(fail3); - hunt_nic_pio_free(enp, etp->et_pio_bufnum, etp->et_pio_blknum); + ef10_nic_pio_free(enp, etp->et_pio_bufnum, etp->et_pio_blknum); etp->et_pio_size = 0; fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } void -hunt_tx_qpio_disable( +ef10_tx_qpio_disable( __in efx_txq_t *etp) { efx_nic_t *enp = etp->et_enp; if (etp->et_pio_size != 0) { /* Unlink the piobuf from this TXQ */ - hunt_nic_pio_unlink(enp, etp->et_index); + ef10_nic_pio_unlink(enp, etp->et_index); /* Free the sub-allocated PIO block */ - hunt_nic_pio_free(enp, etp->et_pio_bufnum, etp->et_pio_blknum); + ef10_nic_pio_free(enp, etp->et_pio_bufnum, etp->et_pio_blknum); etp->et_pio_size = 0; etp->et_pio_write_offset = 0; } } - __checkReturn int -hunt_tx_qpio_write( + __checkReturn efx_rc_t +ef10_tx_qpio_write( __in efx_txq_t *etp, __in_ecount(length) uint8_t *buffer, __in size_t length, @@ -318,7 +321,7 @@ hunt_tx_qpio_write( uint32_t write_offset; uint32_t write_offset_limit; efx_qword_t *eqp; - int rc; + efx_rc_t rc; EFSYS_ASSERT(length % sizeof (efx_qword_t) == 0); @@ -349,13 +352,13 @@ hunt_tx_qpio_write( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_tx_qpio_post( + __checkReturn efx_rc_t +ef10_tx_qpio_post( __in efx_txq_t *etp, __in size_t pkt_length, __in unsigned int completed, @@ -365,7 +368,7 @@ hunt_tx_qpio_post( unsigned int id; size_t offset; unsigned int added = *addedp; - int rc; + efx_rc_t rc; if (added - completed + 1 > EFX_TXQ_LIMIT(etp->et_mask + 1)) { @@ -402,13 +405,13 @@ hunt_tx_qpio_post( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_tx_qpost( + __checkReturn efx_rc_t +ef10_tx_qpost( __in efx_txq_t *etp, __in_ecount(n) efx_buffer_t *eb, __in unsigned int n, @@ -417,7 +420,7 @@ hunt_tx_qpost( { unsigned int added = *addedp; unsigned int i; - int rc; + efx_rc_t rc; if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) { rc = ENOSPC; @@ -459,7 +462,7 @@ hunt_tx_qpost( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -470,7 +473,7 @@ fail1: * hardware decides not to use the pushed descriptor. */ void -hunt_tx_qpush( +ef10_tx_qpush( __in efx_txq_t *etp, __in unsigned int added, __in unsigned int pushed) @@ -499,8 +502,8 @@ hunt_tx_qpush( &oword); } - __checkReturn int -hunt_tx_qdesc_post( + __checkReturn efx_rc_t +ef10_tx_qdesc_post( __in efx_txq_t *etp, __in_ecount(n) efx_desc_t *ed, __in unsigned int n, @@ -509,7 +512,7 @@ hunt_tx_qdesc_post( { unsigned int added = *addedp; unsigned int i; - int rc; + efx_rc_t rc; if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) { rc = ENOSPC; @@ -536,13 +539,13 @@ hunt_tx_qdesc_post( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } void -hunt_tx_qdesc_dma_create( +ef10_tx_qdesc_dma_create( __in efx_txq_t *etp, __in efsys_dma_addr_t addr, __in size_t size, @@ -586,7 +589,7 @@ hunt_tx_qdesc_tso_create( } void -hunt_tx_qdesc_vlantci_create( +ef10_tx_qdesc_vlantci_create( __in efx_txq_t *etp, __in uint16_t tci, __out efx_desc_t *edp) @@ -603,12 +606,12 @@ hunt_tx_qdesc_vlantci_create( } - __checkReturn int -hunt_tx_qpace( + __checkReturn efx_rc_t +ef10_tx_qpace( __in efx_txq_t *etp, __in unsigned int ns) { - int rc; + efx_rc_t rc; /* FIXME */ _NOTE(ARGUNUSED(etp, ns)) @@ -621,17 +624,17 @@ hunt_tx_qpace( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_tx_qflush( + __checkReturn efx_rc_t +ef10_tx_qflush( __in efx_txq_t *etp) { efx_nic_t *enp = etp->et_enp; - int rc; + efx_rc_t rc; if ((rc = efx_mcdi_fini_txq(enp, etp->et_index)) != 0) goto fail1; @@ -639,13 +642,13 @@ hunt_tx_qflush( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } void -hunt_tx_qenable( +ef10_tx_qenable( __in efx_txq_t *etp) { /* FIXME */ @@ -655,15 +658,10 @@ hunt_tx_qenable( #if EFSYS_OPT_QSTATS void -hunt_tx_qstats_update( +ef10_tx_qstats_update( __in efx_txq_t *etp, __inout_ecount(TX_NQSTATS) efsys_stat_t *stat) { - /* - * TBD: Consider a common Siena/Huntington function. The code is - * essentially identical. - */ - unsigned int id; for (id = 0; id < TX_NQSTATS; id++) { diff --git a/sys/dev/sfxge/common/hunt_vpd.c b/sys/dev/sfxge/common/hunt_vpd.c index 536ebbc..58e9a66 100644 --- a/sys/dev/sfxge/common/hunt_vpd.c +++ b/sys/dev/sfxge/common/hunt_vpd.c @@ -31,10 +31,7 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" -#include "efx_types.h" -#include "efx_regs.h" #include "efx_impl.h" @@ -44,17 +41,18 @@ __FBSDID("$FreeBSD$"); #include "ef10_tlv_layout.h" - __checkReturn int -hunt_vpd_init( + __checkReturn efx_rc_t +ef10_vpd_init( __in efx_nic_t *enp) { caddr_t svpd; size_t svpd_size; uint32_t pci_pf; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE); - EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); pci_pf = enp->en_nic_cfg.enc_pf; /* @@ -64,7 +62,7 @@ hunt_vpd_init( */ svpd = NULL; svpd_size = 0; - rc = hunt_nvram_partn_read_tlv(enp, + rc = ef10_nvram_partn_read_tlv(enp, NVRAM_PARTITION_TYPE_STATIC_CONFIG, TLV_TAG_PF_STATIC_VPD(pci_pf), &svpd, &svpd_size); @@ -81,8 +79,8 @@ hunt_vpd_init( goto fail2; } - enp->en_u.hunt.enu_svpd = svpd; - enp->en_u.hunt.enu_svpd_length = svpd_size; + enp->en_arch.ef10.ena_svpd = svpd; + enp->en_arch.ef10.ena_svpd_length = svpd_size; out: return (0); @@ -92,19 +90,20 @@ fail2: EFSYS_KMEM_FREE(enp->en_esip, svpd_size, svpd); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_vpd_size( + __checkReturn efx_rc_t +ef10_vpd_size( __in efx_nic_t *enp, __out size_t *sizep) { - int rc; + efx_rc_t rc; - EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); /* * This function returns the total size the user should allocate @@ -113,19 +112,19 @@ hunt_vpd_size( * which is the size of the DYNAMIC_CONFIG partition. */ if ((rc = efx_mcdi_nvram_info(enp, NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, - sizep, NULL, NULL)) != 0) + sizep, NULL, NULL, NULL)) != 0) goto fail1; return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_vpd_read( + __checkReturn efx_rc_t +ef10_vpd_read( __in efx_nic_t *enp, __out_bcount(size) caddr_t data, __in size_t size) @@ -133,13 +132,14 @@ hunt_vpd_read( caddr_t dvpd; size_t dvpd_size; uint32_t pci_pf; - int rc; + efx_rc_t rc; - EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); pci_pf = enp->en_nic_cfg.enc_pf; - if ((rc = hunt_nvram_partn_read_tlv(enp, + if ((rc = ef10_nvram_partn_read_tlv(enp, NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, TLV_TAG_PF_DYNAMIC_VPD(pci_pf), &dvpd, &dvpd_size)) != 0) @@ -163,13 +163,13 @@ fail2: EFSYS_KMEM_FREE(enp->en_esip, dvpd_size, dvpd); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_vpd_verify( + __checkReturn efx_rc_t +ef10_vpd_verify( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size) @@ -180,14 +180,15 @@ hunt_vpd_verify( efx_vpd_keyword_t dkey; unsigned int scont; unsigned int dcont; - int rc; + efx_rc_t rc; - EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); /* * Strictly you could take the view that dynamic vpd is optional. * Instead, to conform more closely to the read/verify/reinit() - * paradigm, we require dynamic vpd. hunt_vpd_reinit() will + * paradigm, we require dynamic vpd. ef10_vpd_reinit() will * reinitialize it as required. */ if ((rc = efx_vpd_hunk_verify(data, size, NULL)) != 0) @@ -197,7 +198,7 @@ hunt_vpd_verify( * Verify that there is no duplication between the static and * dynamic cfg sectors. */ - if (enp->en_u.hunt.enu_svpd_length == 0) + if (enp->en_arch.ef10.ena_svpd_length == 0) goto done; dcont = 0; @@ -213,8 +214,8 @@ hunt_vpd_verify( _NOTE(CONSTANTCONDITION) while (1) { if ((rc = efx_vpd_hunk_next( - enp->en_u.hunt.enu_svpd, - enp->en_u.hunt.enu_svpd_length, &stag, &skey, + enp->en_arch.ef10.ena_svpd, + enp->en_arch.ef10.ena_svpd_length, &stag, &skey, NULL, NULL, &scont)) != 0) goto fail3; if (scont == 0) @@ -237,31 +238,31 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_vpd_reinit( + __checkReturn efx_rc_t +ef10_vpd_reinit( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size) { boolean_t wantpid; - int rc; + efx_rc_t rc; /* * Only create an ID string if the dynamic cfg doesn't have one */ - if (enp->en_u.hunt.enu_svpd_length == 0) + if (enp->en_arch.ef10.ena_svpd_length == 0) wantpid = B_TRUE; else { unsigned int offset; uint8_t length; - rc = efx_vpd_hunk_get(enp->en_u.hunt.enu_svpd, - enp->en_u.hunt.enu_svpd_length, + rc = efx_vpd_hunk_get(enp->en_arch.ef10.ena_svpd, + enp->en_arch.ef10.ena_svpd_length, EFX_VPD_ID, 0, &offset, &length); if (rc == 0) wantpid = B_FALSE; @@ -279,13 +280,13 @@ hunt_vpd_reinit( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_vpd_get( + __checkReturn efx_rc_t +ef10_vpd_get( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size, @@ -293,18 +294,19 @@ hunt_vpd_get( { unsigned int offset; uint8_t length; - int rc; + efx_rc_t rc; - EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); /* Attempt to satisfy the request from svpd first */ - if (enp->en_u.hunt.enu_svpd_length > 0) { - if ((rc = efx_vpd_hunk_get(enp->en_u.hunt.enu_svpd, - enp->en_u.hunt.enu_svpd_length, evvp->evv_tag, + if (enp->en_arch.ef10.ena_svpd_length > 0) { + if ((rc = efx_vpd_hunk_get(enp->en_arch.ef10.ena_svpd, + enp->en_arch.ef10.ena_svpd_length, evvp->evv_tag, evvp->evv_keyword, &offset, &length)) == 0) { evvp->evv_length = length; memcpy(evvp->evv_value, - enp->en_u.hunt.enu_svpd + offset, length); + enp->en_arch.ef10.ena_svpd + offset, length); return (0); } else if (rc != ENOENT) goto fail1; @@ -323,29 +325,30 @@ hunt_vpd_get( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_vpd_set( + __checkReturn efx_rc_t +ef10_vpd_set( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size, __in efx_vpd_value_t *evvp) { - int rc; + efx_rc_t rc; - EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); /* If the provided (tag,keyword) exists in svpd, then it is readonly */ - if (enp->en_u.hunt.enu_svpd_length > 0) { + if (enp->en_arch.ef10.ena_svpd_length > 0) { unsigned int offset; uint8_t length; - if ((rc = efx_vpd_hunk_get(enp->en_u.hunt.enu_svpd, - enp->en_u.hunt.enu_svpd_length, evvp->evv_tag, + if ((rc = efx_vpd_hunk_get(enp->en_arch.ef10.ena_svpd, + enp->en_arch.ef10.ena_svpd_length, evvp->evv_tag, evvp->evv_keyword, &offset, &length)) == 0) { rc = EACCES; goto fail1; @@ -360,13 +363,13 @@ hunt_vpd_set( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int -hunt_vpd_next( + __checkReturn efx_rc_t +ef10_vpd_next( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size, @@ -378,17 +381,18 @@ hunt_vpd_next( return (ENOTSUP); } - __checkReturn int -hunt_vpd_write( + __checkReturn efx_rc_t +ef10_vpd_write( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size) { size_t vpd_length; uint32_t pci_pf; - int rc; + efx_rc_t rc; - EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); pci_pf = enp->en_nic_cfg.enc_pf; @@ -396,11 +400,11 @@ hunt_vpd_write( if ((rc = efx_vpd_hunk_length(data, size, &vpd_length)) != 0) goto fail1; - /* Store new dynamic VPD in DYNAMIC_CONFIG partition */ - if ((rc = hunt_nvram_partn_write_tlv(enp, + /* Store new dynamic VPD in all segments in DYNAMIC_CONFIG partition */ + if ((rc = ef10_nvram_partn_write_segment_tlv(enp, NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, TLV_TAG_PF_DYNAMIC_VPD(pci_pf), - data, vpd_length)) != 0) { + data, vpd_length, B_TRUE)) != 0) { goto fail2; } @@ -410,23 +414,24 @@ fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } void -hunt_vpd_fini( +ef10_vpd_fini( __in efx_nic_t *enp) { - EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); - if (enp->en_u.hunt.enu_svpd_length > 0) { - EFSYS_KMEM_FREE(enp->en_esip, enp->en_u.hunt.enu_svpd_length, - enp->en_u.hunt.enu_svpd); + if (enp->en_arch.ef10.ena_svpd_length > 0) { + EFSYS_KMEM_FREE(enp->en_esip, enp->en_arch.ef10.ena_svpd_length, + enp->en_arch.ef10.ena_svpd); - enp->en_u.hunt.enu_svpd = NULL; - enp->en_u.hunt.enu_svpd_length = 0; + enp->en_arch.ef10.ena_svpd = NULL; + enp->en_arch.ef10.ena_svpd_length = 0; } } diff --git a/sys/dev/sfxge/common/mcdi_mon.c b/sys/dev/sfxge/common/mcdi_mon.c index ec692be..4c7f961 100644 --- a/sys/dev/sfxge/common/mcdi_mon.c +++ b/sys/dev/sfxge/common/mcdi_mon.c @@ -31,7 +31,6 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" #include "efx_impl.h" @@ -149,6 +148,13 @@ static const struct mcdi_sensor_map_s { STAT(Px, CONTROLLER_SLAVE_VPTAT_EXT_ADC), /* 0x46 SLAVE_VPTAT_EXT_ADC */ STAT(Px, CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC), /* 0x47 SLAVE_INTERNAL_TEMP_EXT_ADC */ + STAT_NO_SENSOR(), /* 0x48 (no sensor) */ + STAT(Px, SODIMM_VOUT), /* 0x49 SODIMM_VOUT */ + STAT(Px, SODIMM_0_TEMP), /* 0x4a SODIMM_0_TEMP */ + STAT(Px, SODIMM_1_TEMP), /* 0x4b SODIMM_1_TEMP */ + STAT(Px, PHY0_VCC), /* 0x4c PHY0_VCC */ + STAT(Px, PHY1_VCC), /* 0x4d PHY1_VCC */ + STAT(Px, CONTROLLER_TDIODE_TEMP), /* 0x4e CONTROLLER_TDIODE_TEMP */ }; #define MCDI_STATIC_SENSOR_ASSERT(_field) \ @@ -162,7 +168,7 @@ mcdi_mon_decode_stats( __in size_t sensor_mask_size, __in_opt efsys_mem_t *esmp, __out_ecount_opt(sensor_mask_size) uint32_t *stat_maskp, - __out_ecount_opt(EFX_MON_NSTATS) efx_mon_stat_value_t *stat) + __inout_ecount_opt(EFX_MON_NSTATS) efx_mon_stat_value_t *stat) { efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); uint16_t port_mask; @@ -245,7 +251,7 @@ mcdi_mon_decode_stats( } } - __checkReturn int + __checkReturn efx_rc_t mcdi_mon_ev( __in efx_nic_t *enp, __in efx_qword_t *eqp, @@ -259,7 +265,7 @@ mcdi_mon_ev( uint16_t state; uint16_t value; efx_mon_stat_t id; - int rc; + efx_rc_t rc; port_mask = (emip->emi_port == 1) ? MCDI_MON_PORT_P1 @@ -293,13 +299,13 @@ mcdi_mon_ev( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_read_sensors( __in efx_nic_t *enp, __in efsys_mem_t *esmp, @@ -328,7 +334,7 @@ efx_mcdi_read_sensors( return (req.emr_rc); } -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_sensor_info_npages( __in efx_nic_t *enp, __out uint32_t *npagesp) @@ -337,7 +343,7 @@ efx_mcdi_sensor_info_npages( uint8_t payload[MAX(MC_CMD_SENSOR_INFO_EXT_IN_LEN, MC_CMD_SENSOR_INFO_OUT_LENMAX)]; int page; - int rc; + efx_rc_t rc; EFSYS_ASSERT(npagesp != NULL); @@ -366,12 +372,12 @@ efx_mcdi_sensor_info_npages( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t efx_mcdi_sensor_info( __in efx_nic_t *enp, __out_ecount(npages) uint32_t *sensor_maskp, @@ -381,7 +387,7 @@ efx_mcdi_sensor_info( uint8_t payload[MAX(MC_CMD_SENSOR_INFO_EXT_IN_LEN, MC_CMD_SENSOR_INFO_OUT_LENMAX)]; uint32_t page; - int rc; + efx_rc_t rc; EFSYS_ASSERT(sensor_maskp != NULL); @@ -426,20 +432,20 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t mcdi_mon_stats_update( __in efx_nic_t *enp, __in efsys_mem_t *esmp, - __out_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values) + __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values) { efx_nic_cfg_t *encp = &(enp->en_nic_cfg); uint32_t size = encp->enc_mon_stat_dma_buf_size; - int rc; + efx_rc_t rc; if ((rc = efx_mcdi_read_sensors(enp, esmp, size)) != 0) goto fail1; @@ -454,18 +460,18 @@ mcdi_mon_stats_update( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t mcdi_mon_cfg_build( __in efx_nic_t *enp) { efx_nic_cfg_t *encp = &(enp->en_nic_cfg); uint32_t npages; - int rc; + efx_rc_t rc; switch (enp->en_family) { #if EFSYS_OPT_SIENA @@ -478,6 +484,11 @@ mcdi_mon_cfg_build( encp->enc_mon_type = EFX_MON_SFC91X0; break; #endif +#if EFSYS_OPT_MEDFORD + case EFX_FAMILY_MEDFORD: + encp->enc_mon_type = EFX_MON_SFC92X0; + break; +#endif default: rc = EINVAL; goto fail1; @@ -528,7 +539,7 @@ fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } diff --git a/sys/dev/sfxge/common/mcdi_mon.h b/sys/dev/sfxge/common/mcdi_mon.h index 30bb150..440a887 100644 --- a/sys/dev/sfxge/common/mcdi_mon.h +++ b/sys/dev/sfxge/common/mcdi_mon.h @@ -43,7 +43,7 @@ extern "C" { #if EFSYS_OPT_MON_STATS - __checkReturn int + __checkReturn efx_rc_t mcdi_mon_cfg_build( __in efx_nic_t *enp); @@ -52,18 +52,18 @@ mcdi_mon_cfg_free( __in efx_nic_t *enp); -extern __checkReturn int +extern __checkReturn efx_rc_t mcdi_mon_ev( __in efx_nic_t *enp, __in efx_qword_t *eqp, __out efx_mon_stat_t *idp, __out efx_mon_stat_value_t *valuep); -extern __checkReturn int +extern __checkReturn efx_rc_t mcdi_mon_stats_update( __in efx_nic_t *enp, __in efsys_mem_t *esmp, - __out_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values); + __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values); #endif /* EFSYS_OPT_MON_STATS */ diff --git a/sys/dev/sfxge/common/medford_impl.h b/sys/dev/sfxge/common/medford_impl.h new file mode 100644 index 0000000..11084dc --- /dev/null +++ b/sys/dev/sfxge/common/medford_impl.h @@ -0,0 +1,47 @@ +/*- + * Copyright (c) 2015 Solarflare Communications Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + * + * $FreeBSD$ + */ + +#ifndef _SYS_MEDFORD_IMPL_H +#define _SYS_MEDFORD_IMPL_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define MEDFORD_PIOBUF_NBUFS (16) + + +#ifdef __cplusplus +} +#endif + +#endif /* _SYS_MEDFORD_IMPL_H */ diff --git a/sys/dev/sfxge/common/medford_nic.c b/sys/dev/sfxge/common/medford_nic.c new file mode 100644 index 0000000..68c8184 --- /dev/null +++ b/sys/dev/sfxge/common/medford_nic.c @@ -0,0 +1,45 @@ +/*- + * Copyright (c) 2015 Solarflare Communications Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * The views and conclusions contained in the software and documentation are + * those of the authors and should not be interpreted as representing official + * policies, either expressed or implied, of the FreeBSD Project. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include "efx.h" +#include "efx_impl.h" +#include "mcdi_mon.h" + +#if EFSYS_OPT_MEDFORD + +#include "ef10_tlv_layout.h" + + + + +#endif /* EFSYS_OPT_MEDFORD */ diff --git a/sys/dev/sfxge/common/siena_flash.h b/sys/dev/sfxge/common/siena_flash.h index c1ee1c5..48ddfac 100644 --- a/sys/dev/sfxge/common/siena_flash.h +++ b/sys/dev/sfxge/common/siena_flash.h @@ -91,6 +91,19 @@ typedef struct blob_hdr_s { /* GENERATED BY scripts/genfwdef */ #define BLOB_CPU_TYPE_RXDI_VTBL1 (14) #define BLOB_CPU_TYPE_TXDI_VTBL1 (15) #define BLOB_CPU_TYPE_DUMPSPEC (32) +#define BLOB_CPU_TYPE_MC_XIP (33) + +#define BLOB_CPU_TYPE_INVALID (31) + +/* + * The upper four bits of the CPU type field specify the compression + * algorithm used for this blob. + */ +#define BLOB_COMPRESSION_MASK (0xf0000000) +#define BLOB_CPU_TYPE_MASK (0x0fffffff) + +#define BLOB_COMPRESSION_NONE (0x00000000) /* Stored as is */ +#define BLOB_COMPRESSION_LZ (0x10000000) /* see lib/lzdecoder.c */ typedef struct siena_mc_boot_hdr_s { /* GENERATED BY scripts/genfwdef */ efx_dword_t magic; /* = SIENA_MC_BOOT_MAGIC */ @@ -193,7 +206,7 @@ typedef struct siena_mc_combo_rom_hdr_s { /* GENERATED BY scripts/genfwdef */ efx_byte_t infoblk_len;/* length of space reserved for one infoblk structure */ efx_byte_t reserved[7];/* (set to 0) */ } v2; - }; + } data; } siena_mc_combo_rom_hdr_t; #pragma pack() diff --git a/sys/dev/sfxge/common/siena_impl.h b/sys/dev/sfxge/common/siena_impl.h index b65e399..639ac6b 100644 --- a/sys/dev/sfxge/common/siena_impl.h +++ b/sys/dev/sfxge/common/siena_impl.h @@ -55,29 +55,29 @@ typedef enum siena_phy_prop_e { #define SIENA_NVRAM_CHUNK 0x80 -extern __checkReturn int +extern __checkReturn efx_rc_t siena_nic_probe( __in efx_nic_t *enp); #if EFSYS_OPT_PCIE_TUNE -extern __checkReturn int +extern __checkReturn efx_rc_t siena_nic_pcie_extended_sync( __in efx_nic_t *enp); #endif -extern __checkReturn int +extern __checkReturn efx_rc_t siena_nic_reset( __in efx_nic_t *enp); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_nic_init( __in efx_nic_t *enp); #if EFSYS_OPT_DIAG -extern __checkReturn int +extern __checkReturn efx_rc_t siena_nic_register_test( __in efx_nic_t *enp); @@ -99,7 +99,7 @@ siena_sram_init( #if EFSYS_OPT_DIAG -extern __checkReturn int +extern __checkReturn efx_rc_t siena_sram_test( __in efx_nic_t *enp, __in efx_sram_pattern_fn_t func); @@ -108,7 +108,7 @@ siena_sram_test( #if EFSYS_OPT_MCDI -extern __checkReturn int +extern __checkReturn efx_rc_t siena_mcdi_init( __in efx_nic_t *enp, __in const efx_mcdi_transport_t *mtp); @@ -122,15 +122,22 @@ siena_mcdi_request_copyin( __in boolean_t new_epoch); extern __checkReturn boolean_t -siena_mcdi_request_poll( +siena_mcdi_poll_response( __in efx_nic_t *enp); extern void +siena_mcdi_read_response( + __in efx_nic_t *enp, + __out_bcount(length) void *bufferp, + __in size_t offset, + __in size_t length); + +extern void siena_mcdi_request_copyout( __in efx_nic_t *enp, __in efx_mcdi_req_t *emrp); -extern int +extern efx_rc_t siena_mcdi_poll_reboot( __in efx_nic_t *enp); @@ -138,50 +145,46 @@ extern void siena_mcdi_fini( __in efx_nic_t *enp); -extern __checkReturn int -siena_mcdi_fw_update_supported( - __in efx_nic_t *enp, - __out boolean_t *supportedp); - -extern __checkReturn int -siena_mcdi_macaddr_change_supported( +extern __checkReturn efx_rc_t +siena_mcdi_feature_supported( __in efx_nic_t *enp, + __in efx_mcdi_feature_id_t id, __out boolean_t *supportedp); #endif /* EFSYS_OPT_MCDI */ #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD -extern __checkReturn int +extern __checkReturn efx_rc_t siena_nvram_partn_size( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __out size_t *sizep); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_nvram_partn_lock( __in efx_nic_t *enp, - __in unsigned int partn); + __in uint32_t partn); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_nvram_partn_read( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __in unsigned int offset, __out_bcount(size) caddr_t data, __in size_t size); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_nvram_partn_erase( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __in unsigned int offset, __in size_t size); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_nvram_partn_write( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __in unsigned int offset, __out_bcount(size) caddr_t data, __in size_t size); @@ -189,12 +192,12 @@ siena_nvram_partn_write( extern void siena_nvram_partn_unlock( __in efx_nic_t *enp, - __in unsigned int partn); + __in uint32_t partn); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_nvram_get_dynamic_cfg( __in efx_nic_t *enp, - __in unsigned int index, + __in uint32_t partn, __in boolean_t vpd, __out siena_mc_dynamic_config_hdr_t **dcfgp, __out size_t *sizep); @@ -205,38 +208,38 @@ siena_nvram_get_dynamic_cfg( #if EFSYS_OPT_DIAG -extern __checkReturn int +extern __checkReturn efx_rc_t siena_nvram_test( __in efx_nic_t *enp); #endif /* EFSYS_OPT_DIAG */ -extern __checkReturn int +extern __checkReturn efx_rc_t siena_nvram_size( __in efx_nic_t *enp, __in efx_nvram_type_t type, __out size_t *sizep); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_nvram_get_subtype( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __out uint32_t *subtypep); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_nvram_get_version( __in efx_nic_t *enp, __in efx_nvram_type_t type, __out uint32_t *subtypep, __out_ecount(4) uint16_t version[4]); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_nvram_rw_start( __in efx_nic_t *enp, __in efx_nvram_type_t type, __out size_t *pref_chunkp); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_nvram_read_chunk( __in efx_nic_t *enp, __in efx_nvram_type_t type, @@ -244,12 +247,12 @@ siena_nvram_read_chunk( __out_bcount(size) caddr_t data, __in size_t size); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_nvram_erase( __in efx_nic_t *enp, __in efx_nvram_type_t type); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_nvram_write_chunk( __in efx_nic_t *enp, __in efx_nvram_type_t type, @@ -262,58 +265,64 @@ siena_nvram_rw_finish( __in efx_nic_t *enp, __in efx_nvram_type_t type); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_nvram_set_version( __in efx_nic_t *enp, __in efx_nvram_type_t type, __in_ecount(4) uint16_t version[4]); +extern __checkReturn efx_rc_t +siena_nvram_type_to_partn( + __in efx_nic_t *enp, + __in efx_nvram_type_t type, + __out uint32_t *partnp); + #endif /* EFSYS_OPT_NVRAM */ #if EFSYS_OPT_VPD -extern __checkReturn int +extern __checkReturn efx_rc_t siena_vpd_init( __in efx_nic_t *enp); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_vpd_size( __in efx_nic_t *enp, __out size_t *sizep); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_vpd_read( __in efx_nic_t *enp, __out_bcount(size) caddr_t data, __in size_t size); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_vpd_verify( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_vpd_reinit( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_vpd_get( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size, __inout efx_vpd_value_t *evvp); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_vpd_set( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size, __in efx_vpd_value_t *evvp); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_vpd_next( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, @@ -321,7 +330,7 @@ siena_vpd_next( __out efx_vpd_value_t *evvp, __inout unsigned int *contp); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_vpd_write( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, @@ -350,44 +359,44 @@ siena_phy_link_ev( __in efx_qword_t *eqp, __out efx_link_mode_t *link_modep); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_phy_get_link( __in efx_nic_t *enp, __out siena_link_state_t *slsp); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_phy_power( __in efx_nic_t *enp, __in boolean_t on); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_phy_reconfigure( __in efx_nic_t *enp); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_phy_verify( __in efx_nic_t *enp); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_phy_oui_get( __in efx_nic_t *enp, __out uint32_t *ouip); #if EFSYS_OPT_PHY_STATS -extern void +extern void siena_phy_decode_stats( - __in efx_nic_t *enp, - __in uint32_t vmask, - __in_opt efsys_mem_t *esmp, - __out_opt uint64_t *smaskp, - __out_ecount_opt(EFX_PHY_NSTATS) uint32_t *stat); + __in efx_nic_t *enp, + __in uint32_t vmask, + __in_opt efsys_mem_t *esmp, + __out_opt uint64_t *smaskp, + __inout_ecount_opt(EFX_PHY_NSTATS) uint32_t *stat); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_phy_stats_update( __in efx_nic_t *enp, __in efsys_mem_t *esmp, - __out_ecount(EFX_PHY_NSTATS) uint32_t *stat); + __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); #endif /* EFSYS_OPT_PHY_STATS */ @@ -402,14 +411,14 @@ siena_phy_prop_name( #endif /* EFSYS_OPT_NAMES */ -extern __checkReturn int +extern __checkReturn efx_rc_t siena_phy_prop_get( __in efx_nic_t *enp, __in unsigned int id, __in uint32_t flags, __out uint32_t *valp); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_phy_prop_set( __in efx_nic_t *enp, __in unsigned int id, @@ -419,12 +428,12 @@ siena_phy_prop_set( #if EFSYS_OPT_BIST -extern __checkReturn int +extern __checkReturn efx_rc_t siena_phy_bist_start( __in efx_nic_t *enp, __in efx_bist_type_t type); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_phy_bist_poll( __in efx_nic_t *enp, __in efx_bist_type_t type, @@ -442,23 +451,23 @@ siena_phy_bist_stop( #endif /* EFSYS_OPT_BIST */ -extern __checkReturn int +extern __checkReturn efx_rc_t siena_mac_poll( __in efx_nic_t *enp, __out efx_link_mode_t *link_modep); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_mac_up( __in efx_nic_t *enp, __out boolean_t *mac_upp); -extern __checkReturn int +extern __checkReturn efx_rc_t siena_mac_reconfigure( __in efx_nic_t *enp); #if EFSYS_OPT_LOOPBACK -extern __checkReturn int +extern __checkReturn efx_rc_t siena_mac_loopback_set( __in efx_nic_t *enp, __in efx_link_mode_t link_mode, @@ -468,12 +477,12 @@ siena_mac_loopback_set( #if EFSYS_OPT_MAC_STATS -extern __checkReturn int +extern __checkReturn efx_rc_t siena_mac_stats_update( __in efx_nic_t *enp, __in efsys_mem_t *esmp, - __out_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, - __out_opt uint32_t *generationp); + __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, + __inout_opt uint32_t *generationp); #endif /* EFSYS_OPT_MAC_STATS */ diff --git a/sys/dev/sfxge/common/siena_mac.c b/sys/dev/sfxge/common/siena_mac.c index beeaea1..12ecffd 100644 --- a/sys/dev/sfxge/common/siena_mac.c +++ b/sys/dev/sfxge/common/siena_mac.c @@ -31,20 +31,19 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" #include "efx_impl.h" #if EFSYS_OPT_SIENA - __checkReturn int + __checkReturn efx_rc_t siena_mac_poll( __in efx_nic_t *enp, __out efx_link_mode_t *link_modep) { efx_port_t *epp = &(enp->en_port); siena_link_state_t sls; - int rc; + efx_rc_t rc; if ((rc = siena_phy_get_link(enp, &sls)) != 0) goto fail1; @@ -57,20 +56,20 @@ siena_mac_poll( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); *link_modep = EFX_LINK_UNKNOWN; return (rc); } - __checkReturn int + __checkReturn efx_rc_t siena_mac_up( __in efx_nic_t *enp, __out boolean_t *mac_upp) { siena_link_state_t sls; - int rc; + efx_rc_t rc; /* * Because Siena doesn't *require* polling, we can't rely on @@ -84,12 +83,12 @@ siena_mac_up( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t siena_mac_reconfigure( __in efx_nic_t *enp) { @@ -101,7 +100,7 @@ siena_mac_reconfigure( MAX(MC_CMD_SET_MCAST_HASH_IN_LEN, MC_CMD_SET_MCAST_HASH_OUT_LEN))]; unsigned int fcntl; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_SET_MAC; @@ -184,14 +183,14 @@ siena_mac_reconfigure( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } #if EFSYS_OPT_LOOPBACK - __checkReturn int + __checkReturn efx_rc_t siena_mac_loopback_set( __in efx_nic_t *enp, __in efx_link_mode_t link_mode, @@ -201,7 +200,7 @@ siena_mac_loopback_set( efx_phy_ops_t *epop = epp->ep_epop; efx_loopback_type_t old_loopback_type; efx_link_mode_t old_loopback_link_mode; - int rc; + efx_rc_t rc; /* The PHY object handles this on Siena */ old_loopback_type = epp->ep_loopback_type; @@ -230,12 +229,12 @@ fail1: #define SIENA_MAC_STAT_READ(_esmp, _field, _eqp) \ EFSYS_MEM_READQ((_esmp), (_field) * sizeof (efx_qword_t), _eqp) - __checkReturn int + __checkReturn efx_rc_t siena_mac_stats_update( __in efx_nic_t *enp, __in efsys_mem_t *esmp, - __out_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, - __out_opt uint32_t *generationp) + __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, + __inout_opt uint32_t *generationp) { efx_qword_t value; efx_qword_t generation_start; diff --git a/sys/dev/sfxge/common/siena_mcdi.c b/sys/dev/sfxge/common/siena_mcdi.c index b2224ac..f3af2bf6f 100644 --- a/sys/dev/sfxge/common/siena_mcdi.c +++ b/sys/dev/sfxge/common/siena_mcdi.c @@ -31,7 +31,6 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" #include "efx_impl.h" @@ -53,52 +52,85 @@ __FBSDID("$FreeBSD$"); : MC_SMEM_P1_STATUS_OFST >> 2) - void -siena_mcdi_request_copyin( +static void +siena_mcdi_send_request( __in efx_nic_t *enp, - __in efx_mcdi_req_t *emrp, - __in unsigned int seq, - __in boolean_t ev_cpl, - __in boolean_t new_epoch) + __in void *hdrp, + __in size_t hdr_len, + __in void *sdup, + __in size_t sdu_len) { efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); efx_dword_t dword; - unsigned int xflags; unsigned int pdur; unsigned int dbr; unsigned int pos; EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA); - _NOTE(ARGUNUSED(new_epoch)) EFSYS_ASSERT(emip->emi_port == 1 || emip->emi_port == 2); pdur = SIENA_MCDI_PDU(emip); dbr = SIENA_MCDI_DOORBELL(emip); + /* Write the header */ + EFSYS_ASSERT3U(hdr_len, ==, sizeof (efx_dword_t)); + dword = *(efx_dword_t *)hdrp; + EFX_BAR_TBL_WRITED(enp, FR_CZ_MC_TREG_SMEM, pdur, &dword, B_TRUE); + + /* Write the payload */ + for (pos = 0; pos < sdu_len; pos += sizeof (efx_dword_t)) { + dword = *(efx_dword_t *)((uint8_t *)sdup + pos); + EFX_BAR_TBL_WRITED(enp, FR_CZ_MC_TREG_SMEM, + pdur + 1 + (pos >> 2), &dword, B_FALSE); + } + + /* Ring the doorbell */ + EFX_POPULATE_DWORD_1(dword, EFX_DWORD_0, 0xd004be11); + EFX_BAR_TBL_WRITED(enp, FR_CZ_MC_TREG_SMEM, dbr, &dword, B_FALSE); +} + + void +siena_mcdi_request_copyin( + __in efx_nic_t *enp, + __in efx_mcdi_req_t *emrp, + __in unsigned int seq, + __in boolean_t ev_cpl, + __in boolean_t new_epoch) +{ +#if EFSYS_OPT_MCDI_LOGGING + const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp; +#endif + efx_dword_t hdr; + size_t hdr_len; + unsigned int xflags; + + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA); + _NOTE(ARGUNUSED(new_epoch)) + xflags = 0; if (ev_cpl) xflags |= MCDI_HEADER_XFLAGS_EVREQ; - /* Construct the header in shared memory */ - EFX_POPULATE_DWORD_6(dword, + /* Construct the header */ + hdr_len = sizeof (hdr); + EFX_POPULATE_DWORD_6(hdr, MCDI_HEADER_CODE, emrp->emr_cmd, MCDI_HEADER_RESYNC, 1, MCDI_HEADER_DATALEN, emrp->emr_in_length, MCDI_HEADER_SEQ, seq, MCDI_HEADER_RESPONSE, 0, MCDI_HEADER_XFLAGS, xflags); - EFX_BAR_TBL_WRITED(enp, FR_CZ_MC_TREG_SMEM, pdur, &dword, B_TRUE); - for (pos = 0; pos < emrp->emr_in_length; pos += sizeof (efx_dword_t)) { - memcpy(&dword, MCDI_IN(*emrp, efx_dword_t, pos), - MIN(sizeof (dword), emrp->emr_in_length - pos)); - EFX_BAR_TBL_WRITED(enp, FR_CZ_MC_TREG_SMEM, - pdur + 1 + (pos >> 2), &dword, B_FALSE); +#if EFSYS_OPT_MCDI_LOGGING + if (emtp->emt_logger != NULL) { + emtp->emt_logger(emtp->emt_context, EFX_LOG_MCDI_REQUEST, + &hdr, sizeof (hdr), + emrp->emr_in_buf, emrp->emr_in_length); } +#endif /* EFSYS_OPT_MCDI_LOGGING */ - /* Ring the doorbell */ - EFX_POPULATE_DWORD_1(dword, EFX_DWORD_0, 0xd004be11); - EFX_BAR_TBL_WRITED(enp, FR_CZ_MC_TREG_SMEM, dbr, &dword, B_FALSE); + siena_mcdi_send_request(enp, &hdr, hdr_len, + emrp->emr_in_buf, emrp->emr_in_length); } void @@ -106,27 +138,31 @@ siena_mcdi_request_copyout( __in efx_nic_t *enp, __in efx_mcdi_req_t *emrp) { - efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); - unsigned int pos; - unsigned int pdur; - efx_dword_t data; - - pdur = SIENA_MCDI_PDU(emip); +#if EFSYS_OPT_MCDI_LOGGING + const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp; + efx_dword_t hdr; +#endif + size_t bytes = MIN(emrp->emr_out_length_used, emrp->emr_out_length); /* Copy payload out if caller supplied buffer */ if (emrp->emr_out_buf != NULL) { - size_t bytes = MIN(emrp->emr_out_length_used, - emrp->emr_out_length); - for (pos = 0; pos < bytes; pos += sizeof (efx_dword_t)) { - EFX_BAR_TBL_READD(enp, FR_CZ_MC_TREG_SMEM, - pdur + 1 + (pos >> 2), &data, B_FALSE); - memcpy(MCDI_OUT(*emrp, efx_dword_t, pos), &data, - MIN(sizeof (data), bytes - pos)); - } + siena_mcdi_read_response(enp, emrp->emr_out_buf, + sizeof (efx_dword_t), bytes); } + +#if EFSYS_OPT_MCDI_LOGGING + if (emtp->emt_logger != NULL) { + siena_mcdi_read_response(enp, &hdr, 0, sizeof (hdr)); + + emtp->emt_logger(emtp->emt_context, + EFX_LOG_MCDI_RESPONSE, + &hdr, sizeof (hdr), + emrp->emr_out_buf, bytes); + } +#endif /* EFSYS_OPT_MCDI_LOGGING */ } - int + efx_rc_t siena_mcdi_poll_reboot( __in efx_nic_t *enp) { @@ -163,124 +199,45 @@ siena_mcdi_poll_reboot( #endif } - __checkReturn boolean_t -siena_mcdi_request_poll( +extern __checkReturn boolean_t +siena_mcdi_poll_response( __in efx_nic_t *enp) { efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); - efx_mcdi_req_t *emrp; - efx_dword_t dword; + efx_dword_t hdr; unsigned int pdur; - unsigned int seq; - unsigned int length; - int state; - int rc; - - EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); - - /* Serialise against post-watchdog efx_mcdi_ev* */ - EFSYS_LOCK(enp->en_eslp, state); - - EFSYS_ASSERT(emip->emi_pending_req != NULL); - EFSYS_ASSERT(!emip->emi_ev_cpl); - emrp = emip->emi_pending_req; - - /* Check for reboot atomically w.r.t efx_mcdi_request_start */ - if (emip->emi_poll_cnt++ == 0) { - if ((rc = siena_mcdi_poll_reboot(enp)) != 0) { - emip->emi_pending_req = NULL; - EFSYS_UNLOCK(enp->en_eslp, state); - - goto fail1; - } - } EFSYS_ASSERT(emip->emi_port == 1 || emip->emi_port == 2); pdur = SIENA_MCDI_PDU(emip); - /* Read the command header */ - EFX_BAR_TBL_READD(enp, FR_CZ_MC_TREG_SMEM, pdur, &dword, B_FALSE); - if (EFX_DWORD_FIELD(dword, MCDI_HEADER_RESPONSE) == 0) { - EFSYS_UNLOCK(enp->en_eslp, state); - return (B_FALSE); - } - - /* Request complete */ - emip->emi_pending_req = NULL; - seq = (emip->emi_seq - 1) & EFX_MASK32(MCDI_HEADER_SEQ); - - /* Check for synchronous reboot */ - if (EFX_DWORD_FIELD(dword, MCDI_HEADER_ERROR) != 0 && - EFX_DWORD_FIELD(dword, MCDI_HEADER_DATALEN) == 0) { - /* Consume status word */ - EFSYS_SPIN(EFX_MCDI_STATUS_SLEEP_US); - siena_mcdi_poll_reboot(enp); - EFSYS_UNLOCK(enp->en_eslp, state); - rc = EIO; - goto fail2; - } - - EFSYS_UNLOCK(enp->en_eslp, state); + EFX_BAR_TBL_READD(enp, FR_CZ_MC_TREG_SMEM, pdur, &hdr, B_FALSE); + return (EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE) ? B_TRUE : B_FALSE); +} - /* Check that the returned data is consistent */ - if (EFX_DWORD_FIELD(dword, MCDI_HEADER_CODE) != emrp->emr_cmd || - EFX_DWORD_FIELD(dword, MCDI_HEADER_SEQ) != seq) { - /* Response is for a different request */ - rc = EIO; - goto fail3; - } + void +siena_mcdi_read_response( + __in efx_nic_t *enp, + __out_bcount(length) void *bufferp, + __in size_t offset, + __in size_t length) +{ + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); + unsigned int pdur; + unsigned int pos; + efx_dword_t data; - length = EFX_DWORD_FIELD(dword, MCDI_HEADER_DATALEN); - if (EFX_DWORD_FIELD(dword, MCDI_HEADER_ERROR)) { - efx_dword_t errdword; - int errcode; + EFSYS_ASSERT(emip->emi_port == 1 || emip->emi_port == 2); + pdur = SIENA_MCDI_PDU(emip); - EFSYS_ASSERT3U(length, ==, 4); + for (pos = 0; pos < length; pos += sizeof (efx_dword_t)) { EFX_BAR_TBL_READD(enp, FR_CZ_MC_TREG_SMEM, - pdur + 1 + (MC_CMD_ERR_CODE_OFST >> 2), - &errdword, B_FALSE); - errcode = EFX_DWORD_FIELD(errdword, EFX_DWORD_0); - rc = efx_mcdi_request_errcode(errcode); - if (!emrp->emr_quiet) { - EFSYS_PROBE2(mcdi_err, int, emrp->emr_cmd, - int, errcode); - } - goto fail4; - - } else { - emrp->emr_out_length_used = length; - emrp->emr_rc = 0; - siena_mcdi_request_copyout(enp, emrp); + pdur + ((offset + pos) >> 2), &data, B_FALSE); + memcpy((uint8_t *)bufferp + pos, &data, + MIN(sizeof (data), length - pos)); } - - goto out; - -fail4: - if (!emrp->emr_quiet) - EFSYS_PROBE(fail4); -fail3: - if (!emrp->emr_quiet) - EFSYS_PROBE(fail3); -fail2: - if (!emrp->emr_quiet) - EFSYS_PROBE(fail2); -fail1: - if (!emrp->emr_quiet) - EFSYS_PROBE1(fail1, int, rc); - - /* Fill out error state */ - emrp->emr_rc = rc; - emrp->emr_out_length_used = 0; - - /* Reboot/Assertion */ - if (rc == EIO || rc == EINTR) - efx_mcdi_raise_exception(enp, emrp, rc); - -out: - return (B_TRUE); } - __checkReturn int + __checkReturn efx_rc_t siena_mcdi_init( __in efx_nic_t *enp, __in const efx_mcdi_transport_t *mtp) @@ -288,7 +245,7 @@ siena_mcdi_init( efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); efx_oword_t oword; unsigned int portnum; - int rc; + efx_rc_t rc; EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA); @@ -306,6 +263,9 @@ siena_mcdi_init( goto fail1; } + /* Siena BootROM and firmware only support MCDIv1 */ + emip->emi_max_version = 1; + /* * Wipe the atomic reboot status so subsequent MCDI requests succeed. * BOOT_STATUS is preserved so eno_nic_probe() can boot out of the @@ -316,7 +276,7 @@ siena_mcdi_init( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -327,28 +287,35 @@ siena_mcdi_fini( { } - __checkReturn int -siena_mcdi_fw_update_supported( + __checkReturn efx_rc_t +siena_mcdi_feature_supported( __in efx_nic_t *enp, + __in efx_mcdi_feature_id_t id, __out boolean_t *supportedp) { + efx_rc_t rc; + EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); - *supportedp = B_TRUE; + switch (id) { + case EFX_MCDI_FEATURE_FW_UPDATE: + case EFX_MCDI_FEATURE_LINK_CONTROL: + case EFX_MCDI_FEATURE_MACADDR_CHANGE: + case EFX_MCDI_FEATURE_MAC_SPOOFING: + *supportedp = B_TRUE; + break; + default: + rc = ENOTSUP; + goto fail1; + break; + } return (0); -} - __checkReturn int -siena_mcdi_macaddr_change_supported( - __in efx_nic_t *enp, - __out boolean_t *supportedp) -{ - EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); - - *supportedp = B_TRUE; +fail1: + EFSYS_PROBE1(fail1, efx_rc_t, rc); - return (0); + return (rc); } #endif /* EFSYS_OPT_SIENA && EFSYS_OPT_MCDI */ diff --git a/sys/dev/sfxge/common/siena_nic.c b/sys/dev/sfxge/common/siena_nic.c index 3dcf48e..70e7b5d 100644 --- a/sys/dev/sfxge/common/siena_nic.c +++ b/sys/dev/sfxge/common/siena_nic.c @@ -31,14 +31,13 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" #include "efx_impl.h" #include "mcdi_mon.h" #if EFSYS_OPT_SIENA -static __checkReturn int +static __checkReturn efx_rc_t siena_nic_get_partn_mask( __in efx_nic_t *enp, __out unsigned int *maskp) @@ -46,7 +45,7 @@ siena_nic_get_partn_mask( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_NVRAM_TYPES_IN_LEN, MC_CMD_NVRAM_TYPES_OUT_LEN)]; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_NVRAM_TYPES; @@ -74,18 +73,18 @@ siena_nic_get_partn_mask( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } #if EFSYS_OPT_PCIE_TUNE - __checkReturn int + __checkReturn efx_rc_t siena_nic_pcie_extended_sync( __in efx_nic_t *enp) { - int rc; + efx_rc_t rc; if ((rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG17230, B_TRUE, NULL) != 0)) @@ -94,14 +93,14 @@ siena_nic_pcie_extended_sync( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } #endif /* EFSYS_OPT_PCIE_TUNE */ -static __checkReturn int +static __checkReturn efx_rc_t siena_board_cfg( __in efx_nic_t *enp) { @@ -110,7 +109,7 @@ siena_board_cfg( efx_dword_t capabilities; uint32_t board_type; uint32_t nevq, nrxq, ntxq; - int rc; + efx_rc_t rc; /* External port identifier using one-based port numbering */ encp->enc_external_port = (uint8_t)enp->en_mcdi.em_emip.emi_port; @@ -170,23 +169,24 @@ siena_board_cfg( encp->enc_hw_tx_insert_vlan_enabled = B_FALSE; encp->enc_fw_assisted_tso_enabled = B_FALSE; + encp->enc_allow_set_mac_with_installed_filters = B_TRUE; return (0); fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } -static __checkReturn int +static __checkReturn efx_rc_t siena_phy_cfg( __in efx_nic_t *enp) { efx_nic_cfg_t *encp = &(enp->en_nic_cfg); - int rc; + efx_rc_t rc; /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */ if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0) @@ -201,12 +201,12 @@ siena_phy_cfg( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t siena_nic_probe( __in efx_nic_t *enp) { @@ -215,7 +215,7 @@ siena_nic_probe( siena_link_state_t sls; unsigned int mask; efx_oword_t oword; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); @@ -314,17 +314,17 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t siena_nic_reset( __in efx_nic_t *enp) { efx_mcdi_req_t req; - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); @@ -360,7 +360,7 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (0); } @@ -395,11 +395,11 @@ siena_nic_usrev_dis( EFX_BAR_WRITEO(enp, FR_CZ_USR_EV_CFG, &oword); } - __checkReturn int + __checkReturn efx_rc_t siena_nic_init( __in efx_nic_t *enp) { - int rc; + efx_rc_t rc; EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA); @@ -419,12 +419,14 @@ siena_nic_init( if ((rc = siena_phy_reconfigure(enp)) != 0) goto fail2; + enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V1; + return (0); fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -506,7 +508,7 @@ static const uint32_t __siena_table_masks[] = { 0xFFFF07FF, 0xFFFFFFFF, 0x0000007F, 0x00000000, }; - __checkReturn int + __checkReturn efx_rc_t siena_nic_register_test( __in efx_nic_t *enp) { @@ -514,7 +516,7 @@ siena_nic_register_test( const uint32_t *dwordp; unsigned int nitems; unsigned int count; - int rc; + efx_rc_t rc; /* Fill out the register mask entries */ EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_register_masks) @@ -571,7 +573,7 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } diff --git a/sys/dev/sfxge/common/siena_nvram.c b/sys/dev/sfxge/common/siena_nvram.c index 7d20ec0..8f107b4 100644 --- a/sys/dev/sfxge/common/siena_nvram.c +++ b/sys/dev/sfxge/common/siena_nvram.c @@ -31,30 +31,28 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" -#include "efx_types.h" -#include "efx_regs.h" #include "efx_impl.h" #if EFSYS_OPT_SIENA #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM - __checkReturn int + __checkReturn efx_rc_t siena_nvram_partn_size( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __out size_t *sizep) { - int rc; + efx_rc_t rc; if ((1 << partn) & ~enp->en_u.siena.enu_partn_mask) { rc = ENOTSUP; goto fail1; } - if ((rc = efx_mcdi_nvram_info(enp, partn, sizep, NULL, NULL)) != 0) { + if ((rc = efx_mcdi_nvram_info(enp, partn, sizep, + NULL, NULL, NULL)) != 0) { goto fail2; } @@ -63,17 +61,17 @@ siena_nvram_partn_size( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t siena_nvram_partn_lock( __in efx_nic_t *enp, - __in unsigned int partn) + __in uint32_t partn) { - int rc; + efx_rc_t rc; if ((rc = efx_mcdi_nvram_update_start(enp, partn)) != 0) { goto fail1; @@ -82,21 +80,21 @@ siena_nvram_partn_lock( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t siena_nvram_partn_read( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __in unsigned int offset, __out_bcount(size) caddr_t data, __in size_t size) { size_t chunk; - int rc; + efx_rc_t rc; while (size > 0) { chunk = MIN(size, SIENA_NVRAM_CHUNK); @@ -114,19 +112,19 @@ siena_nvram_partn_read( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t siena_nvram_partn_erase( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __in unsigned int offset, __in size_t size) { - int rc; + efx_rc_t rc; if ((rc = efx_mcdi_nvram_erase(enp, partn, offset, size)) != 0) { goto fail1; @@ -135,21 +133,21 @@ siena_nvram_partn_erase( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t siena_nvram_partn_write( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __in unsigned int offset, __out_bcount(size) caddr_t data, __in size_t size) { size_t chunk; - int rc; + efx_rc_t rc; while (size > 0) { chunk = MIN(size, SIENA_NVRAM_CHUNK); @@ -167,7 +165,7 @@ siena_nvram_partn_write( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -175,10 +173,10 @@ fail1: void siena_nvram_partn_unlock( __in efx_nic_t *enp, - __in unsigned int partn) + __in uint32_t partn) { boolean_t reboot; - int rc; + efx_rc_t rc; /* * Reboot into the new image only for PHYs. The driver has to @@ -195,7 +193,7 @@ siena_nvram_partn_unlock( return; fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); } #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */ @@ -231,37 +229,41 @@ static siena_parttbl_entry_t siena_parttbl[] = { {MC_CMD_NVRAM_TYPE_CPLD, 2, EFX_NVRAM_CPLD}, }; -static __checkReturn siena_parttbl_entry_t * -siena_parttbl_entry( + __checkReturn efx_rc_t +siena_nvram_type_to_partn( __in efx_nic_t *enp, - __in efx_nvram_type_t type) + __in efx_nvram_type_t type, + __out uint32_t *partnp) { efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); - siena_parttbl_entry_t *entry; unsigned int i; EFSYS_ASSERT3U(type, <, EFX_NVRAM_NTYPES); + EFSYS_ASSERT(partnp != NULL); for (i = 0; i < EFX_ARRAY_SIZE(siena_parttbl); i++) { - entry = &siena_parttbl[i]; + siena_parttbl_entry_t *entry = &siena_parttbl[i]; - if (entry->port == emip->emi_port && entry->nvtype == type) - return (entry); + if (entry->port == emip->emi_port && entry->nvtype == type) { + *partnp = entry->partn; + return (0); + } } - return (NULL); + return (ENOTSUP); } + #if EFSYS_OPT_DIAG - __checkReturn int + __checkReturn efx_rc_t siena_nvram_test( __in efx_nic_t *enp) { efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); siena_parttbl_entry_t *entry; unsigned int i; - int rc; + efx_rc_t rc; /* * Iterate over the list of supported partition types @@ -282,28 +284,26 @@ siena_nvram_test( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } #endif /* EFSYS_OPT_DIAG */ - __checkReturn int + __checkReturn efx_rc_t siena_nvram_size( __in efx_nic_t *enp, __in efx_nvram_type_t type, __out size_t *sizep) { - siena_parttbl_entry_t *entry; - int rc; + uint32_t partn; + efx_rc_t rc; - if ((entry = siena_parttbl_entry(enp, type)) == NULL) { - rc = ENOTSUP; + if ((rc = siena_nvram_type_to_partn(enp, type, &partn)) != 0) goto fail1; - } - if ((rc = siena_nvram_partn_size(enp, entry->partn, sizep)) != 0) + if ((rc = siena_nvram_partn_size(enp, partn, sizep)) != 0) goto fail2; return (0); @@ -311,7 +311,7 @@ siena_nvram_size( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); *sizep = 0; @@ -322,10 +322,10 @@ fail1: (sizeof (siena_mc_dynamic_config_hdr_t) + ((_nitems) * \ sizeof (((siena_mc_dynamic_config_hdr_t *)NULL)->fw_version[0]))) - __checkReturn int + __checkReturn efx_rc_t siena_nvram_get_dynamic_cfg( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __in boolean_t vpd, __out siena_mc_dynamic_config_hdr_t **dcfgp, __out size_t *sizep) @@ -339,7 +339,7 @@ siena_nvram_get_dynamic_cfg( unsigned int nversions; unsigned int pos; unsigned int region; - int rc; + efx_rc_t rc; EFSYS_ASSERT(partn == MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 || partn == MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1); @@ -446,22 +446,22 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t siena_nvram_get_subtype( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __out uint32_t *subtypep) { efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_GET_BOARD_CFG_IN_LEN, MC_CMD_GET_BOARD_CFG_OUT_LENMAX)]; efx_word_t *fw_list; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_GET_BOARD_CFG; @@ -500,12 +500,12 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t siena_nvram_get_version( __in efx_nic_t *enp, __in efx_nvram_type_t type, @@ -514,16 +514,13 @@ siena_nvram_get_version( { siena_mc_dynamic_config_hdr_t *dcfg; siena_parttbl_entry_t *entry; - unsigned int dcfg_partn; - unsigned int partn; + uint32_t dcfg_partn; + uint32_t partn; unsigned int i; - int rc; + efx_rc_t rc; - if ((entry = siena_parttbl_entry(enp, type)) == NULL) { - rc = ENOTSUP; + if ((rc = siena_nvram_type_to_partn(enp, type, &partn)) != 0) goto fail1; - } - partn = entry->partn; if ((1 << partn) & ~enp->en_u.siena.enu_partn_mask) { rc = ENOTSUP; @@ -593,26 +590,24 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t siena_nvram_rw_start( __in efx_nic_t *enp, __in efx_nvram_type_t type, __out size_t *chunk_sizep) { - siena_parttbl_entry_t *entry; - int rc; + uint32_t partn; + efx_rc_t rc; - if ((entry = siena_parttbl_entry(enp, type)) == NULL) { - rc = ENOTSUP; + if ((rc = siena_nvram_type_to_partn(enp, type, &partn)) != 0) goto fail1; - } - if ((rc = siena_nvram_partn_lock(enp, entry->partn)) != 0) + if ((rc = siena_nvram_partn_lock(enp, partn)) != 0) goto fail2; if (chunk_sizep != NULL) @@ -623,12 +618,12 @@ siena_nvram_rw_start( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t siena_nvram_read_chunk( __in efx_nic_t *enp, __in efx_nvram_type_t type, @@ -636,16 +631,13 @@ siena_nvram_read_chunk( __out_bcount(size) caddr_t data, __in size_t size) { - siena_parttbl_entry_t *entry; - int rc; + uint32_t partn; + efx_rc_t rc; - if ((entry = siena_parttbl_entry(enp, type)) == NULL) { - rc = ENOTSUP; + if ((rc = siena_nvram_type_to_partn(enp, type, &partn)) != 0) goto fail1; - } - if ((rc = siena_nvram_partn_read(enp, entry->partn, - offset, data, size)) != 0) + if ((rc = siena_nvram_partn_read(enp, partn, offset, data, size)) != 0) goto fail2; return (0); @@ -653,29 +645,27 @@ siena_nvram_read_chunk( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t siena_nvram_erase( __in efx_nic_t *enp, __in efx_nvram_type_t type) { - siena_parttbl_entry_t *entry; size_t size; - int rc; + uint32_t partn; + efx_rc_t rc; - if ((entry = siena_parttbl_entry(enp, type)) == NULL) { - rc = ENOTSUP; + if ((rc = siena_nvram_type_to_partn(enp, type, &partn)) != 0) goto fail1; - } - if ((rc = siena_nvram_partn_size(enp, entry->partn, &size)) != 0) + if ((rc = siena_nvram_partn_size(enp, partn, &size)) != 0) goto fail2; - if ((rc = siena_nvram_partn_erase(enp, entry->partn, 0, size)) != 0) + if ((rc = siena_nvram_partn_erase(enp, partn, 0, size)) != 0) goto fail3; return (0); @@ -685,12 +675,12 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t siena_nvram_write_chunk( __in efx_nic_t *enp, __in efx_nvram_type_t type, @@ -698,16 +688,13 @@ siena_nvram_write_chunk( __in_bcount(size) caddr_t data, __in size_t size) { - siena_parttbl_entry_t *entry; - int rc; + uint32_t partn; + efx_rc_t rc; - if ((entry = siena_parttbl_entry(enp, type)) == NULL) { - rc = ENOTSUP; + if ((rc = siena_nvram_type_to_partn(enp, type, &partn)) != 0) goto fail1; - } - if ((rc = siena_nvram_partn_write(enp, entry->partn, - offset, data, size)) != 0) + if ((rc = siena_nvram_partn_write(enp, partn, offset, data, size)) != 0) goto fail2; return (0); @@ -715,7 +702,7 @@ siena_nvram_write_chunk( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -725,22 +712,24 @@ siena_nvram_rw_finish( __in efx_nic_t *enp, __in efx_nvram_type_t type) { - siena_parttbl_entry_t *entry; + uint32_t partn; + efx_rc_t rc; - if ((entry = siena_parttbl_entry(enp, type)) != NULL) - siena_nvram_partn_unlock(enp, entry->partn); + if ((rc = siena_nvram_type_to_partn(enp, type, &partn)) == 0) + siena_nvram_partn_unlock(enp, partn); } - __checkReturn int + __checkReturn efx_rc_t siena_nvram_set_version( __in efx_nic_t *enp, __in efx_nvram_type_t type, __in_ecount(4) uint16_t version[4]) { + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); siena_mc_dynamic_config_hdr_t *dcfg = NULL; - siena_parttbl_entry_t *entry; - unsigned int dcfg_partn; - size_t partn_size; + siena_mc_fw_version_t *fwverp; + uint32_t dcfg_partn, partn; + size_t dcfg_size; unsigned int hdr_length; unsigned int vpd_length; unsigned int vpd_offset; @@ -750,18 +739,16 @@ siena_nvram_set_version( uint8_t cksum; uint32_t subtype; size_t length; - int rc; + efx_rc_t rc; - if ((entry = siena_parttbl_entry(enp, type)) == NULL) { - rc = ENOTSUP; + if ((rc = siena_nvram_type_to_partn(enp, type, &partn)) != 0) goto fail1; - } - dcfg_partn = (entry->port == 1) + dcfg_partn = (emip->emi_port == 1) ? MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 : MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1; - if ((rc = siena_nvram_partn_size(enp, dcfg_partn, &partn_size)) != 0) + if ((rc = siena_nvram_partn_size(enp, dcfg_partn, &dcfg_size)) != 0) goto fail2; if ((rc = siena_nvram_partn_lock(enp, dcfg_partn)) != 0) @@ -780,7 +767,7 @@ siena_nvram_set_version( * NOTE: This function will blatt any fields trailing the version * vector, or the VPD chunk. */ - required_hdr_length = SIENA_DYNAMIC_CFG_SIZE(entry->partn + 1); + required_hdr_length = SIENA_DYNAMIC_CFG_SIZE(partn + 1); if (required_hdr_length + vpd_length > length) { rc = ENOSPC; goto fail4; @@ -803,24 +790,20 @@ siena_nvram_set_version( } /* Get the subtype to insert into the fw_subtype array */ - if ((rc = siena_nvram_get_subtype(enp, entry->partn, &subtype)) != 0) + if ((rc = siena_nvram_get_subtype(enp, partn, &subtype)) != 0) goto fail5; /* Fill out the new version */ - EFX_POPULATE_DWORD_1(dcfg->fw_version[entry->partn].fw_subtype, - EFX_DWORD_0, subtype); - EFX_POPULATE_WORD_1(dcfg->fw_version[entry->partn].version_w, - EFX_WORD_0, version[0]); - EFX_POPULATE_WORD_1(dcfg->fw_version[entry->partn].version_x, - EFX_WORD_0, version[1]); - EFX_POPULATE_WORD_1(dcfg->fw_version[entry->partn].version_y, - EFX_WORD_0, version[2]); - EFX_POPULATE_WORD_1(dcfg->fw_version[entry->partn].version_z, - EFX_WORD_0, version[3]); + fwverp = &dcfg->fw_version[partn]; + EFX_POPULATE_DWORD_1(fwverp->fw_subtype, EFX_DWORD_0, subtype); + EFX_POPULATE_WORD_1(fwverp->version_w, EFX_WORD_0, version[0]); + EFX_POPULATE_WORD_1(fwverp->version_x, EFX_WORD_0, version[1]); + EFX_POPULATE_WORD_1(fwverp->version_y, EFX_WORD_0, version[2]); + EFX_POPULATE_WORD_1(fwverp->version_z, EFX_WORD_0, version[3]); /* Update the version count */ - if (nitems < entry->partn + 1) { - nitems = entry->partn + 1; + if (nitems < partn + 1) { + nitems = partn + 1; EFX_POPULATE_DWORD_1(dcfg->num_fw_version_items, EFX_DWORD_0, nitems); } @@ -832,7 +815,7 @@ siena_nvram_set_version( dcfg->csum.eb_u8[0] -= cksum; /* Erase and write the new partition */ - if ((rc = siena_nvram_partn_erase(enp, dcfg_partn, 0, partn_size)) != 0) + if ((rc = siena_nvram_partn_erase(enp, dcfg_partn, 0, dcfg_size)) != 0) goto fail6; /* Write out the new structure to nvram */ @@ -861,7 +844,7 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } diff --git a/sys/dev/sfxge/common/siena_phy.c b/sys/dev/sfxge/common/siena_phy.c index fd0871d..920314a 100644 --- a/sys/dev/sfxge/common/siena_phy.c +++ b/sys/dev/sfxge/common/siena_phy.c @@ -31,7 +31,6 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" #include "efx_impl.h" @@ -167,12 +166,12 @@ siena_phy_link_ev( *link_modep = link_mode; } - __checkReturn int + __checkReturn efx_rc_t siena_phy_power( __in efx_nic_t *enp, __in boolean_t power) { - int rc; + efx_rc_t rc; if (!power) return (0); @@ -186,12 +185,12 @@ siena_phy_power( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t siena_phy_get_link( __in efx_nic_t *enp, __out siena_link_state_t *slsp) @@ -199,7 +198,7 @@ siena_phy_get_link( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_GET_LINK_IN_LEN, MC_CMD_GET_LINK_OUT_LEN)]; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_GET_LINK; @@ -261,12 +260,12 @@ siena_phy_get_link( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t siena_phy_reconfigure( __in efx_nic_t *enp) { @@ -279,7 +278,7 @@ siena_phy_reconfigure( uint32_t cap_mask; unsigned int led_mode; unsigned int speed; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_SET_LINK; @@ -377,12 +376,12 @@ siena_phy_reconfigure( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t siena_phy_verify( __in efx_nic_t *enp) { @@ -390,7 +389,7 @@ siena_phy_verify( uint8_t payload[MAX(MC_CMD_GET_PHY_STATE_IN_LEN, MC_CMD_GET_PHY_STATE_OUT_LEN)]; uint32_t state; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_GET_PHY_STATE; @@ -426,12 +425,12 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t siena_phy_oui_get( __in efx_nic_t *enp, __out uint32_t *ouip) @@ -466,7 +465,7 @@ siena_phy_decode_stats( __in uint32_t vmask, __in_opt efsys_mem_t *esmp, __out_opt uint64_t *smaskp, - __out_ecount_opt(EFX_PHY_NSTATS) uint32_t *stat) + __inout_ecount_opt(EFX_PHY_NSTATS) uint32_t *stat) { uint64_t smask = 0; @@ -546,11 +545,11 @@ siena_phy_decode_stats( *smaskp = smask; } - __checkReturn int + __checkReturn efx_rc_t siena_phy_stats_update( __in efx_nic_t *enp, __in efsys_mem_t *esmp, - __out_ecount(EFX_PHY_NSTATS) uint32_t *stat) + __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat) { efx_nic_cfg_t *encp = &(enp->en_nic_cfg); uint32_t vmask = encp->enc_mcdi_phy_stat_mask; @@ -558,7 +557,7 @@ siena_phy_stats_update( efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_PHY_STATS_IN_LEN, MC_CMD_PHY_STATS_OUT_DMA_LEN)]; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_PHY_STATS; @@ -586,7 +585,7 @@ siena_phy_stats_update( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (0); } @@ -609,7 +608,7 @@ siena_phy_prop_name( #endif /* EFSYS_OPT_NAMES */ -extern __checkReturn int +extern __checkReturn efx_rc_t siena_phy_prop_get( __in efx_nic_t *enp, __in unsigned int id, @@ -621,7 +620,7 @@ siena_phy_prop_get( return (ENOTSUP); } -extern __checkReturn int +extern __checkReturn efx_rc_t siena_phy_prop_set( __in efx_nic_t *enp, __in unsigned int id, @@ -636,12 +635,12 @@ siena_phy_prop_set( #if EFSYS_OPT_BIST - __checkReturn int + __checkReturn efx_rc_t siena_phy_bist_start( __in efx_nic_t *enp, __in efx_bist_type_t type) { - int rc; + efx_rc_t rc; if ((rc = efx_mcdi_bist_start(enp, type)) != 0) goto fail1; @@ -649,7 +648,7 @@ siena_phy_bist_start( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } @@ -674,7 +673,7 @@ siena_phy_sft9001_bist_status( } } - __checkReturn int + __checkReturn efx_rc_t siena_phy_bist_poll( __in efx_nic_t *enp, __in efx_bist_type_t type, @@ -691,7 +690,7 @@ siena_phy_bist_poll( uint32_t value_mask = 0; efx_mcdi_req_t req; uint32_t result; - int rc; + efx_rc_t rc; (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_POLL_BIST; @@ -823,7 +822,7 @@ siena_phy_bist_poll( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } diff --git a/sys/dev/sfxge/common/siena_sram.c b/sys/dev/sfxge/common/siena_sram.c index cf36067..762de42 100644 --- a/sys/dev/sfxge/common/siena_sram.c +++ b/sys/dev/sfxge/common/siena_sram.c @@ -31,7 +31,6 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" #include "efx_impl.h" @@ -77,7 +76,7 @@ siena_sram_init( #if EFSYS_OPT_DIAG - __checkReturn int + __checkReturn efx_rc_t siena_sram_test( __in efx_nic_t *enp, __in efx_sram_pattern_fn_t func) @@ -88,7 +87,7 @@ siena_sram_test( size_t rows; unsigned int wptr; unsigned int rptr; - int rc; + efx_rc_t rc; EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA); @@ -168,7 +167,7 @@ siena_sram_test( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); /* Restore back to FULL buffer table mode */ EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 1); diff --git a/sys/dev/sfxge/common/siena_vpd.c b/sys/dev/sfxge/common/siena_vpd.c index 4d4b825..9a07f91 100644 --- a/sys/dev/sfxge/common/siena_vpd.c +++ b/sys/dev/sfxge/common/siena_vpd.c @@ -31,20 +31,17 @@ #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); -#include "efsys.h" #include "efx.h" -#include "efx_types.h" -#include "efx_regs.h" #include "efx_impl.h" #if EFSYS_OPT_VPD #if EFSYS_OPT_SIENA -static __checkReturn int +static __checkReturn efx_rc_t siena_vpd_get_static( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __deref_out_bcount_opt(*sizep) caddr_t *svpdp, __out size_t *sizep) { @@ -57,7 +54,7 @@ siena_vpd_get_static( unsigned int hdr_length; unsigned int pos; unsigned int region; - int rc; + efx_rc_t rc; EFSYS_ASSERT(partn == MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 || partn == MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1); @@ -152,12 +149,12 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t siena_vpd_init( __in efx_nic_t *enp) { @@ -165,7 +162,7 @@ siena_vpd_init( caddr_t svpd = NULL; unsigned partn; size_t size = 0; - int rc; + efx_rc_t rc; EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA); @@ -196,19 +193,19 @@ fail2: EFSYS_KMEM_FREE(enp->en_esip, size, svpd); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t siena_vpd_size( __in efx_nic_t *enp, __out size_t *sizep) { efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); - unsigned int partn; - int rc; + uint32_t partn; + efx_rc_t rc; EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA); @@ -230,12 +227,12 @@ siena_vpd_size( return (0); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t siena_vpd_read( __in efx_nic_t *enp, __out_bcount(size) caddr_t data, @@ -247,7 +244,7 @@ siena_vpd_read( unsigned int vpd_offset; unsigned int dcfg_partn; size_t dcfg_size; - int rc; + efx_rc_t rc; EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA); @@ -282,12 +279,12 @@ fail2: EFSYS_KMEM_FREE(enp->en_esip, dcfg_size, dcfg); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t siena_vpd_verify( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, @@ -300,7 +297,7 @@ siena_vpd_verify( unsigned int scont; unsigned int dcont; - int rc; + efx_rc_t rc; EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA); @@ -357,19 +354,19 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t siena_vpd_reinit( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size) { boolean_t wantpid; - int rc; + efx_rc_t rc; /* * Only create a PID if the dynamic cfg doesn't have one @@ -399,12 +396,12 @@ siena_vpd_reinit( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t siena_vpd_get( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, @@ -413,7 +410,7 @@ siena_vpd_get( { unsigned int offset; uint8_t length; - int rc; + efx_rc_t rc; EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA); @@ -443,19 +440,19 @@ siena_vpd_get( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t siena_vpd_set( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, __in size_t size, __in efx_vpd_value_t *evvp) { - int rc; + efx_rc_t rc; EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA); @@ -480,12 +477,12 @@ siena_vpd_set( fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } - __checkReturn int + __checkReturn efx_rc_t siena_vpd_next( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, @@ -498,7 +495,7 @@ siena_vpd_next( return (ENOTSUP); } - __checkReturn int + __checkReturn efx_rc_t siena_vpd_write( __in efx_nic_t *enp, __in_bcount(size) caddr_t data, @@ -513,7 +510,7 @@ siena_vpd_write( uint8_t cksum; size_t partn_size, dcfg_size; size_t vpd_length; - int rc; + efx_rc_t rc; EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA); @@ -588,7 +585,7 @@ fail3: fail2: EFSYS_PROBE(fail2); fail1: - EFSYS_PROBE1(fail1, int, rc); + EFSYS_PROBE1(fail1, efx_rc_t, rc); return (rc); } diff --git a/sys/dev/sfxge/sfxge.c b/sys/dev/sfxge/sfxge.c index f78d175..b82fba4 100644 --- a/sys/dev/sfxge/sfxge.c +++ b/sys/dev/sfxge/sfxge.c @@ -102,6 +102,19 @@ SYSCTL_INT(_hw_sfxge, OID_AUTO, stats_update_period, CTLFLAG_RDTUN, &sfxge_stats_update_period, 0, "netstat interface statistics update period in ticks"); +#define SFXGE_PARAM_RESTART_ATTEMPTS SFXGE_PARAM(restart_attempts) +static int sfxge_restart_attempts = 3; +TUNABLE_INT(SFXGE_PARAM_RESTART_ATTEMPTS, &sfxge_restart_attempts); +SYSCTL_INT(_hw_sfxge, OID_AUTO, restart_attempts, CTLFLAG_RDTUN, + &sfxge_restart_attempts, 0, + "Maximum number of attempts to bring interface up after reset"); + +#if EFSYS_OPT_MCDI_LOGGING +#define SFXGE_PARAM_MCDI_LOGGING SFXGE_PARAM(mcdi_logging) +static int sfxge_mcdi_logging = 0; +TUNABLE_INT(SFXGE_PARAM_MCDI_LOGGING, &sfxge_mcdi_logging); +#endif + static void sfxge_reset(void *arg, int npending); @@ -559,6 +572,9 @@ sfxge_ifnet_init(struct ifnet *ifp, struct sfxge_softc *sc) ifp->if_capabilities = SFXGE_CAP; ifp->if_capenable = SFXGE_CAP_ENABLE; + ifp->if_hw_tsomax = SFXGE_TSO_MAX_SIZE; + ifp->if_hw_tsomaxsegcount = SFXGE_TX_MAPPING_MAX_SEG; + ifp->if_hw_tsomaxsegsize = PAGE_SIZE; #ifdef SFXGE_LRO ifp->if_capabilities |= IFCAP_LRO; @@ -641,6 +657,9 @@ sfxge_create(struct sfxge_softc *sc) efx_nic_t *enp; int error; char rss_param_name[sizeof(SFXGE_PARAM(%d.max_rss_channels))]; +#if EFSYS_OPT_MCDI_LOGGING + char mcdi_log_param_name[sizeof(SFXGE_PARAM(%d.mcdi_logging))]; +#endif dev = sc->dev; @@ -651,6 +670,13 @@ sfxge_create(struct sfxge_softc *sc) SFXGE_PARAM(%d.max_rss_channels), (int)device_get_unit(dev)); TUNABLE_INT_FETCH(rss_param_name, &sc->max_rss_channels); +#if EFSYS_OPT_MCDI_LOGGING + sc->mcdi_logging = sfxge_mcdi_logging; + snprintf(mcdi_log_param_name, sizeof(mcdi_log_param_name), + SFXGE_PARAM(%d.mcdi_logging), + (int)device_get_unit(dev)); + TUNABLE_INT_FETCH(mcdi_log_param_name, &sc->mcdi_logging); +#endif sc->stats_node = SYSCTL_ADD_NODE( device_get_sysctl_ctx(dev), @@ -999,7 +1025,7 @@ sfxge_reset(void *arg, int npending) sfxge_stop(sc); efx_nic_reset(sc->enp); - for (attempt = 0; attempt < 3; ++attempt) { + for (attempt = 0; attempt < sfxge_restart_attempts; ++attempt) { if ((rc = sfxge_start(sc)) == 0) goto done; diff --git a/sys/dev/sfxge/sfxge.h b/sys/dev/sfxge/sfxge.h index cfaf06d..bea1eba 100644 --- a/sys/dev/sfxge/sfxge.h +++ b/sys/dev/sfxge/sfxge.h @@ -284,6 +284,9 @@ struct sfxge_softc { unsigned int txq_count; int tso_fw_assisted; +#if EFSYS_OPT_MCDI_LOGGING + int mcdi_logging; +#endif }; #define SFXGE_LINK_UP(sc) ((sc)->port.link_mode != EFX_LINK_DOWN) diff --git a/sys/dev/sfxge/sfxge_mcdi.c b/sys/dev/sfxge/sfxge_mcdi.c index fb9f650..3a85c28 100644 --- a/sys/dev/sfxge/sfxge_mcdi.c +++ b/sys/dev/sfxge/sfxge_mcdi.c @@ -49,6 +49,10 @@ __FBSDID("$FreeBSD$"); #include "sfxge.h" +#if EFSYS_OPT_MCDI_LOGGING +#include <dev/pci/pcivar.h> +#endif + #define SFXGE_MCDI_POLL_INTERVAL_MIN 10 /* 10us in 1us units */ #define SFXGE_MCDI_POLL_INTERVAL_MAX 100000 /* 100ms in 1us units */ #define SFXGE_MCDI_WATCHDOG_INTERVAL 10000000 /* 10s in 1us units */ @@ -163,6 +167,64 @@ sfxge_mcdi_exception(void *arg, efx_mcdi_exception_t eme) sfxge_schedule_reset(sc); } +#if EFSYS_OPT_MCDI_LOGGING + +#define SFXGE_MCDI_LOG_BUF_SIZE 128 + +static size_t +sfxge_mcdi_do_log(char *buffer, void *data, size_t data_size, + size_t pfxsize, size_t position) +{ + uint32_t *words = data; + size_t i; + + for (i = 0; i < data_size; i += sizeof(*words)) { + if (position + 2 * sizeof(*words) + 1 >= SFXGE_MCDI_LOG_BUF_SIZE) { + buffer[position] = '\0'; + printf("%s \\\n", buffer); + position = pfxsize; + } + snprintf(buffer + position, SFXGE_MCDI_LOG_BUF_SIZE - position, + " %08x", *words); + words++; + position += 2 * sizeof(uint32_t) + 1; + } + return (position); +} + +static void +sfxge_mcdi_logger(void *arg, efx_log_msg_t type, + void *header, size_t header_size, + void *data, size_t data_size) +{ + struct sfxge_softc *sc = (struct sfxge_softc *)arg; + char buffer[SFXGE_MCDI_LOG_BUF_SIZE]; + size_t pfxsize; + size_t start; + + if (!sc->mcdi_logging) + return; + + pfxsize = snprintf(buffer, sizeof(buffer), + "sfc %04x:%02x:%02x.%02x %s MCDI RPC %s:", + pci_get_domain(sc->dev), + pci_get_bus(sc->dev), + pci_get_slot(sc->dev), + pci_get_function(sc->dev), + device_get_nameunit(sc->dev), + type == EFX_LOG_MCDI_REQUEST ? "REQ" : + type == EFX_LOG_MCDI_RESPONSE ? "RESP" : "???"); + start = sfxge_mcdi_do_log(buffer, header, header_size, + pfxsize, pfxsize); + start = sfxge_mcdi_do_log(buffer, data, data_size, pfxsize, start); + if (start != pfxsize) { + buffer[start] = '\0'; + printf("%s\n", buffer); + } +} + +#endif + int sfxge_mcdi_ioctl(struct sfxge_softc *sc, sfxge_ioc_t *ip) { @@ -269,6 +331,14 @@ sfxge_mcdi_init(struct sfxge_softc *sc) emtp->emt_execute = sfxge_mcdi_execute; emtp->emt_ev_cpl = sfxge_mcdi_ev_cpl; emtp->emt_exception = sfxge_mcdi_exception; +#if EFSYS_OPT_MCDI_LOGGING + emtp->emt_logger = sfxge_mcdi_logger; + SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), + OID_AUTO, "mcdi_logging", CTLFLAG_RW, + &sc->mcdi_logging, 0, + "MCDI logging"); +#endif if ((rc = efx_mcdi_init(enp, emtp)) != 0) goto fail; diff --git a/sys/dev/sfxge/sfxge_tx.c b/sys/dev/sfxge/sfxge_tx.c index 398272d..780ed26 100644 --- a/sys/dev/sfxge/sfxge_tx.c +++ b/sys/dev/sfxge/sfxge_tx.c @@ -710,6 +710,84 @@ sfxge_if_qflush(struct ifnet *ifp) sfxge_tx_qdpl_flush(sc->txq[i]); } +#if SFXGE_TX_PARSE_EARLY + +/* There is little space for user data in mbuf pkthdr, so we + * use l*hlen fields which are not used by the driver otherwise + * to store header offsets. + * The fields are 8-bit, but it's ok, no header may be longer than 255 bytes. + */ + + +#define TSO_MBUF_PROTO(_mbuf) ((_mbuf)->m_pkthdr.PH_loc.sixteen[0]) +/* We abuse l5hlen here because PH_loc can hold only 64 bits of data */ +#define TSO_MBUF_FLAGS(_mbuf) ((_mbuf)->m_pkthdr.l5hlen) +#define TSO_MBUF_PACKETID(_mbuf) ((_mbuf)->m_pkthdr.PH_loc.sixteen[1]) +#define TSO_MBUF_SEQNUM(_mbuf) ((_mbuf)->m_pkthdr.PH_loc.thirtytwo[1]) + +static void sfxge_parse_tx_packet(struct mbuf *mbuf) +{ + struct ether_header *eh = mtod(mbuf, struct ether_header *); + const struct tcphdr *th; + struct tcphdr th_copy; + + /* Find network protocol and header */ + TSO_MBUF_PROTO(mbuf) = eh->ether_type; + if (TSO_MBUF_PROTO(mbuf) == htons(ETHERTYPE_VLAN)) { + struct ether_vlan_header *veh = + mtod(mbuf, struct ether_vlan_header *); + TSO_MBUF_PROTO(mbuf) = veh->evl_proto; + mbuf->m_pkthdr.l2hlen = sizeof(*veh); + } else { + mbuf->m_pkthdr.l2hlen = sizeof(*eh); + } + + /* Find TCP header */ + if (TSO_MBUF_PROTO(mbuf) == htons(ETHERTYPE_IP)) { + const struct ip *iph = (const struct ip *)mtodo(mbuf, mbuf->m_pkthdr.l2hlen); + + KASSERT(iph->ip_p == IPPROTO_TCP, + ("TSO required on non-TCP packet")); + mbuf->m_pkthdr.l3hlen = mbuf->m_pkthdr.l2hlen + 4 * iph->ip_hl; + TSO_MBUF_PACKETID(mbuf) = iph->ip_id; + } else { + KASSERT(TSO_MBUF_PROTO(mbuf) == htons(ETHERTYPE_IPV6), + ("TSO required on non-IP packet")); + KASSERT(((const struct ip6_hdr *)mtodo(mbuf, mbuf->m_pkthdr.l2hlen))->ip6_nxt == + IPPROTO_TCP, + ("TSO required on non-TCP packet")); + mbuf->m_pkthdr.l3hlen = mbuf->m_pkthdr.l2hlen + sizeof(struct ip6_hdr); + TSO_MBUF_PACKETID(mbuf) = 0; + } + + KASSERT(mbuf->m_len >= mbuf->m_pkthdr.l3hlen, + ("network header is fragmented in mbuf")); + + /* We need TCP header including flags (window is the next) */ + if (mbuf->m_len < mbuf->m_pkthdr.l3hlen + offsetof(struct tcphdr, th_win)) { + m_copydata(mbuf, mbuf->m_pkthdr.l3hlen, sizeof(th_copy), + (caddr_t)&th_copy); + th = &th_copy; + } else { + th = (const struct tcphdr *)mtodo(mbuf, mbuf->m_pkthdr.l3hlen); + } + + mbuf->m_pkthdr.l4hlen = mbuf->m_pkthdr.l3hlen + 4 * th->th_off; + TSO_MBUF_SEQNUM(mbuf) = ntohl(th->th_seq); + + /* These flags must not be duplicated */ + /* + * RST should not be duplicated as well, but FreeBSD kernel + * generates TSO packets with RST flag. So, do not assert + * its absence. + */ + KASSERT(!(th->th_flags & (TH_URG | TH_SYN)), + ("incompatible TCP flag 0x%x on TSO packet", + th->th_flags & (TH_URG | TH_SYN))); + TSO_MBUF_FLAGS(mbuf) = th->th_flags; +} +#endif + /* * TX start -- called by the stack. */ @@ -744,6 +822,10 @@ sfxge_if_transmit(struct ifnet *ifp, struct mbuf *m) index = sc->rx_indir_table[hash % SFXGE_RX_SCALE_MAX]; } +#if SFXGE_TX_PARSE_EARLY + if (m->m_pkthdr.csum_flags & CSUM_TSO) + sfxge_parse_tx_packet(m); +#endif txq = sc->txq[SFXGE_TXQ_IP_TCP_UDP_CKSUM + index]; } else if (m->m_pkthdr.csum_flags & CSUM_DELAY_IP) { txq = sc->txq[SFXGE_TXQ_IP_CKSUM]; @@ -781,26 +863,32 @@ struct sfxge_tso_state { unsigned seg_size; /* TCP segment size */ int fw_assisted; /* Use FW-assisted TSO */ u_short packet_id; /* IPv4 packet ID from the original packet */ + uint8_t tcp_flags; /* TCP flags */ efx_desc_t header_desc; /* Precomputed header descriptor for * FW-assisted TSO */ }; +#if !SFXGE_TX_PARSE_EARLY static const struct ip *tso_iph(const struct sfxge_tso_state *tso) { KASSERT(tso->protocol == htons(ETHERTYPE_IP), ("tso_iph() in non-IPv4 state")); return (const struct ip *)(tso->mbuf->m_data + tso->nh_off); } + static __unused const struct ip6_hdr *tso_ip6h(const struct sfxge_tso_state *tso) { KASSERT(tso->protocol == htons(ETHERTYPE_IPV6), ("tso_ip6h() in non-IPv6 state")); return (const struct ip6_hdr *)(tso->mbuf->m_data + tso->nh_off); } + static const struct tcphdr *tso_tcph(const struct sfxge_tso_state *tso) { return (const struct tcphdr *)(tso->mbuf->m_data + tso->tcph_off); } +#endif + /* Size of preallocated TSO header buffers. Larger blocks must be * allocated from the heap. @@ -857,15 +945,18 @@ static void tso_start(struct sfxge_txq *txq, struct sfxge_tso_state *tso, const bus_dma_segment_t *hdr_dma_seg, struct mbuf *mbuf) { - struct ether_header *eh = mtod(mbuf, struct ether_header *); const efx_nic_cfg_t *encp = efx_nic_cfg_get(txq->sc->enp); +#if !SFXGE_TX_PARSE_EARLY + struct ether_header *eh = mtod(mbuf, struct ether_header *); const struct tcphdr *th; struct tcphdr th_copy; +#endif tso->fw_assisted = txq->sc->tso_fw_assisted; tso->mbuf = mbuf; /* Find network protocol and header */ +#if !SFXGE_TX_PARSE_EARLY tso->protocol = eh->ether_type; if (tso->protocol == htons(ETHERTYPE_VLAN)) { struct ether_vlan_header *veh = @@ -875,7 +966,14 @@ static void tso_start(struct sfxge_txq *txq, struct sfxge_tso_state *tso, } else { tso->nh_off = sizeof(*eh); } - +#else + tso->protocol = TSO_MBUF_PROTO(mbuf); + tso->nh_off = mbuf->m_pkthdr.l2hlen; + tso->tcph_off = mbuf->m_pkthdr.l3hlen; + tso->packet_id = TSO_MBUF_PACKETID(mbuf); +#endif + +#if !SFXGE_TX_PARSE_EARLY /* Find TCP header */ if (tso->protocol == htons(ETHERTYPE_IP)) { KASSERT(tso_iph(tso)->ip_p == IPPROTO_TCP, @@ -890,12 +988,17 @@ static void tso_start(struct sfxge_txq *txq, struct sfxge_tso_state *tso, tso->tcph_off = tso->nh_off + sizeof(struct ip6_hdr); tso->packet_id = 0; } +#endif + + if (tso->fw_assisted && __predict_false(tso->tcph_off > encp->enc_tx_tso_tcp_header_offset_limit)) { tso->fw_assisted = 0; } + +#if !SFXGE_TX_PARSE_EARLY KASSERT(mbuf->m_len >= tso->tcph_off, ("network header is fragmented in mbuf")); /* We need TCP header including flags (window is the next) */ @@ -906,10 +1009,13 @@ static void tso_start(struct sfxge_txq *txq, struct sfxge_tso_state *tso, } else { th = tso_tcph(tso); } - tso->header_len = tso->tcph_off + 4 * th->th_off; +#else + tso->header_len = mbuf->m_pkthdr.l4hlen; +#endif tso->seg_size = mbuf->m_pkthdr.tso_segsz; +#if !SFXGE_TX_PARSE_EARLY tso->seqnum = ntohl(th->th_seq); /* These flags must not be duplicated */ @@ -921,6 +1027,11 @@ static void tso_start(struct sfxge_txq *txq, struct sfxge_tso_state *tso, KASSERT(!(th->th_flags & (TH_URG | TH_SYN)), ("incompatible TCP flag 0x%x on TSO packet", th->th_flags & (TH_URG | TH_SYN))); + tso->tcp_flags = th->th_flags; +#else + tso->seqnum = TSO_MBUF_SEQNUM(mbuf); + tso->tcp_flags = TSO_MBUF_FLAGS(mbuf); +#endif tso->out_len = mbuf->m_pkthdr.len - tso->header_len; @@ -1001,7 +1112,7 @@ static int tso_start_new_packet(struct sfxge_txq *txq, int rc; if (tso->fw_assisted) { - uint8_t tcp_flags = tso_tcph(tso)->th_flags; + uint8_t tcp_flags = tso->tcp_flags; if (tso->out_len > tso->seg_size) tcp_flags &= ~(TH_FIN | TH_PUSH); @@ -1328,10 +1439,10 @@ sfxge_tx_qstart(struct sfxge_softc *sc, unsigned int index) flags = 0; break; case SFXGE_TXQ_IP_CKSUM: - flags = EFX_CKSUM_IPV4; + flags = EFX_TXQ_CKSUM_IPV4; break; case SFXGE_TXQ_IP_TCP_UDP_CKSUM: - flags = EFX_CKSUM_IPV4 | EFX_CKSUM_TCPUDP; + flags = EFX_TXQ_CKSUM_IPV4 | EFX_TXQ_CKSUM_TCPUDP; break; default: KASSERT(0, ("Impossible TX queue")); diff --git a/sys/dev/sfxge/sfxge_tx.h b/sys/dev/sfxge/sfxge_tx.h index 9d411ea..816856a 100644 --- a/sys/dev/sfxge/sfxge_tx.h +++ b/sys/dev/sfxge/sfxge_tx.h @@ -40,6 +40,11 @@ #include <netinet/ip.h> #include <netinet/tcp.h> +/* If defined, parse TX packets directly in if_transmit + * for better cache locality and reduced time under TX lock + */ +#define SFXGE_TX_PARSE_EARLY 1 + /* Maximum size of TSO packet */ #define SFXGE_TSO_MAX_SIZE (65535) @@ -51,11 +56,15 @@ /* Maximum number of DMA segments needed to map an mbuf chain. With * TSO, the mbuf length may be just over 64K, divided into 2K mbuf - * clusters. (The chain could be longer than this initially, but can - * be shortened with m_collapse().) + * clusters taking into account that the first may be not 2K cluster + * boundary aligned. + * Packet header may be split into two segments because of, for example, + * VLAN header insertion. + * The chain could be longer than this initially, but can be shortened + * with m_collapse(). */ #define SFXGE_TX_MAPPING_MAX_SEG \ - (1 + howmany(SFXGE_TSO_MAX_SIZE, MCLBYTES)) + (2 + howmany(SFXGE_TSO_MAX_SIZE, MCLBYTES) + 1) /* * Buffer mapping flags. diff --git a/sys/modules/if_gif/Makefile b/sys/modules/if_gif/Makefile index d8ba44c..6d713b4 100644 --- a/sys/modules/if_gif/Makefile +++ b/sys/modules/if_gif/Makefile @@ -17,7 +17,9 @@ OPT_INET!= cat ${KERNBUILDDIR}/opt_inet.h; echo .if empty(OPT_INET) MK_INET_SUPPORT= no .endif +.endif +.if !defined(KERNBUILDDIR) .if ${MK_INET6_SUPPORT} != "no" opt_inet6.h: echo "#define INET6 1" > ${.TARGET} diff --git a/sys/modules/sfxge/Makefile b/sys/modules/sfxge/Makefile index a7b3c0d..c444152 100644 --- a/sys/modules/sfxge/Makefile +++ b/sys/modules/sfxge/Makefile @@ -31,11 +31,16 @@ SRCS+= siena_mac.c siena_mcdi.c siena_nic.c siena_nvram.c siena_phy.c SRCS+= siena_sram.c siena_vpd.c SRCS+= siena_flash.h siena_impl.h +SRCS+= ef10_impl.h + SRCS+= hunt_ev.c hunt_intr.c hunt_mac.c hunt_mcdi.c hunt_nic.c SRCS+= hunt_nvram.c hunt_rx.c hunt_phy.c hunt_sram.c hunt_tx.c hunt_vpd.c SRCS+= hunt_filter.c SRCS+= hunt_impl.h +SRCS+= medford_nic.c +SRCS+= medford_impl.h + # Extra debug checks #CFLAGS += -DDEBUG=1 diff --git a/sys/net/if_lagg.c b/sys/net/if_lagg.c index 2522fb6..9449df0 100644 --- a/sys/net/if_lagg.c +++ b/sys/net/if_lagg.c @@ -1062,9 +1062,25 @@ lagg_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) /* Set to LAGG_PROTO_NONE during the attach. */ LAGG_WLOCK(sc); if (sc->sc_proto != LAGG_PROTO_NONE) { + int (*sc_detach)(struct lagg_softc *sc); + + /* Reset protocol and pointers */ sc->sc_proto = LAGG_PROTO_NONE; - if (sc->sc_detach != NULL) - sc->sc_detach(sc); + sc_detach = sc->sc_detach; + sc->sc_detach = NULL; + sc->sc_start = NULL; + sc->sc_input = NULL; + sc->sc_port_create = NULL; + sc->sc_port_destroy = NULL; + sc->sc_linkstate = NULL; + sc->sc_init = NULL; + sc->sc_stop = NULL; + sc->sc_lladdr = NULL; + sc->sc_req = NULL; + sc->sc_portreq = NULL; + + if (sc_detach != NULL) + sc_detach(sc); else LAGG_WUNLOCK(sc); } else diff --git a/sys/sys/pmc.h b/sys/sys/pmc.h index bb225d5..7e52824 100644 --- a/sys/sys/pmc.h +++ b/sys/sys/pmc.h @@ -534,14 +534,15 @@ struct pmc_op_configurelog { */ struct pmc_op_getdriverstats { - int pm_intr_ignored; /* #interrupts ignored */ - int pm_intr_processed; /* #interrupts processed */ - int pm_intr_bufferfull; /* #interrupts with ENOSPC */ - int pm_syscalls; /* #syscalls */ - int pm_syscall_errors; /* #syscalls with errors */ - int pm_buffer_requests; /* #buffer requests */ - int pm_buffer_requests_failed; /* #failed buffer requests */ - int pm_log_sweeps; /* #sample buffer processing passes */ + unsigned int pm_intr_ignored; /* #interrupts ignored */ + unsigned int pm_intr_processed; /* #interrupts processed */ + unsigned int pm_intr_bufferfull; /* #interrupts with ENOSPC */ + unsigned int pm_syscalls; /* #syscalls */ + unsigned int pm_syscall_errors; /* #syscalls with errors */ + unsigned int pm_buffer_requests; /* #buffer requests */ + unsigned int pm_buffer_requests_failed; /* #failed buffer requests */ + unsigned int pm_log_sweeps; /* #sample buffer processing + passes */ }; /* @@ -598,6 +599,7 @@ struct pmc_op_getdyneventinfo { #include <sys/malloc.h> #include <sys/sysctl.h> +#include <sys/_cpuset.h> #include <machine/frame.h> @@ -713,7 +715,8 @@ struct pmc { pmc_value_t pm_initial; /* counting PMC modes */ } pm_sc; - uint32_t pm_stalled; /* marks stalled sampling PMCs */ + volatile cpuset_t pm_stalled; /* marks stalled sampling PMCs */ + volatile cpuset_t pm_cpustate; /* CPUs where PMC should be active */ uint32_t pm_caps; /* PMC capabilities */ enum pmc_event pm_event; /* event being measured */ uint32_t pm_flags; /* additional flags PMC_F_... */ diff --git a/tools/build/mk/OptionalObsoleteFiles.inc b/tools/build/mk/OptionalObsoleteFiles.inc index 886fbaa..f75e1c7 100644 --- a/tools/build/mk/OptionalObsoleteFiles.inc +++ b/tools/build/mk/OptionalObsoleteFiles.inc @@ -2204,6 +2204,13 @@ OLD_FILES+=rescue/ping6 # to be filled in #.endif +.if ${MK_INETD} == no +OLD_FILES+=etc/rc.d/inetd +OLD_FILES+=usr/sbin/inetd +OLD_FILES+=usr/share/man/man5/inetd.conf.5.gz +OLD_FILES+=usr/share/man/man8/inetd.8.gz +.endif + .if ${MK_IPFILTER} == no OLD_FILES+=etc/periodic/security/510.ipfdenied OLD_FILES+=rescue/ipf diff --git a/tools/regression/geom_concat/conf.sh b/tools/regression/geom_concat/conf.sh index 0eaf1ba..c8692bb 100644 --- a/tools/regression/geom_concat/conf.sh +++ b/tools/regression/geom_concat/conf.sh @@ -1,7 +1,7 @@ #!/bin/sh # $FreeBSD$ -name="test" +name="$(mktemp -u concat.XXXXXX)" class="concat" base=`basename $0` diff --git a/tools/regression/geom_mirror/conf.sh b/tools/regression/geom_mirror/conf.sh index 8a60a16..5e7e15a 100644 --- a/tools/regression/geom_mirror/conf.sh +++ b/tools/regression/geom_mirror/conf.sh @@ -1,7 +1,7 @@ #!/bin/sh # $FreeBSD$ -name="test" +name="$(mktemp -u mirror.XXXXXX)" class="mirror" base=`basename $0` diff --git a/tools/regression/geom_raid3/conf.sh b/tools/regression/geom_raid3/conf.sh index 93e7dea..ff6485c 100644 --- a/tools/regression/geom_raid3/conf.sh +++ b/tools/regression/geom_raid3/conf.sh @@ -1,7 +1,7 @@ #!/bin/sh # $FreeBSD$ -name="test" +name="$(mktemp -u graid3.XXXXXX)" class="raid3" base=`basename $0` diff --git a/tools/regression/geom_shsec/conf.sh b/tools/regression/geom_shsec/conf.sh index 7648862..dc416db 100644 --- a/tools/regression/geom_shsec/conf.sh +++ b/tools/regression/geom_shsec/conf.sh @@ -1,7 +1,7 @@ #!/bin/sh # $FreeBSD$ -name="test" +name="$(mktemp -u shsec.XXXXXX)" class="shsec" base=`basename $0` diff --git a/tools/regression/geom_stripe/conf.sh b/tools/regression/geom_stripe/conf.sh index 22e5864..54a0c36 100644 --- a/tools/regression/geom_stripe/conf.sh +++ b/tools/regression/geom_stripe/conf.sh @@ -1,7 +1,7 @@ #!/bin/sh # $FreeBSD$ -name="test" +name="$(mktemp -u stripe.XXXXXX)" class="stripe" base=`basename $0` diff --git a/tools/regression/geom_subr.sh b/tools/regression/geom_subr.sh index 6047829..0ffb8c8 100644 --- a/tools/regression/geom_subr.sh +++ b/tools/regression/geom_subr.sh @@ -1,7 +1,12 @@ #!/bin/sh # $FreeBSD$ -kldstat -q -m g_${class} || g${class} load || exit 1 +if [ $(id -u) -ne 0 ]; then + echo 'Tests must be run as root' + echo 'Bail out!' + exit 1 +fi +kldstat -q -m g_${class} || geom ${class} load || exit 1 devwait() { @@ -12,3 +17,32 @@ devwait() sleep 0.2 done } + +# Need to keep track of the test md devices to avoid the scenario where a test +# failing will cause the other tests to bomb out, or a test failing will leave +# a large number of md(4) devices lingering around +: ${TMPDIR=/tmp} +export TMPDIR +TEST_MDS_FILE=${TMPDIR}/test_mds + +attach_md() +{ + local test_md + + test_md=$(mdconfig -a "$@") || exit + echo $test_md >> $TEST_MDS_FILE || exit + echo $test_md +} + +geom_test_cleanup() +{ + local test_md + + if [ -f $TEST_MDS_FILE ]; then + while read test_md; do + # The "#" tells the TAP parser this is a comment + echo "# Removing test memory disk: $test_md" + mdconfig -d -u $test_md + done < $TEST_MDS_FILE + fi +} diff --git a/usr.bin/cap_mkdb/cap_mkdb.c b/usr.bin/cap_mkdb/cap_mkdb.c index 2f8bd96..bbcedd5 100644 --- a/usr.bin/cap_mkdb/cap_mkdb.c +++ b/usr.bin/cap_mkdb/cap_mkdb.c @@ -119,7 +119,7 @@ main(int argc, char *argv[]) (void)snprintf(buf, sizeof(buf), "%s.db", capname ? capname : *argv); if ((capname = strdup(buf)) == NULL) errx(1, "strdup failed"); - if ((capdbp = dbopen(capname, O_CREAT | O_TRUNC | O_RDWR, + if ((capdbp = dbopen(capname, O_CREAT | O_TRUNC | O_RDWR | O_SYNC, DEFFILEMODE, DB_HASH, &openinfo)) == NULL) err(1, "%s", buf); diff --git a/usr.bin/truss/syscall.h b/usr.bin/truss/syscall.h index a240749..5af5ebc 100644 --- a/usr.bin/truss/syscall.h +++ b/usr.bin/truss/syscall.h @@ -43,7 +43,7 @@ enum Argtype { None = 1, Hex, Octal, Int, LongHex, Name, Ptr, Stat, Ioctl, Quad, Umtx, Sigset, Sigprocmask, StatFs, Kevent, Sockdomain, Socktype, Open, Fcntlflag, Rusage, BinString, Shutdown, Resource, Rlimit, Timeval2, Pathconf, Rforkflags, ExitStatus, Waitoptions, Idtype, Procctl, - LinuxSockArgs, Umtxop, Atfd, Atflags, Accessmode, Long, + LinuxSockArgs, Umtxop, Atfd, Atflags, Timespec2, Accessmode, Long, Sysarch, ExecArgs, ExecEnv, PipeFds, QuadHex }; #define ARG_MASK 0xff diff --git a/usr.bin/truss/syscalls.c b/usr.bin/truss/syscalls.c index 7815fd1..f7d8797 100644 --- a/usr.bin/truss/syscalls.c +++ b/usr.bin/truss/syscalls.c @@ -162,6 +162,8 @@ static struct syscall decoded_syscalls[] = { .args = { { Int, 0 }, { StatFs | OUT, 1 } } }, { .name = "ftruncate", .ret_type = 1, .nargs = 2, .args = { { Int | IN, 0 }, { QuadHex | IN, 1 + QUAD_ALIGN } } }, + { .name = "futimens", .ret_type = 1, .nargs = 2, + .args = { { Int, 0 }, { Timespec2 | IN, 1 } } }, { .name = "futimes", .ret_type = 1, .nargs = 2, .args = { { Int, 0 }, { Timeval2 | IN, 1 } } }, { .name = "futimesat", .ret_type = 1, .nargs = 3, @@ -341,6 +343,9 @@ static struct syscall decoded_syscalls[] = { .args = { { Atfd, 0 }, { Name, 1 }, { Atflags, 2 } } }, { .name = "unmount", .ret_type = 1, .nargs = 2, .args = { { Name, 0 }, { Int, 1 } } }, + { .name = "utimensat", .ret_type = 1, .nargs = 4, + .args = { { Atfd, 0 }, { Name | IN, 1 }, { Timespec2 | IN, 2 }, + { Atflags, 3 } } }, { .name = "utimes", .ret_type = 1, .nargs = 2, .args = { { Name | IN, 0 }, { Timeval2 | IN, 1 } } }, { .name = "wait4", .ret_type = 1, .nargs = 4, @@ -1083,6 +1088,37 @@ print_arg(struct syscall_args *sc, unsigned long *args, long *retval, fprintf(fp, "0x%lx", args[sc->offset]); break; } + case Timespec2: { + struct timespec ts[2]; + const char *sep; + unsigned int i; + + if (get_struct(pid, (void *)args[sc->offset], &ts, sizeof(ts)) + != -1) { + fputs("{ ", fp); + sep = ""; + for (i = 0; i < nitems(ts); i++) { + fputs(sep, fp); + sep = ", "; + switch (ts[i].tv_nsec) { + case UTIME_NOW: + fprintf(fp, "UTIME_NOW"); + break; + case UTIME_OMIT: + fprintf(fp, "UTIME_OMIT"); + break; + default: + fprintf(fp, "%jd.%09ld", + (intmax_t)ts[i].tv_sec, + ts[i].tv_nsec); + break; + } + } + fputs(" }", fp); + } else + fprintf(fp, "0x%lx", args[sc->offset]); + break; + } case Timeval: { struct timeval tv; diff --git a/usr.sbin/pmcstat/pmcpl_gprof.c b/usr.sbin/pmcstat/pmcpl_gprof.c index 9ff78e8..5fc9b41 100644 --- a/usr.sbin/pmcstat/pmcpl_gprof.c +++ b/usr.sbin/pmcstat/pmcpl_gprof.c @@ -74,6 +74,14 @@ __FBSDID("$FreeBSD$"); #include "pmcpl_callgraph.h" #include "pmcpl_gprof.h" +typedef uint64_t WIDEHISTCOUNTER; + +#define WIDEHISTCOUNTER_MAX UINT64_MAX +#define HISTCOUNTER_MAX USHRT_MAX +#define WIDEHISTCOUNTER_GMONTYPE ((int) 64) +#define HISTCOUNTER_GMONTYPE ((int) 0) +static int hc_sz=0; + /* * struct pmcstat_gmonfile tracks a given 'gmon.out' file. These * files are mmap()'ed in as needed. @@ -126,11 +134,13 @@ pmcstat_gmon_create_file(struct pmcstat_gmonfile *pgf, gm.lpc = image->pi_start; gm.hpc = image->pi_end; - gm.ncnt = (pgf->pgf_nbuckets * sizeof(HISTCOUNTER)) + - sizeof(struct gmonhdr); + gm.ncnt = (pgf->pgf_nbuckets * hc_sz) + sizeof(struct gmonhdr); gm.version = GMONVERSION; gm.profrate = 0; /* use ticks */ - gm.histcounter_type = 0; /* compatibility with moncontrol() */ + if (args.pa_flags & FLAG_DO_WIDE_GPROF_HC) + gm.histcounter_type = WIDEHISTCOUNTER_GMONTYPE; + else + gm.histcounter_type = HISTCOUNTER_GMONTYPE; gm.spare[0] = gm.spare[1] = 0; /* Write out the gmon header */ @@ -400,6 +410,7 @@ pmcpl_gmon_process(struct pmcstat_process *pp, struct pmcstat_pmcrecord *pmcr, struct pmcstat_gmonfile *pgf; uintfptr_t bucket; HISTCOUNTER *hc; + WIDEHISTCOUNTER *whc; pmc_id_t pmcid; (void) nsamples; (void) usermode; (void) cpu; @@ -437,6 +448,14 @@ pmcpl_gmon_process(struct pmcstat_process *pp, struct pmcstat_pmcrecord *pmcr, */ pgf = pmcstat_image_find_gmonfile(image, pmcid); if (pgf == NULL) { + if (hc_sz == 0) { + /* Determine the correct histcounter size. */ + if (args.pa_flags & FLAG_DO_WIDE_GPROF_HC) + hc_sz = sizeof(WIDEHISTCOUNTER); + else + hc_sz = sizeof(HISTCOUNTER); + } + if ((pgf = calloc(1, sizeof(*pgf))) == NULL) err(EX_OSERR, "ERROR:"); @@ -448,7 +467,7 @@ pmcpl_gmon_process(struct pmcstat_process *pp, struct pmcstat_pmcrecord *pmcr, pgf->pgf_nbuckets = (image->pi_end - image->pi_start) / FUNCTION_ALIGNMENT; /* see <machine/profile.h> */ pgf->pgf_ndatabytes = sizeof(struct gmonhdr) + - pgf->pgf_nbuckets * sizeof(HISTCOUNTER); + pgf->pgf_nbuckets * hc_sz; pgf->pgf_nsamples = 0; pgf->pgf_file = NULL; @@ -474,14 +493,25 @@ pmcpl_gmon_process(struct pmcstat_process *pp, struct pmcstat_pmcrecord *pmcr, assert(bucket < pgf->pgf_nbuckets); - hc = (HISTCOUNTER *) ((uintptr_t) pgf->pgf_gmondata + - sizeof(struct gmonhdr)); - - /* saturating add */ - if (hc[bucket] < 0xFFFFU) /* XXX tie this to sizeof(HISTCOUNTER) */ - hc[bucket]++; - else /* mark that an overflow occurred */ - pgf->pgf_overflow = 1; + if (args.pa_flags & FLAG_DO_WIDE_GPROF_HC) { + whc = (WIDEHISTCOUNTER *) ((uintptr_t) pgf->pgf_gmondata + + sizeof(struct gmonhdr)); + + /* saturating add */ + if (whc[bucket] < WIDEHISTCOUNTER_MAX) + whc[bucket]++; + else /* mark that an overflow occurred */ + pgf->pgf_overflow = 1; + } else { + hc = (HISTCOUNTER *) ((uintptr_t) pgf->pgf_gmondata + + sizeof(struct gmonhdr)); + + /* saturating add */ + if (hc[bucket] < HISTCOUNTER_MAX) + hc[bucket]++; + else /* mark that an overflow occurred */ + pgf->pgf_overflow = 1; + } pgf->pgf_nsamples++; } diff --git a/usr.sbin/pmcstat/pmcstat.8 b/usr.sbin/pmcstat/pmcstat.8 index 7de335d..31b136b 100644 --- a/usr.sbin/pmcstat/pmcstat.8 +++ b/usr.sbin/pmcstat/pmcstat.8 @@ -25,7 +25,7 @@ .\" .\" $FreeBSD$ .\" -.Dd May 27, 2015 +.Dd November 18, 2015 .Dt PMCSTAT 8 .Os .Sh NAME @@ -49,6 +49,7 @@ .Op Fl a Ar pathname .Op Fl c Ar cpu-spec .Op Fl d +.Op Fl e .Op Fl f Ar pluginopt .Op Fl g .Op Fl k Ar kerneldir @@ -260,6 +261,12 @@ The default is to measure events for the target process alone. .Fl P , or .Fl S ) . +.It Fl e +Specify that the gprof profile files will use a wide history counter. +These files are produced in a format compatible with +.Xr gprof 1 . +However, other tools that cannot fully parse a BSD-style +gmon header might be unable to correctly parse these files. .It Fl f Ar pluginopt Pass option string to the active plugin. .br diff --git a/usr.sbin/pmcstat/pmcstat.c b/usr.sbin/pmcstat/pmcstat.c index 5ae53aa..481213a 100644 --- a/usr.sbin/pmcstat/pmcstat.c +++ b/usr.sbin/pmcstat/pmcstat.c @@ -506,6 +506,7 @@ pmcstat_show_usage(void) "\t -a <file>\t print sampled PCs and callgraph to \"file\"\n" "\t -c cpu-list\t set cpus for subsequent system-wide PMCs\n" "\t -d\t\t (toggle) track descendants\n" + "\t -e\t\t use wide history counter for gprof(1) output\n" "\t -f spec\t pass \"spec\" to as plugin option\n" "\t -g\t\t produce gprof(1) compatible profiles\n" "\t -k dir\t\t set the path to the kernel\n" @@ -627,7 +628,7 @@ main(int argc, char **argv) CPU_COPY(&rootmask, &cpumask); while ((option = getopt(argc, argv, - "CD:EF:G:M:NO:P:R:S:TWa:c:df:gk:l:m:n:o:p:qr:s:t:vw:z:")) != -1) + "CD:EF:G:M:NO:P:R:S:TWa:c:def:gk:l:m:n:o:p:qr:s:t:vw:z:")) != -1) switch (option) { case 'a': /* Annotate + callgraph */ args.pa_flags |= FLAG_DO_ANNOTATE; @@ -668,6 +669,10 @@ main(int argc, char **argv) args.pa_required |= FLAG_HAS_PROCESS_PMCS; break; + case 'e': /* wide gprof metrics */ + args.pa_flags |= FLAG_DO_WIDE_GPROF_HC; + break; + case 'F': /* produce a system-wide calltree */ args.pa_flags |= FLAG_DO_CALLGRAPHS; args.pa_plugin = PMCSTAT_PL_CALLTREE; @@ -1022,6 +1027,13 @@ main(int argc, char **argv) "ERROR: options -g/-G/-m/-T require sampling PMCs or -R to be specified." ); + /* check if -e was specified without -g */ + if ((args.pa_flags & FLAG_DO_WIDE_GPROF_HC) && + !(args.pa_flags & FLAG_DO_GPROF)) + errx(EX_USAGE, +"ERROR: option -e requires gprof mode to be specified." + ); + /* check if -O was spuriously specified */ if ((args.pa_flags & FLAG_HAS_OUTPUT_LOGFILE) && (args.pa_required & FLAG_HAS_OUTPUT_LOGFILE) == 0) @@ -1500,14 +1512,24 @@ main(int argc, char **argv) "ERROR: Cannot retrieve driver statistics"); if (ds_start.pm_intr_bufferfull != ds_end.pm_intr_bufferfull && args.pa_verbosity > 0) - warnx("WARNING: some samples were dropped.\n" -"Please consider tuning the \"kern.hwpmc.nsamples\" tunable." + warnx( +"WARNING: sampling was paused at least %u time%s.\n" +"Please consider tuning the \"kern.hwpmc.nsamples\" tunable.", + ds_end.pm_intr_bufferfull - + ds_start.pm_intr_bufferfull, + ((ds_end.pm_intr_bufferfull - + ds_start.pm_intr_bufferfull) != 1) ? "s" : "" ); if (ds_start.pm_buffer_requests_failed != ds_end.pm_buffer_requests_failed && args.pa_verbosity > 0) - warnx("WARNING: some events were discarded.\n" -"Please consider tuning the \"kern.hwpmc.nbuffers\" tunable." + warnx( +"WARNING: at least %u event%s were discarded while running.\n" +"Please consider tuning the \"kern.hwpmc.nbuffers\" tunable.", + ds_end.pm_buffer_requests_failed - + ds_start.pm_buffer_requests_failed, + ((ds_end.pm_buffer_requests_failed - + ds_start.pm_buffer_requests_failed) != 1) ? "s" : "" ); } diff --git a/usr.sbin/pmcstat/pmcstat.h b/usr.sbin/pmcstat/pmcstat.h index 29dfeb7..5b1d3d9 100644 --- a/usr.sbin/pmcstat/pmcstat.h +++ b/usr.sbin/pmcstat/pmcstat.h @@ -55,6 +55,7 @@ #define FLAG_DO_ANALYSIS 0x00020000 /* -g or -G or -m or -T */ #define FLAGS_HAS_CPUMASK 0x00040000 /* -c */ #define FLAG_HAS_DURATION 0x00080000 /* -l secs */ +#define FLAG_DO_WIDE_GPROF_HC 0x00100000 /* -e */ #define DEFAULT_SAMPLE_COUNT 65536 #define DEFAULT_WAIT_INTERVAL 5.0 diff --git a/usr.sbin/services_mkdb/services_mkdb.c b/usr.sbin/services_mkdb/services_mkdb.c index a91340e..9ea66de 100644 --- a/usr.sbin/services_mkdb/services_mkdb.c +++ b/usr.sbin/services_mkdb/services_mkdb.c @@ -44,6 +44,7 @@ __FBSDID("$FreeBSD$"); #include <stdlib.h> #include <string.h> #include <unistd.h> +#include <libgen.h> #include <libutil.h> #include <ctype.h> #include <errno.h> @@ -91,6 +92,8 @@ main(int argc, char *argv[]) size_t cnt = 0; StringList *sl, ***svc; size_t port, proto; + char *dbname_dir; + int dbname_dir_fd = -1; setprogname(argv[0]); @@ -138,7 +141,7 @@ main(int argc, char *argv[]) err(1, "Cannot install exit handler"); (void)snprintf(tname, sizeof(tname), "%s.tmp", dbname); - db = dbopen(tname, O_RDWR | O_CREAT | O_EXCL, + db = dbopen(tname, O_RDWR | O_CREAT | O_EXCL | O_SYNC, (S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH), DB_HASH, &hinfo); if (!db) err(1, "Error opening temporary database `%s'", tname); @@ -164,8 +167,21 @@ main(int argc, char *argv[]) if ((db->close)(db)) err(1, "Error closing temporary database `%s'", tname); - if (rename(tname, dbname) == -1) + /* + * Make sure file is safe on disk. To improve performance we will call + * fsync() to the directory where file lies + */ + if (rename(tname, dbname) == -1 || + (dbname_dir = dirname(dbname)) == NULL || + (dbname_dir_fd = open(dbname_dir, O_RDONLY|O_DIRECTORY)) == -1 || + fsync(dbname_dir_fd) != 0) { + if (dbname_dir_fd != -1) + close(dbname_dir_fd); err(1, "Cannot rename `%s' to `%s'", tname, dbname); + } + + if (dbname_dir_fd != -1) + close(dbname_dir_fd); return 0; } |
