diff options
| -rw-r--r-- | sys/amd64/amd64/identcpu.c | 7 | ||||
| -rw-r--r-- | sys/amd64/amd64/initcpu.c | 3 | ||||
| -rw-r--r-- | sys/amd64/include/md_var.h | 3 | ||||
| -rw-r--r-- | sys/i386/i386/identcpu.c | 7 | ||||
| -rw-r--r-- | sys/i386/i386/initcpu.c | 3 | ||||
| -rw-r--r-- | sys/i386/include/md_var.h | 3 | ||||
| -rw-r--r-- | sys/x86/include/specialreg.h | 23 |
7 files changed, 49 insertions, 0 deletions
diff --git a/sys/amd64/amd64/identcpu.c b/sys/amd64/amd64/identcpu.c index e63affc..27ea9a6 100644 --- a/sys/amd64/amd64/identcpu.c +++ b/sys/amd64/amd64/identcpu.c @@ -532,6 +532,13 @@ identify_cpu(void) } } + if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) { + do_cpuid(5, regs); + cpu_mon_mwait_flags = regs[2]; + cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE; + cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE; + } + if (cpu_high >= 7) { cpuid_count(7, 0, regs); cpu_stdext_feature = regs[1]; diff --git a/sys/amd64/amd64/initcpu.c b/sys/amd64/amd64/initcpu.c index 4abed4c..f7574b1 100644 --- a/sys/amd64/amd64/initcpu.c +++ b/sys/amd64/amd64/initcpu.c @@ -75,6 +75,9 @@ u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */ u_int cpu_clflush_line_size = 32; u_int cpu_stdext_feature; u_int cpu_max_ext_state_size; +u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */ +u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */ +u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */ SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD, &via_feature_rng, 0, "VIA RNG feature available in CPU"); diff --git a/sys/amd64/include/md_var.h b/sys/amd64/include/md_var.h index 6ffcf63..34bfde4 100644 --- a/sys/amd64/include/md_var.h +++ b/sys/amd64/include/md_var.h @@ -58,6 +58,9 @@ extern u_int cpu_procinfo; extern u_int cpu_procinfo2; extern char cpu_vendor[]; extern u_int cpu_vendor_id; +extern u_int cpu_mon_mwait_flags; +extern u_int cpu_mon_min_size; +extern u_int cpu_mon_max_size; extern char ctx_switch_xsave[]; extern char kstack[]; extern char sigcode[]; diff --git a/sys/i386/i386/identcpu.c b/sys/i386/i386/identcpu.c index b47972c..beec9b1 100644 --- a/sys/i386/i386/identcpu.c +++ b/sys/i386/i386/identcpu.c @@ -1121,6 +1121,13 @@ finishidentcpu(void) } } + if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) { + do_cpuid(5, regs); + cpu_mon_mwait_flags = regs[2]; + cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE; + cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE; + } + /* Detect AMD features (PTE no-execute bit, 3dnow, 64 bit mode etc) */ if (cpu_vendor_id == CPU_VENDOR_INTEL || cpu_vendor_id == CPU_VENDOR_AMD) { diff --git a/sys/i386/i386/initcpu.c b/sys/i386/i386/initcpu.c index 97454bc..5f33897 100644 --- a/sys/i386/i386/initcpu.c +++ b/sys/i386/i386/initcpu.c @@ -97,6 +97,9 @@ u_int cpu_procinfo2 = 0; /* Multicore info */ char cpu_vendor[20] = ""; /* CPU Origin code */ u_int cpu_vendor_id = 0; /* CPU vendor ID */ u_int cpu_clflush_line_size = 32; +u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */ +u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */ +u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */ SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD, &via_feature_rng, 0, "VIA RNG feature available in CPU"); diff --git a/sys/i386/include/md_var.h b/sys/i386/include/md_var.h index 3563e6c..9c8a693 100644 --- a/sys/i386/include/md_var.h +++ b/sys/i386/include/md_var.h @@ -57,6 +57,9 @@ extern u_int cpu_procinfo2; extern char cpu_vendor[]; extern u_int cpu_vendor_id; extern u_int cyrix_did; +extern u_int cpu_mon_mwait_flags; +extern u_int cpu_mon_min_size; +extern u_int cpu_mon_max_size; extern char kstack[]; extern char sigcode[]; extern int szsigcode; diff --git a/sys/x86/include/specialreg.h b/sys/x86/include/specialreg.h index bf1333f..4247ee2 100644 --- a/sys/x86/include/specialreg.h +++ b/sys/x86/include/specialreg.h @@ -240,6 +240,29 @@ #define CPUID_LOCAL_APIC_ID 0xff000000 /* + * CPUID instruction 5 info + */ +#define CPUID5_MON_MIN_SIZE 0x0000ffff /* eax */ +#define CPUID5_MON_MAX_SIZE 0x0000ffff /* ebx */ +#define CPUID5_MON_MWAIT_EXT 0x00000001 /* ecx */ +#define CPUID5_MWAIT_INTRBREAK 0x00000002 /* ecx */ + +/* + * MWAIT cpu power states. Lower 4 bits are sub-states. + */ +#define MWAIT_C0 0xf0 +#define MWAIT_C1 0x00 +#define MWAIT_C2 0x10 +#define MWAIT_C3 0x20 +#define MWAIT_C4 0x30 + +/* + * MWAIT extensions. + */ +/* Interrupt breaks MWAIT even when masked. */ +#define MWAIT_INTRBREAK 0x00000001 + +/* * CPUID instruction 6 ecx info */ #define CPUID_PERF_STAT 0x00000001 |
