diff options
| -rw-r--r-- | share/doc/handbook/authors.sgml | 3 | ||||
| -rw-r--r-- | share/doc/handbook/hw.sgml | 61 |
2 files changed, 59 insertions, 5 deletions
diff --git a/share/doc/handbook/authors.sgml b/share/doc/handbook/authors.sgml index 669a81b..d90321b 100644 --- a/share/doc/handbook/authors.sgml +++ b/share/doc/handbook/authors.sgml @@ -1,4 +1,4 @@ -<!-- $Id: authors.sgml,v 1.4 1995/06/14 18:38:47 jfieber Exp $ --> +<!-- $Id: authors.sgml,v 1.5 1995/07/29 13:08:00 jfieber Exp $ --> <!-- The FreeBSD Documentation Project --> <!-- @@ -23,4 +23,5 @@ entities when referencing people. <!ENTITY a.nik "Nik Clayton <tt><nik@blueberry.co.uk></tt>"> <!ENTITY a.phk "Poul-Henning Kamp <tt><phk@FreeBSD.org></tt>"> <!ENTITY a.paul "Paul Richards <tt><paul@FreeBSD.org></tt>"> +<!ENTITY a.rgrimes "Rodney Grimes <tt><rgrimes@FreeBSD.org></tt>"> <!ENTITY a.wilko "Wilko Bulte <tt><wilko@yedi.iaf.nl></tt>"> diff --git a/share/doc/handbook/hw.sgml b/share/doc/handbook/hw.sgml index b0db439..7290c38 100644 --- a/share/doc/handbook/hw.sgml +++ b/share/doc/handbook/hw.sgml @@ -1,6 +1,10 @@ -<!-- $Id: hw.sgml,v 1.1 1995/06/14 18:38:53 jfieber Exp $ --> +<!-- $Id: hw.sgml,v 1.2 1995/06/20 16:29:54 jfieber Exp $ --> <!-- The FreeBSD Documentation Project --> +<!-- +<!DOCTYPE linuxdoc PUBLIC "-//FreeBSD//DTD linuxdoc//EN"> +--> + <chapt><heading>PC Hardware compatibility<label id="hw"></heading> <p>Issues of hardware compatibility are among the most @@ -28,13 +32,62 @@ FreeBSD you are using and include as many details of your hardware as possible. -<sect><heading>* Core/Processing<label id="hw:core"></heading> +<sect><heading>Core/Processing<label id="hw:core"></heading> -<sect1><heading>* Motherboards</heading> +<sect1><heading>Motherboards, busses, and chipsets</heading> <sect2><heading>* ISA</heading> <sect2><heading>* EISA</heading> <sect2><heading>* VLB</heading> - <sect2><heading>* PCI</heading> + <sect2><heading>PCI</heading> + + <p><em>Contributed by &a.rgrimes;.<newline>25 April 1995.</em></p> + + <p>Of the Intel PCI chip sets the following is a list + of brokenness from worst to best and a short + description of brokenness.</p> + + <p><descrip> + + <tag>Mercury:</tag> Cache coherency problems, + especially if there are ISA bus masters behind + the ISA to PCI bridge chip. Hardware flaw, only + known work around is to turn the cache + off. + + <tag>Saturn-I <em>(ie, 82424ZX at rev 0, 1 or + 2)</em>:</tag> write back cache coherency + problems. Hardware flaw, only known work around + is to set the external cache to write-through + mode. Upgrade to Saturn-II. + + <tag>Saturn-II <em>(ie, 82424ZX at rev 3 or + 4)</em>:</tag> Works fine, but many MB + manufactures leave out the external dirty bit + SRAM needed for write back operation. Work + arounds are either run it in write through mode, + or get the dirty bit SRAM installed. (I have + these for the ASUS PCI/I-486SP3G rev 1.6 and + later boards). + + <tag>Neptune:</tag> Can not run more than 2 bus + master devices. Admitted Intel design flaw. + Workarounds include don't run more than 2 bus + masters, special hardware design to replace the + PCI bus arbiter (appears on Intel Altair board + and several other Intel server group MB's). And + of course Intel's official answer, move to the + Triton chip set, we ``fixed it there''. + + <tag>Triton:</tag> No known cache coherency or bus + master problems, chip set does not implement + parity checking. Workaround for parity issue. + Wait for Triton-II. + + <tag>Triton-II:</tag> Unknown, not yet shipping. + + </descrip> + </p> + <sect1><heading>* CPUs/FPUs</heading> <sect1><heading>* Memory</heading> <sect1><heading>* BIOS</heading> |
