diff options
| -rw-r--r-- | lib/libpmc/Makefile | 2 | ||||
| -rw-r--r-- | lib/libpmc/libpmc.c | 62 | ||||
| -rw-r--r-- | lib/libpmc/pmc.haswell.3 | 975 | ||||
| -rw-r--r-- | lib/libpmc/pmc.haswelluc.3 | 237 | ||||
| -rw-r--r-- | sys/dev/hwpmc/hwpmc_core.c | 367 | ||||
| -rw-r--r-- | sys/dev/hwpmc/hwpmc_intel.c | 8 | ||||
| -rw-r--r-- | sys/dev/hwpmc/hwpmc_uncore.c | 68 | ||||
| -rw-r--r-- | sys/dev/hwpmc/pmc_events.h | 276 | ||||
| -rw-r--r-- | sys/sys/pmc.h | 1 |
9 files changed, 1809 insertions, 187 deletions
diff --git a/lib/libpmc/Makefile b/lib/libpmc/Makefile index c15d38a..dde87bb 100644 --- a/lib/libpmc/Makefile +++ b/lib/libpmc/Makefile @@ -27,6 +27,8 @@ MAN+= pmc.soft.3 MAN+= pmc.atom.3 MAN+= pmc.core.3 MAN+= pmc.core2.3 +MAN+= pmc.haswell.3 +MAN+= pmc.haswelluc.3 MAN+= pmc.iaf.3 MAN+= pmc.ivybridge.3 MAN+= pmc.ivybridgexeon.3 diff --git a/lib/libpmc/libpmc.c b/lib/libpmc/libpmc.c index 1866e7f..74956a9 100644 --- a/lib/libpmc/libpmc.c +++ b/lib/libpmc/libpmc.c @@ -183,6 +183,11 @@ static const struct pmc_event_descr corei7_event_table[] = __PMC_EV_ALIAS_COREI7() }; +static const struct pmc_event_descr haswell_event_table[] = +{ + __PMC_EV_ALIAS_HASWELL() +}; + static const struct pmc_event_descr ivybridge_event_table[] = { __PMC_EV_ALIAS_IVYBRIDGE() @@ -213,6 +218,11 @@ static const struct pmc_event_descr corei7uc_event_table[] = __PMC_EV_ALIAS_COREI7UC() }; +static const struct pmc_event_descr haswelluc_event_table[] = +{ + __PMC_EV_ALIAS_HASWELLUC() +}; + static const struct pmc_event_descr sandybridgeuc_event_table[] = { __PMC_EV_ALIAS_SANDYBRIDGEUC() @@ -237,6 +247,7 @@ PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); PMC_MDEP_TABLE(core, IAP, PMC_CLASS_SOFT, PMC_CLASS_TSC); PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); +PMC_MDEP_TABLE(haswell, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); PMC_MDEP_TABLE(ivybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); PMC_MDEP_TABLE(ivybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC); PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP); @@ -277,6 +288,7 @@ PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap); PMC_CLASS_TABLE_DESC(core, IAP, core, iap); PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap); PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap); +PMC_CLASS_TABLE_DESC(haswell, IAP, haswell, iap); PMC_CLASS_TABLE_DESC(ivybridge, IAP, ivybridge, iap); PMC_CLASS_TABLE_DESC(ivybridge_xeon, IAP, ivybridge_xeon, iap); PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap); @@ -284,6 +296,7 @@ PMC_CLASS_TABLE_DESC(sandybridge_xeon, IAP, sandybridge_xeon, iap); PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap); PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf); PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp); +PMC_CLASS_TABLE_DESC(haswelluc, UCP, haswelluc, ucp); PMC_CLASS_TABLE_DESC(sandybridgeuc, UCP, sandybridgeuc, ucp); PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp); #endif @@ -582,6 +595,8 @@ static struct pmc_event_alias core2_aliases_without_iaf[] = { #define atom_aliases_without_iaf core2_aliases_without_iaf #define corei7_aliases core2_aliases #define corei7_aliases_without_iaf core2_aliases_without_iaf +#define haswell_aliases core2_aliases +#define haswell_aliases_without_iaf core2_aliases_without_iaf #define ivybridge_aliases core2_aliases #define ivybridge_aliases_without_iaf core2_aliases_without_iaf #define ivybridge_xeon_aliases core2_aliases @@ -740,6 +755,31 @@ static struct pmc_masks iap_rsp_mask_sb_sbx_ib[] = { NULLMASK }; +static struct pmc_masks iap_rsp_mask_haswell[] = { + PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)), + PMCMASK(REQ_DMND_RFO, (1ULL << 1)), + PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)), + PMCMASK(REQ_PF_DATA_RD, (1ULL << 4)), + PMCMASK(REQ_PF_RFO, (1ULL << 5)), + PMCMASK(REQ_PF_IFETCH, (1ULL << 6)), + PMCMASK(REQ_OTHER, (1ULL << 15)), + PMCMASK(RES_ANY, (1ULL << 16)), + PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)), + PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)), + PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)), + PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)), + PMCMASK(RES_SUPPLIER_LLC_HITF, (1ULL << 21)), + PMCMASK(RES_SUPPLIER_LOCAL, (1ULL << 22)), + PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)), + PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)), + PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)), + PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)), + PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)), + PMCMASK(RES_SNOOP_HITM, (1ULL << 36)), + PMCMASK(RES_NON_DRAM, (1ULL << 37)), + NULLMASK +}; + static int iap_allocate_pmc(enum pmc_event pe, char *ctrspec, struct pmc_op_pmcallocate *pmc_config) @@ -822,6 +862,11 @@ iap_allocate_pmc(enum pmc_event pe, char *ctrspec, n = pmc_parse_mask(iap_rsp_mask_sb_sbx_ib, p, &rsp); } else return (-1); + } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_HASWELL) { + if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) { + n = pmc_parse_mask(iap_rsp_mask_haswell, p, &rsp); + } else + return (-1); } else return (-1); @@ -2690,6 +2735,10 @@ pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames, ev = corei7_event_table; count = PMC_EVENT_TABLE_SIZE(corei7); break; + case PMC_CPU_INTEL_HASWELL: + ev = haswell_event_table; + count = PMC_EVENT_TABLE_SIZE(haswell); + break; case PMC_CPU_INTEL_IVYBRIDGE: ev = ivybridge_event_table; count = PMC_EVENT_TABLE_SIZE(ivybridge); @@ -2727,6 +2776,10 @@ pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames, ev = corei7uc_event_table; count = PMC_EVENT_TABLE_SIZE(corei7uc); break; + case PMC_CPU_INTEL_HASWELL: + ev = haswelluc_event_table; + count = PMC_EVENT_TABLE_SIZE(haswelluc); + break; case PMC_CPU_INTEL_SANDYBRIDGE: ev = sandybridgeuc_event_table; count = PMC_EVENT_TABLE_SIZE(sandybridgeuc); @@ -2994,6 +3047,11 @@ pmc_init(void) pmc_class_table[n++] = &corei7uc_class_table_descr; PMC_MDEP_INIT_INTEL_V2(corei7); break; + case PMC_CPU_INTEL_HASWELL: + pmc_class_table[n++] = &ucf_class_table_descr; + pmc_class_table[n++] = &haswelluc_class_table_descr; + PMC_MDEP_INIT_INTEL_V2(haswell); + break; case PMC_CPU_INTEL_IVYBRIDGE: PMC_MDEP_INIT_INTEL_V2(ivybridge); break; @@ -3138,6 +3196,10 @@ _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu) ev = corei7_event_table; evfence = corei7_event_table + PMC_EVENT_TABLE_SIZE(corei7); break; + case PMC_CPU_INTEL_HASWELL: + ev = haswell_event_table; + evfence = haswell_event_table + PMC_EVENT_TABLE_SIZE(haswell); + break; case PMC_CPU_INTEL_IVYBRIDGE: ev = ivybridge_event_table; evfence = ivybridge_event_table + PMC_EVENT_TABLE_SIZE(ivybridge); diff --git a/lib/libpmc/pmc.haswell.3 b/lib/libpmc/pmc.haswell.3 new file mode 100644 index 0000000..f73f549 --- /dev/null +++ b/lib/libpmc/pmc.haswell.3 @@ -0,0 +1,975 @@ +.\" Copyright (c) 2013 Hiren Panchasara <hiren.panchasara@gmail.com> +.\" All rights reserved. +.\" +.\" Redistribution and use in source and binary forms, with or without +.\" modification, are permitted provided that the following conditions +.\" are met: +.\" 1. Redistributions of source code must retain the above copyright +.\" notice, this list of conditions and the following disclaimer. +.\" 2. Redistributions in binary form must reproduce the above copyright +.\" notice, this list of conditions and the following disclaimer in the +.\" documentation and/or other materials provided with the distribution. +.\" +.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +.\" SUCH DAMAGE. +.\" +.\" $FreeBSD$ +.\" +.Dd March 22, 2013 +.Dt PMC.HASWELL 3 +.Os +.Sh NAME +.Nm pmc.haswell +.Nd measurement events for +.Tn Intel +.Tn Haswsell +family CPUs +.Sh LIBRARY +.Lb libpmc +.Sh SYNOPSIS +.In pmc.h +.Sh DESCRIPTION +.Tn Intel +.Tn "Haswell" +CPUs contain PMCs conforming to version 2 of the +.Tn Intel +performance measurement architecture. +These CPUs may contain up to two classes of PMCs: +.Bl -tag -width "Li PMC_CLASS_IAP" +.It Li PMC_CLASS_IAF +Fixed-function counters that count only one hardware event per counter. +.It Li PMC_CLASS_IAP +Programmable counters that may be configured to count one of a defined +set of hardware events. +.El +.Pp +The number of PMCs available in each class and their widths need to be +determined at run time by calling +.Xr pmc_cpuinfo 3 . +.Pp +Intel Haswell PMCs are documented in +.Rs +.%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" +.%T "Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B and 3C" +.%N "Order Number: 325462-045US" +.%D January 2013 +.%Q "Intel Corporation" +.Re +.Ss HASWELL FIXED FUNCTION PMCS +These PMCs and their supported events are documented in +.Xr pmc.iaf 3 . +.Ss HASWELL PROGRAMMABLE PMCS +The programmable PMCs support the following capabilities: +.Bl -column "PMC_CAP_INTERRUPT" "Support" +.It Em Capability Ta Em Support +.It PMC_CAP_CASCADE Ta \&No +.It PMC_CAP_EDGE Ta Yes +.It PMC_CAP_INTERRUPT Ta Yes +.It PMC_CAP_INVERT Ta Yes +.It PMC_CAP_READ Ta Yes +.It PMC_CAP_PRECISE Ta \&No +.It PMC_CAP_SYSTEM Ta Yes +.It PMC_CAP_TAGGING Ta \&No +.It PMC_CAP_THRESHOLD Ta Yes +.It PMC_CAP_USER Ta Yes +.It PMC_CAP_WRITE Ta Yes +.El +.Ss Event Qualifiers +Event specifiers for these PMCs support the following common +qualifiers: +.Bl -tag -width indent +.It Li rsp= Ns Ar value +Configure the Off-core Response bits. +.Bl -tag -width indent +.It Li DMND_DATA_RD +Counts the number of demand and DCU prefetch data reads of full +and partial cachelines as well as demand data page table entry +cacheline reads. Does not count L2 data read prefetches or +instruction fetches. +.It Li REQ_DMND_RFO +Counts the number of demand and DCU prefetch reads for ownership (RFO) +requests generated by a write to data cacheline. Does not count L2 RFO +prefetches. +.It Li REQ_DMND_IFETCH +Counts the number of demand and DCU prefetch instruction cacheline reads. +Does not count L2 code read prefetches. +.It Li REQ_WB +Counts the number of writeback (modified to exclusive) transactions. +.It Li REQ_PF_DATA_RD +Counts the number of data cacheline reads generated by L2 prefetchers. +.It Li REQ_PF_RFO +Counts the number of RFO requests generated by L2 prefetchers. +.It Li REQ_PF_IFETCH +Counts the number of code reads generated by L2 prefetchers. +.It Li REQ_PF_LLC_DATA_RD +L2 prefetcher to L3 for loads. +.It Li REQ_PF_LLC_RFO +RFO requests generated by L2 prefetcher +.It Li REQ_PF_LLC_IFETCH +L2 prefetcher to L3 for instruction fetches. +.It Li REQ_BUS_LOCKS +Bus lock and split lock requests. +.It Li REQ_STRM_ST +Streaming store requests. +.It Li REQ_OTHER +Any other request that crosses IDI, including I/O. +.It Li RES_ANY +Catch all value for any response types. +.It Li RES_SUPPLIER_NO_SUPP +No Supplier Information available. +.It Li RES_SUPPLIER_LLC_HITM +M-state initial lookup stat in L3. +.It Li RES_SUPPLIER_LLC_HITE +E-state. +.It Li RES_SUPPLIER_LLC_HITS +S-state. +.It Li RES_SUPPLIER_LLC_HITF +F-state. +.It Li RES_SUPPLIER_LOCAL +Local DRAM Controller. +.It Li RES_SNOOP_SNP_NONE +No details on snoop-related information. +.It Li RES_SNOOP_SNP_NO_NEEDED +No snoop was needed to satisfy the request. +.It Li RES_SNOOP_SNP_MISS +A snoop was needed and it missed all snooped caches: +-For LLC Hit, ReslHitl was returned by all cores +-For LLC Miss, Rspl was returned by all sockets and data was returned from +DRAM. +.It Li RES_SNOOP_HIT_NO_FWD +A snoop was needed and it hits in at least one snooped cache. Hit denotes a +cache-line was valid before snoop effect. This includes: +-Snoop Hit w/ Invalidation (LLC Hit, RFO) +-Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) +-Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) +In the LLC Miss case, data is returned from DRAM. +.It Li RES_SNOOP_HIT_FWD +A snoop was needed and data was forwarded from a remote socket. +This includes: +-Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). +.It Li RES_SNOOP_HITM +A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a +cache-line was in modified state before effect as a results of snoop. This +includes: +-Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) +-Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) +-Snoop MtoS (LLC Hit, IFetch/Data_RD). +.It Li RES_NON_DRAM +Target was non-DRAM system address. This includes MMIO transactions. +.El +.It Li cmask= Ns Ar value +Configure the PMC to increment only if the number of configured +events measured in a cycle is greater than or equal to +.Ar value . +.It Li edge +Configure the PMC to count the number of de-asserted to asserted +transitions of the conditions expressed by the other qualifiers. +If specified, the counter will increment only once whenever a +condition becomes true, irrespective of the number of clocks during +which the condition remains true. +.It Li inv +Invert the sense of comparison when the +.Dq Li cmask +qualifier is present, making the counter increment when the number of +events per cycle is less than the value specified by the +.Dq Li cmask +qualifier. +.It Li os +Configure the PMC to count events happening at processor privilege +level 0. +.It Li usr +Configure the PMC to count events occurring at privilege levels 1, 2 +or 3. +.El +.Pp +If neither of the +.Dq Li os +or +.Dq Li usr +qualifiers are specified, the default is to enable both. +.Ss Event Specifiers (Programmable PMCs) +Haswell programmable PMCs support the following events: +.Bl -tag -width indent +.It Li LD_BLOCKS.STORE_FORWARD +.Pq Event 03H , Umask 02H +Loads blocked by overlapping with store buffer that +cannot be forwarded. +.It Li MISALIGN_MEM_REF.LOADS +.Pq Event 05H , Umask 01H +Speculative cache-line split load uops dispatched to +L1D. +.It Li MISALIGN_MEM_REF.STORES +.Pq Event 05H , Umask 02H +Speculative cache-line split Store-address uops +dispatched to L1D. +.It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS +.Pq Event 07H , Umask 01H +False dependencies in MOB due to partial compare +on address. +.It Li DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK +.Pq Event 08H , Umask 01H +Misses in all TLB levels that cause a page walk of any +page size. +.It Li DTLB_LOAD_MISSES.WALK_COMPLETED_4K +.Pq Event 08H , Umask 02H +Completed page walks due to demand load misses +that caused 4K page walks in any TLB levels. +.It Li DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4K +.Pq Event 08H , Umask 02H +Completed page walks due to demand load misses +that caused 2M/4M page walks in any TLB levels. +.It Li DTLB_LOAD_MISSES.WALK_COMPLETED +.Pq Event 08H , Umask 0EH +Completed page walks in any TLB of any page size +due to demand load misses +.It Li DTLB_LOAD_MISSES.WALK_DURATION +.Pq Event 08H , Umask 10H +Cycle PMH is busy with a walk. +.It Li DTLB_LOAD_MISSES.STLB_HIT_4K +.Pq Event 08H , Umask 20H +Load misses that missed DTLB but hit STLB (4K). +.It Li DTLB_LOAD_MISSES.STLB_HIT_2M +.Pq Event 08H , Umask 40H +Load misses that missed DTLB but hit STLB (2M). +.It Li DTLB_LOAD_MISSES.STLB_HIT +.Pq Event 08H , Umask 60H +Number of cache load STLB hits. No page walk. +.It Li DTLB_LOAD_MISSES.PDE_CACHE_MISS +.Pq Event 08H , Umask 80H +DTLB demand load misses with low part of linear-to- +physical address translation missed +.It Li INT_MISC.RECOVERY_CYCLES +.Pq Event 0DH , Umask 03H +Cycles waiting to recover after Machine Clears +except JEClear. Set Cmask= 1. +.It Li UOPS_ISSUED.ANY +.Pq Event 0EH , Umask 01H +ncrements each cycle the # of Uops issued by the +RAT to RS. +Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles +of this core. +.It Li UOPS_ISSUED.FLAGS_MERGE +.Pq Event 0EH , Umask 10H +Number of flags-merge uops allocated. Such uops +adds delay. +.It Li UOPS_ISSUED.SLOW_LEA +.Pq Event 0EH , Umask 20H +Number of slow LEA or similar uops allocated. Such +uop has 3 sources (e.g. 2 sources + immediate) +regardless if as a result of LEA instruction or not. +.It Li UOPS_ISSUED.SiNGLE_MUL +.Pq Event 0EH , Umask 40H +Number of multiply packed/scalar single precision +uops allocated. +.It Li L2_RQSTS.DEMAND_DATA_RD_MISS +.Pq Event 24H , Umask 21H +Demand Data Read requests that missed L2, no +rejects. +.It Li L2_RQSTS.DEMAND_DATA_RD_HIT +.Pq Event 24H , Umask 41H +Demand Data Read requests that hit L2 cache. +.It Li L2_RQSTS.ALL_DEMAND_DATA_RD +.Pq Event 24H , Umask E1H +Counts any demand and L1 HW prefetch data load +requests to L2. +.It Li L2_RQSTS.RFO_HIT +.Pq Event 24H , Umask 42H +Counts the number of store RFO requests that hit +the L2 cache. +.It Li L2_RQSTS.RFO_MISS +.Pq Event 24H , Umask 22H +Counts the number of store RFO requests that miss +the L2 cache. +.It Li L2_RQSTS.ALL_RFO +.Pq Event 24H , Umask E2H +Counts all L2 store RFO requests. +.It Li L2_RQSTS.CODE_RD_HIT +.Pq Event 24H , Umask 44H +Number of instruction fetches that hit the L2 cache. +.It Li L2_RQSTS.CODE_RD_MISS +.Pq Event 24H , Umask 24H +Number of instruction fetches that missed the L2 +cache. +.It Li L2_RQSTS.ALL_DEMAND_MISS +.Pq Event 24H , Umask 27H +Demand requests that miss L2 cache. +.It Li L2_RQSTS.ALL_DEMAND_REFERENCES +.Pq Event 24H , Umask E7H +Demand requests to L2 cache. +.It Li L2_RQSTS.ALL_CODE_RD +.Pq Event 24H , Umask E4H +Counts all L2 code requests. +.It Li L2_RQSTS.L2_PF_HIT +.Pq Event 24H , Umask 50H +Counts all L2 HW prefetcher requests that hit L2. +.It Li L2_RQSTS.L2_PF_MISS +.Pq Event 24H , Umask 30H +Counts all L2 HW prefetcher requests that missed +L2. +.It Li L2_RQSTS.ALL_PF +.Pq Event 24H , Umask F8H +Counts all L2 HW prefetcher requests. +.It Li L2_RQSTS.MISS +.Pq Event 24H , Umask 3FH +All requests that missed L2. +.It Li L2_RQSTS.REFERENCES +.Pq Event 24H , Umask FFH +All requests to L2 cache. +.It Li L2_DEMAND_RQSTS.WB_HIT +.Pq Event 27H , Umask 50H +Not rejected writebacks that hit L2 cache +.It Li LONGEST_LAT_CACHE.REFERENCE +.Pq Event 2EH , Umask 4FH +This event counts requests originating from the core +that reference a cache line in the last level cache. +.It Li LONGEST_LAT_CACHE.MISS +.Pq Event 2EH , Umask 41H +This event counts each cache miss condition for +references to the last level cache. +.It Li CPU_CLK_UNHALTED.THREAD_P +.Pq Event 3CH , Umask 00H +Counts the number of thread cycles while the thread +is not in a halt state. The thread enters the halt state +when it is running the HLT instruction. The core +frequency may change from time to time due to +power or thermal throttling. +.It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK +.Pq Event 3CH , Umask 01H +Increments at the frequency of XCLK (100 MHz) +when not halted. +.It Li L1D_PEND_MISS.PENDING +.Pq Event 48H , Umask 01H +Increments the number of outstanding L1D misses +every cycle. Set Cmaks = 1 and Edge =1 to count +occurrences. +.It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK +.Pq Event 49H , Umask 01H +Miss in all TLB levels causes an page walk of any +page size (4K/2M/4M/1G). +.It Li DTLB_STORE_MISSES.WALK_COMPLETED_4K +.Pq Event 49H , Umask 02H +Completed page walks due to store misses in one or +more TLB levels of 4K page structure. +.It Li DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M +.Pq Event 49H , Umask 04H +Completed page walks due to store misses in one or +more TLB levels of 2M/4M page structure. +.It Li DTLB_STORE_MISSES.WALK_COMPLETED +.Pq Event 49H , Umask 0EH +Completed page walks due to store miss in any TLB +levels of any page size (4K/2M/4M/1G). +.It Li DTLB_STORE_MISSES.WALK_DURATION +.Pq Event 49H , Umask 10H +Cycles PMH is busy with this walk. +.It Li DTLB_STORE_MISSES.STLB_HIT_4K +.Pq Event 49H , Umask 20H +Store misses that missed DTLB but hit STLB (4K). +.It Li DTLB_STORE_MISSES.STLB_HIT_2M +.Pq Event 49H , Umask 40H +Store misses that missed DTLB but hit STLB (2M). +.It Li DTLB_STORE_MISSES.STLB_HIT +.Pq Event 49H , Umask 60H +Store operations that miss the first TLB level but hit +the second and do not cause page walks. +.It Li DTLB_STORE_MISSES.PDE_CACHE_MISS +.Pq Event 49H , Umask 80H +DTLB store misses with low part of linear-to-physical +address translation missed. +.It Li LOAD_HIT_PRE.SW_PF +.Pq Event 4CH , Umask 01H +Non-SW-prefetch load dispatches that hit fill buffer +allocated for S/W prefetch. +.It Li LOAD_HIT_PRE.HW_PF +.Pq Event 4CH , Umask 02H +Non-SW-prefetch load dispatches that hit fill buffer +allocated for H/W prefetch. +.It Li L1D.REPLACEMENT +.Pq Event 51H , Umask 01H +Counts the number of lines brought into the L1 data +cache. +.It Li MOVE_ELIMINATION.INT_NOT_ELIMINATED +.Pq Event 58H , Umask 04H +Number of integer Move Elimination candidate uops +that were not eliminated. +.It Li MOVE_ELIMINATION.SMID_NOT_ELIMINATED +.Pq Event 58H , Umask 08H +Number of SIMD Move Elimination candidate uops +that were not eliminated. +.It Li MOVE_ELIMINATION.INT_ELIMINATED +.Pq Event 58H , Umask 01H +Unhalted core cycles when the thread is in ring 0. +.It Li MOVE_ELIMINATION.SMID_ELIMINATED +.Pq Event 58H , Umask 02H +Number of SIMD Move Elimination candidate uops +that were eliminated. +.It Li CPL_CYCLES.RING0 +.Pq Event 5CH , Umask 02H +Unhalted core cycles when the thread is in ring 0. +.It Li CPL_CYCLES.RING123 +.Pq Event 5CH , Umask 01H +Unhalted core cycles when the thread is not in ring 0. +.It Li RS_EVENTS.EMPTY_CYCLES +.Pq Event 5EH , Umask 01H +Cycles the RS is empty for the thread. +.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD +.Pq Event 60H , Umask 01H +Offcore outstanding Demand Data Read transactions +in SQ to uncore. Set Cmask=1 to count cycles. +.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CORE_RD +.Pq Event 60H , Umask 02H +Offcore outstanding Demand code Read transactions +in SQ to uncore. Set Cmask=1 to count cycles. +.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO +.Pq Event 60H , Umask 04H +Offcore outstanding RFO store transactions in SQ to +uncore. Set Cmask=1 to count cycles. +.It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD +.Pq Event 60H , Umask 08H +Offcore outstanding cacheable data read +transactions in SQ to uncore. Set Cmask=1 to count +cycles. +.It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION +.Pq Event 63H , Umask 01H +Cycles in which the L1D and L2 are locked, due to a +UC lock or split lock. +.It Li LOCK_CYCLES.CACHE_LOCK_DURATION +.Pq Event 63H , Umask 02H +Cycles in which the L1D is locked. +.It Li IDQ.EMPTY +.Pq Event 79H , Umask 02H +Counts cycles the IDQ is empty. +.It Li IDQ.MITE_UOPS +.Pq Event 79H , Umask 04H +Increment each cycle # of uops delivered to IDQ from +MITE path. +Set Cmask = 1 to count cycles. +.It Li IDQ.DSB_UOPS +.Pq Event 79H , Umask 08H +Increment each cycle. # of uops delivered to IDQ +from DSB path. +Set Cmask = 1 to count cycles. +.It Li IDQ.MS_DSB_UOPS +.Pq Event 79H , Umask 10H +Increment each cycle # of uops delivered to IDQ +when MS_busy by DSB. Set Cmask = 1 to count +cycles. Add Edge=1 to count # of delivery. +.It Li IDQ.MS_MITE_UOPS +.Pq Event 79H , Umask 20H +ncrement each cycle # of uops delivered to IDQ +when MS_busy by MITE. Set Cmask = 1 to count +cycles. +.It Li IDQ.MS_UOPS +.Pq Event 79H , Umask 30H +Increment each cycle # of uops delivered to IDQ from +MS by either DSB or MITE. Set Cmask = 1 to count +cycles. +.It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS +.Pq Event 79H , Umask 18H +Counts cycles DSB is delivered at least one uops. Set +Cmask = 1. +.It Li IDQ.ALL_DSB_CYCLES_4_UOPS +.Pq Event 79H , Umask 18H +Counts cycles DSB is delivered four uops. Set Cmask +=4. +.It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS +.Pq Event 79H , Umask 24H +Counts cycles MITE is delivered at least one uops. Set +Cmask = 1. +.It Li IDQ.ALL_MITE_CYCLES_4_UOPS +.Pq Event 79H , Umask 24H +Counts cycles MITE is delivered four uops. Set Cmask +=4. +.It Li IDQ.MITE_ALL_UOPS +.Pq Event 79H , Umask 3CH +# of uops delivered to IDQ from any path. +.It Li ICACHE.MISSES +.Pq Event 80H , Umask 02H +Number of Instruction Cache, Streaming Buffer and +Victim Cache Misses. Includes UC accesses. +.It Li ITLB_MISSES.MISS_CAUSES_A_WALK +.Pq Event 85H , Umask 01H +Misses in ITLB that causes a page walk of any page +size. +.It Li ITLB_MISSES.WALK_COMPLETED_4K +.Pq Event 85H , Umask 02H +Completed page walks due to misses in ITLB 4K page +entries. +.It Li TLB_MISSES.WALK_COMPLETED_2M_4M +.Pq Event 85H , Umask 04H +Completed page walks due to misses in ITLB 2M/4M +page entries. +.It Li ITLB_MISSES.WALK_COMPLETED +.Pq Event 85H , Umask 0EH +Completed page walks in ITLB of any page size. +.It Li ITLB_MISSES.WALK_DURATION +.Pq Event 85H , Umask 10H +Cycle PMH is busy with a walk. +.It Li ITLB_MISSES.STLB_HIT_4K +.Pq Event 85H , Umask 20H +ITLB misses that hit STLB (4K). +.It Li ITLB_MISSES.STLB_HIT_2M +.Pq Event 85H , Umask 40H +ITLB misses that hit STLB (2K). +.It Li ITLB_MISSES.STLB_HIT +.Pq Event 85H , Umask 60H +TLB misses that hit STLB. No page walk. +.It Li ILD_STALL.LCP +.Pq Event 87H , Umask 01H +Stalls caused by changing prefix length of the +instruction. +.It Li ILD_STALL.IQ_FULL +.Pq Event 87H , Umask 04H +Stall cycles due to IQ is full. +.It Li BR_INST_EXEC.COND +.Pq Event 88H , Umask 01H +Qualify conditional near branch instructions +executed, but not necessarily retired. +.It Li BR_INST_EXEC.DIRECT_JMP +.Pq Event 88H , Umask 02H +Qualify all unconditional near branch instructions +excluding calls and indirect branches. +.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET +.Pq Event 88H , Umask 04H +Qualify executed indirect near branch instructions +that are not calls nor returns. +.It Li BR_INST_EXEC.RETURN_NEAR +.Pq Event 88H , Umask 08H +Qualify indirect near branches that have a return +mnemonic. +.It Li BR_INST_EXEC.DIRECT_NEAR_CALL +.Pq Event 88H , Umask 10H +Qualify unconditional near call branch instructions, +excluding non call branch, executed. +.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL +.Pq Event 88H , Umask 20H +Qualify indirect near calls, including both register and +memory indirect, executed. +.It Li BR_INST_EXEC.NONTAKEN +.Pq Event 88H , Umask 40H +Qualify non-taken near branches executed. +.It Li BR_INST_EXEC.TAKEN +.Pq Event 88H , Umask 80H +Qualify taken near branches executed. Must combine +with 01H,02H, 04H, 08H, 10H, 20H. +.It Li BR_INST_EXEC.ALL_BRANCHES +.Pq Event 88H , Umask FFH +Counts all near executed branches (not necessarily +retired). +.It Li BR_MISP_EXEC.COND +.Pq Event 89H , Umask 01H +Qualify conditional near branch instructions +mispredicted. +.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET +.Pq Event 89H , Umask 04H +Qualify mispredicted indirect near branch +instructions that are not calls nor returns. +.It Li BR_MISP_EXEC.RETURN_NEAR +.Pq Event 89H , Umask 08H +Qualify mispredicted indirect near branches that +have a return mnemonic. +.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL +.Pq Event 89H , Umask 10H +Qualify mispredicted unconditional near call branch +instructions, excluding non call branch, executed. +.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL +.Pq Event 89H , Umask 20H +Qualify mispredicted indirect near calls, including +both register and memory indirect, executed. +.It Li BR_MISP_EXEC.NONTAKEN +.Pq Event 89H , Umask 40H +Qualify mispredicted non-taken near branches +executed. +.It Li BR_MISP_EXEC.TAKEN +.Pq Event 89H , Umask 80H +Qualify mispredicted taken near branches executed. +Must combine with 01H,02H, 04H, 08H, 10H, 20H. +.It Li BR_MISP_EXEC.ALL_BRANCHES +.Pq Event 89H , Umask FFH +Counts all near executed branches (not necessarily +retired). +.It Li IDQ_UOPS_NOT_DELIVERED.CORE +.Pq Event 9CH , Umask 01H +Count number of non-delivered uops to RAT per +thread. +.It Li UOPS_EXECUTED_PORT.PORT_0 +.Pq Event A1H , Umask 01H +Cycles which a Uop is dispatched on port 0 in this +thread. +.It Li UOPS_EXECUTED_PORT.PORT_1 +.Pq Event A1H , Umask 02H +Cycles which a Uop is dispatched on port 1 in this +thread. +.It Li UOPS_EXECUTED_PORT.PORT_2 +.Pq Event A1H , Umask 04H +Cycles which a Uop is dispatched on port 2 in this +thread. +.It Li UOPS_EXECUTED_PORT.PORT_3 +.Pq Event A1H , Umask 08H +Cycles which a Uop is dispatched on port 3 in this +thread. +.It Li UOPS_EXECUTED_PORT.PORT_4 +.Pq Event A1H , Umask 10H +Cycles which a Uop is dispatched on port 4 in this +thread. +.It Li UOPS_EXECUTED_PORT.PORT_5 +.Pq Event A1H , Umask 20H +Cycles which a Uop is dispatched on port 5 in this +thread. +.It Li UOPS_EXECUTED_PORT.PORT_6 +.Pq Event A1H , Umask 40H +Cycles which a Uop is dispatched on port 6 in this +thread. +.It Li UOPS_EXECUTED_PORT.PORT_7 +.Pq Event A1H , Umask 80H +Cycles which a Uop is dispatched on port 7 in this +thread. +.It Li RESOURCE_STALLS.ANY +.Pq Event A2H , Umask 01H +Cycles Allocation is stalled due to Resource Related +reason. +.It Li RESOURCE_STALLS.RS +.Pq Event A2H , Umask 04H +Cycles stalled due to no eligible RS entry available. +.It Li RESOURCE_STALLS.SB +.Pq Event A2H , Umask 08H +Cycles stalled due to no store buffers available (not +including draining form sync). +.It Li RESOURCE_STALLS.ROB +.Pq Event A2H , Umask 10H +Cycles stalled due to re-order buffer full. +.It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING +.Pq Event A3H , Umask 01H +Cycles with pending L2 miss loads. Set Cmask=2 to +count cycle. +.It Li CYCLE_ACTIVITY.CYCLES_LDM_PENDING +.Pq Event A3H , Umask 02H +Cycles with pending memory loads. Set Cmask=2 to +count cycle. +.It Li CYCLE_ACTIVITY.STALLS_L2_PENDING +.Pq Event A3H , Umask 05H +Number of loads missed L2. +.It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING +.Pq Event A3H , Umask 08H +Cycles with pending L1 cache miss loads. Set +Cmask=8 to count cycle. +.It Li ITLB.ITLB_FLUSH +.Pq Event AEH , Umask 01H +Counts the number of ITLB flushes, includes +4k/2M/4M pages. +.It Li OFFCORE_REQUESTS.DEMAND_DATA_RD +.Pq Event B0H , Umask 01H +Demand data read requests sent to uncore. +.It Li OFFCORE_REQUESTS.DEMAND_CODE_RD +.Pq Event B0H , Umask 02H +Demand code read requests sent to uncore. +.It Li OFFCORE_REQUESTS.DEMAND_RFO +.Pq Event B0H , Umask 04H +Demand RFO read requests sent to uncore, including +regular RFOs, locks, ItoM. +.It Li OFFCORE_REQUESTS.ALL_DATA_RD +.Pq Event B0H , Umask 08H +Data read requests sent to uncore (demand and +prefetch). +.It Li UOPS_EXECUTED.CORE +.Pq Event B1H , Umask 02H +Counts total number of uops to be executed per-core +each cycle. +.It Li OFF_CORE_RESPONSE_0 +.Pq Event B7H , Umask 01H +Requires MSR 01A6H +.It Li OFF_CORE_RESPONSE_1 +.Pq Event BBH , Umask 01H +Requires MSR 01A7H +.It Li PAGE_WALKER_LOADS.DTLB_L1 +.Pq Event BCH , Umask 11H +Number of DTLB page walker loads that hit in the +L1+FB. +.It Li PAGE_WALKER_LOADS.ITLB_L1 +.Pq Event BCH , Umask 21H +Number of ITLB page walker loads that hit in the +L1+FB. +.It Li PAGE_WALKER_LOADS.DTLB_L2 +.Pq Event BCH , Umask 12H +Number of DTLB page walker loads that hit in the L2. +.It Li PAGE_WALKER_LOADS.ITLB_L2 +.Pq Event BCH , Umask 22H +Number of ITLB page walker loads that hit in the L2. +.It Li PAGE_WALKER_LOADS.DTLB_L3 +.Pq Event BCH , Umask 14H +Number of DTLB page walker loads that hit in the L3. +.It Li PAGE_WALKER_LOADS.ITLB_L3 +.Pq Event BCH , Umask 24H +Number of ITLB page walker loads that hit in the L3. +.It Li PAGE_WALKER_LOADS.DTLB_MEMORY +.Pq Event BCH , Umask 18H +Number of DTLB page walker loads from memory. +.It Li PAGE_WALKER_LOADS.ITLB_MEMORY +.Pq Event BCH , Umask 28H +Number of ITLB page walker loads from memory. +.It Li TLB_FLUSH.DTLB_THREAD +.Pq Event BDH , Umask 01H +DTLB flush attempts of the thread-specific entries. +.It Li TLB_FLUSH.STLB_ANY +.Pq Event BDH , Umask 20H +Count number of STLB flush attempts. +.It Li INST_RETIRED.ANY_P +.Pq Event C0H , Umask 00H +Number of instructions at retirement. +.It Li INST_RETIRED.ALL +.Pq Event C0H , Umask 01H +Precise instruction retired event with HW to reduce +effect of PEBS shadow in IP distribution. +.It Li OTHER_ASSISTS.AVX_TO_SSE +.Pq Event C1H , Umask 08H +Number of transitions from AVX-256 to legacy SSE +when penalty applicable. +.It Li OTHER_ASSISTS.SSE_TO_AVX +.Pq Event C1H , Umask 10H +Number of transitions from SSE to AVX-256 when +penalty applicable. +.It Li OTHER_ASSISTS.ANY_WB_ASSIST +.Pq Event C1H , Umask 40H +Number of microcode assists invoked by HW upon +uop writeback. +.It Li UOPS_RETIRED.ALL +.Pq Event C2H , Umask 01H +Counts the number of micro-ops retired, Use +cmask=1 and invert to count active cycles or stalled +cycles. +.It Li UOPS_RETIRED.RETIRE_SLOTS +.Pq Event C2H , Umask 02H +Counts the number of retirement slots used each +cycle. +.It Li MACHINE_CLEARS.MEMORY_ORDERING +.Pq Event C3H , Umask 02H +Counts the number of machine clears due to memory +order conflicts. +.It Li MACHINE_CLEARS.SMC +.Pq Event C3H , Umask 04H +Number of self-modifying-code machine clears +detected. +.It Li MACHINE_CLEARS.MASKMOV +.Pq Event C3H , Umask 20H +Counts the number of executed AVX masked load +operations that refer to an illegal address range with +the mask bits set to 0. +.It Li BR_INST_RETIRED.ALL_BRANCHES +.Pq Event C4H , Umask 00H +Branch instructions at retirement. +.It Li BR_INST_RETIRED.CONDITIONAL +.Pq Event C4H , Umask 01H +Counts the number of conditional branch instructions Supports PEBS +retired. +.It Li BR_INST_RETIRED.NEAR_CALL +.Pq Event C4H , Umask 02H +Direct and indirect near call instructions retired. +.It Li BR_INST_RETIRED.ALL_BRANCHES +.Pq Event C4H , Umask 04H +Counts the number of branch instructions retired. +.It Li BR_INST_RETIRED.NEAR_RETURN +.Pq Event C4H , Umask 08H +Counts the number of near return instructions +retired. +.It Li BR_INST_RETIRED.NOT_TAKEN +.Pq Event C4H , Umask 10H +Counts the number of not taken branch instructions +retired. + It Li BR_INST_RETIRED.NEAR_TAKEN +.Pq Event C4H , Umask 20H +Number of near taken branches retired. +.It Li BR_INST_RETIRED.FAR_BRANCH +.Pq Event C4H , Umask 40H +Number of far branches retired. +.It Li BR_MISP_RETIRED.ALL_BRANCHES +.Pq Event C5H , Umask 00H +Mispredicted branch instructions at retirement +.It Li BR_MISP_RETIRED.CONDITIONAL +.Pq Event C5H , Umask 01H +Mispredicted conditional branch instructions retired. +.It Li BR_MISP_RETIRED.CONDITIONAL +.Pq Event C5H , Umask 04H +Mispredicted macro branch instructions retired. +.It Li FP_ASSIST.X87_OUTPUT +.Pq Event CAH , Umask 02H +Number of X87 FP assists due to Output values. +.It Li FP_ASSIST.X87_INPUT +.Pq Event CAH , Umask 04H +Number of X87 FP assists due to input values. +.It Li FP_ASSIST.SIMD_OUTPUT +.Pq Event CAH , Umask 08H +Number of SIMD FP assists due to Output values. +.It Li FP_ASSIST.SIMD_INPUT +.Pq Event CAH , Umask 10H +Number of SIMD FP assists due to input values. +.It Li FP_ASSIST.ANY +.Pq Event CAH , Umask 1EH +Cycles with any input/output SSE* or FP assists. +.It Li ROB_MISC_EVENTS.LBR_INSERTS +.Pq Event CCH , Umask 20H +Count cases of saving new LBR records by hardware. +.It Li MEM_TRANS_RETIRED.LOAD_LATENCY +.Pq Event CDH , Umask 01H +Randomly sampled loads whose latency is above a +user defined threshold. A small fraction of the overall +loads are sampled due to randomization. +.It Li MEM_UOP_RETIRED.LOADS +.Pq Event D0H , Umask 01H +Qualify retired memory uops that are loads. Combine Supports PEBS and +with umask 10H, 20H, 40H, 80H. +.It Li MEM_UOP_RETIRED.STORES +.Pq Event D0H , Umask 02H +Qualify retired memory uops that are stores. +Combine with umask 10H, 20H, 40H, 80H. +.It Li MEM_UOP_RETIRED.STLB_MISS +.Pq Event D0H , Umask 10H +Qualify retired memory uops with STLB miss. Must +combine with umask 01H, 02H, to produce counts. +.It Li MEM_UOP_RETIRED.LOCK +.Pq Event D0H , Umask 20H +Qualify retired memory uops with lock. Must combine Supports PEBS and +with umask 01H, 02H, to produce counts. +.It Li MEM_UOP_RETIRED.SPLIT +.Pq Event D0H , Umask 40H +Qualify retired memory uops with line split. Must +combine with umask 01H, 02H, to produce counts. +.It Li MEM_UOP_RETIRED.ALL +.Pq Event D0H , Umask 80H +Qualify any retired memory uops. Must combine with Supports PEBS and +umask 01H, 02H, to produce counts. +.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT +.Pq Event D1H , Umask 01H +Retired load uops with L1 cache hits as data sources. +.It Li MEM_LOAD_UOPS_RETIRED.L2_HIT +.Pq Event D1H , Umask 02H +Retired load uops with L2 cache hits as data sources. +.It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT +.Pq Event D1H , Umask 04H +Retired load uops with LLC cache hits as data +sources. +.It Li MEM_LOAD_UOPS_RETIRED.L2_MISS +.Pq Event D1H , Umask 10H +Retired load uops missed L2. Unknown data source +excluded. +.It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB +.Pq Event D1H , Umask 40H +Retired load uops which data sources were load uops +missed L1 but hit FB due to preceding miss to the +same cache line with data not ready. +.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS +.Pq Event D2H , Umask 01H +Retired load uops which data sources were LLC hit +and cross-core snoop missed in on-pkg core cache. +.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT +.Pq Event D2H , Umask 02H +Retired load uops which data sources were LLC and +cross-core snoop hits in on-pkg core cache. +.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM +.Pq Event D2H , Umask 04H +Retired load uops which data sources were HitM +responses from shared LLC. +.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE +.Pq Event D2H , Umask 08H +Retired load uops which data sources were hits in +LLC without snoops required. +.It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM +.Pq Event D3H , Umask 01H +Retired load uops which data sources missed LLC but +serviced from local dram. +.It Li BACLEARS.ANY +.Pq Event E6H , Umask 1FH +Number of front end re-steers due to BPU +misprediction. +.It Li L2_TRANS.DEMAND_DATA_RD +.Pq Event F0H , Umask 01H +Demand Data Read requests that access L2 cache. +.It Li L2_TRANS.RFO +.Pq Event F0H , Umask 02H +RFO requests that access L2 cache. +.It Li L2_TRANS.CODE_RD +.Pq Event F0H , Umask 04H +L2 cache accesses when fetching instructions. +.It Li L2_TRANS.ALL_PF +.Pq Event F0H , Umask 08H +Any MLC or LLC HW prefetch accessing L2, including +rejects. +.It Li L2_TRANS.L1D_WB +.Pq Event F0H , Umask 10H +L1D writebacks that access L2 cache. +.It Li L2_TRANS.L2_FILL +.Pq Event F0H , Umask 20H +L2 fill requests that access L2 cache. +.It Li L2_TRANS.L2_WB +.Pq Event F0H , Umask 40H +L2 writebacks that access L2 cache. +.It Li L2_TRANS.ALL_REQUESTS +.Pq Event F0H , Umask 80H +Transactions accessing L2 pipe. +.It Li L2_LINES_IN.I +.Pq Event F1H , Umask 01H +L2 cache lines in I state filling L2. +.It Li L2_LINES_IN.S +.Pq Event F1H , Umask 02H +L2 cache lines in S state filling L2. +.It Li L2_LINES_IN.E +.Pq Event F1H , Umask 04H +L2 cache lines in E state filling L2. +.It Li L2_LINES_IN.ALL +.Pq Event F1H , Umask 07H +L2 cache lines filling L2. +.It Li L2_LINES_OUT.DEMAND_CLEAN +.Pq Event F2H , Umask 05H +Clean L2 cache lines evicted by demand. +.It Li L2_LINES_OUT.DEMAND_DIRTY +.Pq Event F2H , Umask 06H +Dirty L2 cache lines evicted by demand. +.El +.Sh SEE ALSO +.Xr pmc 3 , +.Xr pmc.atom 3 , +.Xr pmc.core 3 , +.Xr pmc.iaf 3 , +.Xr pmc.ucf 3 , +.Xr pmc.k7 3 , +.Xr pmc.k8 3 , +.Xr pmc.p4 3 , +.Xr pmc.p5 3 , +.Xr pmc.p6 3 , +.Xr pmc.corei7 3 , +.Xr pmc.corei7uc 3 , +.Xr pmc.haswelluc 3 , +.Xr pmc.ivybridge 3 , +.Xr pmc.ivybridgexeon 3 , +.Xr pmc.sandybridge 3 , +.Xr pmc.sandybridgeuc 3 , +.Xr pmc.sandybridgexeon 3 , +.Xr pmc.westmere 3 , +.Xr pmc.westmereuc 3 , +.Xr pmc.soft 3 , +.Xr pmc.tsc 3 , +.Xr pmc_cpuinfo 3 , +.Xr pmclog 3 , +.Xr hwpmc 4 +.Sh HISTORY +The +.Nm pmc +library first appeared in +.Fx 6.0 . +.Sh AUTHORS +The +.Lb libpmc +library was written by +.An "Joseph Koshy" +.Aq jkoshy@FreeBSD.org . +The support for the Haswell +microarchitecture was written by +.An "Hiren Panchasara" +.Aq hiren.panchasara@gmail.com . diff --git a/lib/libpmc/pmc.haswelluc.3 b/lib/libpmc/pmc.haswelluc.3 new file mode 100644 index 0000000..5adef59 --- /dev/null +++ b/lib/libpmc/pmc.haswelluc.3 @@ -0,0 +1,237 @@ +.\" Copyright (c) 2013 Hiren Panchasara <hiren.panchasara@gmail.com> +.\" All rights reserved. +.\" +.\" Redistribution and use in source and binary forms, with or without +.\" modification, are permitted provided that the following conditions +.\" are met: +.\" 1. Redistributions of source code must retain the above copyright +.\" notice, this list of conditions and the following disclaimer. +.\" 2. Redistributions in binary form must reproduce the above copyright +.\" notice, this list of conditions and the following disclaimer in the +.\" documentation and/or other materials provided with the distribution. +.\" +.\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND +.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE +.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +.\" SUCH DAMAGE. +.\" +.\" $FreeBSD$ +.\" +.Dd March 22, 2013 +.Dt PMC.HASWELLUC 3 +.Os +.Sh NAME +.Nm pmc.haswelluc +.Nd uncore measurement events for +.Tn Intel +.Tn Haswell +family CPUs +.Sh LIBRARY +.Lb libpmc +.Sh SYNOPSIS +.In pmc.h +.Sh DESCRIPTION +.Tn Intel +.Tn "Haswell" +CPUs contain PMCs conforming to version 3 of the +.Tn Intel +performance measurement architecture. +These CPUs contain two classes of PMCs: +.Bl -tag -width "Li PMC_CLASS_UCP" +.It Li PMC_CLASS_UCF +Fixed-function counters that count only one hardware event per counter. +.It Li PMC_CLASS_UCP +Programmable counters that may be configured to count one of a defined +set of hardware events. +.El +.Pp +The number of PMCs available in each class and their widths need to be +determined at run time by calling +.Xr pmc_cpuinfo 3 . +.Pp +Intel Haswell PMCs are documented in +.Rs +.%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual" +.%T "Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B and 3C" +.%N "Order Number: 325462-045US" +.%D January 2013 +.%Q "Intel Corporation" +.Re +.Ss HASWELL UNCORE FIXED FUNCTION PMCS +These PMCs and their supported events are documented in +.Xr pmc.ucf 3 . +Not all CPUs in this family implement fixed-function counters. +.Ss HASWELL UNCORE PROGRAMMABLE PMCS +The programmable PMCs support the following capabilities: +.Bl -column "PMC_CAP_INTERRUPT" "Support" +.It Em Capability Ta Em Support +.It PMC_CAP_CASCADE Ta \&No +.It PMC_CAP_EDGE Ta Yes +.It PMC_CAP_INTERRUPT Ta \&No +.It PMC_CAP_INVERT Ta Yes +.It PMC_CAP_READ Ta Yes +.It PMC_CAP_PRECISE Ta \&No +.It PMC_CAP_SYSTEM Ta \&No +.It PMC_CAP_TAGGING Ta \&No +.It PMC_CAP_THRESHOLD Ta Yes +.It PMC_CAP_USER Ta \&No +.It PMC_CAP_WRITE Ta Yes +.El +.Ss Event Qualifiers +Event specifiers for these PMCs support the following common +qualifiers: +.Bl -tag -width indent +.It Li cmask= Ns Ar value +Configure the PMC to increment only if the number of configured +events measured in a cycle is greater than or equal to +.Ar value . +.It Li edge +Configure the PMC to count the number of de-asserted to asserted +transitions of the conditions expressed by the other qualifiers. +If specified, the counter will increment only once whenever a +condition becomes true, irrespective of the number of clocks during +which the condition remains true. +.It Li inv +Invert the sense of comparison when the +.Dq Li cmask +qualifier is present, making the counter increment when the number of +events per cycle is less than the value specified by the +.Dq Li cmask +qualifier. +.El +.Ss Event Specifiers (Programmable PMCs) +Haswell programmable PMCs support the following events: +.Bl -tag -width indent +.It Li UNC_CBO_XSNP_RESPONSE.MISS +.Pq Event 22H , Umask 01H +A snoop misses in some processor core. +.It Li UNC_CBO_XSNP_RESPONSE.INVAL +.Pq Event 22H , Umask 02H +A snoop invalidates a non-modified line in some +processor core. +.It Li UNC_CBO_XSNP_RESPONSE.HIT +.Pq Event 22H , Umask 04H +A snoop hits a non-modified line in some processor +core. +.It Li UNC_CBO_XSNP_RESPONSE.HITM +.Pq Event 22H , Umask 08H +A snoop hits a modified line in some processor core. +.It Li UNC_CBO_XSNP_RESPONSE.INVAL_M +.Pq Event 22H , Umask 10H +A snoop invalidates a modified line in some processor +core. +.It Li UNC_CBO_XSNP_RESPONSE.EXTERNAL_FILTER +.Pq Event 22H , Umask 20H +Filter on cross-core snoops initiated by this Cbox due +to external snoop request. +.It Li UNC_CBO_XSNP_RESPONSE.XCORE_FILTER +.Pq Event 22H , Umask 40H +Filter on cross-core snoops initiated by this Cbox due +to processor core memory request. +.It Li UNC_CBO_XSNP_RESPONSE.EVICTION_FILTER +.Pq Event 22H , Umask 80H +Filter on cross-core snoops initiated by this Cbox due +to LLC eviction. +.It Li UNC_CBO_CACHE_LOOKUP.M +.Pq Event 34H , Umask 01H +LLC lookup request that access cache and found line in +M-state. +.It Li UNC_CBO_CACHE_LOOKUP.ES +.Pq Event 34H , Umask 06H +LLC lookup request that access cache and found line in +E or S state. +.It Li UNC_CBO_CACHE_LOOKUP.I +.Pq Event 34H , Umask 08H +LLC lookup request that access cache and found line in +I-state. +.It Li UNC_CBO_CACHE_LOOKUP.READ_FILTER +.Pq Event 34H , Umask 10H +Filter on processor core initiated cacheable read +requests. Must combine with at least one of 01H, 02H, +04H, 08H. +.It Li UNC_CBO_CACHE_LOOKUP.WRITE_FILTER +.Pq Event 34H , Umask 20H +Filter on processor core initiated cacheable write +requests. Must combine with at least one of 01H, 02H, +04H, 08H. +.It Li UNC_CBO_CACHE_LOOKUP.EXTSNP_FILTER +.Pq Event 34H , Umask 40H +Filter on external snoop requests. Must combine with +at least one of 01H, 02H, 04H, 08H. +.It Li UNC_CBO_CACHE_LOOKUP.ANY_REQUEST_FILTER +.Pq Event 34H , Umask 80H +Filter on any IRQ or IPQ initiated requests including +uncacheable, non-coherent requests. Must combine +with at least one of 01H, 02H, 04H, 08H. +.It Li UNC_ARB_TRK_OCCUPANCY.ALL +.Pq Event 80H , Umask 01H +Counts cycles weighted by the number of requests +waiting for data returning from the memory controller. +Accounts for coherent and non-coherent requests +initiated by IA cores, processor graphic units, or LLC. +.It Li UNC_ARB_TRK_REQUEST.ALL +.Pq Event 81H , Umask 01H +Counts the number of coherent and in-coherent +requests initiated by IA cores, processor graphic units, +or LLC. +.It Li UNC_ARB_TRK_REQUEST.WRITES +.Pq Event 81H , Umask 20H +Counts the number of allocated write entries, include +full, partial, and LLC evictions. +.It Li UNC_ARB_TRK_REQUEST.EVICTIONS +.Pq Event 81H , Umask 80H +Counts the number of LLC evictions allocated. +.It Li UNC_ARB_COH , Umask TRK_OCCUPANCY.ALL +.Pq Event 83H , Umask 01H +Cycles weighted by number of requests pending in +Coherency Tracker. +.It Li UNC_ARB_COH , Umask TRK_REQUEST.ALL +.Pq Event 84H , Umask 01H +Number of requests allocated in Coherency Tracker. +.El +.Sh SEE ALSO +.Xr pmc 3 , +.Xr pmc.atom 3 , +.Xr pmc.core 3 , +.Xr pmc.corei7 3 , +.Xr pmc.corei7uc 3 , +.Xr pmc.haswell 3 , +.Xr pmc.iaf 3 , +.Xr pmc.k7 3 , +.Xr pmc.k8 3 , +.Xr pmc.p4 3 , +.Xr pmc.p5 3 , +.Xr pmc.p6 3 , +.Xr pmc.sandybridge 3 , +.Xr pmc.sandybridgeuc 3 , +.Xr pmc.sandybridgexeon 3 , +.Xr pmc.soft 3 , +.Xr pmc.tsc 3 , +.Xr pmc.ucf 3 , +.Xr pmc.westmere 3 , +.Xr pmc.westmereuc 3 , +.Xr pmc_cpuinfo 3 , +.Xr pmclog 3 , +.Xr hwpmc 4 +.Sh HISTORY +The +.Nm pmc +library first appeared in +.Fx 6.0 . +.Sh AUTHORS +The +.Lb libpmc +library was written by +.An "Joseph Koshy" +.Aq jkoshy@FreeBSD.org . +The support for the Haswell +microarchitecture was added by +.An "Hiren Panchasara" +.Aq hiren.panchasara@gmail.com . diff --git a/sys/dev/hwpmc/hwpmc_core.c b/sys/dev/hwpmc/hwpmc_core.c index 77eb93b..4426e3f 100644 --- a/sys/dev/hwpmc/hwpmc_core.c +++ b/sys/dev/hwpmc/hwpmc_core.c @@ -561,7 +561,8 @@ struct iap_event_descr { #define IAP_F_IB (1 << 7) /* CPU: Ivy Bridge */ #define IAP_F_SBX (1 << 8) /* CPU: Sandy Bridge Xeon */ #define IAP_F_IBX (1 << 9) /* CPU: Ivy Bridge */ -#define IAP_F_FM (1 << 10) /* Fixed mask */ +#define IAP_F_HW (1 << 10) /* CPU: Haswell */ +#define IAP_F_FM (1 << 11) /* Fixed mask */ #define IAP_F_ALLCPUSCORE2 \ (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA) @@ -604,7 +605,7 @@ static struct iap_event_descr iap_events[] = { IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_SBX), IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | IAP_F_SBX), @@ -620,9 +621,9 @@ static struct iap_event_descr iap_events[] = { IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O), IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 | @@ -635,7 +636,8 @@ static struct iap_event_descr iap_events[] = { IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | - IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | + IAP_F_HW), IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA), @@ -643,21 +645,23 @@ static struct iap_event_descr iap_events[] = { IAP_F_SBX), IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX), + IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW), IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX), + IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW), IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_WM | IAP_F_SB | IAP_F_SBX), + IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW), IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA), IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA), IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA), IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA), + IAPDESCR(08H_0EH, 0x08, 0x0E, IAP_F_FM | IAP_F_HW), IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | - IAP_F_SBX), - IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), - IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7O), - IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7), + IAP_F_SBX | IAP_F_HW), + IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW), + IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW), + IAPDESCR(08H_60H, 0x08, 0x60, IAP_F_FM | IAP_F_HW), + IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_HW), IAPDESCR(08H_81H, 0x08, 0x81, IAP_F_FM | IAP_F_IB | IAP_F_IBX), IAPDESCR(08H_82H, 0x08, 0x82, IAP_F_FM | IAP_F_IB | IAP_F_IBX), IAPDESCR(08H_84H, 0x08, 0x84, IAP_F_FM | IAP_F_IB | IAP_F_IBX), @@ -676,15 +680,15 @@ static struct iap_event_descr iap_events[] = { IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2), IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA), - IAPDESCR(0DH_03H, 0x0D, 0x03, IAP_F_FM | IAP_F_SB | IAP_F_SBX), + IAPDESCR(0DH_03H, 0x0D, 0x03, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_HW), IAPDESCR(0DH_40H, 0x0D, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), - IAPDESCR(0EH_10H, 0x0E, 0x10, IAP_F_FM | IAP_F_IB | IAP_F_IBX), - IAPDESCR(0EH_20H, 0x0E, 0x20, IAP_F_FM | IAP_F_IB | IAP_F_IBX), - IAPDESCR(0EH_40H, 0x0E, 0x40, IAP_F_FM | IAP_F_IB | IAP_F_IBX), + IAPDESCR(0EH_10H, 0x0E, 0x10, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), + IAPDESCR(0EH_20H, 0x0E, 0x20, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), + IAPDESCR(0EH_40H, 0x0E, 0x40, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7), IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), @@ -775,16 +779,30 @@ static struct iap_event_descr iap_events[] = { IAP_F_SBX | IAP_F_IBX), IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAPDESCR(24H_21H, 0x24, 0x21, IAP_F_FM | IAP_F_HW), + IAPDESCR(24H_22H, 0x24, 0x22, IAP_F_FM | IAP_F_HW), + IAPDESCR(24H_24H, 0x24, 0x24, IAP_F_FM | IAP_F_HW), + IAPDESCR(24H_27H, 0x24, 0x27, IAP_F_FM | IAP_F_HW), IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAPDESCR(24H_41H, 0x24, 0x41, IAP_F_FM | IAP_F_HW), + IAPDESCR(24H_42H, 0x24, 0x42, IAP_F_FM | IAP_F_HW), + IAPDESCR(24H_44H, 0x24, 0x44, IAP_F_FM | IAP_F_HW), + IAPDESCR(24H_50H, 0x24, 0x50, IAP_F_FM | IAP_F_HW), IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAPDESCR(24H_E1H, 0x24, 0xE1, IAP_F_FM | IAP_F_HW), + IAPDESCR(24H_E2H, 0x24, 0xE2, IAP_F_FM | IAP_F_HW), + IAPDESCR(24H_E4H, 0x24, 0xE4, IAP_F_FM | IAP_F_HW), + IAPDESCR(24H_E7H, 0x24, 0xE7, IAP_F_FM | IAP_F_HW), IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM), - IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM), + IAPDESCR(24H_F8H, 0x24, 0xF8, IAP_F_FM | IAP_F_HW), + IAPDESCR(24H_3FH, 0x24, 0x3F, IAP_F_FM | IAP_F_HW), + IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW), IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUSCORE2), @@ -815,6 +833,7 @@ static struct iap_event_descr iap_events[] = { IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), + IAPDESCR(27H_50H, 0x27, 0x50, IAP_F_FM | IAP_F_HW), IAPDESCR(27H_80H, 0x27, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(27H_E0H, 0x27, 0xE0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), @@ -841,9 +860,9 @@ static struct iap_event_descr iap_events[] = { IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM), IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM), IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), @@ -856,9 +875,9 @@ static struct iap_event_descr iap_events[] = { IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | - IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | - IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O), @@ -900,21 +919,23 @@ static struct iap_event_descr iap_events[] = { IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(48H_01H, 0x48, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7O), IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), + IAPDESCR(49H_0EH, 0x49, 0x0E, IAP_F_FM | IAP_F_HW), IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), - IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7), - IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O), - IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), + IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_HW), + IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW), + IAPDESCR(49H_60H, 0x49, 0x60, IAP_F_FM | IAP_F_HW), + IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7 | IAP_F_HW), IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7O), @@ -924,9 +945,9 @@ static struct iap_event_descr iap_events[] = { IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(4CH_02H, 0x4C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O), @@ -943,7 +964,7 @@ static struct iap_event_descr iap_events[] = { IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM), IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX), IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | @@ -955,10 +976,10 @@ static struct iap_event_descr iap_events[] = { IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), - IAPDESCR(58H_01H, 0x58, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_IBX), - IAPDESCR(58H_02H, 0x58, 0x02, IAP_F_FM | IAP_F_IB | IAP_F_IBX), - IAPDESCR(58H_04H, 0x58, 0x04, IAP_F_FM | IAP_F_IB | IAP_F_IBX), - IAPDESCR(58H_08H, 0x58, 0x08, IAP_F_FM | IAP_F_IB | IAP_F_IBX), + IAPDESCR(58H_01H, 0x58, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), + IAPDESCR(58H_02H, 0x58, 0x02, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), + IAPDESCR(58H_04H, 0x58, 0x04, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), + IAPDESCR(58H_08H, 0x58, 0x08, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), IAPDESCR(59H_20H, 0x59, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_SBX), IAPDESCR(59H_40H, 0x59, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), @@ -970,25 +991,25 @@ static struct iap_event_descr iap_events[] = { IAPDESCR(5BH_4FH, 0x5B, 0x4F, IAP_F_FM | IAP_F_SB | IAP_F_SBX), IAPDESCR(5CH_01H, 0x5C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(5CH_02H, 0x5C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(5EH_01H, 0x5E, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(5FH_01H, 0x5F, 0x01, IAP_F_FM | IAP_F_IB), IAPDESCR(5FH_04H, 0x5F, 0x04, IAP_F_IBX), IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB | - IAP_F_IBX), + IAP_F_IBX | IAP_F_HW), IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC), @@ -1000,9 +1021,9 @@ static struct iap_event_descr iap_events[] = { IAP_F_CA | IAP_F_CC2), IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC), IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC), @@ -1044,20 +1065,20 @@ static struct iap_event_descr iap_events[] = { IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2), IAPDESCR(79H_02H, 0x79, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(79H_04H, 0x79, 0x04, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(79H_08H, 0x79, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(79H_10H, 0x79, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(79H_20H, 0x79, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(79H_30H, 0x79, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), - IAPDESCR(79H_18H, 0x79, 0x18, IAP_F_FM | IAP_F_IB | IAP_F_IBX), - IAPDESCR(79H_24H, 0x79, 0x24, IAP_F_FM | IAP_F_IB | IAP_F_IBX), - IAPDESCR(79H_3CH, 0x79, 0x3C, IAP_F_FM | IAP_F_IB | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), + IAPDESCR(79H_18H, 0x79, 0x18, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), + IAPDESCR(79H_24H, 0x79, 0x24, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), + IAPDESCR(79H_3CH, 0x79, 0x3C, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), @@ -1073,7 +1094,7 @@ static struct iap_event_descr iap_events[] = { IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 | - IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), @@ -1094,72 +1115,74 @@ static struct iap_event_descr iap_events[] = { IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), + IAPDESCR(85H_0EH, 0x85, 0x0E, IAP_F_FM | IAP_F_HW), IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), - IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O), - IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), + IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O | IAP_F_HW), + IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW), + IAPDESCR(85H_60H, 0x85, 0x60, IAP_F_FM | IAP_F_HW), IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O), IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(88H_80H, 0x88, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(88H_FFH, 0x88, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(89H_80H, 0x89, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(89H_FFH, 0x89, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), @@ -1175,44 +1198,44 @@ static struct iap_event_descr iap_events[] = { IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(9CH_01H, 0x9C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(A1H_30H, 0xA1, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(A1H_40H, 0xA1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(A1H_80H, 0xA1, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX), IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX), IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | @@ -1220,10 +1243,11 @@ static struct iap_event_descr iap_events[] = { IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX), - IAPDESCR(A3H_01H, 0xA3, 0x01, IAP_F_FM | IAP_F_SBX | IAP_F_IBX), - IAPDESCR(A3H_02H, 0xA3, 0x02, IAP_F_FM | IAP_F_SBX | IAP_F_IBX), + IAPDESCR(A3H_01H, 0xA3, 0x01, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), + IAPDESCR(A3H_02H, 0xA3, 0x02, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(A3H_04H, 0xA3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX), - IAPDESCR(A3H_08H, 0xA3, 0x08, IAP_F_IBX), + IAPDESCR(A3H_05H, 0xA3, 0x05, IAP_F_FM | IAP_F_HW), + IAPDESCR(A3H_08H, 0xA3, 0x08, IAP_F_FM | IAP_F_IBX | IAP_F_HW), IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), @@ -1245,17 +1269,17 @@ static struct iap_event_descr iap_events[] = { IAPDESCR(ACH_0AH, 0xAC, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX), IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB | - IAP_F_IBX), + IAP_F_IBX | IAP_F_HW), IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O), IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O), IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), @@ -1265,7 +1289,7 @@ static struct iap_event_descr iap_events[] = { IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(B1H_02H, 0xB1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), @@ -1302,7 +1326,7 @@ static struct iap_event_descr iap_events[] = { IAPDESCR(B6H_01H, 0xB6, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_SBX), IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), @@ -1312,20 +1336,29 @@ static struct iap_event_descr iap_events[] = { IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O), IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), + + IAPDESCR(BCH_11H, 0xBC, 0x11, IAP_F_FM | IAP_F_HW), + IAPDESCR(BCH_12H, 0xBC, 0x12, IAP_F_FM | IAP_F_HW), + IAPDESCR(BCH_14H, 0xBC, 0x14, IAP_F_FM | IAP_F_HW), + IAPDESCR(BCH_18H, 0xBC, 0x18, IAP_F_FM | IAP_F_HW), + IAPDESCR(BCH_21H, 0xBC, 0x21, IAP_F_FM | IAP_F_HW), + IAPDESCR(BCH_22H, 0xBC, 0x22, IAP_F_FM | IAP_F_HW), + IAPDESCR(BCH_24H, 0xBC, 0x24, IAP_F_FM | IAP_F_HW), + IAPDESCR(BCH_28H, 0xBC, 0x28, IAP_F_FM | IAP_F_HW), IAPDESCR(BDH_01H, 0xBD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(BDH_20H, 0xBD, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(BFH_05H, 0xBF, 0x05, IAP_F_FM | IAP_F_SB | IAP_F_SBX), IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | - IAP_F_IBX), + IAP_F_IBX | IAP_F_HW), IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB), IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | @@ -1336,20 +1369,21 @@ static struct iap_event_descr iap_events[] = { IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(C1H_02H, 0xC1, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), IAPDESCR(C1H_08H, 0xC1, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(C1H_10H, 0xC1, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(C1H_20H, 0xC1, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAPDESCR(C1H_40H, 0xC1, 0x40, IAP_F_FM | IAP_F_HW), IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | - IAP_F_IBX), + IAP_F_IBX | IAP_F_HW), IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | - IAP_F_IBX), + IAP_F_IBX | IAP_F_HW), IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2), @@ -1361,46 +1395,46 @@ static struct iap_event_descr iap_events[] = { IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | - IAP_F_IBX), + IAP_F_IBX | IAP_F_HW), IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O), IAPDESCR(C3H_20H, 0xC3, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | - IAP_F_IBX), + IAP_F_IBX | IAP_F_HW), IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | - IAP_F_IBX), + IAP_F_IBX | IAP_F_HW), IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | - IAP_F_IBX), + IAP_F_IBX | IAP_F_HW), IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | - IAP_F_IBX), + IAP_F_IBX | IAP_F_HW), IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA), IAPDESCR(C4H_10H, 0xC4, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(C4H_20H, 0xC4, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(C4H_40H, 0xC4, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | - IAP_F_IBX), + IAP_F_IBX | IAP_F_HW), IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | - IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | - IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(C5H_10H, 0xC5, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(C5H_20H, 0xC5, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | @@ -1431,15 +1465,15 @@ static struct iap_event_descr iap_events[] = { IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(CAH_10H, 0xCA, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(CAH_1EH, 0xCA, 0x1E, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), @@ -1461,11 +1495,11 @@ static struct iap_event_descr iap_events[] = { IAP_F_I7 | IAP_F_WM), IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(CCH_20H, 0xCC, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(CDH_01H, 0xCD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(CDH_02H, 0xCD, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), @@ -1474,43 +1508,44 @@ static struct iap_event_descr iap_events[] = { IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(D0H_02H, 0xD0, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(D0H_10H, 0xD0, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(D0H_20H, 0xD0, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(D0H_40H, 0xD0, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(D0H_80H, 0xD0, 0X80, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | - IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), + IAPDESCR(D1H_10H, 0xD1, 0x10, IAP_F_HW), IAPDESCR(D1H_20H, 0xD1, 0x20, IAP_F_FM | IAP_F_SBX | IAP_F_IBX), IAPDESCR(D1H_40H, 0xD1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_IBX), + IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_IBX | IAP_F_HW), IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_IBX), + IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_IBX | IAP_F_HW), IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_IBX), + IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_IBX | IAP_F_HW), IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | - IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_IBX), + IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_IBX | IAP_F_HW), IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E), IAPDESCR(D3H_01H, 0xD3, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_SBX | - IAP_F_IBX), + IAP_F_IBX | IAP_F_HW), IAPDESCR(D3H_04H, 0xD3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX), IAPDESCR(D3H_10H, 0xD3, 0x10, IAP_F_IBX), IAPDESCR(D3H_20H, 0xD3, 0x20, IAP_F_IBX), @@ -1572,7 +1607,7 @@ static struct iap_event_descr iap_events[] = { IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM | IAP_F_SBX), IAPDESCR(E6H_02H, 0xE6, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), - IAPDESCR(E6H_1FH, 0xE6, 0x1F, IAP_F_IBX), + IAPDESCR(E6H_1FH, 0xE6, 0x1F, IAP_F_FM | IAP_F_IBX | IAP_F_HW), IAPDESCR(E8H_01H, 0xE8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(E8H_02H, 0xE8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), @@ -1582,30 +1617,30 @@ static struct iap_event_descr iap_events[] = { IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(F1H_01H, 0xF1, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | - IAP_F_SBX | IAP_F_IBX), + IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), @@ -1613,6 +1648,8 @@ static struct iap_event_descr iap_events[] = { IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), + IAPDESCR(F2H_05H, 0xF2, 0x05, IAP_F_FM | IAP_F_HW), + IAPDESCR(F2H_06H, 0xF2, 0x06, IAP_F_FM | IAP_F_HW), IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(F2H_0AH, 0xF2, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX | @@ -1915,6 +1952,7 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm, case PMC_CPU_INTEL_SANDYBRIDGE_XEON: case PMC_CPU_INTEL_IVYBRIDGE: case PMC_CPU_INTEL_IVYBRIDGE_XEON: + case PMC_CPU_INTEL_HASWELL: if (iap_event_sb_sbx_ib_ibx_ok_on_counter(ev, ri) == 0) return (EINVAL); break; @@ -1949,6 +1987,9 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm, case PMC_CPU_INTEL_COREI7: cpuflag = IAP_F_I7; break; + case PMC_CPU_INTEL_HASWELL: + cpuflag = IAP_F_HW; + break; case PMC_CPU_INTEL_IVYBRIDGE: cpuflag = IAP_F_IB; break; diff --git a/sys/dev/hwpmc/hwpmc_intel.c b/sys/dev/hwpmc/hwpmc_intel.c index 00ec29e..ab928fb 100644 --- a/sys/dev/hwpmc/hwpmc_intel.c +++ b/sys/dev/hwpmc/hwpmc_intel.c @@ -158,6 +158,10 @@ pmc_intel_initialize(void) cputype = PMC_CPU_INTEL_IVYBRIDGE_XEON; nclasses = 3; break; + case 0x3C: /* Per Intel document 325462-045US 01/2013. */ + cputype = PMC_CPU_INTEL_HASWELL; + nclasses = 5; + break; } break; #if defined(__i386__) || defined(__amd64__) @@ -201,6 +205,7 @@ pmc_intel_initialize(void) case PMC_CPU_INTEL_WESTMERE: case PMC_CPU_INTEL_SANDYBRIDGE_XEON: case PMC_CPU_INTEL_IVYBRIDGE_XEON: + case PMC_CPU_INTEL_HASWELL: error = pmc_core_initialize(pmc_mdep, ncpus); break; @@ -251,6 +256,7 @@ pmc_intel_initialize(void) * Intel Corei7 and Westmere processors. */ case PMC_CPU_INTEL_COREI7: + case PMC_CPU_INTEL_HASWELL: case PMC_CPU_INTEL_SANDYBRIDGE: case PMC_CPU_INTEL_WESTMERE: error = pmc_uncore_initialize(pmc_mdep, ncpus); @@ -281,6 +287,7 @@ pmc_intel_finalize(struct pmc_mdep *md) case PMC_CPU_INTEL_CORE2: case PMC_CPU_INTEL_CORE2EXTREME: case PMC_CPU_INTEL_COREI7: + case PMC_CPU_INTEL_HASWELL: case PMC_CPU_INTEL_IVYBRIDGE: case PMC_CPU_INTEL_SANDYBRIDGE: case PMC_CPU_INTEL_WESTMERE: @@ -315,6 +322,7 @@ pmc_intel_finalize(struct pmc_mdep *md) #if defined(__i386__) || defined(__amd64__) switch (md->pmd_cputype) { case PMC_CPU_INTEL_COREI7: + case PMC_CPU_INTEL_HASWELL: case PMC_CPU_INTEL_SANDYBRIDGE: case PMC_CPU_INTEL_WESTMERE: pmc_uncore_finalize(md); diff --git a/sys/dev/hwpmc/hwpmc_uncore.c b/sys/dev/hwpmc/hwpmc_uncore.c index 007aa6a..c6f0fcb 100644 --- a/sys/dev/hwpmc/hwpmc_uncore.c +++ b/sys/dev/hwpmc/hwpmc_uncore.c @@ -51,10 +51,12 @@ __FBSDID("$FreeBSD$"); PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) #define SELECTSEL(x) \ - (((x) == PMC_CPU_INTEL_SANDYBRIDGE) ? UCP_CB0_EVSEL0 : UCP_EVSEL0) + (((x) == PMC_CPU_INTEL_SANDYBRIDGE || (x) == PMC_CPU_INTEL_HASWELL) ? \ + UCP_CB0_EVSEL0 : UCP_EVSEL0) #define SELECTOFF(x) \ - (((x) == PMC_CPU_INTEL_SANDYBRIDGE) ? UCF_OFFSET_SB : UCF_OFFSET) + (((x) == PMC_CPU_INTEL_SANDYBRIDGE || (x) == PMC_CPU_INTEL_HASWELL) ? \ + UCF_OFFSET_SB : UCF_OFFSET) static enum pmc_cputype uncore_cputype; @@ -469,7 +471,8 @@ struct ucp_event_descr { #define UCP_F_I7 (1 << 0) /* CPU: Core i7 */ #define UCP_F_WM (1 << 1) /* CPU: Westmere */ #define UCP_F_SB (1 << 2) /* CPU: Sandy Bridge */ -#define UCP_F_FM (1 << 3) /* Fixed mask */ +#define UCP_F_HW (1 << 3) /* CPU: Haswell */ +#define UCP_F_FM (1 << 4) /* Fixed mask */ #define UCP_F_ALLCPUS \ (UCP_F_I7 | UCP_F_WM) @@ -573,15 +576,16 @@ static struct ucp_event_descr ucp_events[] = { UCPDESCR(21H_04H, 0x21, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), UCPDESCR(22H_01H, 0x22, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM | - UCP_F_SB), + UCP_F_SB | UCP_F_HW), UCPDESCR(22H_02H, 0x22, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM | - UCP_F_SB), + UCP_F_SB | UCP_F_HW), UCPDESCR(22H_04H, 0x22, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM | - UCP_F_SB), - UCPDESCR(22H_08H, 0x22, 0x08, UCP_F_FM | UCP_F_SB), - UCPDESCR(22H_20H, 0x22, 0x20, UCP_F_FM | UCP_F_SB), - UCPDESCR(22H_40H, 0x22, 0x40, UCP_F_FM | UCP_F_SB), - UCPDESCR(22H_80H, 0x22, 0x80, UCP_F_FM | UCP_F_SB), + UCP_F_SB | UCP_F_HW), + UCPDESCR(22H_08H, 0x22, 0x08, UCP_F_FM | UCP_F_SB | UCP_F_HW), + UCPDESCR(22H_10H, 0x22, 0x10, UCP_F_FM | UCP_F_HW), + UCPDESCR(22H_20H, 0x22, 0x20, UCP_F_FM | UCP_F_SB | UCP_F_HW), + UCPDESCR(22H_40H, 0x22, 0x40, UCP_F_FM | UCP_F_SB | UCP_F_HW), + UCPDESCR(22H_80H, 0x22, 0x80, UCP_F_FM | UCP_F_SB | UCP_F_HW), UCPDESCR(23H_01H, 0x23, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), UCPDESCR(23H_02H, 0x23, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), @@ -671,14 +675,19 @@ static struct ucp_event_descr ucp_events[] = { UCPDESCR(33H_04H, 0x33, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), UCPDESCR(33H_07H, 0x33, 0x07, UCP_F_FM | UCP_F_WM), - UCPDESCR(34H_01H, 0x34, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB), + UCPDESCR(34H_01H, 0x34, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB | + UCP_F_HW), UCPDESCR(34H_02H, 0x34, 0x02, UCP_F_FM | UCP_F_WM | UCP_F_SB), UCPDESCR(34H_04H, 0x34, 0x04, UCP_F_FM | UCP_F_WM | UCP_F_SB), - UCPDESCR(34H_08H, 0x34, 0x08, UCP_F_FM | UCP_F_WM | UCP_F_SB), - UCPDESCR(34H_10H, 0x34, 0x10, UCP_F_FM | UCP_F_WM | UCP_F_SB), - UCPDESCR(34H_20H, 0x34, 0x20, UCP_F_FM | UCP_F_WM | UCP_F_SB), - UCPDESCR(34H_40H, 0x34, 0x40, UCP_F_FM | UCP_F_SB), - UCPDESCR(34H_80H, 0x34, 0x80, UCP_F_FM | UCP_F_SB), + UCPDESCR(34H_06H, 0x34, 0x06, UCP_F_FM | UCP_F_HW), + UCPDESCR(34H_08H, 0x34, 0x08, UCP_F_FM | UCP_F_WM | UCP_F_SB | + UCP_F_HW), + UCPDESCR(34H_10H, 0x34, 0x10, UCP_F_FM | UCP_F_WM | UCP_F_SB | + UCP_F_HW), + UCPDESCR(34H_20H, 0x34, 0x20, UCP_F_FM | UCP_F_WM | UCP_F_SB | + UCP_F_HW), + UCPDESCR(34H_40H, 0x34, 0x40, UCP_F_FM | UCP_F_SB | UCP_F_HW), + UCPDESCR(34H_80H, 0x34, 0x80, UCP_F_FM | UCP_F_SB | UCP_F_HW), UCPDESCR(35H_01H, 0x35, 0x01, UCP_F_FM | UCP_F_WM), UCPDESCR(35H_02H, 0x35, 0x02, UCP_F_FM | UCP_F_WM), @@ -746,26 +755,30 @@ static struct ucp_event_descr ucp_events[] = { UCPDESCR(67H_01H, 0x67, 0x01, UCP_F_FM | UCP_F_WM), - UCPDESCR(80H_01H, 0x80, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB), + UCPDESCR(80H_01H, 0x80, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB | + UCP_F_HW), UCPDESCR(80H_02H, 0x80, 0x02, UCP_F_FM | UCP_F_WM), UCPDESCR(80H_04H, 0x80, 0x04, UCP_F_FM | UCP_F_WM), UCPDESCR(80H_08H, 0x80, 0x08, UCP_F_FM | UCP_F_WM), - UCPDESCR(81H_01H, 0x81, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB), + UCPDESCR(81H_01H, 0x81, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB | + UCP_F_HW), UCPDESCR(81H_02H, 0x81, 0x02, UCP_F_FM | UCP_F_WM), UCPDESCR(81H_04H, 0x81, 0x04, UCP_F_FM | UCP_F_WM), UCPDESCR(81H_08H, 0x81, 0x08, UCP_F_FM | UCP_F_WM), - UCPDESCR(81H_20H, 0x81, 0x20, UCP_F_FM | UCP_F_SB), - UCPDESCR(81H_80H, 0x81, 0x80, UCP_F_FM | UCP_F_SB), + UCPDESCR(81H_20H, 0x81, 0x20, UCP_F_FM | UCP_F_SB | UCP_F_HW), + UCPDESCR(81H_80H, 0x81, 0x80, UCP_F_FM | UCP_F_SB | UCP_F_HW), UCPDESCR(82H_01H, 0x82, 0x01, UCP_F_FM | UCP_F_WM), - UCPDESCR(83H_01H, 0x83, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB), + UCPDESCR(83H_01H, 0x83, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB | + UCP_F_HW), UCPDESCR(83H_02H, 0x83, 0x02, UCP_F_FM | UCP_F_WM), UCPDESCR(83H_04H, 0x83, 0x04, UCP_F_FM | UCP_F_WM), UCPDESCR(83H_08H, 0x83, 0x08, UCP_F_FM | UCP_F_WM), - UCPDESCR(84H_01H, 0x84, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB), + UCPDESCR(84H_01H, 0x84, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB | + UCP_F_HW), UCPDESCR(84H_02H, 0x84, 0x02, UCP_F_FM | UCP_F_WM), UCPDESCR(84H_04H, 0x84, 0x04, UCP_F_FM | UCP_F_WM), UCPDESCR(84H_08H, 0x84, 0x08, UCP_F_FM | UCP_F_WM), @@ -788,8 +801,11 @@ ucp_reload_count_to_perfctr_value(pmc_value_t rlc) return (1ULL << uncore_ucp_width) - rlc; } +/* + * Counter specific event information for Sandybridge and Haswell + */ static int -ucp_event_sandybridge_ok_on_counter(enum pmc_event pe, int ri) +ucp_event_sb_hw_ok_on_counter(enum pmc_event pe, int ri) { uint32_t mask; @@ -831,8 +847,9 @@ ucp_allocate_pmc(int cpu, int ri, struct pmc *pm, ev = pm->pm_event; switch (uncore_cputype) { + case PMC_CPU_INTEL_HASWELL: case PMC_CPU_INTEL_SANDYBRIDGE: - if (ucp_event_sandybridge_ok_on_counter(ev, ri) == 0) + if (ucp_event_sb_hw_ok_on_counter(ev, ri) == 0) return (EINVAL); break; default: @@ -849,6 +866,9 @@ ucp_allocate_pmc(int cpu, int ri, struct pmc *pm, case PMC_CPU_INTEL_COREI7: cpuflag = UCP_F_I7; break; + case PMC_CPU_INTEL_HASWELL: + cpuflag = UCP_F_HW; + break; case PMC_CPU_INTEL_SANDYBRIDGE: cpuflag = UCP_F_SB; break; diff --git a/sys/dev/hwpmc/pmc_events.h b/sys/dev/hwpmc/pmc_events.h index 8f246f6..e9d8586 100644 --- a/sys/dev/hwpmc/pmc_events.h +++ b/sys/dev/hwpmc/pmc_events.h @@ -506,9 +506,11 @@ __PMC_EV(IAP, EVENT_08H_06H) \ __PMC_EV(IAP, EVENT_08H_07H) \ __PMC_EV(IAP, EVENT_08H_08H) \ __PMC_EV(IAP, EVENT_08H_09H) \ +__PMC_EV(IAP, EVENT_08H_0EH) \ __PMC_EV(IAP, EVENT_08H_10H) \ __PMC_EV(IAP, EVENT_08H_20H) \ __PMC_EV(IAP, EVENT_08H_40H) \ +__PMC_EV(IAP, EVENT_08H_60H) \ __PMC_EV(IAP, EVENT_08H_80H) \ __PMC_EV(IAP, EVENT_08H_81H) \ __PMC_EV(IAP, EVENT_08H_82H) \ @@ -581,6 +583,14 @@ __PMC_EV(IAP, EVENT_1EH_01H) \ __PMC_EV(IAP, EVENT_20H_01H) \ __PMC_EV(IAP, EVENT_21H) \ __PMC_EV(IAP, EVENT_22H) \ +__PMC_EV(IAP, EVENT_22H_01H) \ +__PMC_EV(IAP, EVENT_22H_02H) \ +__PMC_EV(IAP, EVENT_22H_04H) \ +__PMC_EV(IAP, EVENT_22H_08H) \ +__PMC_EV(IAP, EVENT_22H_10H) \ +__PMC_EV(IAP, EVENT_22H_20H) \ +__PMC_EV(IAP, EVENT_22H_40H) \ +__PMC_EV(IAP, EVENT_22H_80H) \ __PMC_EV(IAP, EVENT_23H) \ __PMC_EV(IAP, EVENT_24H) \ __PMC_EV(IAP, EVENT_24H_01H) \ @@ -591,11 +601,26 @@ __PMC_EV(IAP, EVENT_24H_08H) \ __PMC_EV(IAP, EVENT_24H_0CH) \ __PMC_EV(IAP, EVENT_24H_10H) \ __PMC_EV(IAP, EVENT_24H_20H) \ +__PMC_EV(IAP, EVENT_24H_21H) \ +__PMC_EV(IAP, EVENT_24H_22H) \ +__PMC_EV(IAP, EVENT_24H_24H) \ +__PMC_EV(IAP, EVENT_24H_27H) \ __PMC_EV(IAP, EVENT_24H_30H) \ __PMC_EV(IAP, EVENT_24H_40H) \ +__PMC_EV(IAP, EVENT_24H_41H) \ +__PMC_EV(IAP, EVENT_24H_42H) \ +__PMC_EV(IAP, EVENT_24H_44H) \ +__PMC_EV(IAP, EVENT_24H_50H) \ __PMC_EV(IAP, EVENT_24H_80H) \ __PMC_EV(IAP, EVENT_24H_AAH) \ +__PMC_EV(IAP, EVENT_24H_3FH) \ +__PMC_EV(IAP, EVENT_24H_BFH) \ __PMC_EV(IAP, EVENT_24H_C0H) \ +__PMC_EV(IAP, EVENT_24H_E1H) \ +__PMC_EV(IAP, EVENT_24H_E2H) \ +__PMC_EV(IAP, EVENT_24H_E4H) \ +__PMC_EV(IAP, EVENT_24H_E7H) \ +__PMC_EV(IAP, EVENT_24H_F8H) \ __PMC_EV(IAP, EVENT_24H_FFH) \ __PMC_EV(IAP, EVENT_25H) \ __PMC_EV(IAP, EVENT_26H) \ @@ -620,6 +645,7 @@ __PMC_EV(IAP, EVENT_27H_0FH) \ __PMC_EV(IAP, EVENT_27H_10H) \ __PMC_EV(IAP, EVENT_27H_20H) \ __PMC_EV(IAP, EVENT_27H_40H) \ +__PMC_EV(IAP, EVENT_27H_50H) \ __PMC_EV(IAP, EVENT_27H_80H) \ __PMC_EV(IAP, EVENT_27H_E0H) \ __PMC_EV(IAP, EVENT_27H_F0H) \ @@ -676,12 +702,14 @@ __PMC_EV(IAP, EVENT_48H_00H) \ __PMC_EV(IAP, EVENT_48H_01H) \ __PMC_EV(IAP, EVENT_48H_02H) \ __PMC_EV(IAP, EVENT_49H_00H) \ +__PMC_EV(IAP, EVENT_49H_0EH) \ __PMC_EV(IAP, EVENT_49H_01H) \ __PMC_EV(IAP, EVENT_49H_02H) \ __PMC_EV(IAP, EVENT_49H_04H) \ __PMC_EV(IAP, EVENT_49H_10H) \ __PMC_EV(IAP, EVENT_49H_20H) \ __PMC_EV(IAP, EVENT_49H_40H) \ +__PMC_EV(IAP, EVENT_49H_60H) \ __PMC_EV(IAP, EVENT_49H_80H) \ __PMC_EV(IAP, EVENT_4BH_00H) \ __PMC_EV(IAP, EVENT_4BH_01H) \ @@ -788,9 +816,11 @@ __PMC_EV(IAP, EVENT_85H_00H) \ __PMC_EV(IAP, EVENT_85H_01H) \ __PMC_EV(IAP, EVENT_85H_02H) \ __PMC_EV(IAP, EVENT_85H_04H) \ +__PMC_EV(IAP, EVENT_85H_0EH) \ __PMC_EV(IAP, EVENT_85H_10H) \ __PMC_EV(IAP, EVENT_85H_20H) \ __PMC_EV(IAP, EVENT_85H_40H) \ +__PMC_EV(IAP, EVENT_85H_60H) \ __PMC_EV(IAP, EVENT_85H_80H) \ __PMC_EV(IAP, EVENT_86H_00H) \ __PMC_EV(IAP, EVENT_87H_00H) \ @@ -862,6 +892,7 @@ __PMC_EV(IAP, EVENT_A2H_80H) \ __PMC_EV(IAP, EVENT_A3H_01H) \ __PMC_EV(IAP, EVENT_A3H_02H) \ __PMC_EV(IAP, EVENT_A3H_04H) \ +__PMC_EV(IAP, EVENT_A3H_05H) \ __PMC_EV(IAP, EVENT_A3H_08H) \ __PMC_EV(IAP, EVENT_A6H_01H) \ __PMC_EV(IAP, EVENT_A7H_01H) \ @@ -920,6 +951,14 @@ __PMC_EV(IAP, EVENT_B8H_04H) \ __PMC_EV(IAP, EVENT_BAH_01H) \ __PMC_EV(IAP, EVENT_BAH_02H) \ __PMC_EV(IAP, EVENT_BBH_01H) \ +__PMC_EV(IAP, EVENT_BCH_11H) \ +__PMC_EV(IAP, EVENT_BCH_12H) \ +__PMC_EV(IAP, EVENT_BCH_14H) \ +__PMC_EV(IAP, EVENT_BCH_18H) \ +__PMC_EV(IAP, EVENT_BCH_21H) \ +__PMC_EV(IAP, EVENT_BCH_22H) \ +__PMC_EV(IAP, EVENT_BCH_24H) \ +__PMC_EV(IAP, EVENT_BCH_28H) \ __PMC_EV(IAP, EVENT_BDH_01H) \ __PMC_EV(IAP, EVENT_BDH_20H) \ __PMC_EV(IAP, EVENT_BFH_05H) \ @@ -934,6 +973,7 @@ __PMC_EV(IAP, EVENT_C1H_02H) \ __PMC_EV(IAP, EVENT_C1H_08H) \ __PMC_EV(IAP, EVENT_C1H_10H) \ __PMC_EV(IAP, EVENT_C1H_20H) \ +__PMC_EV(IAP, EVENT_C1H_40H) \ __PMC_EV(IAP, EVENT_C1H_FEH) \ __PMC_EV(IAP, EVENT_C2H_00H) \ __PMC_EV(IAP, EVENT_C2H_01H) \ @@ -1013,6 +1053,7 @@ __PMC_EV(IAP, EVENT_D1H_01H) \ __PMC_EV(IAP, EVENT_D1H_02H) \ __PMC_EV(IAP, EVENT_D1H_04H) \ __PMC_EV(IAP, EVENT_D1H_08H) \ +__PMC_EV(IAP, EVENT_D1H_10H) \ __PMC_EV(IAP, EVENT_D1H_20H) \ __PMC_EV(IAP, EVENT_D1H_40H) \ __PMC_EV(IAP, EVENT_D2H_01H) \ @@ -1086,6 +1127,8 @@ __PMC_EV(IAP, EVENT_F1H_07H) \ __PMC_EV(IAP, EVENT_F2H_01H) \ __PMC_EV(IAP, EVENT_F2H_02H) \ __PMC_EV(IAP, EVENT_F2H_04H) \ +__PMC_EV(IAP, EVENT_F2H_05H) \ +__PMC_EV(IAP, EVENT_F2H_06H) \ __PMC_EV(IAP, EVENT_F2H_08H) \ __PMC_EV(IAP, EVENT_F2H_0AH) \ __PMC_EV(IAP, EVENT_F2H_0FH) \ @@ -2403,6 +2446,210 @@ __PMC_EV_ALIAS("SIMD_INT_64.PACKED_LOGICAL", IAP_EVENT_FDH_10H) \ __PMC_EV_ALIAS("SIMD_INT_64.PACKED_ARITH", IAP_EVENT_FDH_20H) \ __PMC_EV_ALIAS("SIMD_INT_64.SHUFFLE_MOVE", IAP_EVENT_FDH_40H) +/* + * Aliases for Haswell core PMC events + */ +#define __PMC_EV_ALIAS_HASWELL() \ +__PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \ +__PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \ +__PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H) \ +__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \ +__PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_01H) \ +__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED_4K", IAP_EVENT_08H_02H) \ +__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4K", IAP_EVENT_08H_02H) \ +__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_0EH) \ +__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_DURATION", IAP_EVENT_08H_10H) \ +__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT_4K", IAP_EVENT_08H_20H) \ +__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT_2M", IAP_EVENT_08H_40H) \ +__PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_08H_60H) \ +__PMC_EV_ALIAS("DTLB_LOAD_MISSES.PDE_CACHE_MISS", IAP_EVENT_08H_80H) \ +__PMC_EV_ALIAS("INT_MISC.RECOVERY_CYCLES", IAP_EVENT_0DH_03H) \ +__PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \ +__PMC_EV_ALIAS("UOPS_ISSUED.FLAGS_MERGE", IAP_EVENT_0EH_10H) \ +__PMC_EV_ALIAS("UOPS_ISSUED.SLOW_LEA", IAP_EVENT_0EH_20H) \ +__PMC_EV_ALIAS("UOPS_ISSUED.SiNGLE_MUL", IAP_EVENT_0EH_40H) \ +__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_MISS", IAP_EVENT_24H_21H) \ +__PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_41H) \ +__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_E1H) \ +__PMC_EV_ALIAS("L2_RQSTS.RFO_HIT", IAP_EVENT_24H_42H) \ +__PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_22H) \ +__PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_E2H) \ +__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_HIT", IAP_EVENT_24H_44H) \ +__PMC_EV_ALIAS("L2_RQSTS.CODE_RD_MISS", IAP_EVENT_24H_24H) \ +__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_MISS", IAP_EVENT_24H_27H) \ +__PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_REFERENCES", IAP_EVENT_24H_E7H) \ +__PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_E4H) \ +__PMC_EV_ALIAS("L2_RQSTS.L2_PF_HIT", IAP_EVENT_24H_50H) \ +__PMC_EV_ALIAS("L2_RQSTS.L2_PF_MISS", IAP_EVENT_24H_30H) \ +__PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_F8H) \ +__PMC_EV_ALIAS("L2_RQSTS.MISS", IAP_EVENT_24H_3FH) \ +__PMC_EV_ALIAS("L2_RQSTS.REFERENCES", IAP_EVENT_24H_FFH) \ +__PMC_EV_ALIAS("L2_DEMAND_RQSTS.WB_HIT", IAP_EVENT_27H_50H) \ +__PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \ +__PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \ +__PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \ +__PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H) \ +__PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H) \ +__PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_49H_01H) \ +__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED_4K", IAP_EVENT_49H_02H) \ +__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", IAP_EVENT_49H_04H) \ +__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED", IAP_EVENT_49H_0EH) \ +__PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_DURATION", IAP_EVENT_49H_10H) \ +__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT_4K", IAP_EVENT_49H_20H) \ +__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT_2M", IAP_EVENT_49H_40H) \ +__PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT", IAP_EVENT_49H_60H) \ +__PMC_EV_ALIAS("DTLB_STORE_MISSES.PDE_CACHE_MISS", IAP_EVENT_49H_80H) \ +__PMC_EV_ALIAS("LOAD_HIT_PRE.SW_PF", IAP_EVENT_4CH_01H) \ +__PMC_EV_ALIAS("LOAD_HIT_PRE.HW_PF", IAP_EVENT_4CH_02H) \ +__PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H) \ +__PMC_EV_ALIAS("MOVE_ELIMINATION.INT_NOT_ELIMINATED", IAP_EVENT_58H_04H) \ +__PMC_EV_ALIAS("MOVE_ELIMINATION.SMID_NOT_ELIMINATED", IAP_EVENT_58H_08H) \ +__PMC_EV_ALIAS("MOVE_ELIMINATION.INT_ELIMINATED", IAP_EVENT_58H_01H) \ +__PMC_EV_ALIAS("MOVE_ELIMINATION.SMID_ELIMINATED", IAP_EVENT_58H_02H) \ +__PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_02H) \ +__PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_01H) \ +__PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \ +__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", IAP_EVENT_60H_01H) \ +__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CORE_RD", IAP_EVENT_60H_02H) \ +__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", IAP_EVENT_60H_04H) \ +__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", IAP_EVENT_60H_08H) \ +__PMC_EV_ALIAS("LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", IAP_EVENT_63H_01H) \ +__PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H) \ +__PMC_EV_ALIAS("IDQ.EMPTY", IAP_EVENT_79H_02H) \ +__PMC_EV_ALIAS("IDQ.MITE_UOPS", IAP_EVENT_79H_04H) \ +__PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H) \ +__PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H) \ +__PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H) \ +__PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H) \ +__PMC_EV_ALIAS("IDQ.ALL_DSB_CYCLES_ANY_UOPS", IAP_EVENT_79H_18H) \ +__PMC_EV_ALIAS("IDQ.ALL_DSB_CYCLES_4_UOPS", IAP_EVENT_79H_18H) \ +__PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_ANY_UOPS", IAP_EVENT_79H_24H) \ +__PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_4_UOPS", IAP_EVENT_79H_24H) \ +__PMC_EV_ALIAS("IDQ.MITE_ALL_UOPS", IAP_EVENT_79H_3CH) \ +__PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \ +__PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H) \ +__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED_4K", IAP_EVENT_85H_02H) \ +__PMC_EV_ALIAS("TLB_MISSES.WALK_COMPLETED_2M_4M", IAP_EVENT_85H_04H) \ +__PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_0EH) \ +__PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_10H) \ +__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT_4K", IAP_EVENT_85H_20H) \ +__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT_2M", IAP_EVENT_85H_40H) \ +__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_60H) \ +__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \ +__PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_02H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", IAP_EVENT_88H_04H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN", IAP_EVENT_88H_40H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_80H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.COND", IAP_EVENT_89H_01H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", IAP_EVENT_89H_04H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN", IAP_EVENT_89H_40H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_80H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \ +__PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \ +__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_0", IAP_EVENT_A1H_01H) \ +__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_1", IAP_EVENT_A1H_02H) \ +__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_2", IAP_EVENT_A1H_04H) \ +__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_3", IAP_EVENT_A1H_08H) \ +__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_4", IAP_EVENT_A1H_10H) \ +__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_5", IAP_EVENT_A1H_20H) \ +__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_6", IAP_EVENT_A1H_40H) \ +__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_7", IAP_EVENT_A1H_80H) \ +__PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \ +__PMC_EV_ALIAS("RESOURCE_STALLS.RS", IAP_EVENT_A2H_04H) \ +__PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H) \ +__PMC_EV_ALIAS("RESOURCE_STALLS.ROB", IAP_EVENT_A2H_10H) \ +__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L2_PENDING", IAP_EVENT_A3H_01H) \ +__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_LDM_PENDING", IAP_EVENT_A3H_02H) \ +__PMC_EV_ALIAS("CYCLE_ACTIVITY.STALLS_L2_PENDING", IAP_EVENT_A3H_05H) \ +__PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L1D_PENDING", IAP_EVENT_A3H_08H) \ +__PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H) \ +__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H) \ +__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_CODE_RD", IAP_EVENT_B0H_02H) \ +__PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H) \ +__PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H) \ +__PMC_EV_ALIAS("UOPS_EXECUTED.CORE", IAP_EVENT_B1H_02H) \ +__PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \ +__PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \ +__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L1", IAP_EVENT_BCH_11H) \ +__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L1", IAP_EVENT_BCH_21H) \ +__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L2", IAP_EVENT_BCH_12H) \ +__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L2", IAP_EVENT_BCH_22H) \ +__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L3", IAP_EVENT_BCH_14H) \ +__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L3", IAP_EVENT_BCH_24H) \ +__PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_MEMORY", IAP_EVENT_BCH_18H) \ +__PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_MEMORY", IAP_EVENT_BCH_28H) \ +__PMC_EV_ALIAS("TLB_FLUSH.DTLB_THREAD", IAP_EVENT_BDH_01H) \ +__PMC_EV_ALIAS("TLB_FLUSH.STLB_ANY", IAP_EVENT_BDH_20H) \ +__PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \ +__PMC_EV_ALIAS("INST_RETIRED.ALL", IAP_EVENT_C0H_01H) \ +__PMC_EV_ALIAS("OTHER_ASSISTS.AVX_TO_SSE", IAP_EVENT_C1H_08H) \ +__PMC_EV_ALIAS("OTHER_ASSISTS.SSE_TO_AVX", IAP_EVENT_C1H_10H) \ +__PMC_EV_ALIAS("OTHER_ASSISTS.ANY_WB_ASSIST", IAP_EVENT_C1H_40H) \ +__PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_01H) \ +__PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \ +__PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \ +__PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \ +__PMC_EV_ALIAS("MACHINE_CLEARS.MASKMOV", IAP_EVENT_C3H_20H) \ +__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_00H) \ +__PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \ +__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \ +__PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \ +__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H) \ +__PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H) \ +__PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H) \ +__PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H) \ +__PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \ +__PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \ +__PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_04H) \ +__PMC_EV_ALIAS("FP_ASSIST.X87_OUTPUT", IAP_EVENT_CAH_02H) \ +__PMC_EV_ALIAS("FP_ASSIST.X87_INPUT", IAP_EVENT_CAH_04H) \ +__PMC_EV_ALIAS("FP_ASSIST.SIMD_OUTPUT", IAP_EVENT_CAH_08H) \ +__PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H) \ +__PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \ +__PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \ +__PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \ +__PMC_EV_ALIAS("MEM_UOP_RETIRED.LOADS", IAP_EVENT_D0H_01H) \ +__PMC_EV_ALIAS("MEM_UOP_RETIRED.STORES", IAP_EVENT_D0H_02H) \ +__PMC_EV_ALIAS("MEM_UOP_RETIRED.STLB_MISS", IAP_EVENT_D0H_10H) \ +__PMC_EV_ALIAS("MEM_UOP_RETIRED.LOCK", IAP_EVENT_D0H_20H) \ +__PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT", IAP_EVENT_D0H_40H) \ +__PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL", IAP_EVENT_D0H_80H) \ +__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \ +__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \ +__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_HIT", IAP_EVENT_D1H_04H) \ +__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_MISS", IAP_EVENT_D1H_10H) \ +__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.HIT_LFB", IAP_EVENT_D1H_40H) \ +__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", IAP_EVENT_D2H_01H) \ +__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", IAP_EVENT_D2H_02H) \ +__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", IAP_EVENT_D2H_04H) \ +__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", IAP_EVENT_D2H_08H) \ +__PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", IAP_EVENT_D3H_01H) \ +__PMC_EV_ALIAS("BACLEARS.ANY", IAP_EVENT_E6H_1FH) \ +__PMC_EV_ALIAS("L2_TRANS.DEMAND_DATA_RD", IAP_EVENT_F0H_01H) \ +__PMC_EV_ALIAS("L2_TRANS.RFO", IAP_EVENT_F0H_02H) \ +__PMC_EV_ALIAS("L2_TRANS.CODE_RD", IAP_EVENT_F0H_04H) \ +__PMC_EV_ALIAS("L2_TRANS.ALL_PF", IAP_EVENT_F0H_08H) \ +__PMC_EV_ALIAS("L2_TRANS.L1D_WB", IAP_EVENT_F0H_10H) \ +__PMC_EV_ALIAS("L2_TRANS.L2_FILL", IAP_EVENT_F0H_20H) \ +__PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H) \ +__PMC_EV_ALIAS("L2_TRANS.ALL_REQUESTS", IAP_EVENT_F0H_80H) \ +__PMC_EV_ALIAS("L2_LINES_IN.I", IAP_EVENT_F1H_01H) \ +__PMC_EV_ALIAS("L2_LINES_IN.S", IAP_EVENT_F1H_02H) \ +__PMC_EV_ALIAS("L2_LINES_IN.E", IAP_EVENT_F1H_04H) \ +__PMC_EV_ALIAS("L2_LINES_IN.ALL", IAP_EVENT_F1H_07H) \ +__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_05H) \ +__PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_06H) + + #define __PMC_EV_ALIAS_IVYBRIDGE() \ __PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \ __PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \ @@ -3317,6 +3564,7 @@ __PMC_EV(UCP, EVENT_22H_01H) \ __PMC_EV(UCP, EVENT_22H_02H) \ __PMC_EV(UCP, EVENT_22H_04H) \ __PMC_EV(UCP, EVENT_22H_08H) \ +__PMC_EV(UCP, EVENT_22H_10H) \ __PMC_EV(UCP, EVENT_22H_20H) \ __PMC_EV(UCP, EVENT_22H_40H) \ __PMC_EV(UCP, EVENT_22H_80H) \ @@ -3394,6 +3642,7 @@ __PMC_EV(UCP, EVENT_33H_07H) \ __PMC_EV(UCP, EVENT_34H_01H) \ __PMC_EV(UCP, EVENT_34H_02H) \ __PMC_EV(UCP, EVENT_34H_04H) \ +__PMC_EV(UCP, EVENT_34H_06H) \ __PMC_EV(UCP, EVENT_34H_08H) \ __PMC_EV(UCP, EVENT_34H_10H) \ __PMC_EV(UCP, EVENT_34H_20H) \ @@ -3654,6 +3903,33 @@ __PMC_EV_ALIAS("DRAM_PRE_ALL.CH0", UCP_EVENT_66H_01H) \ __PMC_EV_ALIAS("DRAM_PRE_ALL.CH1", UCP_EVENT_66H_02H) \ __PMC_EV_ALIAS("DRAM_PRE_ALL.CH2", UCP_EVENT_66H_04H) +/* + * Aliases for Haswell uncore PMC events + */ +#define __PMC_EV_ALIAS_HASWELLUC() \ +__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.MISS", UCP_EVENT_22H_01H) \ +__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.INVAL", UCP_EVENT_22H_02H) \ +__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.HIT", UCP_EVENT_22H_04H) \ +__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.HITM", UCP_EVENT_22H_08H) \ +__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.INVAL_M", UCP_EVENT_22H_10H) \ +__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.EXTERNAL_FILTER", UCP_EVENT_22H_20H) \ +__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.XCORE_FILTER", UCP_EVENT_22H_40H) \ +__PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.EVICTION_FILTER", UCP_EVENT_22H_80H) \ +__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.M", UCP_EVENT_34H_01H) \ +__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.ES", UCP_EVENT_34H_06H) \ +__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.I", UCP_EVENT_34H_08H) \ +__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.READ_FILTER", UCP_EVENT_34H_10H) \ +__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.WRITE_FILTER", UCP_EVENT_34H_20H) \ +__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.EXTSNP_FILTER", UCP_EVENT_34H_40H) \ +__PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.ANY_REQUEST_FILTER", UCP_EVENT_34H_80H) \ +__PMC_EV_ALIAS("UNC_ARB_TRK_OCCUPANCY.ALL", UCP_EVENT_80H_01H) \ +__PMC_EV_ALIAS("UNC_ARB_TRK_REQUEST.ALL", UCP_EVENT_81H_01H) \ +__PMC_EV_ALIAS("UNC_ARB_TRK_REQUEST.WRITES", UCP_EVENT_81H_20H) \ +__PMC_EV_ALIAS("UNC_ARB_TRK_REQUEST.EVICTIONS", UCP_EVENT_81H_80H) \ +__PMC_EV_ALIAS("UNC_ARB_COH_TRK_OCCUPANCY.ALL", UCP_EVENT_83H_01H) \ +__PMC_EV_ALIAS("UNC_ARB_COH_TRK_REQUEST.ALL", UCP_EVENT_84H_01H) + + #define __PMC_EV_ALIAS_WESTMEREUC() \ __PMC_EV_ALIAS("GQ_CYCLES_FULL.READ_TRACKER", UCP_EVENT_00H_01H) \ __PMC_EV_ALIAS("GQ_CYCLES_FULL.WRITE_TRACKER", UCP_EVENT_00H_02H) \ diff --git a/sys/sys/pmc.h b/sys/sys/pmc.h index 2d7665a..e5a9c45 100644 --- a/sys/sys/pmc.h +++ b/sys/sys/pmc.h @@ -90,6 +90,7 @@ __PMC_CPU(INTEL_IVYBRIDGE, 0x8E, "Intel Ivy Bridge") \ __PMC_CPU(INTEL_SANDYBRIDGE_XEON, 0x8F, "Intel Sandy Bridge Xeon") \ __PMC_CPU(INTEL_IVYBRIDGE_XEON, 0x90, "Intel Ivy Bridge Xeon") \ + __PMC_CPU(INTEL_HASWELL, 0x91, "Intel Haswell") \ __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \ __PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \ __PMC_CPU(MIPS_OCTEON, 0x201, "Cavium Octeon") \ |
