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author | dim <dim@FreeBSD.org> | 2011-07-17 15:36:56 +0000 |
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committer | dim <dim@FreeBSD.org> | 2011-07-17 15:36:56 +0000 |
commit | 1176aa52646fe641a4243a246aa7f960c708a274 (patch) | |
tree | c8086addb211fa670a9d2b1038d8c2e453229755 /utils/TableGen/CodeGenTarget.cpp | |
parent | ece02cd5829cea836e9365b0845a8ef042d17b0a (diff) | |
download | FreeBSD-src-1176aa52646fe641a4243a246aa7f960c708a274.zip FreeBSD-src-1176aa52646fe641a4243a246aa7f960c708a274.tar.gz |
Vendor import of llvm trunk r135360:
http://llvm.org/svn/llvm-project/llvm/trunk@135360
Diffstat (limited to 'utils/TableGen/CodeGenTarget.cpp')
-rw-r--r-- | utils/TableGen/CodeGenTarget.cpp | 33 |
1 files changed, 13 insertions, 20 deletions
diff --git a/utils/TableGen/CodeGenTarget.cpp b/utils/TableGen/CodeGenTarget.cpp index a0c64ff..929791c 100644 --- a/utils/TableGen/CodeGenTarget.cpp +++ b/utils/TableGen/CodeGenTarget.cpp @@ -90,6 +90,7 @@ std::string llvm::getEnumName(MVT::SimpleValueType T) { case MVT::Metadata: return "MVT::Metadata"; case MVT::iPTR: return "MVT::iPTR"; case MVT::iPTRAny: return "MVT::iPTRAny"; + case MVT::untyped: return "MVT::untyped"; default: assert(0 && "ILLEGAL VALUE TYPE!"); return ""; } } @@ -163,40 +164,32 @@ CodeGenRegBank &CodeGenTarget::getRegBank() const { return *RegBank; } -void CodeGenTarget::ReadRegisterClasses() const { - std::vector<Record*> RegClasses = - Records.getAllDerivedDefinitions("RegisterClass"); - if (RegClasses.empty()) - throw std::string("No 'RegisterClass' subclasses defined!"); - - RegisterClasses.reserve(RegClasses.size()); - RegisterClasses.assign(RegClasses.begin(), RegClasses.end()); +void CodeGenTarget::ReadRegAltNameIndices() const { + RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex"); + std::sort(RegAltNameIndices.begin(), RegAltNameIndices.end(), LessRecord()); } /// getRegisterByName - If there is a register with the specific AsmName, /// return it. const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const { - const std::vector<CodeGenRegister> &Regs = getRegBank().getRegisters(); - for (unsigned i = 0, e = Regs.size(); i != e; ++i) { - const CodeGenRegister &Reg = Regs[i]; - if (Reg.TheDef->getValueAsString("AsmName") == Name) - return &Reg; - } + const std::vector<CodeGenRegister*> &Regs = getRegBank().getRegisters(); + for (unsigned i = 0, e = Regs.size(); i != e; ++i) + if (Regs[i]->TheDef->getValueAsString("AsmName") == Name) + return Regs[i]; return 0; } std::vector<MVT::SimpleValueType> CodeGenTarget:: getRegisterVTs(Record *R) const { + const CodeGenRegister *Reg = getRegBank().getReg(R); std::vector<MVT::SimpleValueType> Result; const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses(); for (unsigned i = 0, e = RCs.size(); i != e; ++i) { - const CodeGenRegisterClass &RC = RegisterClasses[i]; - for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) { - if (R == RC.Elements[ei]) { - const std::vector<MVT::SimpleValueType> &InVTs = RC.getValueTypes(); - Result.insert(Result.end(), InVTs.begin(), InVTs.end()); - } + const CodeGenRegisterClass &RC = RCs[i]; + if (RC.contains(Reg)) { + const std::vector<MVT::SimpleValueType> &InVTs = RC.getValueTypes(); + Result.insert(Result.end(), InVTs.begin(), InVTs.end()); } } |