- Add a new ioctl to /dev/pci to fetch details on an individual BAR of a

  device.  The details include the current value of the BAR (including all
  the flag bits and the current base address), its length, and whether or not
  it is enabled.  Since this operation is not invasive, non-root users are
  allowed to use it (unlike manual config register access which requires
  root).  The intention is that userland apps (such as Xorg) will use this
  interface rather than dangerously frobbing the BARs from userland to
  obtain this information.
- Add a new sub-mode to the 'list' mode of pciconf.  The -b flag when used
  with -l will now list all the active BARs for each device.

MFC after:	1 month

1 files changed, 27 insertions, 1 deletions

diff --git a/usr.sbin/pciconf/pciconf.8 b/usr.sbin/pciconf/pciconf.8
index 64d2f21..7492b5d 100644
--- a/usr.sbin/pciconf/pciconf.8
+++ b/usr.sbin/pciconf/pciconf.8
@@ -33,7 +33,7 @@
 .Nd diagnostic utility for the PCI bus
 .Sh SYNOPSIS
 .Nm
-.Fl l Op Fl cv
+.Fl l Op Fl bcv
 .Nm
 .Fl a Ar selector
 .Nm
@@ -112,6 +112,32 @@ device, which contains several (similar or independent) functions on
 one chip.
 .Pp
 If the
+.Fl b
+option is supplied,
+.Nm
+will list any base address registers
+.Pq BARs
+that are assigned resources for each device.
+Each BAR will be enumerated via a line in the following format:
+.Bd -literal
+    bar   [10] = type Memory, range 32, base 0xda060000, size 131072, enabled
+.Ed
+.Pp
+The first value after the
+.Dq Li bar
+prefix in the square brackets is the offset of the BAR in config space in
+hexadecimal.
+The type of a BAR is one of
+.Dq Memory ,
+.Dq Prefetchable Memory ,
+or
+.Dq I/O Port .
+The range indicates the maximum address the BAR decodes.
+The base and size indicate the start and length of the BAR's address window,
+respectively.
+Finally, the last flag indicates if the BAR is enabled or disabled.
+.Pp
+If the
 .Fl c
 option is supplied,
 .Nm