Revamp the x86 instruction emulation in bhyve.

On a nested page table fault the hypervisor will:
- fetch the instruction using the guest %rip and %cr3
- decode the instruction in 'struct vie'
- emulate the instruction in host kernel context for local apic accesses
- any other type of mmio access is punted up to user-space (e.g. ioapic)

The decoded instruction is passed as collateral to the user-space process
that is handling the PAGING exit.

The emulation code is fleshed out to include more addressing modes (e.g. SIB)
and more types of operands (e.g. imm8). The source code is unified into a
single file (vmm_instruction_emul.c) that is compiled into vmm.ko as well
as /usr/sbin/bhyve.

Reviewed by:	grehan
Obtained from:	NetApp

1 files changed, 1 insertions, 1 deletions

diff --git a/usr.sbin/bhyve/mem.h b/usr.sbin/bhyve/mem.h
index 53c4f72..b34c1fd 100644
--- a/usr.sbin/bhyve/mem.h
+++ b/usr.sbin/bhyve/mem.h
@@ -51,7 +51,7 @@ struct mem_range {
 
 void	init_mem(void);
 int     emulate_mem(struct vmctx *, int vcpu, uint64_t paddr, uint64_t rip,
-		    uint64_t cr3, int mode);
+		    uint64_t cr3, int mode, struct vie *vie);
 		    
 int	register_mem(struct mem_range *memp);