Update LLVM to r94309.

75 files changed, 837 insertions, 497 deletions

diff --git a/test/Analysis/PostDominators/pr6047_a.ll b/test/Analysis/PostDominators/pr6047_a.ll
new file mode 100644
index 0000000..ec1455b
--- /dev/null
+++ b/test/Analysis/PostDominators/pr6047_a.ll
@@ -0,0 +1,15 @@
+; RUN: opt < %s -postdomtree -analyze | FileCheck %s
+define internal void @f() {
+entry:
+  br i1 undef, label %bb35, label %bb3.i
+
+bb3.i:
+  br label %bb3.i
+
+bb35.loopexit3:
+  br label %bb35
+
+bb35:
+  ret void
+}
+; CHECK: [3] %entry
diff --git a/test/Analysis/PostDominators/pr6047_b.ll b/test/Analysis/PostDominators/pr6047_b.ll
new file mode 100644
index 0000000..7bd2c86
--- /dev/null
+++ b/test/Analysis/PostDominators/pr6047_b.ll
@@ -0,0 +1,19 @@
+; RUN: opt < %s -postdomtree -analyze | FileCheck %s
+define internal void @f() {
+entry:
+  br i1 undef, label %a, label %bb3.i
+
+a:
+  br i1 undef, label %bb35, label %bb3.i
+
+bb3.i:
+  br label %bb3.i
+
+
+bb35.loopexit3:
+  br label %bb35
+
+bb35:
+  ret void
+}
+; CHECK: [4] %entry
diff --git a/test/Analysis/PostDominators/pr6047_c.ll b/test/Analysis/PostDominators/pr6047_c.ll
new file mode 100644
index 0000000..08c9551
--- /dev/null
+++ b/test/Analysis/PostDominators/pr6047_c.ll
@@ -0,0 +1,147 @@
+; RUN: opt < %s -postdomtree -analyze | FileCheck %s
+define internal void @f() {
+entry:
+  br i1 undef, label %bb35, label %bb3.i
+
+bb3.i:
+  br label %bb3.i
+
+bb:
+  br label %bb35
+
+bb.i:
+  br label %bb35
+
+_float32_unpack.exit:
+  br label %bb35
+
+bb.i5:
+  br label %bb35
+
+_float32_unpack.exit8:
+  br label %bb35
+
+bb32.preheader:
+  br label %bb35
+
+bb3:
+  br label %bb35
+
+bb3.split.us:
+  br label %bb35
+
+bb.i4.us:
+  br label %bb35
+
+bb7.i.us:
+  br label %bb35
+
+bb.i4.us.backedge:
+  br label %bb35
+
+bb1.i.us:
+  br label %bb35
+
+bb6.i.us:
+  br label %bb35
+
+bb4.i.us:
+  br label %bb35
+
+bb8.i.us:
+  br label %bb35
+
+bb3.i.loopexit.us:
+  br label %bb35
+
+bb.nph21:
+  br label %bb35
+
+bb4:
+  br label %bb35
+
+bb5:
+  br label %bb35
+
+bb14.preheader:
+  br label %bb35
+
+bb.nph18:
+  br label %bb35
+
+bb8.us.preheader:
+  br label %bb35
+
+bb8.preheader:
+  br label %bb35
+
+bb8.us:
+  br label %bb35
+
+bb8:
+  br label %bb35
+
+bb15.loopexit:
+  br label %bb35
+
+bb15.loopexit2:
+  br label %bb35
+
+bb15:
+  br label %bb35
+
+bb16:
+  br label %bb35
+
+bb17.loopexit.split:
+  br label %bb35
+
+bb.nph14:
+  br label %bb35
+
+bb19:
+  br label %bb35
+
+bb20:
+  br label %bb35
+
+bb29.preheader:
+  br label %bb35
+
+bb.nph:
+  br label %bb35
+
+bb23.us.preheader:
+  br label %bb35
+
+bb23.preheader:
+  br label %bb35
+
+bb23.us:
+  br label %bb35
+
+bb23:
+  br label %bb35
+
+bb30.loopexit:
+  br label %bb35
+
+bb30.loopexit1:
+  br label %bb35
+
+bb30:
+  br label %bb35
+
+bb31:
+  br label %bb35
+
+bb35.loopexit:
+  br label %bb35
+
+bb35.loopexit3:
+  br label %bb35
+
+bb35:
+  ret void
+}
+; CHECK: [3] %entry
diff --git a/test/Analysis/PostDominators/pr6047_d.ll b/test/Analysis/PostDominators/pr6047_d.ll
new file mode 100644
index 0000000..4cfa880
--- /dev/null
+++ b/test/Analysis/PostDominators/pr6047_d.ll
@@ -0,0 +1,24 @@
+; RUN: opt < %s -postdomtree -analyze | FileCheck %s
+define internal void @f() {
+entry:
+  br i1 1, label %a, label %b
+
+a:
+br label %c
+
+b:
+br label %c
+
+c:
+  br i1 undef, label %bb35, label %bb3.i
+
+bb3.i:
+  br label %bb3.i
+
+bb35.loopexit3:
+  br label %bb35
+
+bb35:
+  ret void
+}
+; CHECK: [4] %entry
diff --git a/test/Assembler/functionlocal-metadata.ll b/test/Assembler/functionlocal-metadata.ll
index 8265aa1..16bc9d0 100644
--- a/test/Assembler/functionlocal-metadata.ll
+++ b/test/Assembler/functionlocal-metadata.ll
@@ -9,17 +9,24 @@ entry:
   call void @llvm.dbg.declare(metadata !{i32* %1}, metadata !{i32* %1})
 ; CHECK: metadata !{i32* %1}, metadata !{i32* %1}
   call void @llvm.dbg.declare(metadata !{i32 %two}, metadata !{i32 %0})
+; CHECK: metadata !{i32 %two}, metadata !{i32 %0}
   call void @llvm.dbg.declare(metadata !{i32 %0}, metadata !{i32* %1, i32 %0})
+; CHECK: metadata !{i32 %0}, metadata !{i32* %1, i32 %0}
   call void @llvm.dbg.declare(metadata !{i32* %1}, metadata !{i32 %b, i32 %0})
+; CHECK: metadata !{i32* %1}, metadata !{i32 %b, i32 %0}
   call void @llvm.dbg.declare(metadata !{i32 %a}, metadata !{i32 %a, metadata !"foo"})
-; CHECK: metadata !{i32 %a, metadata !"foo"}
+; CHECK: metadata !{i32 %a}, metadata !{i32 %a, metadata !"foo"}
   call void @llvm.dbg.declare(metadata !{i32 %b}, metadata !{metadata !0, i32 %two})
+; CHECK: metadata !{i32 %b}, metadata !{metadata !0, i32 %two}
 
   call void @llvm.dbg.value(metadata !{ i32 %a }, i64 0, metadata !1)
+; CHECK: metadata !{i32 %a}, i64 0, metadata !1
   call void @llvm.dbg.value(metadata !{ i32 %0 }, i64 25, metadata !0)
+; CHECK: metadata !{i32 %0}, i64 25, metadata !0
   call void @llvm.dbg.value(metadata !{ i32* %1 }, i64 16, metadata !"foo")
 ; CHECK: call void @llvm.dbg.value(metadata !{i32* %1}, i64 16, metadata !"foo")
   call void @llvm.dbg.value(metadata !"foo", i64 12, metadata !"bar")
+; CHECK: metadata !"foo", i64 12, metadata !"bar"
 
   ret void, !foo !0, !bar !1
 ; CHECK: ret void, !foo !0, !bar !1
diff --git a/test/CodeGen/ARM/ctz.ll b/test/CodeGen/ARM/ctz.ll
new file mode 100644
index 0000000..1d2ced3
--- /dev/null
+++ b/test/CodeGen/ARM/ctz.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=arm -mattr=+v6t2 | FileCheck %s
+
+declare i32 @llvm.cttz.i32(i32)
+
+define i32 @f1(i32 %a) {
+; CHECK: f1:
+; CHECK: rbit
+; CHECK: clz
+  %tmp = call i32 @llvm.cttz.i32( i32 %a )
+  ret i32 %tmp
+}
diff --git a/test/CodeGen/ARM/indirectbr.ll b/test/CodeGen/ARM/indirectbr.ll
index cd16084..5135d03 100644
--- a/test/CodeGen/ARM/indirectbr.ll
+++ b/test/CodeGen/ARM/indirectbr.ll
@@ -12,6 +12,10 @@ define internal arm_apcscc i32 @foo(i32 %i) nounwind {
 entry:
   %0 = load i8** @nextaddr, align 4               ; <i8*> [#uses=2]
   %1 = icmp eq i8* %0, null                       ; <i1> [#uses=1]
+; indirect branch gets duplicated here
+; ARM: bx
+; THUMB: mov pc, r1
+; THUMB2: mov pc, r1
   br i1 %1, label %bb3, label %bb2
 
 bb2:                                              ; preds = %entry, %bb3
diff --git a/test/CodeGen/ARM/vbits.ll b/test/CodeGen/ARM/vbits.ll
index e1d23a1..293d229 100644
--- a/test/CodeGen/ARM/vbits.ll
+++ b/test/CodeGen/ARM/vbits.ll
@@ -442,7 +442,7 @@ define <2 x i64> @v_ornQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 
 define <8 x i8> @vtsti8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK: vtsti8:
-;CHECK: vtst.i8
+;CHECK: vtst.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
 	%tmp3 = and <8 x i8> %tmp1, %tmp2
@@ -453,7 +453,7 @@ define <8 x i8> @vtsti8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 
 define <4 x i16> @vtsti16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ;CHECK: vtsti16:
-;CHECK: vtst.i16
+;CHECK: vtst.16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
 	%tmp3 = and <4 x i16> %tmp1, %tmp2
@@ -464,7 +464,7 @@ define <4 x i16> @vtsti16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 
 define <2 x i32> @vtsti32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ;CHECK: vtsti32:
-;CHECK: vtst.i32
+;CHECK: vtst.32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
 	%tmp3 = and <2 x i32> %tmp1, %tmp2
@@ -475,7 +475,7 @@ define <2 x i32> @vtsti32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 
 define <16 x i8> @vtstQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ;CHECK: vtstQi8:
-;CHECK: vtst.i8
+;CHECK: vtst.8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
 	%tmp3 = and <16 x i8> %tmp1, %tmp2
@@ -486,7 +486,7 @@ define <16 x i8> @vtstQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 
 define <8 x i16> @vtstQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ;CHECK: vtstQi16:
-;CHECK: vtst.i16
+;CHECK: vtst.16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
 	%tmp3 = and <8 x i16> %tmp1, %tmp2
@@ -497,7 +497,7 @@ define <8 x i16> @vtstQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 
 define <4 x i32> @vtstQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ;CHECK: vtstQi32:
-;CHECK: vtst.i32
+;CHECK: vtst.32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
 	%tmp3 = and <4 x i32> %tmp1, %tmp2
diff --git a/test/CodeGen/CellSPU/call_indirect.ll b/test/CodeGen/CellSPU/call_indirect.ll
index f25d6b5..08dad74 100644
--- a/test/CodeGen/CellSPU/call_indirect.ll
+++ b/test/CodeGen/CellSPU/call_indirect.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=cellspu > %t1.s
-; RUN: llc < %s -march=cellspu -mattr=large_mem > %t2.s
+; RUN: llc < %s -march=cellspu -asm-verbose=0 > %t1.s
+; RUN: llc < %s -march=cellspu -mattr=large_mem -asm-verbose=0 > %t2.s
 ; RUN: grep bisl    %t1.s | count 7
 ; RUN: grep ila     %t1.s | count 1
 ; RUN: grep rotqby  %t1.s | count 5
diff --git a/test/CodeGen/Generic/GC/frame_size.ll b/test/CodeGen/Generic/GC/frame_size.ll
deleted file mode 100644
index 31783cd..0000000
--- a/test/CodeGen/Generic/GC/frame_size.ll
+++ /dev/null
@@ -1,14 +0,0 @@
-; RUN: llc < %s -asm-verbose | grep {frame size} | grep -v 0x0
-
-declare void @llvm.gcroot(i8** %value, i8* %tag)
-declare void @g() gc "ocaml"
-
-define void @f(i8* %arg.0, void()* %arg.1) gc "ocaml" {
-entry:
-	%gcroot.0 = alloca i8*
-	call void @llvm.gcroot(i8** %gcroot.0, i8* null)
-	store i8* %arg.0, i8** %gcroot.0
-	call void @g()
-	call void %arg.1()
-	ret void
-}
diff --git a/test/CodeGen/MSP430/bit.ll b/test/CodeGen/MSP430/bit.ll
index 0dc2158..cd664a1 100644
--- a/test/CodeGen/MSP430/bit.ll
+++ b/test/CodeGen/MSP430/bit.ll
@@ -1,5 +1,4 @@
 ; RUN: llvm-as < %s | llc -march=msp430 | FileCheck %s
-; XFAIL: *
 target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:32"
 target triple = "msp430-generic-generic"
 
diff --git a/test/CodeGen/MSP430/setcc.ll b/test/CodeGen/MSP430/setcc.ll
index ecf0661..9db51cc 100644
--- a/test/CodeGen/MSP430/setcc.ll
+++ b/test/CodeGen/MSP430/setcc.ll
@@ -1,5 +1,4 @@
 ; RUN: llc -march=msp430 < %s | FileCheck %s
-; XFAIL: *
 target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:32"
 target triple = "msp430-generic-generic"
 
@@ -32,7 +31,7 @@ define i16 @sccwne(i16 %a, i16 %b) nounwind {
 	ret i16 %t2
 }
 ; CHECK:sccwne:
-; CHECK:	cmp.w	r15, r14
+; CHECK:	cmp.w	r14, r15
 ; CHECK-NEXT:	mov.w	r2, r15
 ; CHECK-NEXT:	rra.w	r15
 ; CHECK-NEXT:	and.w	#1, r15
@@ -43,7 +42,7 @@ define i16 @sccweq(i16 %a, i16 %b) nounwind {
 	ret i16 %t2
 }
 ; CHECK:sccweq:
-; CHECK:	cmp.w	r15, r14
+; CHECK:	cmp.w	r14, r15
 ; CHECK-NEXT:	mov.w	r2, r15
 ; CHECK-NEXT:	rra.w	r15
 ; CHECK-NEXT:	and.w	#1, r15
@@ -55,7 +54,7 @@ define i16 @sccwugt(i16 %a, i16 %b) nounwind {
 	ret i16 %t2
 }
 ; CHECK:sccwugt:
-; CHECK:	cmp.w	r14, r15
+; CHECK:	cmp.w	r15, r14
 ; CHECK-NEXT:	mov.w	r2, r15
 ; CHECK-NEXT:	and.w	#1, r15
 ; CHECK-NEXT:	xor.w	#1, r15
@@ -66,7 +65,7 @@ define i16 @sccwuge(i16 %a, i16 %b) nounwind {
 	ret i16 %t2
 }
 ; CHECK:sccwuge:
-; CHECK:	cmp.w	r15, r14
+; CHECK:	cmp.w	r14, r15
 ; CHECK-NEXT:	mov.w	r2, r15
 ; CHECK-NEXT:	and.w	#1, r15
 
@@ -76,7 +75,7 @@ define i16 @sccwult(i16 %a, i16 %b) nounwind {
 	ret i16 %t2
 }
 ; CHECK:sccwult:
-; CHECK:	cmp.w	r15, r14
+; CHECK:	cmp.w	r14, r15
 ; CHECK-NEXT:	mov.w	r2, r15
 ; CHECK-NEXT:	and.w	#1, r15
 ; CHECK-NEXT:	xor.w	#1, r15
@@ -87,7 +86,7 @@ define i16 @sccwule(i16 %a, i16 %b) nounwind {
 	ret i16 %t2
 }
 ; CHECK:sccwule:
-; CHECK:	cmp.w	r14, r15
+; CHECK:	cmp.w	r15, r14
 ; CHECK-NEXT:	mov.w	r2, r15
 ; CHECK-NEXT:	and.w	#1, r15
 
diff --git a/test/CodeGen/PIC16/globals.ll b/test/CodeGen/PIC16/globals.ll
index b8c9116..432c291 100644
--- a/test/CodeGen/PIC16/globals.ll
+++ b/test/CodeGen/PIC16/globals.ll
@@ -2,7 +2,8 @@
 
 @G1 = global i32 4712, section "Address=412"
 ; CHECK: @G1.412..user_section.#	IDATA	412
-; CHECK: @G1 dl 4712
+; CHECK: @G1
+; CHECK:     dl 4712
 
 @G2 = global i32 0, section "Address=412"
 ; CHECK: @G2.412..user_section.#	UDATA	412
@@ -10,6 +11,7 @@
 
 @G3 = addrspace(1) constant i32 4712, section "Address=412"
 ; CHECK: @G3.412..user_section.#	ROMDATA	412
-; CHECK: @G3 rom_dl 4712
+; CHECK: @G3
+; CHECK:     rom_dl 4712
 
 
diff --git a/test/CodeGen/PowerPC/2008-12-12-EH.ll b/test/CodeGen/PowerPC/2008-12-12-EH.ll
index b56c22a..2315e36 100644
--- a/test/CodeGen/PowerPC/2008-12-12-EH.ll
+++ b/test/CodeGen/PowerPC/2008-12-12-EH.ll
@@ -1,4 +1,3 @@
-; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | grep ^.L_Z1fv.eh
 ; RUN: llc < %s  -march=ppc32 -mtriple=powerpc-apple-darwin9 | grep ^__Z1fv.eh
 
 define void @_Z1fv() {
diff --git a/test/CodeGen/PowerPC/sections.ll b/test/CodeGen/PowerPC/sections.ll
index 1af3709..0ff4a89 100644
--- a/test/CodeGen/PowerPC/sections.ll
+++ b/test/CodeGen/PowerPC/sections.ll
@@ -4,5 +4,5 @@
 @A = global i32 0
 
 ; CHECK:  .section  .bss,"aw",@nobits
-; CHECK:  .global A
+; CHECK:  .globl A
 
diff --git a/test/CodeGen/PowerPC/stubs.ll b/test/CodeGen/PowerPC/stubs.ll
new file mode 100644
index 0000000..4889263
--- /dev/null
+++ b/test/CodeGen/PowerPC/stubs.ll
@@ -0,0 +1,22 @@
+; RUN: llc %s -o - -mtriple=powerpc-apple-darwin8 | FileCheck %s
+define ppc_fp128 @test1(i64 %X) nounwind readnone {
+entry:
+  %0 = sitofp i64 %X to ppc_fp128
+  ret ppc_fp128 %0
+}
+
+; CHECK: _test1:
+; CHECK: bl ___floatditf$stub
+; CHECK: 	.section	__TEXT,__symbol_stub1,symbol_stubs,pure_instructions,16
+; CHECK: ___floatditf$stub:
+; CHECK: 	.indirect_symbol ___floatditf
+; CHECK: 	lis r11,ha16(___floatditf$lazy_ptr)
+; CHECK: 	lwzu r12,lo16(___floatditf$lazy_ptr)(r11)
+; CHECK: 	mtctr r12
+; CHECK: 	bctr
+; CHECK: 	.section	__DATA,__la_symbol_ptr,lazy_symbol_pointers
+; CHECK: ___floatditf$lazy_ptr:
+; CHECK: 	.indirect_symbol ___floatditf
+; CHECK: 	.long dyld_stub_binding_helper
+
+
diff --git a/test/CodeGen/Thumb/2009-12-17-pre-regalloc-taildup.ll b/test/CodeGen/Thumb/2009-12-17-pre-regalloc-taildup.ll
index 3401915..2a5d9d6 100644
--- a/test/CodeGen/Thumb/2009-12-17-pre-regalloc-taildup.ll
+++ b/test/CodeGen/Thumb/2009-12-17-pre-regalloc-taildup.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O3 -pre-regalloc-taildup < %s | FileCheck %s
+; RUN: llc -O3 < %s | FileCheck %s
 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
 target triple = "thumbv7-apple-darwin10"
 
diff --git a/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll b/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll
new file mode 100644
index 0000000..d676369
--- /dev/null
+++ b/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -regalloc=local -relocation-model=pic | FileCheck %s
+
+target triple = "thumbv6-apple-darwin10"
+
+@fred = internal global i32 0              ; <i32*> [#uses=1]
+
+define arm_apcscc void @foo() nounwind {
+entry:
+; CHECK: str r0, [sp]
+  %0 = call arm_apcscc  i32 (...)* @bar() nounwind ; <i32> [#uses=1]
+; CHECK: blx _bar
+; CHECK: ldr r1, [sp]
+  store i32 %0, i32* @fred, align 4
+  br label %return
+
+return:                                           ; preds = %entry
+  ret void
+}
+
+declare arm_apcscc i32 @bar(...)
diff --git a/test/CodeGen/Thumb2/2010-01-06-TailDuplicateLabels.ll b/test/CodeGen/Thumb2/2010-01-06-TailDuplicateLabels.ll
index 6a05df1..07a3527 100644
--- a/test/CodeGen/Thumb2/2010-01-06-TailDuplicateLabels.ll
+++ b/test/CodeGen/Thumb2/2010-01-06-TailDuplicateLabels.ll
@@ -1,4 +1,4 @@
-; RUN: llc -relocation-model=pic -pre-regalloc-taildup < %s | grep {:$} | sort | uniq -d | count 0
+; RUN: llc -relocation-model=pic < %s | grep {:$} | sort | uniq -d | count 0
 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
 target triple = "thumbv7-apple-darwin10"
 
diff --git a/test/CodeGen/Thumb2/2010-01-19-RemovePredicates.ll b/test/CodeGen/Thumb2/2010-01-19-RemovePredicates.ll
new file mode 100644
index 0000000..41682c1
--- /dev/null
+++ b/test/CodeGen/Thumb2/2010-01-19-RemovePredicates.ll
@@ -0,0 +1,53 @@
+; RUN: llc -O3 -relocation-model=pic -mcpu=cortex-a8 -mattr=+thumb2 < %s
+;
+; This test creates a predicated t2ADDri instruction that is then turned into a t2MOVgpr2gpr instr.
+; Test that that the predicate operands are removed properly.
+;
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
+target triple = "thumbv7-apple-darwin10"
+
+declare arm_apcscc void @etoe53(i16* nocapture, i16* nocapture) nounwind
+
+define arm_apcscc void @earith(double* nocapture %value, i32 %icode, double* nocapture %r1, double* nocapture %r2) nounwind {
+entry:
+  %v = alloca [6 x i16], align 4                  ; <[6 x i16]*> [#uses=1]
+  br i1 undef, label %bb2.i, label %bb5
+
+bb2.i:                                            ; preds = %entry
+  %0 = bitcast double* %value to i16*             ; <i16*> [#uses=1]
+  call arm_apcscc  void @etoe53(i16* null, i16* %0) nounwind
+  ret void
+
+bb5:                                              ; preds = %entry
+  switch i32 %icode, label %bb10 [
+    i32 57, label %bb14
+    i32 58, label %bb18
+    i32 67, label %bb22
+    i32 76, label %bb26
+    i32 77, label %bb35
+  ]
+
+bb10:                                             ; preds = %bb5
+  br label %bb46
+
+bb14:                                             ; preds = %bb5
+  unreachable
+
+bb18:                                             ; preds = %bb5
+  unreachable
+
+bb22:                                             ; preds = %bb5
+  unreachable
+
+bb26:                                             ; preds = %bb5
+  br label %bb46
+
+bb35:                                             ; preds = %bb5
+  unreachable
+
+bb46:                                             ; preds = %bb26, %bb10
+  %1 = bitcast double* %value to i16*             ; <i16*> [#uses=1]
+  %v47 = getelementptr inbounds [6 x i16]* %v, i32 0, i32 0 ; <i16*> [#uses=1]
+  call arm_apcscc  void @etoe53(i16* %v47, i16* %1) nounwind
+  ret void
+}
diff --git a/test/CodeGen/X86/2007-08-13-SpillerReuse.ll b/test/CodeGen/X86/2007-08-13-SpillerReuse.ll
deleted file mode 100644
index d6ea510..0000000
--- a/test/CodeGen/X86/2007-08-13-SpillerReuse.ll
+++ /dev/null
@@ -1,102 +0,0 @@
-; RUN: llc < %s -mtriple=i686-apple-darwin | grep "48(%esp)" | count 5
-
-	%struct..0anon = type { i32 }
-	%struct.rtvec_def = type { i32, [1 x %struct..0anon] }
-	%struct.rtx_def = type { i16, i8, i8, [1 x %struct..0anon] }
-@rtx_format = external global [116 x i8*]		; <[116 x i8*]*> [#uses=1]
-@rtx_length = external global [117 x i32]		; <[117 x i32]*> [#uses=1]
-
-declare %struct.rtx_def* @fixup_memory_subreg(%struct.rtx_def*, %struct.rtx_def*, i32)
-
-define %struct.rtx_def* @walk_fixup_memory_subreg(%struct.rtx_def* %x, %struct.rtx_def* %insn) {
-entry:
-	%tmp2 = icmp eq %struct.rtx_def* %x, null		; <i1> [#uses=1]
-	br i1 %tmp2, label %UnifiedReturnBlock, label %cond_next
-
-cond_next:		; preds = %entry
-	%tmp6 = getelementptr %struct.rtx_def* %x, i32 0, i32 0		; <i16*> [#uses=1]
-	%tmp7 = load i16* %tmp6		; <i16> [#uses=2]
-	%tmp78 = zext i16 %tmp7 to i32		; <i32> [#uses=2]
-	%tmp10 = icmp eq i16 %tmp7, 54		; <i1> [#uses=1]
-	br i1 %tmp10, label %cond_true13, label %cond_next32
-
-cond_true13:		; preds = %cond_next
-	%tmp15 = getelementptr %struct.rtx_def* %x, i32 0, i32 3		; <[1 x %struct..0anon]*> [#uses=1]
-	%tmp1718 = bitcast [1 x %struct..0anon]* %tmp15 to %struct.rtx_def**		; <%struct.rtx_def**> [#uses=1]
-	%tmp19 = load %struct.rtx_def** %tmp1718		; <%struct.rtx_def*> [#uses=1]
-	%tmp20 = getelementptr %struct.rtx_def* %tmp19, i32 0, i32 0		; <i16*> [#uses=1]
-	%tmp21 = load i16* %tmp20		; <i16> [#uses=1]
-	%tmp22 = icmp eq i16 %tmp21, 57		; <i1> [#uses=1]
-	br i1 %tmp22, label %cond_true25, label %cond_next32
-
-cond_true25:		; preds = %cond_true13
-	%tmp29 = tail call %struct.rtx_def* @fixup_memory_subreg( %struct.rtx_def* %x, %struct.rtx_def* %insn, i32 1 )		; <%struct.rtx_def*> [#uses=1]
-	ret %struct.rtx_def* %tmp29
-
-cond_next32:		; preds = %cond_true13, %cond_next
-	%tmp34 = getelementptr [116 x i8*]* @rtx_format, i32 0, i32 %tmp78		; <i8**> [#uses=1]
-	%tmp35 = load i8** %tmp34, align 4		; <i8*> [#uses=1]
-	%tmp37 = getelementptr [117 x i32]* @rtx_length, i32 0, i32 %tmp78		; <i32*> [#uses=1]
-	%tmp38 = load i32* %tmp37, align 4		; <i32> [#uses=1]
-	%i.011 = add i32 %tmp38, -1		; <i32> [#uses=2]
-	%tmp12513 = icmp sgt i32 %i.011, -1		; <i1> [#uses=1]
-	br i1 %tmp12513, label %bb, label %UnifiedReturnBlock
-
-bb:		; preds = %bb123, %cond_next32
-	%indvar = phi i32 [ %indvar.next26, %bb123 ], [ 0, %cond_next32 ]		; <i32> [#uses=2]
-	%i.01.0 = sub i32 %i.011, %indvar		; <i32> [#uses=5]
-	%tmp42 = getelementptr i8* %tmp35, i32 %i.01.0		; <i8*> [#uses=2]
-	%tmp43 = load i8* %tmp42		; <i8> [#uses=1]
-	switch i8 %tmp43, label %bb123 [
-		 i8 101, label %cond_true47
-		 i8 69, label %bb105.preheader
-	]
-
-cond_true47:		; preds = %bb
-	%tmp52 = getelementptr %struct.rtx_def* %x, i32 0, i32 3, i32 %i.01.0		; <%struct..0anon*> [#uses=1]
-	%tmp5354 = bitcast %struct..0anon* %tmp52 to %struct.rtx_def**		; <%struct.rtx_def**> [#uses=1]
-	%tmp55 = load %struct.rtx_def** %tmp5354		; <%struct.rtx_def*> [#uses=1]
-	%tmp58 = tail call  %struct.rtx_def* @walk_fixup_memory_subreg( %struct.rtx_def* %tmp55, %struct.rtx_def* %insn )		; <%struct.rtx_def*> [#uses=1]
-	%tmp62 = getelementptr %struct.rtx_def* %x, i32 0, i32 3, i32 %i.01.0, i32 0		; <i32*> [#uses=1]
-	%tmp58.c = ptrtoint %struct.rtx_def* %tmp58 to i32		; <i32> [#uses=1]
-	store i32 %tmp58.c, i32* %tmp62
-	%tmp6816 = load i8* %tmp42		; <i8> [#uses=1]
-	%tmp6917 = icmp eq i8 %tmp6816, 69		; <i1> [#uses=1]
-	br i1 %tmp6917, label %bb105.preheader, label %bb123
-
-bb105.preheader:		; preds = %cond_true47, %bb
-	%tmp11020 = getelementptr %struct.rtx_def* %x, i32 0, i32 3, i32 %i.01.0		; <%struct..0anon*> [#uses=1]
-	%tmp11111221 = bitcast %struct..0anon* %tmp11020 to %struct.rtvec_def**		; <%struct.rtvec_def**> [#uses=3]
-	%tmp11322 = load %struct.rtvec_def** %tmp11111221		; <%struct.rtvec_def*> [#uses=1]
-	%tmp11423 = getelementptr %struct.rtvec_def* %tmp11322, i32 0, i32 0		; <i32*> [#uses=1]
-	%tmp11524 = load i32* %tmp11423		; <i32> [#uses=1]
-	%tmp11625 = icmp eq i32 %tmp11524, 0		; <i1> [#uses=1]
-	br i1 %tmp11625, label %bb123, label %bb73
-
-bb73:		; preds = %bb73, %bb105.preheader
-	%j.019 = phi i32 [ %tmp104, %bb73 ], [ 0, %bb105.preheader ]		; <i32> [#uses=3]
-	%tmp81 = load %struct.rtvec_def** %tmp11111221		; <%struct.rtvec_def*> [#uses=2]
-	%tmp92 = getelementptr %struct.rtvec_def* %tmp81, i32 0, i32 1, i32 %j.019		; <%struct..0anon*> [#uses=1]
-	%tmp9394 = bitcast %struct..0anon* %tmp92 to %struct.rtx_def**		; <%struct.rtx_def**> [#uses=1]
-	%tmp95 = load %struct.rtx_def** %tmp9394		; <%struct.rtx_def*> [#uses=1]
-	%tmp98 = tail call  %struct.rtx_def* @walk_fixup_memory_subreg( %struct.rtx_def* %tmp95, %struct.rtx_def* %insn )		; <%struct.rtx_def*> [#uses=1]
-	%tmp101 = getelementptr %struct.rtvec_def* %tmp81, i32 0, i32 1, i32 %j.019, i32 0		; <i32*> [#uses=1]
-	%tmp98.c = ptrtoint %struct.rtx_def* %tmp98 to i32		; <i32> [#uses=1]
-	store i32 %tmp98.c, i32* %tmp101
-	%tmp104 = add i32 %j.019, 1		; <i32> [#uses=2]
-	%tmp113 = load %struct.rtvec_def** %tmp11111221		; <%struct.rtvec_def*> [#uses=1]
-	%tmp114 = getelementptr %struct.rtvec_def* %tmp113, i32 0, i32 0		; <i32*> [#uses=1]
-	%tmp115 = load i32* %tmp114		; <i32> [#uses=1]
-	%tmp116 = icmp ult i32 %tmp104, %tmp115		; <i1> [#uses=1]
-	br i1 %tmp116, label %bb73, label %bb123
-
-bb123:		; preds = %bb73, %bb105.preheader, %cond_true47, %bb
-	%i.0 = add i32 %i.01.0, -1		; <i32> [#uses=1]
-	%tmp125 = icmp sgt i32 %i.0, -1		; <i1> [#uses=1]
-	%indvar.next26 = add i32 %indvar, 1		; <i32> [#uses=1]
-	br i1 %tmp125, label %bb, label %UnifiedReturnBlock
-
-UnifiedReturnBlock:		; preds = %bb123, %cond_next32, %entry
-	%UnifiedRetVal = phi %struct.rtx_def* [ null, %entry ], [ %x, %cond_next32 ], [ %x, %bb123 ]		; <%struct.rtx_def*> [#uses=1]
-	ret %struct.rtx_def* %UnifiedRetVal
-}
diff --git a/test/CodeGen/X86/2008-04-02-unnamedEH.ll b/test/CodeGen/X86/2008-04-02-unnamedEH.ll
index a9f368b..27bbbaa 100644
--- a/test/CodeGen/X86/2008-04-02-unnamedEH.ll
+++ b/test/CodeGen/X86/2008-04-02-unnamedEH.ll
@@ -1,26 +1,16 @@
-; RUN: llc < %s | grep unnamed_1.eh
+; RUN: llc < %s | FileCheck %s
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
 target triple = "i386-apple-darwin8"
 
 define void @_Z3bazv() {
-	call i32 @0( )		; <i32>:1 [#uses=0]
-	br label %2
-; <label>:2		; preds = %0
+	call void @0( )		; <i32>:1 [#uses=0]
 	ret void
 }
 
-define internal i32 @""() {
-	alloca i32		; <i32*>:1 [#uses=2]
-	alloca i32		; <i32*>:2 [#uses=2]
-	bitcast i32 0 to i32		; <i32>:3 [#uses=0]
+define internal void @""() {
 	call i32 @_Z3barv( )		; <i32>:4 [#uses=1]
-	store i32 %4, i32* %2, align 4
-	load i32* %2, align 4		; <i32>:5 [#uses=1]
-	store i32 %5, i32* %1, align 4
-	br label %6
-; <label>:6		; preds = %0
-	load i32* %1		; <i32>:7 [#uses=1]
-	ret i32 %7
+	ret void
 }
+; CHECK: unnamed_1.eh
 
 declare i32 @_Z3barv()
diff --git a/test/CodeGen/X86/2008-09-18-inline-asm-2.ll b/test/CodeGen/X86/2008-09-18-inline-asm-2.ll
index f5bd307..e3b6fdf 100644
--- a/test/CodeGen/X86/2008-09-18-inline-asm-2.ll
+++ b/test/CodeGen/X86/2008-09-18-inline-asm-2.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=x86 | grep "#%ebp %edi %esi 8(%edx) %eax (%ebx)"
-; RUN: llc < %s -march=x86 -regalloc=local | grep "#%edi %edx %ebp 8(%ebx) %eax (%esi)"
+; RUN: llc < %s -march=x86 | grep "#%ebp %esi %edi 8(%edx) %eax (%ebx)"
+; RUN: llc < %s -march=x86 -regalloc=local | grep "#%edi %ebp %edx 8(%ebx) %eax (%esi)"
 ; The 1st, 2nd, 3rd and 5th registers above must all be different.  The registers
 ; referenced in the 4th and 6th operands must not be the same as the 1st or 5th
 ; operand.  There are many combinations that work; this is what llc puts out now.
diff --git a/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll b/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll
index 13a9080..a6cabc4 100644
--- a/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll
+++ b/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=i386-apple-darwin -asm-verbose=0 | FileCheck %s
 ; PR3149
 ; Make sure the copy after inline asm is not coalesced away.
 
diff --git a/test/CodeGen/X86/2009-02-04-sext-i64-gep.ll b/test/CodeGen/X86/2009-02-04-sext-i64-gep.ll
index 6ba046a..4880f62 100644
--- a/test/CodeGen/X86/2009-02-04-sext-i64-gep.ll
+++ b/test/CodeGen/X86/2009-02-04-sext-i64-gep.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s | grep { - 92}
+; RUN: llc < %s | grep p-92
 ; PR3481
 ; The offset should print as -92, not +17179869092
 
diff --git a/test/CodeGen/X86/2009-09-10-SpillComments.ll b/test/CodeGen/X86/2009-09-10-SpillComments.ll
index 1dd9990..f9ca861 100644
--- a/test/CodeGen/X86/2009-09-10-SpillComments.ll
+++ b/test/CodeGen/X86/2009-09-10-SpillComments.ll
@@ -1,5 +1,11 @@
 ; RUN: llc < %s -mtriple=x86_64-unknown-linux | FileCheck %s
 
+; This test shouldn't require spills.
+
+; CHECK: subq  $8, %rsp
+; CHECK-NOT: $rsp
+; CHECK: addq  $8, %rsp
+
 	%struct..0anon = type { i32 }
 	%struct.rtvec_def = type { i32, [1 x %struct..0anon] }
 	%struct.rtx_def = type { i16, i8, i8, [1 x %struct..0anon] }
@@ -10,9 +16,6 @@ declare %struct.rtx_def* @fixup_memory_subreg(%struct.rtx_def*, %struct.rtx_def*
 
 define %struct.rtx_def* @walk_fixup_memory_subreg(%struct.rtx_def* %x, %struct.rtx_def* %insn) {
 entry:
-; CHECK: Spill
-; CHECK: Folded Spill
-; CHECK: Reload
 	%tmp2 = icmp eq %struct.rtx_def* %x, null		; <i1> [#uses=1]
 	br i1 %tmp2, label %UnifiedReturnBlock, label %cond_next
 
diff --git a/test/CodeGen/X86/2010-01-15-SelectionDAGCycle.ll b/test/CodeGen/X86/2010-01-15-SelectionDAGCycle.ll
new file mode 100644
index 0000000..5d96e4a
--- /dev/null
+++ b/test/CodeGen/X86/2010-01-15-SelectionDAGCycle.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -march=x86-64
+; ModuleID = 'bugpoint-reduced-simplified.bc'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @numvec_(i32* noalias %ncelet, i32* noalias %ncel, i32* noalias %nfac, i32* noalias %nfabor, i32* noalias %lregis, i32* noalias %irveci, i32* noalias %irvecb, [0 x [2 x i32]]* noalias %ifacel, [0 x i32]* noalias %ifabor, [0 x i32]* noalias %inumfi, [0 x i32]* noalias %inumfb, [1 x i32]* noalias %iworkf, [0 x i32]* noalias %ismbs) {
+"file bug754399.f90, line 1, bb1":
+	%r1037 = bitcast <2 x double> zeroinitializer to <4 x i32>		; <<4 x i32>> [#uses=1]
+	br label %"file bug754399.f90, line 184, in inner vector loop at depth 0, bb164"
+
+"file bug754399.f90, line 184, in inner vector loop at depth 0, bb164":		; preds = %"file bug754399.f90, line 184, in inner vector loop at depth 0, bb164", %"file bug754399.f90, line 1, bb1"
+	%tmp641 = add i64 0, 48		; <i64> [#uses=1]
+	%tmp641642 = inttoptr i64 %tmp641 to <4 x i32>*		; <<4 x i32>*> [#uses=1]
+	%r1258 = load <4 x i32>* %tmp641642, align 4		; <<4 x i32>> [#uses=2]
+	%r1295 = extractelement <4 x i32> %r1258, i32 3		; <i32> [#uses=1]
+	%r1296 = sext i32 %r1295 to i64		; <i64> [#uses=1]
+	%r1297 = add i64 %r1296, -1		; <i64> [#uses=1]
+	%r1298183 = getelementptr [0 x i32]* %ismbs, i64 0, i64 %r1297		; <i32*> [#uses=1]
+	%r1298184 = load i32* %r1298183, align 4		; <i32> [#uses=1]
+	%r1301 = extractelement <4 x i32> %r1037, i32 3		; <i32> [#uses=1]
+	%r1302 = mul i32 %r1298184, %r1301		; <i32> [#uses=1]
+	%r1306 = insertelement <4 x i32> zeroinitializer, i32 %r1302, i32 3		; <<4 x i32>> [#uses=1]
+	%r1321 = add <4 x i32> %r1306, %r1258		; <<4 x i32>> [#uses=1]
+	%tmp643 = add i64 0, 48		; <i64> [#uses=1]
+	%tmp643644 = inttoptr i64 %tmp643 to <4 x i32>*		; <<4 x i32>*> [#uses=1]
+	store <4 x i32> %r1321, <4 x i32>* %tmp643644, align 4
+	br label %"file bug754399.f90, line 184, in inner vector loop at depth 0, bb164"
+}
diff --git a/test/CodeGen/X86/2010-01-19-OptExtBug.ll b/test/CodeGen/X86/2010-01-19-OptExtBug.ll
new file mode 100644
index 0000000..cd8960b
--- /dev/null
+++ b/test/CodeGen/X86/2010-01-19-OptExtBug.ll
@@ -0,0 +1,57 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin11 -relocation-model=pic -disable-fp-elim -stats |& not grep ext-opt
+
+define fastcc i8* @S_scan_str(i8* %start, i32 %keep_quoted, i32 %keep_delims) nounwind ssp {
+entry:
+  switch i8 undef, label %bb6 [
+    i8 9, label %bb5
+    i8 32, label %bb5
+    i8 10, label %bb5
+    i8 13, label %bb5
+    i8 12, label %bb5
+  ]
+
+bb5:                                              ; preds = %entry, %entry, %entry, %entry, %entry
+  br label %bb6
+
+bb6:                                              ; preds = %bb5, %entry
+  br i1 undef, label %bb7, label %bb9
+
+bb7:                                              ; preds = %bb6
+  unreachable
+
+bb9:                                              ; preds = %bb6
+  %0 = load i8* undef, align 1                    ; <i8> [#uses=3]
+  br i1 undef, label %bb12, label %bb10
+
+bb10:                                             ; preds = %bb9
+  br i1 undef, label %bb12, label %bb11
+
+bb11:                                             ; preds = %bb10
+  unreachable
+
+bb12:                                             ; preds = %bb10, %bb9
+  br i1 undef, label %bb13, label %bb14
+
+bb13:                                             ; preds = %bb12
+  store i8 %0, i8* undef, align 1
+  %1 = zext i8 %0 to i32                          ; <i32> [#uses=1]
+  br label %bb18
+
+bb14:                                             ; preds = %bb12
+  br label %bb18
+
+bb18:                                             ; preds = %bb14, %bb13
+  %termcode.0 = phi i32 [ %1, %bb13 ], [ undef, %bb14 ] ; <i32> [#uses=2]
+  %2 = icmp eq i8 %0, 0                           ; <i1> [#uses=1]
+  br i1 %2, label %bb21, label %bb19
+
+bb19:                                             ; preds = %bb18
+  br i1 undef, label %bb21, label %bb20
+
+bb20:                                             ; preds = %bb19
+  br label %bb21
+
+bb21:                                             ; preds = %bb20, %bb19, %bb18
+  %termcode.1 = phi i32 [ %termcode.0, %bb18 ], [ %termcode.0, %bb19 ], [ undef, %bb20 ] ; <i32> [#uses=0]
+  unreachable
+}
diff --git a/test/CodeGen/X86/bigstructret2.ll b/test/CodeGen/X86/bigstructret2.ll
new file mode 100644
index 0000000..46e0fd2
--- /dev/null
+++ b/test/CodeGen/X86/bigstructret2.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=x86 -o %t
+
+%0 = type { i64, i64 }
+
+declare fastcc %0 @ReturnBigStruct() nounwind readnone
+
+define void @test(%0* %p) {
+  %1 = call fastcc %0 @ReturnBigStruct()
+  store %0 %1, %0* %p
+  ret void
+}
+
diff --git a/test/CodeGen/X86/bss_pagealigned.ll b/test/CodeGen/X86/bss_pagealigned.ll
index 27c5361..da95aca 100644
--- a/test/CodeGen/X86/bss_pagealigned.ll
+++ b/test/CodeGen/X86/bss_pagealigned.ll
@@ -1,4 +1,4 @@
-; RUN: llc --code-model=kernel -march=x86-64 <%s | FileCheck %s
+; RUN: llc --code-model=kernel -march=x86-64 <%s -asm-verbose=0 | FileCheck %s
 ; PR4933
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 target triple = "x86_64-unknown-linux-gnu"
diff --git a/test/CodeGen/X86/full-lsr.ll b/test/CodeGen/X86/full-lsr.ll
index 68575bc..3bd58b6 100644
--- a/test/CodeGen/X86/full-lsr.ll
+++ b/test/CodeGen/X86/full-lsr.ll
@@ -1,6 +1,12 @@
-; RUN: llc < %s -march=x86 -enable-full-lsr >%t
-; RUN: grep {addl	\\\$4,} %t | count 3
-; RUN: not grep {,%} %t
+; RUN: llc < %s -march=x86 >%t
+
+; TODO: Enhance full lsr mode to get this:
+; RUNX: grep {addl	\\\$4,} %t | count 3
+; RUNX: not grep {,%} %t
+
+; For now, it should find this, which is still pretty good:
+; RUN: not grep {addl	\\\$4,} %t
+; RUN: grep {,%} %t | count 6
 
 define void @foo(float* nocapture %A, float* nocapture %B, float* nocapture %C, i32 %N) nounwind {
 entry:
diff --git a/test/CodeGen/X86/global-sections.ll b/test/CodeGen/X86/global-sections.ll
index 38948a7..1a7b577 100644
--- a/test/CodeGen/X86/global-sections.ll
+++ b/test/CodeGen/X86/global-sections.ll
@@ -6,7 +6,6 @@
 @G1 = common global i32 0
 
 ; LINUX: .type   G1,@object
-; LINUX: .section .gnu.linkonce.b.G1,"aw",@nobits
 ; LINUX: .comm  G1,4,4
 
 ; DARWIN: .comm	_G1,4,2
@@ -76,14 +75,14 @@
 ; LINUX:   .section	.gnu.linkonce.r.G6,"a",@progbits
 ; LINUX:   .weak	G6
 ; LINUX: G6:
-; LINUX:   .ascii	"\001"
+; LINUX:   .byte	1
 ; LINUX:   .size	G6, 1
 
 ; DARWIN:  .section __TEXT,__const_coal,coalesced
 ; DARWIN:  .globl _G6
 ; DARWIN:  .weak_definition _G6
 ; DARWIN:_G6:
-; DARWIN:  .ascii "\001"
+; DARWIN:  .byte 1
 
 
 @G7 = constant [10 x i8] c"abcdefghi\00"
@@ -120,4 +119,19 @@
 ; LINUX:G9
 
 
+@G10 = weak global [100 x i32] zeroinitializer, align 32 ; <[100 x i32]*> [#uses=0]
+
+
+; DARWIN: 	.section	__DATA,__datacoal_nt,coalesced
+; DARWIN: .globl _G10
+; DARWIN:	.weak_definition _G10
+; DARWIN:	.align	5
+; DARWIN: _G10:
+; DARWIN:	.space	400
+
+; LINUX:	.bss
+; LINUX:	.weak	G10
+; LINUX:	.align	32
+; LINUX: G10:
+; LINUX:	.zero	400
 
diff --git a/test/CodeGen/X86/i128-and-beyond.ll b/test/CodeGen/X86/i128-and-beyond.ll
index 907a6b8..b741681 100644
--- a/test/CodeGen/X86/i128-and-beyond.ll
+++ b/test/CodeGen/X86/i128-and-beyond.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -mtriple=i686-pc-linux-gnu | grep 18446744073709551615 | count 14
+; RUN: llc < %s -march=x86 -mtriple=i686-pc-linux-gnu | grep -- -1 | count 14
 
 ; These static initializers are too big to hand off to assemblers
 ; as monolithic blobs.
diff --git a/test/CodeGen/X86/illegal-asm.ll b/test/CodeGen/X86/illegal-asm.ll
deleted file mode 100644
index 43128dc..0000000
--- a/test/CodeGen/X86/illegal-asm.ll
+++ /dev/null
@@ -1,34 +0,0 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin -disable-fp-elim
-; RUN: llc < %s -mtriple=i386-linux        -disable-fp-elim
-; XFAIL: *
-; Expected to run out of registers during allocation.
-; PR3864
-; rdar://6251720
-
-	%struct.CABACContext = type { i32, i32, i8* }
-	%struct.H264Context = type { %struct.CABACContext, [460 x i8] }
-@coeff_abs_level_m1_offset = common global [6 x i32] zeroinitializer		; <[6 x i32]*> [#uses=1]
-@coeff_abs_level1_ctx = common global [8 x i8] zeroinitializer		; <[8 x i8]*> [#uses=1]
-
-define i32 @decode_cabac_residual(%struct.H264Context* %h, i32 %cat) nounwind {
-entry:
-	%0 = getelementptr [6 x i32]* @coeff_abs_level_m1_offset, i32 0, i32 %cat		; <i32*> [#uses=1]
-	%1 = load i32* %0, align 4		; <i32> [#uses=1]
-	%2 = load i8* getelementptr ([8 x i8]* @coeff_abs_level1_ctx, i32 0, i32 0), align 1		; <i8> [#uses=1]
-	%3 = zext i8 %2 to i32		; <i32> [#uses=1]
-	%.sum = add i32 %3, %1		; <i32> [#uses=1]
-	%4 = getelementptr %struct.H264Context* %h, i32 0, i32 1, i32 %.sum		; <i8*> [#uses=2]
-	%5 = getelementptr %struct.H264Context* %h, i32 0, i32 0, i32 0		; <i32*> [#uses=2]
-	%6 = getelementptr %struct.H264Context* %h, i32 0, i32 0, i32 1		; <i32*> [#uses=2]
-	%7 = getelementptr %struct.H264Context* %h, i32 0, i32 0, i32 2		; <i8**> [#uses=2]
-	%8 = load i32* %5, align 4		; <i32> [#uses=1]
-	%9 = load i32* %6, align 4		; <i32> [#uses=1]
-	%10 = load i8* %4, align 4		; <i8> [#uses=1]
-	%asmtmp = tail call { i32, i32, i32, i32 } asm sideeffect "#$0 $1 $2 $3 $4 $5", "=&{di},=r,=r,=*m,=&q,=*imr,1,2,*m,5,~{dirflag},~{fpsr},~{flags},~{cx}"(i8** %7, i8* %4, i32 %8, i32 %9, i8** %7, i8 %10) nounwind		; <{ i32, i32, i32, i32 }> [#uses=3]
-	%asmresult = extractvalue { i32, i32, i32, i32 } %asmtmp, 0		; <i32> [#uses=1]
-	%asmresult1 = extractvalue { i32, i32, i32, i32 } %asmtmp, 1		; <i32> [#uses=1]
-	store i32 %asmresult1, i32* %5
-	%asmresult2 = extractvalue { i32, i32, i32, i32 } %asmtmp, 2		; <i32> [#uses=1]
-	store i32 %asmresult2, i32* %6
-	ret i32 %asmresult
-}
diff --git a/test/CodeGen/X86/loop-hoist.ll b/test/CodeGen/X86/loop-hoist.ll
index b52066d..b9008e5 100644
--- a/test/CodeGen/X86/loop-hoist.ll
+++ b/test/CodeGen/X86/loop-hoist.ll
@@ -4,7 +4,7 @@
 
 ; CHECK: _foo:
 ; CHECK:    L_Arr$non_lazy_ptr
-; CHECK: LBB1_1:	## %cond_true
+; CHECK: LBB1_1:
 
 @Arr = external global [0 x i32]		; <[0 x i32]*> [#uses=1]
 
diff --git a/test/CodeGen/X86/loop-strength-reduce4.ll b/test/CodeGen/X86/loop-strength-reduce4.ll
index 87b606f..07e46ec 100644
--- a/test/CodeGen/X86/loop-strength-reduce4.ll
+++ b/test/CodeGen/X86/loop-strength-reduce4.ll
@@ -4,7 +4,7 @@
 @state = external global [0 x i32]		; <[0 x i32]*> [#uses=4]
 @S = external global [0 x i32]		; <[0 x i32]*> [#uses=4]
 
-define i32 @foo() {
+define i32 @foo() nounwind {
 entry:
 	br label %bb
 
diff --git a/test/CodeGen/X86/neg-shl-add.ll b/test/CodeGen/X86/neg-shl-add.ll
new file mode 100644
index 0000000..7aebc38
--- /dev/null
+++ b/test/CodeGen/X86/neg-shl-add.ll
@@ -0,0 +1,17 @@
+; RUN: llc -march=x86-64 < %s | not grep negq
+
+; These sequences don't need neg instructions; they can be done with
+; a single shift and sub each.
+
+define i64 @foo(i64 %x, i64 %y, i64 %n) nounwind {
+  %a = sub i64 0, %y
+  %b = shl i64 %a, %n
+  %c = add i64 %b, %x
+  ret i64 %c
+}
+define i64 @boo(i64 %x, i64 %y, i64 %n) nounwind {
+  %a = sub i64 0, %y
+  %b = shl i64 %a, %n
+  %c = add i64 %x, %b
+  ret i64 %c
+}
diff --git a/test/CodeGen/X86/pr3495-2.ll b/test/CodeGen/X86/pr3495-2.ll
index 1372a15..71aa5a0 100644
--- a/test/CodeGen/X86/pr3495-2.ll
+++ b/test/CodeGen/X86/pr3495-2.ll
@@ -1,5 +1,6 @@
 ; RUN: llc < %s -march=x86 -relocation-model=pic -disable-fp-elim -stats |& grep {Number of reloads omited}
 
+target datalayout = "e-p:32:32:32"
 target triple = "i386-apple-darwin9.6"
 	%struct.constraintVCGType = type { i32, i32, i32, i32 }
 	%struct.nodeVCGType = type { %struct.constraintVCGType*, i32, i32, i32, %struct.constraintVCGType*, i32, i32, i32 }
diff --git a/test/CodeGen/X86/pr3495.ll b/test/CodeGen/X86/pr3495.ll
index 4b62bf4..1795970 100644
--- a/test/CodeGen/X86/pr3495.ll
+++ b/test/CodeGen/X86/pr3495.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -march=x86 -stats |& grep {Number of reloads omited} | grep 1
-; RUN: llc < %s -march=x86 -stats |& grep {Number of available reloads turned into copies} | grep 1
-; RUN: llc < %s -march=x86 -stats |& grep {Number of machine instrs printed} | grep 40
+; RUN: llc < %s -march=x86 -stats |& grep {Number of loads added} | grep 2
+; RUN: llc < %s -march=x86 -stats |& grep {Number of register spills} | grep 1
+; RUN: llc < %s -march=x86 -stats |& grep {Number of machine instrs printed} | grep 38
 ; PR3495
 ; The loop reversal kicks in once here, resulting in one fewer instruction.
 
diff --git a/test/CodeGen/X86/ptrtoint-constexpr.ll b/test/CodeGen/X86/ptrtoint-constexpr.ll
index 72a428e..7e33e79 100644
--- a/test/CodeGen/X86/ptrtoint-constexpr.ll
+++ b/test/CodeGen/X86/ptrtoint-constexpr.ll
@@ -3,6 +3,6 @@
 
 ; CHECK:	.globl r
 ; CHECK: r:
-; CHECK: .quad	((r) & 4294967295)
+; CHECK: .quad	r&4294967295
 
 @r = global %union.x { i64 ptrtoint (%union.x* @r to i64) }, align 4
diff --git a/test/CodeGen/X86/remat-mov-0.ll b/test/CodeGen/X86/remat-mov-0.ll
index c4f768c..5fb445c 100644
--- a/test/CodeGen/X86/remat-mov-0.ll
+++ b/test/CodeGen/X86/remat-mov-0.ll
@@ -1,13 +1,33 @@
-; RUN: llc < %s -march=x86-64 | grep {xorl	%edi, %edi} | count 4
+; RUN: llc < %s -march=x86-64 | FileCheck %s
 
 ; CodeGen should remat the zero instead of spilling it.
 
 declare void @foo(i64 %p)
 
+; CHECK: bar:
+; CHECK: xorl %edi, %edi
+; CHECK: xorl %edi, %edi
 define void @bar() nounwind {
   call void @foo(i64 0)
   call void @foo(i64 0)
-  call void @foo(i64 0)
-  call void @foo(i64 0)
   ret void
 }
+
+; CHECK: bat:
+; CHECK: movq $-1, %rdi
+; CHECK: movq $-1, %rdi
+define void @bat() nounwind {
+  call void @foo(i64 -1)
+  call void @foo(i64 -1)
+  ret void
+}
+
+; CHECK: bau:
+; CHECK: movl $1, %edi
+; CHECK: movl $1, %edi
+define void @bau() nounwind {
+  call void @foo(i64 1)
+  call void @foo(i64 1)
+  ret void
+}
+
diff --git a/test/CodeGen/X86/remat-mov-1.ll b/test/CodeGen/X86/remat-mov-1.ll
deleted file mode 100644
index d71b7a5..0000000
--- a/test/CodeGen/X86/remat-mov-1.ll
+++ /dev/null
@@ -1,40 +0,0 @@
-; RUN: llc < %s -march=x86 | grep -- -1 | grep mov | count 2
-
-	%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
-	%struct.ImgT = type { i8, i8*, i8*, %struct.FILE*, i32, i32, i32, i32, i8*, double*, float*, float*, float*, i32*, double, double, i32*, double*, i32*, i32* }
-	%struct._CompT = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, i8, %struct._PixT*, %struct._CompT*, i8, %struct._CompT* }
-	%struct._PixT = type { i32, i32, %struct._PixT* }
-	%struct.__sFILEX = type opaque
-	%struct.__sbuf = type { i8*, i32 }
-
-declare fastcc void @MergeComponents(%struct._CompT*, %struct._CompT*, %struct._CompT*, %struct._CompT**, %struct.ImgT*) nounwind 
-
-define fastcc void @MergeToLeft(%struct._CompT* %comp, %struct._CompT** %head, %struct.ImgT* %img) nounwind  {
-entry:
-	br label %bb208
-
-bb105:		; preds = %bb200
-	br i1 false, label %bb197, label %bb149
-
-bb149:		; preds = %bb105
-	%tmp151 = getelementptr %struct._CompT* %comp, i32 0, i32 0		; <i32*> [#uses=1]
-	br label %bb193
-
-bb193:		; preds = %bb184, %bb149
-	%tmp196 = load i32* %tmp151, align 4		; <i32> [#uses=1]
-	br label %bb197
-
-bb197:		; preds = %bb193, %bb105
-	%last_comp.0 = phi i32 [ %tmp196, %bb193 ], [ 0, %bb105 ]		; <i32> [#uses=0]
-	%indvar.next = add i32 %indvar, 1		; <i32> [#uses=1]
-	br label %bb200
-
-bb200:		; preds = %bb208, %bb197
-	%indvar = phi i32 [ 0, %bb208 ], [ %indvar.next, %bb197 ]		; <i32> [#uses=2]
-	%xm.0 = sub i32 %indvar, 0		; <i32> [#uses=1]
-	%tmp202 = icmp slt i32 %xm.0, 1		; <i1> [#uses=1]
-	br i1 %tmp202, label %bb105, label %bb208
-
-bb208:		; preds = %bb200, %entry
-	br label %bb200
-}
diff --git a/test/CodeGen/X86/remat-scalar-zero.ll b/test/CodeGen/X86/remat-scalar-zero.ll
index 790ae83..2da96ab 100644
--- a/test/CodeGen/X86/remat-scalar-zero.ll
+++ b/test/CodeGen/X86/remat-scalar-zero.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu > %t
 ; RUN: not grep xor %t
 ; RUN: not grep movap %t
-; RUN: grep {\\.zero} %t
+; RUN: grep {\\.quad.*0} %t
 
 ; Remat should be able to fold the zero constant into the div instructions
 ; as a constant-pool load.
diff --git a/test/CodeGen/X86/splat-scalar-load.ll b/test/CodeGen/X86/splat-scalar-load.ll
index 32d3ab6..2b13029 100644
--- a/test/CodeGen/X86/splat-scalar-load.ll
+++ b/test/CodeGen/X86/splat-scalar-load.ll
@@ -1,21 +1,6 @@
 ; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 | FileCheck %s
 ; rdar://7434544
 
-define <2 x i64> @t1() nounwind ssp {
-entry:
-; CHECK: t1:
-; CHECK: pshufd	$0, (%esp), %xmm0
-  %array = alloca [8 x float], align 16
-  %arrayidx = getelementptr inbounds [8 x float]* %array, i32 0, i32 0
-  %tmp2 = load float* %arrayidx
-  %vecinit = insertelement <4 x float> undef, float %tmp2, i32 0
-  %vecinit5 = insertelement <4 x float> %vecinit, float %tmp2, i32 1
-  %vecinit7 = insertelement <4 x float> %vecinit5, float %tmp2, i32 2
-  %vecinit9 = insertelement <4 x float> %vecinit7, float %tmp2, i32 3
-  %0 = bitcast <4 x float> %vecinit9 to <2 x i64>
-  ret <2 x i64> %0
-}
-
 define <2 x i64> @t2() nounwind ssp {
 entry:
 ; CHECK: t2:
@@ -30,14 +15,3 @@ entry:
   %0 = bitcast <4 x float> %vecinit9 to <2 x i64>
   ret <2 x i64> %0
 }
-
-define <4 x float> @t3(float %tmp1, float %tmp2, float %tmp3) nounwind readnone ssp {
-entry:
-; CHECK: t3:
-; CHECK: pshufd	$-86, (%esp), %xmm0
-  %0 = insertelement <4 x float> undef, float %tmp3, i32 0
-  %1 = insertelement <4 x float> %0, float %tmp3, i32 1
-  %2 = insertelement <4 x float> %1, float %tmp3, i32 2
-  %3 = insertelement <4 x float> %2, float %tmp3, i32 3
-  ret <4 x float> %3
-}
diff --git a/test/CodeGen/X86/stride-reuse.ll b/test/CodeGen/X86/stride-reuse.ll
index a99a9c9..5cbd895 100644
--- a/test/CodeGen/X86/stride-reuse.ll
+++ b/test/CodeGen/X86/stride-reuse.ll
@@ -5,7 +5,7 @@
 @A = external global [1000 x float], align 32
 @P = external global [1000 x i32], align 32
 
-define void @foo(i32 %m) {
+define void @foo(i32 %m) nounwind {
 entry:
 	%tmp1 = icmp sgt i32 %m, 0
 	br i1 %tmp1, label %bb, label %return
diff --git a/test/CodeGen/X86/subreg-to-reg-5.ll b/test/CodeGen/X86/subreg-to-reg-5.ll
deleted file mode 100644
index ba4c307..0000000
--- a/test/CodeGen/X86/subreg-to-reg-5.ll
+++ /dev/null
@@ -1,35 +0,0 @@
-; RUN: llc < %s -march=x86-64 > %t
-; RUN: grep addl %t
-; RUN: not egrep {movl|movq} %t
-
-define float @foo(float* %B) nounwind {
-entry:
-	br label %bb2
-
-bb2:		; preds = %bb3, %entry
-	%B_addr.0.rec = phi i64 [ %indvar.next154, %bb3 ], [ 0, %entry ]		; <i64> [#uses=2]
-        %z = icmp slt i64 %B_addr.0.rec, 20000
-	br i1 %z, label %bb3, label %bb4
-
-bb3:		; preds = %bb2
-	%indvar.next154 = add i64 %B_addr.0.rec, 1		; <i64> [#uses=1]
-	br label %bb2
-
-bb4:		; preds = %bb2
-	%B_addr.0 = getelementptr float* %B, i64 %B_addr.0.rec		; <float*> [#uses=1]
-	%t1 = ptrtoint float* %B_addr.0 to i64		; <i64> [#uses=1]
-	%t2 = and i64 %t1, 4294967295		; <i64> [#uses=1]
-	%t3 = icmp eq i64 %t2, 0		; <i1> [#uses=1]
-	br i1 %t3, label %bb5, label %bb10.preheader
-
-bb10.preheader:		; preds = %bb4
-	br label %bb9
-
-bb5:		; preds = %bb4
-	ret float 7.0
-
-bb9:		; preds = %bb10.preheader
-	%t5 = getelementptr float* %B, i64 0		; <float*> [#uses=1]
-	%t7 = load float* %t5		; <float> [#uses=1]
-	ret float %t7
-}
diff --git a/test/CodeGen/X86/tail-opts.ll b/test/CodeGen/X86/tail-opts.ll
index c5dbb04..7b21e1b 100644
--- a/test/CodeGen/X86/tail-opts.ll
+++ b/test/CodeGen/X86/tail-opts.ll
@@ -109,15 +109,15 @@ altret:
 
 ; CHECK: dont_merge_oddly:
 ; CHECK-NOT:   ret
-; CHECK:        ucomiss %xmm0, %xmm1
+; CHECK:        ucomiss %xmm1, %xmm2
 ; CHECK-NEXT:   jbe .LBB3_3
-; CHECK-NEXT:   ucomiss %xmm2, %xmm0
+; CHECK-NEXT:   ucomiss %xmm0, %xmm1
 ; CHECK-NEXT:   ja .LBB3_4
 ; CHECK-NEXT: .LBB3_2:
 ; CHECK-NEXT:   movb $1, %al
 ; CHECK-NEXT:   ret
 ; CHECK-NEXT: .LBB3_3:
-; CHECK-NEXT:   ucomiss %xmm2, %xmm1
+; CHECK-NEXT:   ucomiss %xmm0, %xmm2
 ; CHECK-NEXT:   jbe .LBB3_2
 ; CHECK-NEXT: .LBB3_4:
 ; CHECK-NEXT:   xorb %al, %al
diff --git a/test/CodeGen/X86/unaligned-load.ll b/test/CodeGen/X86/unaligned-load.ll
index 7778983..b61803d 100644
--- a/test/CodeGen/X86/unaligned-load.ll
+++ b/test/CodeGen/X86/unaligned-load.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=dynamic-no-pic | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=dynamic-no-pic --asm-verbose=0 | FileCheck %s
 
 @.str1 = internal constant [31 x i8] c"DHRYSTONE PROGRAM, SOME STRING\00", align 8
 @.str3 = internal constant [31 x i8] c"DHRYSTONE PROGRAM, 2'ND STRING\00", align 8
@@ -23,5 +23,5 @@ declare void @llvm.memcpy.i64(i8* nocapture, i8* nocapture, i64, i32) nounwind
 ; CHECK: .align  3
 ; CHECK-NEXT: _.str1:
 ; CHECK-NEXT: .asciz "DHRYSTONE PROGRAM, SOME STRING"
-; CHECK-NEXT: .align 3
+; CHECK: .align 3
 ; CHECK-NEXT: _.str3:
diff --git a/test/CodeGen/X86/xor.ll b/test/CodeGen/X86/xor.ll
index 7bd06bb..9bfff8a 100644
--- a/test/CodeGen/X86/xor.ll
+++ b/test/CodeGen/X86/xor.ll
@@ -131,3 +131,14 @@ bb12:
 ; X32:    andl	{{.*}}[[REG]]
 }
 
+define i32 @test8(i32 %a) nounwind {
+; rdar://7553032
+entry:
+  %t1 = sub i32 0, %a
+  %t2 = add i32 %t1, -1
+  ret i32 %t2
+; X64: test8:
+; X64:   notl %eax
+; X32: test8:
+; X32:   notl %eax
+}
diff --git a/test/DebugInfo/2010-01-19-DbgScope.ll b/test/DebugInfo/2010-01-19-DbgScope.ll
new file mode 100644
index 0000000..7afb5a5
--- /dev/null
+++ b/test/DebugInfo/2010-01-19-DbgScope.ll
@@ -0,0 +1,28 @@
+; RUN: llc -O0 < %s -o /dev/null
+; Ignore unreachable scopes.
+declare void @foo(i32) noreturn
+
+define i32 @bar() nounwind ssp {
+entry:
+  br i1 undef, label %bb, label %bb11, !dbg !0
+
+bb:                                               ; preds = %entry
+  call void @foo(i32 0) noreturn nounwind, !dbg !7
+  unreachable, !dbg !7
+
+bb11:                                             ; preds = %entry
+  ret i32 1, !dbg !11
+}
+
+!0 = metadata !{i32 8647, i32 0, metadata !1, null}
+!1 = metadata !{i32 458763, metadata !2}          ; [ DW_TAG_lexical_block ]
+!2 = metadata !{i32 458798, i32 0, metadata !3, metadata !"bar", metadata !"bar", metadata !"bar", metadata !3, i32 8639, metadata !4, i1 true, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ]
+!3 = metadata !{i32 458769, i32 0, i32 1, metadata !"c-parser.c", metadata !"llvmgcc", metadata !"LLVM build 00", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
+!4 = metadata !{i32 458773, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0} ; [ DW_TAG_subroutine_type ]
+!5 = metadata !{metadata !6}
+!6 = metadata !{i32 458788, metadata !3, metadata !"char", metadata !3, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
+!7 = metadata !{i32 8648, i32 0, metadata !8, null}
+!8 = metadata !{i32 458763, metadata !9}          ; [ DW_TAG_lexical_block ]
+!9 = metadata !{i32 458763, metadata !10}         ; [ DW_TAG_lexical_block ]
+!10 = metadata !{i32 458798, i32 0, metadata !3, metadata !"bar2", metadata !"bar2", metadata !"bar2", metadata !3, i32 8639, metadata !4, i1 true, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ]
+!11 = metadata !{i32 8652, i32 0, metadata !1, null}
diff --git a/test/FrontendC/2010-01-18-Inlined-Debug.c b/test/FrontendC/2010-01-18-Inlined-Debug.c
new file mode 100644
index 0000000..4aec7b2
--- /dev/null
+++ b/test/FrontendC/2010-01-18-Inlined-Debug.c
@@ -0,0 +1,12 @@
+// PR: 6058
+// RUN: %llvmgcc -g -S %s -o - | llc -O0 -o /dev/null
+
+static inline int foo(double) __attribute__ ((always_inline));
+static inline int foo(double __x) { return __x; }
+
+void bar(double x) {
+  foo(x);
+}
+
+
+
diff --git a/test/FrontendC/pr5406.c b/test/FrontendC/pr5406.c
new file mode 100644
index 0000000..c873e51
--- /dev/null
+++ b/test/FrontendC/pr5406.c
@@ -0,0 +1,20 @@
+// RUN: %llvmgcc %s -S -emit-llvm -O0 -o - | FileCheck %s
+// PR 5406
+
+// XFAIL: *
+// XTARGET: arm
+
+typedef struct { char x[3]; } A0;
+void foo (int i, ...);
+
+
+// CHECK: call arm_aapcscc  void (i32, ...)* @foo(i32 1, i32 {{.*}}) nounwind
+int main (void)
+{
+  A0 a3;
+  a3.x[0] = 0;
+  a3.x[0] = 0;
+  a3.x[2] = 26;
+  foo (1,  a3 );
+  return 0;
+}
diff --git a/test/MC/AsmParser/X86/x86_instructions.s b/test/MC/AsmParser/X86/x86_instructions.s
index 4c5b698..ed806ee 100644
--- a/test/MC/AsmParser/X86/x86_instructions.s
+++ b/test/MC/AsmParser/X86/x86_instructions.s
@@ -16,7 +16,9 @@
         movl %eax, 10(%ebp, %ebx, 4)
 // CHECK: movl %eax, 10(,%ebx,4)
         movl %eax, 10(, %ebx, 4)
-
+// CHECK: ret
+        ret
+        
 // FIXME: Check that this matches SUB32ri8
 // CHECK: subl $1, %eax
         subl $1, %eax
diff --git a/test/MC/AsmParser/directive_ascii.s b/test/MC/AsmParser/directive_ascii.s
index cc6d23b..5bfc1e9 100644
--- a/test/MC/AsmParser/directive_ascii.s
+++ b/test/MC/AsmParser/directive_ascii.s
@@ -23,27 +23,12 @@ TEST3:
         .asciz "B", "C"
         
 # CHECK: TEST4:
-# CHECK: .byte 1
-# CHECK: .byte 1
-# CHECK: .byte 7
-# CHECK: .byte 0
-# CHECK: .byte 56
-# CHECK: .byte 1
-# CHECK: .byte 0
-# CHECK: .byte 49
-# CHECK: .byte 128
-# CHECK: .byte 0
+# CHECK: .asciz "\001\001\007\0008\001\0001\200"
 TEST4:  
         .ascii "\1\01\07\08\001\0001\200\0"
         
 # CHECK: TEST5:
-# CHECK: .byte 8
-# CHECK: .byte 12
-# CHECK: .byte 10
-# CHECK: .byte 13
-# CHECK: .byte 9
-# CHECK: .byte 92
-# CHECK: .byte 34
+# CHECK: .ascii "\b\f\n\r\t\\\""
 TEST5:
         .ascii "\b\f\n\r\t\\\""
         
diff --git a/test/MC/AsmParser/directive_lcomm.s b/test/MC/AsmParser/directive_lcomm.s
index d38805f..0a0add5 100644
--- a/test/MC/AsmParser/directive_lcomm.s
+++ b/test/MC/AsmParser/directive_lcomm.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -triple i386-unknown-unknown %s | FileCheck %s
+# RUN: llvm-mc -triple i386-apple-darwin10 %s | FileCheck %s
 
 # CHECK: TEST0:
 # CHECK: .zerofill __DATA,__bss,a,7,4
diff --git a/test/MC/AsmParser/directive_space.s b/test/MC/AsmParser/directive_space.s
index a897654..e6353a4 100644
--- a/test/MC/AsmParser/directive_space.s
+++ b/test/MC/AsmParser/directive_space.s
@@ -1,12 +1,11 @@
-# RUN: llvm-mc -triple i386-unknown-unknown %s | FileCheck %s
+# RUN: llvm-mc -triple i386-apple-darwin %s | FileCheck %s
 
 # CHECK: TEST0:
-# CHECK: .byte 0
+# CHECK: .space 1
 TEST0:  
         .space 1
 
 # CHECK: TEST1:
-# CHECK: .byte 3
-# CHECK: .byte 3
+# CHECK: .space	2,3
 TEST1:  
         .space 2, 3
diff --git a/test/Transforms/ConstProp/constant-expr.ll b/test/Transforms/ConstProp/constant-expr.ll
index eece37f..9963032 100644
--- a/test/Transforms/ConstProp/constant-expr.ll
+++ b/test/Transforms/ConstProp/constant-expr.ll
@@ -57,4 +57,11 @@
 @T4 = global i1* inttoptr (i64 trunc (i256 lshr (i256 or (i256 and (i256 and (i256 shl (i256 zext (i64 ptrtoint (i1* @B to i64) to i256), i256 64), i256 -6277101735386680763495507056286727952638980837032266301441), i256 6277101735386680763835789423207666416102355444464034512895), i256 shl (i256 zext (i64 ptrtoint (i1* @A to i64) to i256), i256 192)), i256 64) to i64) to i1*)
 
 ; CHECK: @T5 = global i1* @A
-@T5 = global i1* inttoptr (i64 add (i64 trunc (i256 lshr (i256 or (i256 and (i256 and (i256 shl (i256 zext (i64 ptrtoint (i1* @B to i64) to i256), i256 64), i256 -6277101735386680763495507056286727952638980837032266301441), i256 6277101735386680763835789423207666416102355444464034512895), i256 shl (i256 zext (i64 ptrtoint (i1* @A to i64) to i256), i256 192)), i256 192) to i64), i64 trunc (i256 lshr (i256 or (i256 and (i256 and (i256 shl (i256 zext (i64 ptrtoint (i1* @B to i64) to i256), i256 64), i256 -6277101735386680763495507056286727952638980837032266301441), i256 6277101735386680763835789423207666416102355444464034512895), i256 shl (i256 zext (i64 ptrtoint (i1* @A to i64) to i256), i256 192)), i256 128) to i64)) to i1*)
\ No newline at end of file
+@T5 = global i1* inttoptr (i64 add (i64 trunc (i256 lshr (i256 or (i256 and (i256 and (i256 shl (i256 zext (i64 ptrtoint (i1* @B to i64) to i256), i256 64), i256 -6277101735386680763495507056286727952638980837032266301441), i256 6277101735386680763835789423207666416102355444464034512895), i256 shl (i256 zext (i64 ptrtoint (i1* @A to i64) to i256), i256 192)), i256 192) to i64), i64 trunc (i256 lshr (i256 or (i256 and (i256 and (i256 shl (i256 zext (i64 ptrtoint (i1* @B to i64) to i256), i256 64), i256 -6277101735386680763495507056286727952638980837032266301441), i256 6277101735386680763835789423207666416102355444464034512895), i256 shl (i256 zext (i64 ptrtoint (i1* @A to i64) to i256), i256 192)), i256 128) to i64)) to i1*)
+
+
+
+; PR6096
+
+; No check line. This used to crash llvm-as.
+@T6 = global <2 x i1> fcmp ole (<2 x float> fdiv (<2 x float> undef, <2 x float> <float 1.000000e+00, float 1.000000e+00>), <2 x float> zeroinitializer)
diff --git a/test/Transforms/IndVarSimplify/gep-with-mul-base.ll b/test/Transforms/IndVarSimplify/gep-with-mul-base.ll
index 7809594..19d54ff 100644
--- a/test/Transforms/IndVarSimplify/gep-with-mul-base.ll
+++ b/test/Transforms/IndVarSimplify/gep-with-mul-base.ll
@@ -1,6 +1,7 @@
 ; RUN: opt < %s -indvars -S > %t
-; RUN: grep add %t | count 8
-; RUN: grep mul %t | count 7
+; RUN: grep add %t | count 6
+; RUN: grep sub %t | count 2
+; RUN: grep mul %t | count 6
 
 define void @foo(i64 %n, i64 %m, i64 %o, double* nocapture %p) nounwind {
 entry:
diff --git a/test/Transforms/InstCombine/apint-elim-logicalops.ll b/test/Transforms/InstCombine/apint-elim-logicalops.ll
deleted file mode 100644
index ec60e45..0000000
--- a/test/Transforms/InstCombine/apint-elim-logicalops.ll
+++ /dev/null
@@ -1,39 +0,0 @@
-; Test that elimination of logical operators works with 
-; arbitrary precision integers.
-; RUN: opt < %s -instcombine -S | \
-; RUN:    not grep {(and\|xor\|add\|shl\|shr)}
-; END.
-
-define i33 @test1(i33 %x) {
-        %tmp.1 = and i33 %x, 65535           ; <i33> [#uses=1]
-        %tmp.2 = xor i33 %tmp.1, -32768      ; <i33> [#uses=1]
-        %tmp.3 = add i33 %tmp.2, 32768       ; <i33> [#uses=1]
-        ret i33 %tmp.3
-}
-
-define i33 @test2(i33 %x) {
-        %tmp.1 = and i33 %x, 65535           ; <i33> [#uses=1]
-        %tmp.2 = xor i33 %tmp.1, 32768       ; <i33> [#uses=1]
-        %tmp.3 = add i33 %tmp.2, -32768      ; <i33> [#uses=1]
-        ret i33 %tmp.3
-}
-
-define i33 @test3(i16 %P) {
-        %tmp.1 = zext i16 %P to i33          ; <i33> [#uses=1]
-        %tmp.4 = xor i33 %tmp.1, 32768       ; <i33> [#uses=1]
-        %tmp.5 = add i33 %tmp.4, -32768      ; <i33> [#uses=1]
-        ret i33 %tmp.5
-}
-
-define i33 @test5(i33 %x) {
-	%tmp.1 = and i33 %x, 254
-	%tmp.2 = xor i33 %tmp.1, 128
-	%tmp.3 = add i33 %tmp.2, -128
-	ret i33 %tmp.3
-}
-
-define i33 @test6(i33 %x) {
-        %tmp.2 = shl i33 %x, 16           ; <i33> [#uses=1]
-        %tmp.4 = lshr i33 %tmp.2, 16      ; <i33> [#uses=1]
-        ret i33 %tmp.4
-}
diff --git a/test/Transforms/InstCombine/bitcast-sext-vector.ll b/test/Transforms/InstCombine/bitcast-sext-vector.ll
new file mode 100644
index 0000000..d70bdba
--- /dev/null
+++ b/test/Transforms/InstCombine/bitcast-sext-vector.ll
@@ -0,0 +1,11 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+; CHECK: sext
+; Don't fold zero/sign extensions with a bitcast between a vector and scalar.
+
+define i32 @t(<4 x i8> %src1, <4 x i8> %src2) nounwind readonly {
+entry:
+	%cmp = icmp eq <4 x i8> %src1, %src2; <<4 x i1>> [#uses=1]
+	%sext = sext <4 x i1> %cmp to <4 x i8>
+	%val = bitcast <4 x i8> %sext to i32
+	ret i32 %val
+}
diff --git a/test/Transforms/InstCombine/canonicalize_branch.ll b/test/Transforms/InstCombine/canonicalize_branch.ll
index 52aff3d..24090ab 100644
--- a/test/Transforms/InstCombine/canonicalize_branch.ll
+++ b/test/Transforms/InstCombine/canonicalize_branch.ll
@@ -1,36 +1,44 @@
-; RUN: opt < %s -instcombine -S | \
-; RUN:    not grep {icmp ne\|icmp ule\|icmp uge}
+; RUN: opt < %s -instcombine -S | FileCheck %s
 
 define i32 @test1(i32 %X, i32 %Y) {
-        %C = icmp ne i32 %X, %Y         ; <i1> [#uses=1]
+        %C = icmp ne i32 %X, %Y
         br i1 %C, label %T, label %F
 
-T:              ; preds = %0
-        ret i32 12
+; CHECK: @test1
+; CHECK: %C = icmp eq i32 %X, %Y
+; CHECK: br i1 %C, label %F, label %T
 
-F:              ; preds = %0
+T:
+        ret i32 12
+F:
         ret i32 123
 }
 
 define i32 @test2(i32 %X, i32 %Y) {
-        %C = icmp ule i32 %X, %Y                ; <i1> [#uses=1]
+        %C = icmp ule i32 %X, %Y
         br i1 %C, label %T, label %F
 
-T:              ; preds = %0
-        ret i32 12
+; CHECK: @test2
+; CHECK: %C = icmp ugt i32 %X, %Y
+; CHECK: br i1 %C, label %F, label %T
 
-F:              ; preds = %0
+T:
+        ret i32 12
+F:
         ret i32 123
 }
 
 define i32 @test3(i32 %X, i32 %Y) {
-        %C = icmp uge i32 %X, %Y                ; <i1> [#uses=1]
+        %C = icmp uge i32 %X, %Y
         br i1 %C, label %T, label %F
 
-T:              ; preds = %0
-        ret i32 12
+; CHECK: @test3
+; CHECK: %C = icmp ult i32 %X, %Y
+; CHECK: br i1 %C, label %F, label %T
 
-F:              ; preds = %0
+T:
+        ret i32 12
+F:
         ret i32 123
 }
 
diff --git a/test/Transforms/InstCombine/fsub-fadd.ll b/test/Transforms/InstCombine/fsub-fadd.ll
deleted file mode 100644
index f4cff88..0000000
--- a/test/Transforms/InstCombine/fsub-fadd.ll
+++ /dev/null
@@ -1,39 +0,0 @@
-; RUN: opt < %s -instcombine -S | FileCheck %s
-; <rdar://problem/7530098>
-
-define void @func(double* %rhi, double* %rlo, double %xh, double %xl, double %yh, double %yl) nounwind ssp {
-entry:
-  %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
-  %tmp = fmul double %xh, 0x41A0000002000000      ; <double> [#uses=2]
-  %tmp1 = fsub double %xh, %tmp                   ; <double> [#uses=1]
-  %tmp2 = fadd double %tmp1, %tmp                 ; <double> [#uses=3]
-  %tmp3 = fsub double %xh, %tmp2                  ; <double> [#uses=2]
-  %tmp4 = fmul double %yh, 0x41A0000002000000     ; <double> [#uses=2]
-  %tmp5 = fsub double %yh, %tmp4                  ; <double> [#uses=1]
-  %tmp6 = fadd double %tmp5, %tmp4                ; <double> [#uses=3]
-  %tmp7 = fsub double %yh, %tmp6                  ; <double> [#uses=2]
-  %tmp8 = fmul double %xh, %yh                    ; <double> [#uses=3]
-  %tmp9 = fmul double %tmp2, %tmp6                ; <double> [#uses=1]
-  %tmp10 = fsub double %tmp9, %tmp8               ; <double> [#uses=1]
-  %tmp11 = fmul double %tmp2, %tmp7               ; <double> [#uses=1]
-  %tmp12 = fadd double %tmp10, %tmp11             ; <double> [#uses=1]
-  %tmp13 = fmul double %tmp3, %tmp6               ; <double> [#uses=1]
-  %tmp14 = fadd double %tmp12, %tmp13             ; <double> [#uses=1]
-  %tmp15 = fmul double %tmp3, %tmp7               ; <double> [#uses=1]
-  %tmp16 = fadd double %tmp14, %tmp15             ; <double> [#uses=1]
-  %tmp17 = fmul double %xh, %yl                   ; <double> [#uses=1]
-  %tmp18 = fmul double %xl, %yh                   ; <double> [#uses=1]
-  %tmp19 = fadd double %tmp17, %tmp18             ; <double> [#uses=1]
-  %tmp20 = fadd double %tmp19, %tmp16             ; <double> [#uses=2]
-  %tmp21 = fadd double %tmp8, %tmp20              ; <double> [#uses=1]
-  store double %tmp21, double* %rhi, align 8
-  %tmp22 = load double* %rhi, align 8             ; <double> [#uses=1]
-  %tmp23 = fsub double %tmp8, %tmp22              ; <double> [#uses=1]
-  %tmp24 = fadd double %tmp23, %tmp20             ; <double> [#uses=1]
-
-; CHECK: %tmp23 = fsub double %tmp8, %tmp21
-; CHECK: %tmp24 = fadd double %tmp23, %tmp20
-
-  store double %tmp24, double* %rlo, align 8
-  ret void
-}
diff --git a/test/Transforms/InstCombine/fsub-fsub.ll b/test/Transforms/InstCombine/fsub-fsub.ll
deleted file mode 100644
index 94ebf09..0000000
--- a/test/Transforms/InstCombine/fsub-fsub.ll
+++ /dev/null
@@ -1,8 +0,0 @@
-; RUN: opt < %s -instcombine -S | grep fsub | count 2
-; PR4374
-
-define float @func(float %a, float %b) nounwind {
-        %tmp3 = fsub float %a, %b
-        %tmp4 = fsub float -0.000000e+00, %tmp3
-        ret float %tmp4
-}
diff --git a/test/Transforms/InstCombine/fsub.ll b/test/Transforms/InstCombine/fsub.ll
new file mode 100644
index 0000000..af2fadd
--- /dev/null
+++ b/test/Transforms/InstCombine/fsub.ll
@@ -0,0 +1,23 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+; PR4374
+define float @test1(float %a, float %b) nounwind {
+  %t1 = fsub float %a, %b
+  %t2 = fsub float -0.000000e+00, %t1
+
+; CHECK:       %t1 = fsub float %a, %b
+; CHECK-NEXT:  %t2 = fsub float -0.000000e+00, %t1
+
+  ret float %t2
+}
+
+; <rdar://problem/7530098>
+define double @test2(double %x, double %y) nounwind {
+  %t1 = fadd double %x, %y
+  %t2 = fsub double %x, %t1
+
+; CHECK:      %t1 = fadd double %x, %y
+; CHECK-NEXT: %t2 = fsub double %x, %t1
+
+  ret double %t2
+}
diff --git a/test/Transforms/InstCombine/idioms.ll b/test/Transforms/InstCombine/idioms.ll
new file mode 100644
index 0000000..6b3567f
--- /dev/null
+++ b/test/Transforms/InstCombine/idioms.ll
@@ -0,0 +1,32 @@
+; RUN: opt -instcombine %s -S | FileCheck %s
+
+; Check that code corresponding to the following C function is
+; simplified into a single ASR operation:
+;
+; int test_asr(int a, int b) {
+;   return a < 0 ? -(-a - 1 >> b) - 1 : a >> b;
+; }
+;
+define i32 @test_asr(i32 %a, i32 %b) {
+entry:
+	%c = icmp slt i32 %a, 0
+	br i1 %c, label %bb2, label %bb3
+
+bb2:
+	%t1 = sub i32 0, %a
+	%not = sub i32 %t1, 1
+	%d = ashr i32 %not, %b
+	%t2 = sub i32 0, %d
+	%not2 = sub i32 %t2, 1
+	br label %bb4
+bb3:
+	%e = ashr i32 %a, %b
+	br label %bb4
+bb4:
+        %f = phi i32 [ %not2, %bb2 ], [ %e, %bb3 ]
+	ret i32 %f
+; CHECK: @test_asr
+; CHECK: bb4:
+; CHECK: %f = ashr i32 %a, %b
+; CHECK: ret i32 %f
+}
diff --git a/test/Transforms/InstCombine/signext.ll b/test/Transforms/InstCombine/signext.ll
index 008662e..1c52b62 100644
--- a/test/Transforms/InstCombine/signext.ll
+++ b/test/Transforms/InstCombine/signext.ll
@@ -1,12 +1,16 @@
-; RUN: opt < %s -instcombine -S | \
-; RUN:    not grep {(and\|xor\|add\|shl\|shr)}
-; END.
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128:n8:16:32:64"
 
 define i32 @test1(i32 %x) {
         %tmp.1 = and i32 %x, 65535              ; <i32> [#uses=1]
         %tmp.2 = xor i32 %tmp.1, -32768         ; <i32> [#uses=1]
         %tmp.3 = add i32 %tmp.2, 32768          ; <i32> [#uses=1]
         ret i32 %tmp.3
+; CHECK: @test1
+; CHECK: %sext1 = shl i32 %x, 16
+; CHECK: %tmp.3 = ashr i32 %sext1, 16
+; CHECK: ret i32 %tmp.3
 }
 
 define i32 @test2(i32 %x) {
@@ -14,6 +18,10 @@ define i32 @test2(i32 %x) {
         %tmp.2 = xor i32 %tmp.1, 32768          ; <i32> [#uses=1]
         %tmp.3 = add i32 %tmp.2, -32768         ; <i32> [#uses=1]
         ret i32 %tmp.3
+; CHECK: @test2
+; CHECK: %sext1 = shl i32 %x, 16
+; CHECK: %tmp.3 = ashr i32 %sext1, 16
+; CHECK: ret i32 %tmp.3
 }
 
 define i32 @test3(i16 %P) {
@@ -21,6 +29,9 @@ define i32 @test3(i16 %P) {
         %tmp.4 = xor i32 %tmp.1, 32768          ; <i32> [#uses=1]
         %tmp.5 = add i32 %tmp.4, -32768         ; <i32> [#uses=1]
         ret i32 %tmp.5
+; CHECK: @test3
+; CHECK: %tmp.5 = sext i16 %P to i32
+; CHECK: ret i32 %tmp.5
 }
 
 define i32 @test4(i16 %P) {
@@ -28,18 +39,38 @@ define i32 @test4(i16 %P) {
         %tmp.4 = xor i32 %tmp.1, 32768          ; <i32> [#uses=1]
         %tmp.5 = add i32 %tmp.4, -32768         ; <i32> [#uses=1]
         ret i32 %tmp.5
+; CHECK: @test4
+; CHECK: %tmp.5 = sext i16 %P to i32
+; CHECK: ret i32 %tmp.5
 }
 
 define i32 @test5(i32 %x) {
-        %tmp.1 = and i32 %x, 254                ; <i32> [#uses=1]
+        %tmp.1 = and i32 %x, 255                ; <i32> [#uses=1]
         %tmp.2 = xor i32 %tmp.1, 128            ; <i32> [#uses=1]
         %tmp.3 = add i32 %tmp.2, -128           ; <i32> [#uses=1]
         ret i32 %tmp.3
+; CHECK: @test5
+; CHECK: %sext1 = shl i32 %x, 24
+; CHECK: %tmp.3 = ashr i32 %sext1, 24
+; CHECK: ret i32 %tmp.3
 }
 
 define i32 @test6(i32 %x) {
         %tmp.2 = shl i32 %x, 16         ; <i32> [#uses=1]
         %tmp.4 = ashr i32 %tmp.2, 16            ; <i32> [#uses=1]
         ret i32 %tmp.4
+; CHECK: @test6
+; CHECK: %tmp.2 = shl i32 %x, 16
+; CHECK: %tmp.4 = ashr i32 %tmp.2, 16
+; CHECK: ret i32 %tmp.4
 }
 
+define i32 @test7(i16 %P) {
+  %tmp.1 = zext i16 %P to i32                     ; <i32> [#uses=1]
+  %sext1 = shl i32 %tmp.1, 16                     ; <i32> [#uses=1]
+  %tmp.5 = ashr i32 %sext1, 16                    ; <i32> [#uses=1]
+  ret i32 %tmp.5
+; CHECK: @test7
+; CHECK: %tmp.5 = sext i16 %P to i32
+; CHECK: ret i32 %tmp.5
+}
diff --git a/test/Transforms/InstCombine/xor2.ll b/test/Transforms/InstCombine/xor2.ll
index 23a9915..de3d65d 100644
--- a/test/Transforms/InstCombine/xor2.ll
+++ b/test/Transforms/InstCombine/xor2.ll
@@ -41,3 +41,13 @@ define i32 @test3(i32 %tmp1) {
   %ov110 = xor i32 %ov31, 153
   ret i32 %ov110
 }
+
+define i32 @test4(i32 %A, i32 %B) {
+	%1 = xor i32 %A, -1
+	%2 = ashr i32 %1, %B
+	%3 = xor i32 %2, -1
+	ret i32 %3
+; CHECK: @test4
+; CHECK: %1 = ashr i32 %A, %B
+; CHECK: ret i32 %1
+}
diff --git a/test/Transforms/LoopStrengthReduce/change-compare-stride-trickiness-0.ll b/test/Transforms/LoopStrengthReduce/change-compare-stride-trickiness-0.ll
index 56a89f6..36941ad 100644
--- a/test/Transforms/LoopStrengthReduce/change-compare-stride-trickiness-0.ll
+++ b/test/Transforms/LoopStrengthReduce/change-compare-stride-trickiness-0.ll
@@ -6,7 +6,7 @@ target triple = "x86_64-apple-darwin9"
 ; happens before the relevant use, so the comparison stride can't be
 ; easily changed.
 
-define void @foo() {
+define void @foo() nounwind {
 entry:
 	br label %loop
 
diff --git a/test/Transforms/LoopStrengthReduce/change-compare-stride-trickiness-1.ll b/test/Transforms/LoopStrengthReduce/change-compare-stride-trickiness-1.ll
index 8a3978b..ea8a259 100644
--- a/test/Transforms/LoopStrengthReduce/change-compare-stride-trickiness-1.ll
+++ b/test/Transforms/LoopStrengthReduce/change-compare-stride-trickiness-1.ll
@@ -1,10 +1,10 @@
-; RUN: llc %s -o - --x86-asm-syntax=att | grep {cmpq	\$8}
+; RUN: llc %s -o - --x86-asm-syntax=att | grep {cmp.	\$8}
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 target triple = "x86_64-apple-darwin9"
 
-; This is like change-compare-stride-trickiness-0.ll except the comparison
-; happens after the relevant use, so the comparison stride can be
-; easily changed.
+; The comparison happens after the relevant use, so the stride can easily
+; be changed. The comparison can be done in a narrower mode than the
+; induction variable.
 
 define void @foo() nounwind {
 entry:
diff --git a/test/Transforms/LoopStrengthReduce/icmp_use_postinc.ll b/test/Transforms/LoopStrengthReduce/icmp_use_postinc.ll
deleted file mode 100644
index 4ad5d14..0000000
--- a/test/Transforms/LoopStrengthReduce/icmp_use_postinc.ll
+++ /dev/null
@@ -1,27 +0,0 @@
-; RUN: opt < %s -loop-reduce -S | FileCheck %s
-
-define i32 @main(i32 %argc, i8** nocapture %argv) nounwind ssp {
-entry:
-  br i1 undef, label %bb4.preheader, label %bb.nph8
-
-bb4.preheader:                                    ; preds = %entry
-  br label %bb4
-
-bb1:                                              ; preds = %bb4
-  br i1 undef, label %bb.nph8, label %bb3
-
-bb3:                                              ; preds = %bb1
-  %phitmp = add i32 %indvar, 1                    ; <i32> [#uses=1]
-  br label %bb4
-
-bb4:                                              ; preds = %bb3, %bb4.preheader
-; CHECK: %lsr.iv = phi
-; CHECK: %lsr.iv.next = add i32 %lsr.iv, 1
-; CHECK: %0 = icmp slt i32 %lsr.iv.next, %argc
-  %indvar = phi i32 [ 1, %bb4.preheader ], [ %phitmp, %bb3 ] ; <i32> [#uses=2]
-  %0 = icmp slt i32 %indvar, %argc                ; <i1> [#uses=1]
-  br i1 %0, label %bb1, label %bb.nph8
-
-bb.nph8:                                          ; preds = %bb4, %bb1, %entry
-  unreachable
-}
diff --git a/test/Transforms/LoopStrengthReduce/related_indvars.ll b/test/Transforms/LoopStrengthReduce/related_indvars.ll
index 2494378..12942bf 100644
--- a/test/Transforms/LoopStrengthReduce/related_indvars.ll
+++ b/test/Transforms/LoopStrengthReduce/related_indvars.ll
@@ -7,7 +7,7 @@
 ;     *D++ = F;
 ; }
 
-define void @foo(double* %D, double* %E, double %F) {
+define void @foo(double* %D, double* %E, double %F) nounwind {
 entry:
 	%tmp.24 = icmp eq double* %D, %E		; <i1> [#uses=1]
 	br i1 %tmp.24, label %return, label %no_exit
diff --git a/test/Transforms/Mem2Reg/ConvertDebugInfo.ll b/test/Transforms/Mem2Reg/ConvertDebugInfo.ll
new file mode 100644
index 0000000..8e309c0
--- /dev/null
+++ b/test/Transforms/Mem2Reg/ConvertDebugInfo.ll
@@ -0,0 +1,31 @@
+; RUN: opt < %s -mem2reg -S | FileCheck %s
+
+target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128"
+
+define double @testfunc(i32 %i, double %j) {
+	%I = alloca i32		; <i32*> [#uses=4]
+  call void @llvm.dbg.declare(metadata !{i32* %I}, metadata !0)
+	%J = alloca double		; <double*> [#uses=2]
+  call void @llvm.dbg.declare(metadata !{double* %J}, metadata !1)
+; CHECK: call void @llvm.dbg.value(metadata !{i32 %i}, i64 0, metadata !0)
+	store i32 %i, i32* %I
+; CHECK: call void @llvm.dbg.value(metadata !{double %j}, i64 0, metadata !1)
+	store double %j, double* %J
+	%t1 = load i32* %I		; <i32> [#uses=1]
+	%t2 = add i32 %t1, 1		; <i32> [#uses=1]
+	store i32 %t2, i32* %I
+	%t3 = load i32* %I		; <i32> [#uses=1]
+	%t4 = sitofp i32 %t3 to double		; <double> [#uses=1]
+	%t5 = load double* %J		; <double> [#uses=1]
+	%t6 = fmul double %t4, %t5		; <double> [#uses=1]
+	ret double %t6
+}
+
+declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
+
+!bar = !{!0}
+!foo = !{!2}
+
+!0 = metadata !{i32 459008, metadata !1, metadata !"foo", metadata !2, i32 5, metadata !"foo"} ; [ DW_TAG_auto_variable ]
+!1 = metadata !{i32 459008, metadata !1, metadata !"foo", metadata !0, i32 5, metadata !1} ; [ DW_TAG_auto_variable ]
+!2 = metadata !{i32 458804, i32 0, metadata !2, metadata !"foo", metadata !"bar", metadata !"bar", metadata !2, i32 3, metadata !0, i1 false, i1 true} ; [ DW_TAG_variable ]
diff --git a/test/Transforms/Reassociate/inverses.ll b/test/Transforms/Reassociate/inverses.ll
index fa1a4bd..34abdc7 100644
--- a/test/Transforms/Reassociate/inverses.ll
+++ b/test/Transforms/Reassociate/inverses.ll
@@ -1,28 +1,34 @@
-; RUN: opt < %s -reassociate -dce -S | \
-; RUN:   not grep {\\(and\\|sub\\)}
+; RUN: opt < %s -reassociate -die -S | FileCheck %s
 
 define i32 @test1(i32 %a, i32 %b) {
-	%tmp.2 = and i32 %b, %a		; <i32> [#uses=1]
-	%tmp.4 = xor i32 %a, -1		; <i32> [#uses=1]
+	%tmp.2 = and i32 %b, %a
+	%tmp.4 = xor i32 %a, -1
         ; (A&B)&~A == 0
-	%tmp.5 = and i32 %tmp.2, %tmp.4		; <i32> [#uses=1]
+	%tmp.5 = and i32 %tmp.2, %tmp.4
 	ret i32 %tmp.5
+; CHECK: @test1
+; CHECK: ret i32 0
 }
 
 define i32 @test2(i32 %a, i32 %b) {
-	%tmp.1 = and i32 %a, 1234		; <i32> [#uses=1]
-	%tmp.2 = and i32 %b, %tmp.1		; <i32> [#uses=1]
-	%tmp.4 = xor i32 %a, -1		; <i32> [#uses=1]
+	%tmp.1 = and i32 %a, 1234
+	%tmp.2 = and i32 %b, %tmp.1
+	%tmp.4 = xor i32 %a, -1
 	; A&~A == 0
-        %tmp.5 = and i32 %tmp.2, %tmp.4		; <i32> [#uses=1]
+        %tmp.5 = and i32 %tmp.2, %tmp.4
 	ret i32 %tmp.5
+; CHECK: @test2
+; CHECK: ret i32 0
 }
 
 define i32 @test3(i32 %b, i32 %a) {
-	%tmp.1 = add i32 %a, 1234		; <i32> [#uses=1]
-	%tmp.2 = add i32 %b, %tmp.1		; <i32> [#uses=1]
-	%tmp.4 = sub i32 0, %a		; <i32> [#uses=1]
+	%tmp.1 = add i32 %a, 1234
+	%tmp.2 = add i32 %b, %tmp.1
+	%tmp.4 = sub i32 0, %a
         ; (b+(a+1234))+-a -> b+1234
-  	%tmp.5 = add i32 %tmp.2, %tmp.4		; <i32> [#uses=1]
+  	%tmp.5 = add i32 %tmp.2, %tmp.4
 	ret i32 %tmp.5
+; CHECK: @test3
+; CHECK: %tmp.5 = add i32 %b, 1234
+; CHECK: ret i32 %tmp.5
 }
diff --git a/test/Transforms/ScalarRepl/2010-01-18-SelfCopy.ll b/test/Transforms/ScalarRepl/2010-01-18-SelfCopy.ll
new file mode 100644
index 0000000..74cf251
--- /dev/null
+++ b/test/Transforms/ScalarRepl/2010-01-18-SelfCopy.ll
@@ -0,0 +1,18 @@
+; RUN: opt < %s -scalarrepl -S | FileCheck %s
+; Radar 7552893
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
+
+%struct.test = type { [3 x double ] }
+
+define arm_apcscc void @test_memcpy_self() nounwind {
+; CHECK: @test_memcpy_self
+; CHECK-NOT: alloca
+; CHECK: ret void
+  %1 = alloca %struct.test
+  %2 = bitcast %struct.test* %1 to i8*
+  call void @llvm.memcpy.i32(i8* %2, i8* %2, i32 24, i32 4)
+  ret void
+}
+
+declare void @llvm.memcpy.i32(i8* nocapture, i8* nocapture, i32, i32) nounwind
diff --git a/test/lit.cfg b/test/lit.cfg
index 246f270..8e85168 100644
--- a/test/lit.cfg
+++ b/test/lit.cfg
@@ -133,7 +133,7 @@ def llvm_gcc_supports(name):
 
 bindings = set(site_exp['llvm_bindings'].split(','))
 def llvm_supports_binding(name):
-    return name in langs
+    return name in bindings
 
 # Provide on_clone hook for reading 'dg.exp'.
 import os