diff options
| author | rdivacky <rdivacky@FreeBSD.org> | 2009-10-23 14:19:52 +0000 |
|---|---|---|
| committer | rdivacky <rdivacky@FreeBSD.org> | 2009-10-23 14:19:52 +0000 |
| commit | 9643cca39fb9fb3b49a8912926de98acf882283c (patch) | |
| tree | 22cc59e4b240d84c3a5a60531119c4eca914a256 /test | |
| parent | 1adacceba9c9ee0f16e54388e56c9a249b296f75 (diff) | |
| download | FreeBSD-src-9643cca39fb9fb3b49a8912926de98acf882283c.zip FreeBSD-src-9643cca39fb9fb3b49a8912926de98acf882283c.tar.gz | |
Update LLVM to r84949.
Diffstat (limited to 'test')
93 files changed, 1851 insertions, 256 deletions
diff --git a/test/Analysis/BasicAA/modref.ll b/test/Analysis/BasicAA/modref.ll index 8f7c0a7..69b60d7 100644 --- a/test/Analysis/BasicAA/modref.ll +++ b/test/Analysis/BasicAA/modref.ll @@ -1,15 +1,91 @@ -; A very rudimentary test on AliasAnalysis::getModRefInfo. -; RUN: opt < %s -print-all-alias-modref-info -aa-eval -disable-output |& \ -; RUN: not grep NoModRef +; RUN: opt < %s -basicaa -gvn -dse -S | FileCheck %s -define i32 @callee() { - %X = alloca { i32, i32 } ; <{ i32, i32 }*> [#uses=1] - %Y = getelementptr { i32, i32 }* %X, i64 0, i32 0 ; <i32*> [#uses=1] - %Z = load i32* %Y ; <i32> [#uses=1] - ret i32 %Z +declare void @llvm.memset.i32(i8*, i8, i32, i32) +declare void @llvm.memset.i8(i8*, i8, i8, i32) +declare void @llvm.memcpy.i8(i8*, i8*, i8, i32) +declare void @llvm.lifetime.end(i64, i8* nocapture) + +declare void @external(i32*) + +define i32 @test0(i8* %P) { + %A = alloca i32 + call void @external(i32* %A) + + store i32 0, i32* %A + + call void @llvm.memset.i32(i8* %P, i8 0, i32 42, i32 1) + + %B = load i32* %A + ret i32 %B + +; CHECK: @test0 +; CHECK: ret i32 0 } -define i32 @caller() { - %X = call i32 @callee( ) ; <i32> [#uses=1] - ret i32 %X +declare void @llvm.memcpy.i8(i8*, i8*, i8, i32) + +define i8 @test1() { +; CHECK: @test1 + %A = alloca i8 + %B = alloca i8 + + store i8 2, i8* %B ;; Not written to by memcpy + + call void @llvm.memcpy.i8(i8* %A, i8* %B, i8 -1, i32 0) + + %C = load i8* %B + ret i8 %C +; CHECK: ret i8 2 } + +define i8 @test2(i8* %P) { +; CHECK: @test2 + %P2 = getelementptr i8* %P, i32 127 + store i8 1, i8* %P2 ;; Not dead across memset + call void @llvm.memset.i8(i8* %P, i8 2, i8 127, i32 0) + %A = load i8* %P2 + ret i8 %A +; CHECK: ret i8 1 +} + +define i8 @test2a(i8* %P) { +; CHECK: @test2 + %P2 = getelementptr i8* %P, i32 126 + + ;; FIXME: DSE isn't zapping this dead store. + store i8 1, i8* %P2 ;; Dead, clobbered by memset. + + call void @llvm.memset.i8(i8* %P, i8 2, i8 127, i32 0) + %A = load i8* %P2 + ret i8 %A +; CHECK: %A = load i8* %P2 +; CHECK: ret i8 %A +} + +define void @test3(i8* %P, i8 %X) { +; CHECK: @test3 +; CHECK-NOT: store +; CHECK-NOT: %Y + %Y = add i8 %X, 1 ;; Dead, because the only use (the store) is dead. + + %P2 = getelementptr i8* %P, i32 2 + store i8 %Y, i8* %P2 ;; Not read by lifetime.end, should be removed. +; CHECK: store i8 2, i8* %P2 + call void @llvm.lifetime.end(i64 1, i8* %P) + store i8 2, i8* %P2 +; CHECK-NOT: store + ret void +; CHECK: ret void +} + +define void @test3a(i8* %P, i8 %X) { +; CHECK: @test3a + %Y = add i8 %X, 1 ;; Dead, because the only use (the store) is dead. + + %P2 = getelementptr i8* %P, i32 2 + store i8 %Y, i8* %P2 ;; FIXME: Killed by llvm.lifetime.end, should be zapped. +; CHECK: store i8 %Y, i8* %P2 + call void @llvm.lifetime.end(i64 10, i8* %P) + ret void +; CHECK: ret void +}
\ No newline at end of file diff --git a/test/Assembler/alignstack.ll b/test/Assembler/alignstack.ll new file mode 100644 index 0000000..9f2059f --- /dev/null +++ b/test/Assembler/alignstack.ll @@ -0,0 +1,36 @@ +; RUN: llvm-as < %s | llvm-dis | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" +target triple = "i386-apple-darwin10.0" + +define void @test1() nounwind { +; CHECK: test1 +; CHECK: sideeffect +; CHECK-NOT: alignstack + tail call void asm sideeffect "mov", "~{dirflag},~{fpsr},~{flags}"() nounwind + ret void +; CHECK: ret +} +define void @test2() nounwind { +; CHECK: test2 +; CHECK: sideeffect +; CHECK: alignstack + tail call void asm sideeffect alignstack "mov", "~{dirflag},~{fpsr},~{flags}"() nounwind + ret void +; CHECK: ret +} +define void @test3() nounwind { +; CHECK: test3 +; CHECK-NOT: sideeffect +; CHECK: alignstack + tail call void asm alignstack "mov", "~{dirflag},~{fpsr},~{flags}"() nounwind + ret void +; CHECK: ret +} +define void @test4() nounwind { +; CHECK: test4 +; CHECK-NOT: sideeffect +; CHECK-NOT: alignstack + tail call void asm "mov", "~{dirflag},~{fpsr},~{flags}"() nounwind + ret void +; CHECK: ret +} diff --git a/test/Bindings/Ocaml/vmcore.ml b/test/Bindings/Ocaml/vmcore.ml index 9e976d3..dd0404a 100644 --- a/test/Bindings/Ocaml/vmcore.ml +++ b/test/Bindings/Ocaml/vmcore.ml @@ -936,9 +936,9 @@ let test_builder () = group "memory"; begin let bb08 = append_block context "Bb08" fn in let b = builder_at_end context bb08 in - - (* RUN: grep {Inst20.*malloc.*i8 } < %t.ll - * RUN: grep {Inst21.*malloc.*i8.*P1} < %t.ll + + (* RUN: grep {Inst20.*malloc} < %t.ll + * RUN: grep {Inst21.*malloc} < %t.ll * RUN: grep {Inst22.*alloca.*i32 } < %t.ll * RUN: grep {Inst23.*alloca.*i32.*P2} < %t.ll * RUN: grep {free.*Inst20} < %t.ll diff --git a/test/CodeGen/ARM/2009-10-21-InvalidFNeg.ll b/test/CodeGen/ARM/2009-10-21-InvalidFNeg.ll new file mode 100644 index 0000000..0f021d2 --- /dev/null +++ b/test/CodeGen/ARM/2009-10-21-InvalidFNeg.ll @@ -0,0 +1,48 @@ +; RUN: llc -mcpu=cortex-a8 -mattr=+neon < %s | grep vneg +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" +target triple = "armv7-eabi" + +%aaa = type { %fff, %fff } +%bbb = type { [6 x %ddd] } +%ccc = type { %eee, %fff } +%ddd = type { %fff } +%eee = type { %fff, %fff, %fff, %fff } +%fff = type { %struct.vec_float4 } +%struct.vec_float4 = type { <4 x float> } + +define linkonce_odr arm_aapcs_vfpcc void @foo(%eee* noalias sret %agg.result, i64 %tfrm.0.0, i64 %tfrm.0.1, i64 %tfrm.0.2, i64 %tfrm.0.3, i64 %tfrm.0.4, i64 %tfrm.0.5, i64 %tfrm.0.6, i64 %tfrm.0.7) nounwind noinline { +entry: + %tmp104 = zext i64 %tfrm.0.2 to i512 ; <i512> [#uses=1] + %tmp105 = shl i512 %tmp104, 128 ; <i512> [#uses=1] + %tmp118 = zext i64 %tfrm.0.3 to i512 ; <i512> [#uses=1] + %tmp119 = shl i512 %tmp118, 192 ; <i512> [#uses=1] + %ins121 = or i512 %tmp119, %tmp105 ; <i512> [#uses=1] + %tmp99 = zext i64 %tfrm.0.4 to i512 ; <i512> [#uses=1] + %tmp100 = shl i512 %tmp99, 256 ; <i512> [#uses=1] + %tmp123 = zext i64 %tfrm.0.5 to i512 ; <i512> [#uses=1] + %tmp124 = shl i512 %tmp123, 320 ; <i512> [#uses=1] + %tmp96 = zext i64 %tfrm.0.6 to i512 ; <i512> [#uses=1] + %tmp97 = shl i512 %tmp96, 384 ; <i512> [#uses=1] + %tmp128 = zext i64 %tfrm.0.7 to i512 ; <i512> [#uses=1] + %tmp129 = shl i512 %tmp128, 448 ; <i512> [#uses=1] + %mask.masked = or i512 %tmp124, %tmp100 ; <i512> [#uses=1] + %ins131 = or i512 %tmp129, %tmp97 ; <i512> [#uses=1] + %tmp109132 = zext i64 %tfrm.0.0 to i128 ; <i128> [#uses=1] + %tmp113134 = zext i64 %tfrm.0.1 to i128 ; <i128> [#uses=1] + %tmp114133 = shl i128 %tmp113134, 64 ; <i128> [#uses=1] + %tmp94 = or i128 %tmp114133, %tmp109132 ; <i128> [#uses=1] + %tmp95 = bitcast i128 %tmp94 to <4 x float> ; <<4 x float>> [#uses=0] + %tmp82 = lshr i512 %ins121, 128 ; <i512> [#uses=1] + %tmp83 = trunc i512 %tmp82 to i128 ; <i128> [#uses=1] + %tmp84 = bitcast i128 %tmp83 to <4 x float> ; <<4 x float>> [#uses=0] + %tmp86 = lshr i512 %mask.masked, 256 ; <i512> [#uses=1] + %tmp87 = trunc i512 %tmp86 to i128 ; <i128> [#uses=1] + %tmp88 = bitcast i128 %tmp87 to <4 x float> ; <<4 x float>> [#uses=0] + %tmp90 = lshr i512 %ins131, 384 ; <i512> [#uses=1] + %tmp91 = trunc i512 %tmp90 to i128 ; <i128> [#uses=1] + %tmp92 = bitcast i128 %tmp91 to <4 x float> ; <<4 x float>> [#uses=1] + %tmp = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %tmp92 ; <<4 x float>> [#uses=1] + %tmp28 = getelementptr inbounds %eee* %agg.result, i32 0, i32 3, i32 0, i32 0 ; <<4 x float>*> [#uses=1] + store <4 x float> %tmp, <4 x float>* %tmp28, align 16 + ret void +} diff --git a/test/CodeGen/ARM/globals.ll b/test/CodeGen/ARM/globals.ll new file mode 100644 index 0000000..8ed58bd --- /dev/null +++ b/test/CodeGen/ARM/globals.ll @@ -0,0 +1,75 @@ +; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=static | FileCheck %s -check-prefix=DarwinStatic +; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=dynamic-no-pic | FileCheck %s -check-prefix=DarwinDynamic +; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic | FileCheck %s -check-prefix=DarwinPIC +; RUN: llc < %s -mtriple=arm-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=LinuxPIC + +@G = external global i32 + +define i32 @test1() { + %tmp = load i32* @G + ret i32 %tmp +} + +; DarwinStatic: _test1: +; DarwinStatic: ldr r0, LCPI1_0 +; DarwinStatic: ldr r0, [r0] +; DarwinStatic: bx lr + +; DarwinStatic: .align 2 +; DarwinStatic: LCPI1_0: +; DarwinStatic: .long {{_G$}} + + +; DarwinDynamic: _test1: +; DarwinDynamic: ldr r0, LCPI1_0 +; DarwinDynamic: ldr r0, [r0] +; DarwinDynamic: ldr r0, [r0] +; DarwinDynamic: bx lr + +; DarwinDynamic: .align 2 +; DarwinDynamic: LCPI1_0: +; DarwinDynamic: .long L_G$non_lazy_ptr + +; DarwinDynamic: .section __DATA,__nl_symbol_ptr,non_lazy_symbol_pointers +; DarwinDynamic: .align 2 +; DarwinDynamic: L_G$non_lazy_ptr: +; DarwinDynamic: .indirect_symbol _G +; DarwinDynamic: .long 0 + + + +; DarwinPIC: _test1: +; DarwinPIC: ldr r0, LCPI1_0 +; DarwinPIC: LPC0: +; DarwinPIC: ldr r0, [pc, +r0] +; DarwinPIC: ldr r0, [r0] +; DarwinPIC: bx lr + +; DarwinPIC: .align 2 +; DarwinPIC: LCPI1_0: +; DarwinPIC: .long L_G$non_lazy_ptr-(LPC0+8) + +; DarwinPIC: .section __DATA,__nl_symbol_ptr,non_lazy_symbol_pointers +; DarwinPIC: .align 2 +; DarwinPIC: L_G$non_lazy_ptr: +; DarwinPIC: .indirect_symbol _G +; DarwinPIC: .long 0 + + + +; LinuxPIC: test1: +; LinuxPIC: ldr r0, .LCPI1_0 +; LinuxPIC: ldr r1, .LCPI1_1 + +; LinuxPIC: .LPC0: +; LinuxPIC: add r0, pc, r0 +; LinuxPIC: ldr r0, [r1, +r0] +; LinuxPIC: ldr r0, [r0] +; LinuxPIC: bx lr + +; LinuxPIC: .align 2 +; LinuxPIC: .LCPI1_0: +; LinuxPIC: .long _GLOBAL_OFFSET_TABLE_-(.LPC0+8) +; LinuxPIC: .align 2 +; LinuxPIC: .LCPI1_1: +; LinuxPIC: .long G(GOT) diff --git a/test/CodeGen/ARM/ldrd.ll b/test/CodeGen/ARM/ldrd.ll index 8f7ae55..c366e2d 100644 --- a/test/CodeGen/ARM/ldrd.ll +++ b/test/CodeGen/ARM/ldrd.ll @@ -7,13 +7,13 @@ define i64 @t(i64 %a) nounwind readonly { entry: -;V6: ldrd r2, [r2] +;V6: ldrd r2, [r2] -;V5: ldr r3, [r2] -;V5-NEXT: ldr r2, [r2, #+4] +;V5: ldr r3, [r2] +;V5: ldr r2, [r2, #+4] -;EABI: ldr r3, [r2] -;EABI-NEXT: ldr r2, [r2, #+4] +;EABI: ldr r3, [r2] +;EABI: ldr r2, [r2, #+4] %0 = load i64** @b, align 4 %1 = load i64* %0, align 4 diff --git a/test/CodeGen/ARM/movt.ll b/test/CodeGen/ARM/movt.ll new file mode 100644 index 0000000..e82aca0 --- /dev/null +++ b/test/CodeGen/ARM/movt.ll @@ -0,0 +1,19 @@ +; RUN: llc < %s -march=arm -mattr=+thumb2 | FileCheck %s +; rdar://7317664 + +define i32 @t(i32 %X) nounwind { +; CHECK: t: +; CHECK: movt r0, #65535 +entry: + %0 = or i32 %X, -65536 + ret i32 %0 +} + +define i32 @t2(i32 %X) nounwind { +; CHECK: t2: +; CHECK: movt r0, #65534 +entry: + %0 = or i32 %X, -131072 + %1 = and i32 %0, -65537 + ret i32 %1 +} diff --git a/test/CodeGen/ARM/sbfx.ll b/test/CodeGen/ARM/sbfx.ll index 923f52a..6f1d87d 100644 --- a/test/CodeGen/ARM/sbfx.ll +++ b/test/CodeGen/ARM/sbfx.ll @@ -35,3 +35,13 @@ entry: %tmp2 = lshr i32 %tmp, 29 ret i32 %tmp2 } + +define i32 @f5(i32 %a) { +entry: +; CHECK: f5: +; CHECK-NOT: sbfx +; CHECK: bx + %tmp = shl i32 %a, 3 + %tmp2 = ashr i32 %tmp, 1 + ret i32 %tmp2 +} diff --git a/test/CodeGen/Blackfin/sync-intr.ll b/test/CodeGen/Blackfin/sync-intr.ll index 75084f0..0b103a3 100644 --- a/test/CodeGen/Blackfin/sync-intr.ll +++ b/test/CodeGen/Blackfin/sync-intr.ll @@ -2,8 +2,11 @@ define void @f() nounwind { entry: + ; CHECK-NOT: llvm.bfin ; CHECK: csync; call void @llvm.bfin.csync() + + ; CHECK-NOT: llvm.bfin ; CHECK: ssync; call void @llvm.bfin.ssync() ret void diff --git a/test/CodeGen/CellSPU/2009-01-01-BrCond.ll b/test/CodeGen/CellSPU/2009-01-01-BrCond.ll index 3542231..58e3190 100644 --- a/test/CodeGen/CellSPU/2009-01-01-BrCond.ll +++ b/test/CodeGen/CellSPU/2009-01-01-BrCond.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=cellspu -o - | grep brz +; RUN: llc < %s -march=cellspu -o - | grep brnz ; PR3274 target datalayout = "E-p:32:32:128-i1:8:128-i8:8:128-i16:16:128-i32:32:128-i64:32:128-f32:32:128-f64:64:128-v64:64:64-v128:128:128-a0:0:128-s0:128:128" diff --git a/test/CodeGen/CellSPU/useful-harnesses/lit.local.cfg b/test/CodeGen/CellSPU/useful-harnesses/lit.local.cfg new file mode 100644 index 0000000..e6f55ee --- /dev/null +++ b/test/CodeGen/CellSPU/useful-harnesses/lit.local.cfg @@ -0,0 +1 @@ +config.suffixes = [] diff --git a/test/CodeGen/Generic/switch-lower-feature-2.ll b/test/CodeGen/Generic/switch-lower-feature-2.ll index d6e5647..80e0618 100644 --- a/test/CodeGen/Generic/switch-lower-feature-2.ll +++ b/test/CodeGen/Generic/switch-lower-feature-2.ll @@ -5,9 +5,9 @@ ; RUN: grep 1023 %t | count 1 ; RUN: grep 119 %t | count 1 ; RUN: grep JTI %t | count 2 -; RUN: grep jg %t | count 1 +; RUN: grep jg %t | count 3 ; RUN: grep ja %t | count 1 -; RUN: grep js %t | count 1 +; RUN: grep jns %t | count 1 target triple = "i686-pc-linux-gnu" diff --git a/test/CodeGen/MSP430/Inst16ri.ll b/test/CodeGen/MSP430/Inst16ri.ll new file mode 100644 index 0000000..5115a23 --- /dev/null +++ b/test/CodeGen/MSP430/Inst16ri.ll @@ -0,0 +1,37 @@ +; RUN: llc -march=msp430 < %s | FileCheck %s +target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8" +target triple = "msp430-generic-generic" + +define i16 @mov() nounwind { +; CHECK: mov: +; CHECK: mov.w #1, r15 + ret i16 1 +} + +define i16 @add(i16 %a, i16 %b) nounwind { +; CHECK: add: +; CHECK: add.w #1, r15 + %1 = add i16 %a, 1 + ret i16 %1 +} + +define i16 @and(i16 %a, i16 %b) nounwind { +; CHECK: and: +; CHECK: and.w #1, r15 + %1 = and i16 %a, 1 + ret i16 %1 +} + +define i16 @bis(i16 %a, i16 %b) nounwind { +; CHECK: bis: +; CHECK: bis.w #1, r15 + %1 = or i16 %a, 1 + ret i16 %1 +} + +define i16 @xor(i16 %a, i16 %b) nounwind { +; CHECK: xor: +; CHECK: xor.w #1, r15 + %1 = xor i16 %a, 1 + ret i16 %1 +} diff --git a/test/CodeGen/MSP430/Inst8ri.ll b/test/CodeGen/MSP430/Inst8ri.ll new file mode 100644 index 0000000..ac3418a --- /dev/null +++ b/test/CodeGen/MSP430/Inst8ri.ll @@ -0,0 +1,37 @@ +; RUN: llc -march=msp430 < %s | FileCheck %s +target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8" +target triple = "msp430-generic-generic" + +define i8 @mov() nounwind { +; CHECK: mov: +; CHECK: mov.b #1, r15 + ret i8 1 +} + +define i8 @add(i8 %a, i8 %b) nounwind { +; CHECK: add: +; CHECK: add.b #1, r15 + %1 = add i8 %a, 1 + ret i8 %1 +} + +define i8 @and(i8 %a, i8 %b) nounwind { +; CHECK: and: +; CHECK: and.b #1, r15 + %1 = and i8 %a, 1 + ret i8 %1 +} + +define i8 @bis(i8 %a, i8 %b) nounwind { +; CHECK: bis: +; CHECK: bis.b #1, r15 + %1 = or i8 %a, 1 + ret i8 %1 +} + +define i8 @xor(i8 %a, i8 %b) nounwind { +; CHECK: xor: +; CHECK: xor.b #1, r15 + %1 = xor i8 %a, 1 + ret i8 %1 +} diff --git a/test/CodeGen/PIC16/globals.ll b/test/CodeGen/PIC16/globals.ll index 959eb25..b8c9116 100644 --- a/test/CodeGen/PIC16/globals.ll +++ b/test/CodeGen/PIC16/globals.ll @@ -1,15 +1,15 @@ ; RUN: llc < %s -march=pic16 | FileCheck %s @G1 = global i32 4712, section "Address=412" -; CHECK: @G1.412.idata.0.# IDATA 412 +; CHECK: @G1.412..user_section.# IDATA 412 ; CHECK: @G1 dl 4712 @G2 = global i32 0, section "Address=412" -; CHECK: @G2.412.udata.0.# UDATA 412 +; CHECK: @G2.412..user_section.# UDATA 412 ; CHECK: @G2 RES 4 @G3 = addrspace(1) constant i32 4712, section "Address=412" -; CHECK: @G3.412.romdata.1.# ROMDATA 412 +; CHECK: @G3.412..user_section.# ROMDATA 412 ; CHECK: @G3 rom_dl 4712 diff --git a/test/CodeGen/Thumb/2009-08-20-ISelBug.ll b/test/CodeGen/Thumb/2009-08-20-ISelBug.ll index 1627f61..c31b65b 100644 --- a/test/CodeGen/Thumb/2009-08-20-ISelBug.ll +++ b/test/CodeGen/Thumb/2009-08-20-ISelBug.ll @@ -11,7 +11,7 @@ define arm_apcscc i32 @t(%struct.asl_file_t* %s, i64 %off, i64* %out) nounwind optsize { ; CHECK: t: -; CHECK: adds r4, #8 +; CHECK: adds r3, #8 entry: %val = alloca i64, align 4 ; <i64*> [#uses=3] %0 = icmp eq %struct.asl_file_t* %s, null ; <i1> [#uses=1] diff --git a/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll b/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll new file mode 100644 index 0000000..b4b6ed9 --- /dev/null +++ b/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll @@ -0,0 +1,44 @@ +; RUN: llc < %s -mtriple=thumbv7-eabi -mcpu=cortex-a8 -float-abi=hard | FileCheck %s + +; A fix for PR5204 will require this check to be changed. + +%"struct.__gnu_cxx::__normal_iterator<char*,std::basic_string<char, std::char_traits<char>, std::allocator<char> > >" = type { i8* } +%"struct.__gnu_cxx::new_allocator<char>" = type <{ i8 }> +%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >" = type { %"struct.__gnu_cxx::__normal_iterator<char*,std::basic_string<char, std::char_traits<char>, std::allocator<char> > >" } +%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >::_Rep" = type { %"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >::_Rep_base" } +%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >::_Rep_base" = type { i32, i32, i32 } + + +define weak arm_aapcs_vfpcc i32 @_ZNKSs7compareERKSs(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this, %"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) { +; CHECK: _ZNKSs7compareERKSs: +; CHECK: it ne +; CHECK-NEXT: ldmfdne.w +; CHECK-NEXT: itt eq +; CHECK-NEXT: subeq.w +; CHECK-NEXT: ldmfdeq.w +entry: + %0 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this) ; <i32> [#uses=3] + %1 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) ; <i32> [#uses=3] + %2 = icmp ult i32 %1, %0 ; <i1> [#uses=1] + %3 = select i1 %2, i32 %1, i32 %0 ; <i32> [#uses=1] + %4 = tail call arm_aapcs_vfpcc i8* @_ZNKSs7_M_dataEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this) ; <i8*> [#uses=1] + %5 = tail call arm_aapcs_vfpcc i8* @_ZNKSs4dataEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) ; <i8*> [#uses=1] + %6 = tail call arm_aapcs_vfpcc i32 @memcmp(i8* %4, i8* %5, i32 %3) nounwind readonly ; <i32> [#uses=2] + %7 = icmp eq i32 %6, 0 ; <i1> [#uses=1] + br i1 %7, label %bb, label %bb1 + +bb: ; preds = %entry + %8 = sub i32 %0, %1 ; <i32> [#uses=1] + ret i32 %8 + +bb1: ; preds = %entry + ret i32 %6 +} + +declare arm_aapcs_vfpcc i32 @memcmp(i8* nocapture, i8* nocapture, i32) nounwind readonly + +declare arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this) + +declare arm_aapcs_vfpcc i8* @_ZNKSs7_M_dataEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this) + +declare arm_aapcs_vfpcc i8* @_ZNKSs4dataEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this) diff --git a/test/CodeGen/Thumb2/thumb2-mov.ll b/test/CodeGen/Thumb2/thumb2-mov.ll index e9fdec8..8606e32 100644 --- a/test/CodeGen/Thumb2/thumb2-mov.ll +++ b/test/CodeGen/Thumb2/thumb2-mov.ll @@ -10,29 +10,32 @@ define i32 @t2_const_var2_1_ok_1(i32 %lhs) { ret i32 %ret } -define i32 @t2_const_var2_1_fail_1(i32 %lhs) { -;CHECK: t2_const_var2_1_fail_1: -;CHECK: movt +define i32 @t2_const_var2_1_ok_2(i32 %lhs) { +;CHECK: t2_const_var2_1_ok_2: +;CHECK: #11206656 +;CHECK: #187 %ret = add i32 %lhs, 11206843 ; 0x00ab00bb ret i32 %ret } -define i32 @t2_const_var2_1_fail_2(i32 %lhs) { -;CHECK: t2_const_var2_1_fail_2: -;CHECK: movt +define i32 @t2_const_var2_1_ok_3(i32 %lhs) { +;CHECK: t2_const_var2_1_ok_3: +;CHECK: #11206827 +;CHECK: #16777216 %ret = add i32 %lhs, 27984043 ; 0x01ab00ab ret i32 %ret } -define i32 @t2_const_var2_1_fail_3(i32 %lhs) { -;CHECK: t2_const_var2_1_fail_3: -;CHECK: movt +define i32 @t2_const_var2_1_ok_4(i32 %lhs) { +;CHECK: t2_const_var2_1_ok_4: +;CHECK: #16777472 +;CHECK: #11206827 %ret = add i32 %lhs, 27984299 ; 0x01ab01ab ret i32 %ret } -define i32 @t2_const_var2_1_fail_4(i32 %lhs) { -;CHECK: t2_const_var2_1_fail_4: +define i32 @t2_const_var2_1_fail_1(i32 %lhs) { +;CHECK: t2_const_var2_1_fail_1: ;CHECK: movt %ret = add i32 %lhs, 28027649 ; 0x01abab01 ret i32 %ret @@ -46,29 +49,31 @@ define i32 @t2_const_var2_2_ok_1(i32 %lhs) { ret i32 %ret } -define i32 @t2_const_var2_2_fail_1(i32 %lhs) { -;CHECK: t2_const_var2_2_fail_1: -;CHECK: movt +define i32 @t2_const_var2_2_ok_2(i32 %lhs) { +;CHECK: t2_const_var2_2_ok_2: +;CHECK: #-1426063360 +;CHECK: #47616 %ret = add i32 %lhs, 2868951552 ; 0xab00ba00 ret i32 %ret } -define i32 @t2_const_var2_2_fail_2(i32 %lhs) { -;CHECK: t2_const_var2_2_fail_2: -;CHECK: movt +define i32 @t2_const_var2_2_ok_3(i32 %lhs) { +;CHECK: t2_const_var2_2_ok_3: +;CHECK: #-1426019584 %ret = add i32 %lhs, 2868947728 ; 0xab00ab10 ret i32 %ret } -define i32 @t2_const_var2_2_fail_3(i32 %lhs) { -;CHECK: t2_const_var2_2_fail_3: -;CHECK: movt +define i32 @t2_const_var2_2_ok_4(i32 %lhs) { +;CHECK: t2_const_var2_2_ok_4: +;CHECK: #-1426019584 +;CHECK: #1048592 %ret = add i32 %lhs, 2869996304 ; 0xab10ab10 ret i32 %ret } -define i32 @t2_const_var2_2_fail_4(i32 %lhs) { -;CHECK: t2_const_var2_2_fail_4: +define i32 @t2_const_var2_2_fail_1(i32 %lhs) { +;CHECK: t2_const_var2_2_fail_1: ;CHECK: movt %ret = add i32 %lhs, 279685904 ; 0x10abab10 ret i32 %ret @@ -125,9 +130,10 @@ define i32 @t2_const_var3_2_ok_1(i32 %lhs) { ret i32 %ret } -define i32 @t2_const_var3_2_fail_1(i32 %lhs) { -;CHECK: t2_const_var3_2_fail_1: -;CHECK: movt +define i32 @t2_const_var3_2_ok_2(i32 %lhs) { +;CHECK: t2_const_var3_2_ok_2: +;CHECK: #2097152 +;CHECK: #1843200 %ret = add i32 %lhs, 3940352 ; 0b00000000001111000010000000000000 ret i32 %ret } diff --git a/test/CodeGen/Thumb2/thumb2-mov2.ll b/test/CodeGen/Thumb2/thumb2-mov2.ll index a02f4f0..64e2ddc 100644 --- a/test/CodeGen/Thumb2/thumb2-mov2.ll +++ b/test/CodeGen/Thumb2/thumb2-mov2.ll @@ -2,10 +2,7 @@ define i32 @t2MOVTi16_ok_1(i32 %a) { ; CHECK: t2MOVTi16_ok_1: -; CHECK: movs r1, #0 -; CHECK-NEXT: movt r1, #1234 -; CHECK: movw r1, #65535 -; CHECK-NEXT: movt r1, #1234 +; CHECK: movt r0, #1234 %1 = and i32 %a, 65535 %2 = shl i32 1234, 16 %3 = or i32 %1, %2 @@ -15,10 +12,7 @@ define i32 @t2MOVTi16_ok_1(i32 %a) { define i32 @t2MOVTi16_test_1(i32 %a) { ; CHECK: t2MOVTi16_test_1: -; CHECK: movs r1, #0 -; CHECK-NEXT: movt r1, #1234 -; CHECK: movw r1, #65535 -; CHECK-NEXT: movt r1, #1234 +; CHECK: movt r0, #1234 %1 = shl i32 255, 8 %2 = shl i32 1234, 8 %3 = or i32 %1, 255 ; This give us 0xFFFF in %3 @@ -31,10 +25,7 @@ define i32 @t2MOVTi16_test_1(i32 %a) { define i32 @t2MOVTi16_test_2(i32 %a) { ; CHECK: t2MOVTi16_test_2: -; CHECK: movs r1, #0 -; CHECK-NEXT: movt r1, #1234 -; CHECK: movw r1, #65535 -; CHECK-NEXT: movt r1, #1234 +; CHECK: movt r0, #1234 %1 = shl i32 255, 8 %2 = shl i32 1234, 8 %3 = or i32 %1, 255 ; This give us 0xFFFF in %3 @@ -48,10 +39,7 @@ define i32 @t2MOVTi16_test_2(i32 %a) { define i32 @t2MOVTi16_test_3(i32 %a) { ; CHECK: t2MOVTi16_test_3: -; CHECK: movs r1, #0 -; CHECK-NEXT: movt r1, #1234 -; CHECK: movw r1, #65535 -; CHECK-NEXT: movt r1, #1234 +; CHECK: movt r0, #1234 %1 = shl i32 255, 8 %2 = shl i32 1234, 8 %3 = or i32 %1, 255 ; This give us 0xFFFF in %3 @@ -67,10 +55,10 @@ define i32 @t2MOVTi16_test_3(i32 %a) { define i32 @t2MOVTi16_test_nomatch_1(i32 %a) { ; CHECK: t2MOVTi16_test_nomatch_1: -; CHECK: movw r1, #16384 -; CHECK-NEXT: movt r1, #154 +; CHECK: #8388608 ; CHECK: movw r1, #65535 ; CHECK-NEXT: movt r1, #154 +; CHECK: #1720320 %1 = shl i32 255, 8 %2 = shl i32 1234, 8 %3 = or i32 %1, 255 ; This give us 0xFFFF in %3 diff --git a/test/CodeGen/X86/2007-01-08-InstrSched.ll b/test/CodeGen/X86/2007-01-08-InstrSched.ll index e1bae32..81f0a1d 100644 --- a/test/CodeGen/X86/2007-01-08-InstrSched.ll +++ b/test/CodeGen/X86/2007-01-08-InstrSched.ll @@ -11,9 +11,12 @@ define float @foo(float %x) nounwind { %tmp14 = fadd float %tmp12, %tmp7 ret float %tmp14 -; CHECK: mulss LCPI1_2(%rip) +; CHECK: mulss LCPI1_3(%rip) +; CHECK-NEXT: mulss LCPI1_0(%rip) +; CHECK-NEXT: mulss LCPI1_1(%rip) +; CHECK-NEXT: mulss LCPI1_2(%rip) +; CHECK-NEXT: addss ; CHECK-NEXT: addss -; CHECK-NEXT: mulss LCPI1_3(%rip) ; CHECK-NEXT: addss ; CHECK-NEXT: ret } diff --git a/test/CodeGen/X86/2008-07-11-SpillerBug.ll b/test/CodeGen/X86/2008-07-11-SpillerBug.ll index f75e605..88a5fde 100644 --- a/test/CodeGen/X86/2008-07-11-SpillerBug.ll +++ b/test/CodeGen/X86/2008-07-11-SpillerBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -relocation-model=static -disable-fp-elim | FileCheck %s +; RUN: llc < %s -march=x86 -relocation-model=static -disable-fp-elim -post-RA-scheduler=false | FileCheck %s ; PR2536 diff --git a/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll b/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll index 4d25b0f..d7b9463 100644 --- a/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll +++ b/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=pic -disable-fp-elim -stats |& grep asm-printer | grep 84 +; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=pic -disable-fp-elim -stats |& grep asm-printer | grep 83 ; rdar://6802189 ; Test if linearscan is unfavoring registers for allocation to allow more reuse diff --git a/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll b/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll index c6e6e50..5bd956a 100644 --- a/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll +++ b/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=i386-apple-darwin10.0 -relocation-model=pic \ -; RUN: -disable-fp-elim -mattr=-sse41,-sse3,+sse2 < %s | \ +; RUN: -disable-fp-elim -mattr=-sse41,-sse3,+sse2 -post-RA-scheduler=false < %s | \ ; RUN: FileCheck %s ; rdar://6808032 diff --git a/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll b/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll index 646806e..f3cf1d5 100644 --- a/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll +++ b/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll @@ -9,9 +9,7 @@ entry: br label %bb bb: ; preds = %bb1, %entry -; CHECK: movl %e -; CHECK-NEXT: addl $1 -; CHECK-NEXT: movl %e +; CHECK: addl $1 ; CHECK-NEXT: adcl $0 %i.0 = phi i64 [ 0, %entry ], [ %0, %bb1 ] ; <i64> [#uses=1] %0 = add nsw i64 %i.0, 1 ; <i64> [#uses=2] diff --git a/test/CodeGen/X86/2009-10-14-LiveVariablesBug.ll b/test/CodeGen/X86/2009-10-14-LiveVariablesBug.ll new file mode 100644 index 0000000..c1aa17c --- /dev/null +++ b/test/CodeGen/X86/2009-10-14-LiveVariablesBug.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -mtriple=i386-apple-darwin +; rdar://7299435 + +@i = internal global i32 0 ; <i32*> [#uses=1] +@llvm.used = appending global [1 x i8*] [i8* bitcast (void (i16)* @foo to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] + +define void @foo(i16 signext %source) nounwind ssp { +entry: + %source_addr = alloca i16, align 2 ; <i16*> [#uses=2] + store i16 %source, i16* %source_addr + store i32 4, i32* @i, align 4 + call void asm sideeffect "# top of block", "~{dirflag},~{fpsr},~{flags},~{edi},~{esi},~{edx},~{ecx},~{eax}"() nounwind + %asmtmp = call i16 asm sideeffect "movw $1, $0", "=={ax},*m,~{dirflag},~{fpsr},~{flags},~{memory}"(i16* %source_addr) nounwind ; <i16> [#uses=0] + ret void +} diff --git a/test/CodeGen/X86/2009-10-19-EmergencySpill.ll b/test/CodeGen/X86/2009-10-19-EmergencySpill.ll new file mode 100644 index 0000000..ba44a2e --- /dev/null +++ b/test/CodeGen/X86/2009-10-19-EmergencySpill.ll @@ -0,0 +1,54 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -disable-fp-elim +; rdar://7291624 + +%union.RtreeCoord = type { float } +%struct.RtreeCell = type { i64, [10 x %union.RtreeCoord] } +%struct.Rtree = type { i32, i32*, i32, i32, i32, i32, i8*, i8* } +%struct.RtreeNode = type { i32*, i64, i32, i32, i8*, i32* } + +define fastcc void @nodeOverwriteCell(%struct.Rtree* nocapture %pRtree, %struct.RtreeNode* nocapture %pNode, %struct.RtreeCell* nocapture %pCell, i32 %iCell) nounwind ssp { +entry: + %0 = load i8** undef, align 8 ; <i8*> [#uses=2] + %1 = load i32* undef, align 8 ; <i32> [#uses=1] + %2 = mul i32 %1, %iCell ; <i32> [#uses=1] + %3 = add nsw i32 %2, 4 ; <i32> [#uses=1] + %4 = sext i32 %3 to i64 ; <i64> [#uses=2] + %5 = load i64* null, align 8 ; <i64> [#uses=2] + %6 = lshr i64 %5, 48 ; <i64> [#uses=1] + %7 = trunc i64 %6 to i8 ; <i8> [#uses=1] + store i8 %7, i8* undef, align 1 + %8 = lshr i64 %5, 8 ; <i64> [#uses=1] + %9 = trunc i64 %8 to i8 ; <i8> [#uses=1] + %.sum4 = add i64 %4, 6 ; <i64> [#uses=1] + %10 = getelementptr inbounds i8* %0, i64 %.sum4 ; <i8*> [#uses=1] + store i8 %9, i8* %10, align 1 + %11 = getelementptr inbounds %struct.Rtree* %pRtree, i64 0, i32 3 ; <i32*> [#uses=1] + br i1 undef, label %bb.nph, label %bb2 + +bb.nph: ; preds = %entry + %tmp25 = add i64 %4, 11 ; <i64> [#uses=1] + br label %bb + +bb: ; preds = %bb, %bb.nph + %indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %bb ] ; <i64> [#uses=3] + %scevgep = getelementptr %struct.RtreeCell* %pCell, i64 0, i32 1, i64 %indvar ; <%union.RtreeCoord*> [#uses=1] + %scevgep12 = bitcast %union.RtreeCoord* %scevgep to i32* ; <i32*> [#uses=1] + %tmp = shl i64 %indvar, 2 ; <i64> [#uses=1] + %tmp26 = add i64 %tmp, %tmp25 ; <i64> [#uses=1] + %scevgep27 = getelementptr i8* %0, i64 %tmp26 ; <i8*> [#uses=1] + %12 = load i32* %scevgep12, align 4 ; <i32> [#uses=1] + %13 = lshr i32 %12, 24 ; <i32> [#uses=1] + %14 = trunc i32 %13 to i8 ; <i8> [#uses=1] + store i8 %14, i8* undef, align 1 + store i8 undef, i8* %scevgep27, align 1 + %15 = load i32* %11, align 4 ; <i32> [#uses=1] + %16 = shl i32 %15, 1 ; <i32> [#uses=1] + %17 = icmp sgt i32 %16, undef ; <i1> [#uses=1] + %indvar.next = add i64 %indvar, 1 ; <i64> [#uses=1] + br i1 %17, label %bb, label %bb2 + +bb2: ; preds = %bb, %entry + %18 = getelementptr inbounds %struct.RtreeNode* %pNode, i64 0, i32 3 ; <i32*> [#uses=1] + store i32 1, i32* %18, align 4 + ret void +} diff --git a/test/CodeGen/X86/2009-10-19-atomic-cmp-eflags.ll b/test/CodeGen/X86/2009-10-19-atomic-cmp-eflags.ll new file mode 100644 index 0000000..d7f0c1a --- /dev/null +++ b/test/CodeGen/X86/2009-10-19-atomic-cmp-eflags.ll @@ -0,0 +1,69 @@ +; RUN: llvm-as <%s | llc | FileCheck %s +; PR 5247 +; check that cmp is not scheduled before the add +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target triple = "x86_64-unknown-linux-gnu" + +@.str76843 = external constant [45 x i8] ; <[45 x i8]*> [#uses=1] +@__profiling_callsite_timestamps_live = external global [1216 x i64] ; <[1216 x i64]*> [#uses=2] + +define i32 @cl_init(i32 %initoptions) nounwind { +entry: + %retval.i = alloca i32 ; <i32*> [#uses=3] + %retval = alloca i32 ; <i32*> [#uses=2] + %initoptions.addr = alloca i32 ; <i32*> [#uses=2] + tail call void asm sideeffect "cpuid", "~{ax},~{bx},~{cx},~{dx},~{memory},~{dirflag},~{fpsr},~{flags}"() nounwind + %0 = tail call i64 @llvm.readcyclecounter() nounwind ; <i64> [#uses=1] + store i32 %initoptions, i32* %initoptions.addr + %1 = bitcast i32* %initoptions.addr to { }* ; <{ }*> [#uses=0] + call void asm sideeffect "cpuid", "~{ax},~{bx},~{cx},~{dx},~{memory},~{dirflag},~{fpsr},~{flags}"() nounwind + %2 = call i64 @llvm.readcyclecounter() nounwind ; <i64> [#uses=1] + %call.i = call i32 @lt_dlinit() nounwind ; <i32> [#uses=1] + %tobool.i = icmp ne i32 %call.i, 0 ; <i1> [#uses=1] + br i1 %tobool.i, label %if.then.i, label %if.end.i + +if.then.i: ; preds = %entry + %call1.i = call i32 @warn_dlerror(i8* getelementptr inbounds ([45 x i8]* @.str76843, i32 0, i32 0)) nounwind ; <i32> [#uses=0] + store i32 -1, i32* %retval.i + br label %lt_init.exit + +if.end.i: ; preds = %entry + store i32 0, i32* %retval.i + br label %lt_init.exit + +lt_init.exit: ; preds = %if.end.i, %if.then.i + %3 = load i32* %retval.i ; <i32> [#uses=1] + call void asm sideeffect "cpuid", "~{ax},~{bx},~{cx},~{dx},~{memory},~{dirflag},~{fpsr},~{flags}"() nounwind + %4 = call i64 @llvm.readcyclecounter() nounwind ; <i64> [#uses=1] + %5 = sub i64 %4, %2 ; <i64> [#uses=1] + %6 = call i64 @llvm.atomic.load.add.i64.p0i64(i64* getelementptr inbounds ([1216 x i64]* @__profiling_callsite_timestamps_live, i32 0, i32 51), i64 %5) nounwind ; <i64> [#uses=0] +;CHECK: lock +;CHECK-NEXT: {{xadd|addq}} %rdx, __profiling_callsite_timestamps_live +;CHECK-NEXT: cmpl $0, +;CHECK-NEXT: jne + %cmp = icmp eq i32 %3, 0 ; <i1> [#uses=1] + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %lt_init.exit + call void @cli_rarload() + br label %if.end + +if.end: ; preds = %if.then, %lt_init.exit + store i32 0, i32* %retval + %7 = load i32* %retval ; <i32> [#uses=1] + tail call void asm sideeffect "cpuid", "~{ax},~{bx},~{cx},~{dx},~{memory},~{dirflag},~{fpsr},~{flags}"() nounwind + %8 = tail call i64 @llvm.readcyclecounter() nounwind ; <i64> [#uses=1] + %9 = sub i64 %8, %0 ; <i64> [#uses=1] + %10 = call i64 @llvm.atomic.load.add.i64.p0i64(i64* getelementptr inbounds ([1216 x i64]* @__profiling_callsite_timestamps_live, i32 0, i32 50), i64 %9) ; <i64> [#uses=0] + ret i32 %7 +} + +declare void @cli_rarload() nounwind + +declare i32 @lt_dlinit() + +declare i32 @warn_dlerror(i8*) nounwind + +declare i64 @llvm.atomic.load.add.i64.p0i64(i64* nocapture, i64) nounwind + +declare i64 @llvm.readcyclecounter() nounwind diff --git a/test/CodeGen/X86/abi-isel.ll b/test/CodeGen/X86/abi-isel.ll index a6fd2d8..6d7b2d4 100644 --- a/test/CodeGen/X86/abi-isel.ll +++ b/test/CodeGen/X86/abi-isel.ll @@ -1,16 +1,16 @@ -; RUN: llc < %s -asm-verbose=0 -mtriple=i686-unknown-linux-gnu -march=x86 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=LINUX-32-STATIC -; RUN: llc < %s -asm-verbose=0 -mtriple=i686-unknown-linux-gnu -march=x86 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=LINUX-32-PIC +; RUN: llc < %s -asm-verbose=0 -mtriple=i686-unknown-linux-gnu -march=x86 -relocation-model=static -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=LINUX-32-STATIC +; RUN: llc < %s -asm-verbose=0 -mtriple=i686-unknown-linux-gnu -march=x86 -relocation-model=static -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=LINUX-32-PIC -; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=LINUX-64-STATIC -; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=LINUX-64-PIC +; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=static -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=LINUX-64-STATIC +; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=pic -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=LINUX-64-PIC -; RUN: llc < %s -asm-verbose=0 -mtriple=i686-apple-darwin -march=x86 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=DARWIN-32-STATIC -; RUN: llc < %s -asm-verbose=0 -mtriple=i686-apple-darwin -march=x86 -relocation-model=dynamic-no-pic -code-model=small | FileCheck %s -check-prefix=DARWIN-32-DYNAMIC -; RUN: llc < %s -asm-verbose=0 -mtriple=i686-apple-darwin -march=x86 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=DARWIN-32-PIC +; RUN: llc < %s -asm-verbose=0 -mtriple=i686-apple-darwin -march=x86 -relocation-model=static -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=DARWIN-32-STATIC +; RUN: llc < %s -asm-verbose=0 -mtriple=i686-apple-darwin -march=x86 -relocation-model=dynamic-no-pic -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=DARWIN-32-DYNAMIC +; RUN: llc < %s -asm-verbose=0 -mtriple=i686-apple-darwin -march=x86 -relocation-model=pic -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=DARWIN-32-PIC -; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=DARWIN-64-STATIC -; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=dynamic-no-pic -code-model=small | FileCheck %s -check-prefix=DARWIN-64-DYNAMIC -; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=DARWIN-64-PIC +; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=static -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=DARWIN-64-STATIC +; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=dynamic-no-pic -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=DARWIN-64-DYNAMIC +; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=pic -code-model=small -post-RA-scheduler=false | FileCheck %s -check-prefix=DARWIN-64-PIC @src = external global [131072 x i32] @dst = external global [131072 x i32] diff --git a/test/CodeGen/X86/codegen-prepare-extload.ll b/test/CodeGen/X86/codegen-prepare-extload.ll new file mode 100644 index 0000000..9f57d53 --- /dev/null +++ b/test/CodeGen/X86/codegen-prepare-extload.ll @@ -0,0 +1,20 @@ +; RUN: llc < %s -march=x86-64 | FileCheck %s +; rdar://7304838 + +; CodeGenPrepare should move the zext into the block with the load +; so that SelectionDAG can select it with the load. + +; CHECK: movzbl (%rdi), %eax + +define void @foo(i8* %p, i32* %q) { +entry: + %t = load i8* %p + %a = icmp slt i8 %t, 20 + br i1 %a, label %true, label %false +true: + %s = zext i8 %t to i32 + store i32 %s, i32* %q + ret void +false: + ret void +} diff --git a/test/CodeGen/X86/discontiguous-loops.ll b/test/CodeGen/X86/discontiguous-loops.ll new file mode 100644 index 0000000..479c450 --- /dev/null +++ b/test/CodeGen/X86/discontiguous-loops.ll @@ -0,0 +1,72 @@ +; RUN: llc -verify-loop-info -verify-dom-info -march=x86-64 < %s +; PR5243 + +@.str96 = external constant [37 x i8], align 8 ; <[37 x i8]*> [#uses=1] + +define void @foo() nounwind { +bb: + br label %ybb1 + +ybb1: ; preds = %yybb13, %xbb6, %bb + switch i32 undef, label %bb18 [ + i32 150, label %ybb2 + i32 151, label %bb17 + i32 152, label %bb19 + i32 157, label %ybb8 + ] + +ybb2: ; preds = %ybb1 + %tmp = icmp eq i8** undef, null ; <i1> [#uses=1] + br i1 %tmp, label %bb3, label %xbb6 + +bb3: ; preds = %ybb2 + unreachable + +xbb4: ; preds = %xbb6 + store i32 0, i32* undef, align 8 + br i1 undef, label %xbb6, label %bb5 + +bb5: ; preds = %xbb4 + call fastcc void @decl_mode_check_failed() nounwind + unreachable + +xbb6: ; preds = %xbb4, %ybb2 + %tmp7 = icmp slt i32 undef, 0 ; <i1> [#uses=1] + br i1 %tmp7, label %xbb4, label %ybb1 + +ybb8: ; preds = %ybb1 + %tmp9 = icmp eq i8** undef, null ; <i1> [#uses=1] + br i1 %tmp9, label %bb10, label %ybb12 + +bb10: ; preds = %ybb8 + %tmp11 = load i8** undef, align 8 ; <i8*> [#uses=1] + call void (i8*, ...)* @fatal(i8* getelementptr inbounds ([37 x i8]* @.str96, i64 0, i64 0), i8* %tmp11) nounwind + unreachable + +ybb12: ; preds = %ybb8 + br i1 undef, label %bb15, label %ybb13 + +ybb13: ; preds = %ybb12 + %tmp14 = icmp sgt i32 undef, 0 ; <i1> [#uses=1] + br i1 %tmp14, label %bb16, label %ybb1 + +bb15: ; preds = %ybb12 + call void (i8*, ...)* @fatal(i8* getelementptr inbounds ([37 x i8]* @.str96, i64 0, i64 0), i8* undef) nounwind + unreachable + +bb16: ; preds = %ybb13 + unreachable + +bb17: ; preds = %ybb1 + unreachable + +bb18: ; preds = %ybb1 + unreachable + +bb19: ; preds = %ybb1 + unreachable +} + +declare void @fatal(i8*, ...) + +declare fastcc void @decl_mode_check_failed() nounwind diff --git a/test/CodeGen/X86/fastcc.ll b/test/CodeGen/X86/fastcc.ll index d538264..705ab7b 100644 --- a/test/CodeGen/X86/fastcc.ll +++ b/test/CodeGen/X86/fastcc.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | FileCheck %s +; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 -post-RA-scheduler=false | FileCheck %s ; CHECK: movsd %xmm0, 8(%esp) ; CHECK: xorl %ecx, %ecx diff --git a/test/CodeGen/X86/legalize-fmp-oeq-vector-select.ll b/test/CodeGen/X86/legalize-fmp-oeq-vector-select.ll new file mode 100644 index 0000000..6a8c154 --- /dev/null +++ b/test/CodeGen/X86/legalize-fmp-oeq-vector-select.ll @@ -0,0 +1,11 @@ +; RUN: llc -march=x86-64 -enable-legalize-types-checking < %s +; PR5092 + +define <4 x float> @bug(float %a) nounwind { +entry: + %cmp = fcmp oeq float %a, 0.000000e+00 ; <i1> [#uses=1] + %temp = select i1 %cmp, <4 x float> <float 1.000000e+00, float 0.000000e+00, +float 0.000000e+00, float 0.000000e+00>, <4 x float> zeroinitializer + ret <4 x float> %temp +} + diff --git a/test/CodeGen/X86/loop-blocks.ll b/test/CodeGen/X86/loop-blocks.ll new file mode 100644 index 0000000..c0379d1 --- /dev/null +++ b/test/CodeGen/X86/loop-blocks.ll @@ -0,0 +1,207 @@ +; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -asm-verbose=false | FileCheck %s + +; These tests check for loop branching structure, and that the loop align +; directive is placed in the expected place. + +; CodeGen should insert a branch into the middle of the loop in +; order to avoid a branch within the loop. + +; CHECK: simple: +; CHECK: jmp .LBB1_1 +; CHECK-NEXT: align +; CHECK-NEXT: .LBB1_2: +; CHECK-NEXT: call loop_latch +; CHECK-NEXT: .LBB1_1: +; CHECK-NEXT: call loop_header + +define void @simple() nounwind { +entry: + br label %loop + +loop: + call void @loop_header() + %t0 = tail call i32 @get() + %t1 = icmp slt i32 %t0, 0 + br i1 %t1, label %done, label %bb + +bb: + call void @loop_latch() + br label %loop + +done: + call void @exit() + ret void +} + +; CodeGen should move block_a to the top of the loop so that it +; falls through into the loop, avoiding a branch within the loop. + +; CHECK: slightly_more_involved: +; CHECK: jmp .LBB2_1 +; CHECK-NEXT: align +; CHECK-NEXT: .LBB2_4: +; CHECK-NEXT: call bar99 +; CHECK-NEXT: .LBB2_1: +; CHECK-NEXT: call body + +define void @slightly_more_involved() nounwind { +entry: + br label %loop + +loop: + call void @body() + %t0 = call i32 @get() + %t1 = icmp slt i32 %t0, 2 + br i1 %t1, label %block_a, label %bb + +bb: + %t2 = call i32 @get() + %t3 = icmp slt i32 %t2, 99 + br i1 %t3, label %exit, label %loop + +block_a: + call void @bar99() + br label %loop + +exit: + call void @exit() + ret void +} + +; Same as slightly_more_involved, but block_a is now a CFG diamond with +; fallthrough edges which should be preserved. + +; CHECK: yet_more_involved: +; CHECK: jmp .LBB3_1 +; CHECK-NEXT: align +; CHECK-NEXT: .LBB3_3: +; CHECK-NEXT: call bar99 +; CHECK-NEXT: call get +; CHECK-NEXT: cmpl $2999, %eax +; CHECK-NEXT: jg .LBB3_5 +; CHECK-NEXT: call block_a_true_func +; CHECK-NEXT: jmp .LBB3_6 +; CHECK-NEXT: .LBB3_5: +; CHECK-NEXT: call block_a_false_func +; CHECK-NEXT: .LBB3_6: +; CHECK-NEXT: call block_a_merge_func +; CHECK-NEXT: .LBB3_1: +; CHECK-NEXT: call body + +define void @yet_more_involved() nounwind { +entry: + br label %loop + +loop: + call void @body() + %t0 = call i32 @get() + %t1 = icmp slt i32 %t0, 2 + br i1 %t1, label %block_a, label %bb + +bb: + %t2 = call i32 @get() + %t3 = icmp slt i32 %t2, 99 + br i1 %t3, label %exit, label %loop + +block_a: + call void @bar99() + %z0 = call i32 @get() + %z1 = icmp slt i32 %z0, 3000 + br i1 %z1, label %block_a_true, label %block_a_false + +block_a_true: + call void @block_a_true_func() + br label %block_a_merge + +block_a_false: + call void @block_a_false_func() + br label %block_a_merge + +block_a_merge: + call void @block_a_merge_func() + br label %loop + +exit: + call void @exit() + ret void +} + +; CodeGen should move the CFG islands that are part of the loop but don't +; conveniently fit anywhere so that they are at least contiguous with the +; loop. + +; CHECK: cfg_islands: +; CHECK: jmp .LBB4_1 +; CHECK-NEXT: align +; CHECK-NEXT: .LBB4_7: +; CHECK-NEXT: call bar100 +; CHECK-NEXT: jmp .LBB4_1 +; CHECK-NEXT: .LBB4_8: +; CHECK-NEXT: call bar101 +; CHECK-NEXT: jmp .LBB4_1 +; CHECK-NEXT: .LBB4_9: +; CHECK-NEXT: call bar102 +; CHECK-NEXT: jmp .LBB4_1 +; CHECK-NEXT: .LBB4_5: +; CHECK-NEXT: call loop_latch +; CHECK-NEXT: .LBB4_1: +; CHECK-NEXT: call loop_header + +define void @cfg_islands() nounwind { +entry: + br label %loop + +loop: + call void @loop_header() + %t0 = call i32 @get() + %t1 = icmp slt i32 %t0, 100 + br i1 %t1, label %block100, label %bb + +bb: + %t2 = call i32 @get() + %t3 = icmp slt i32 %t2, 101 + br i1 %t3, label %block101, label %bb1 + +bb1: + %t4 = call i32 @get() + %t5 = icmp slt i32 %t4, 102 + br i1 %t5, label %block102, label %bb2 + +bb2: + %t6 = call i32 @get() + %t7 = icmp slt i32 %t6, 103 + br i1 %t7, label %exit, label %bb3 + +bb3: + call void @loop_latch() + br label %loop + +exit: + call void @exit() + ret void + +block100: + call void @bar100() + br label %loop + +block101: + call void @bar101() + br label %loop + +block102: + call void @bar102() + br label %loop +} + +declare void @bar99() nounwind +declare void @bar100() nounwind +declare void @bar101() nounwind +declare void @bar102() nounwind +declare void @body() nounwind +declare void @exit() nounwind +declare void @loop_header() nounwind +declare void @loop_latch() nounwind +declare i32 @get() nounwind +declare void @block_a_true_func() nounwind +declare void @block_a_false_func() nounwind +declare void @block_a_merge_func() nounwind diff --git a/test/CodeGen/X86/palignr.ll b/test/CodeGen/X86/palignr.ll new file mode 100644 index 0000000..3812c72 --- /dev/null +++ b/test/CodeGen/X86/palignr.ll @@ -0,0 +1,58 @@ +; RUN: llc < %s -march=x86 -mcpu=core2 | FileCheck %s +; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck --check-prefix=YONAH %s + +define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind { +; CHECK: pshufd +; CHECK-YONAH: pshufd + %C = shufflevector <4 x i32> %A, <4 x i32> undef, <4 x i32> < i32 1, i32 2, i32 3, i32 0 > + ret <4 x i32> %C +} + +define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) nounwind { +; CHECK: palignr +; CHECK-YONAH: shufps + %C = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> < i32 1, i32 2, i32 3, i32 4 > + ret <4 x i32> %C +} + +define <4 x i32> @test3(<4 x i32> %A, <4 x i32> %B) nounwind { +; CHECK: palignr + %C = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> < i32 1, i32 2, i32 undef, i32 4 > + ret <4 x i32> %C +} + +define <4 x i32> @test4(<4 x i32> %A, <4 x i32> %B) nounwind { +; CHECK: palignr + %C = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> < i32 6, i32 7, i32 undef, i32 1 > + ret <4 x i32> %C +} + +define <4 x float> @test5(<4 x float> %A, <4 x float> %B) nounwind { +; CHECK: palignr + %C = shufflevector <4 x float> %A, <4 x float> %B, <4 x i32> < i32 6, i32 7, i32 undef, i32 1 > + ret <4 x float> %C +} + +define <8 x i16> @test6(<8 x i16> %A, <8 x i16> %B) nounwind { +; CHECK: palignr + %C = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 3, i32 4, i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10 > + ret <8 x i16> %C +} + +define <8 x i16> @test7(<8 x i16> %A, <8 x i16> %B) nounwind { +; CHECK: palignr + %C = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 undef, i32 6, i32 undef, i32 8, i32 9, i32 10, i32 11, i32 12 > + ret <8 x i16> %C +} + +define <8 x i16> @test8(<8 x i16> %A, <8 x i16> %B) nounwind { +; CHECK: palignr + %C = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 undef, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0 > + ret <8 x i16> %C +} + +define <16 x i8> @test9(<16 x i8> %A, <16 x i8> %B) nounwind { +; CHECK: palignr + %C = shufflevector <16 x i8> %A, <16 x i8> %B, <16 x i32> < i32 5, i32 6, i32 7, i32 undef, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20 > + ret <16 x i8> %C +} diff --git a/test/CodeGen/X86/peep-test-3.ll b/test/CodeGen/X86/peep-test-3.ll index 13a69ed..5aaf81b 100644 --- a/test/CodeGen/X86/peep-test-3.ll +++ b/test/CodeGen/X86/peep-test-3.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 | FileCheck %s +; RUN: llc < %s -march=x86 -post-RA-scheduler=false | FileCheck %s ; rdar://7226797 ; LLVM should omit the testl and use the flags result from the orl. diff --git a/test/CodeGen/X86/pic.ll b/test/CodeGen/X86/pic.ll index 3a547f9..e886ba0 100644 --- a/test/CodeGen/X86/pic.ll +++ b/test/CodeGen/X86/pic.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i686-pc-linux-gnu -relocation-model=pic -asm-verbose=false | FileCheck %s -check-prefix=LINUX +; RUN: llc < %s -mtriple=i686-pc-linux-gnu -relocation-model=pic -asm-verbose=false -post-RA-scheduler=false | FileCheck %s -check-prefix=LINUX @ptr = external global i32* @dst = external global i32 diff --git a/test/CodeGen/X86/sink-hoist.ll b/test/CodeGen/X86/sink-hoist.ll index 0f4e63f..4042a09 100644 --- a/test/CodeGen/X86/sink-hoist.ll +++ b/test/CodeGen/X86/sink-hoist.ll @@ -6,10 +6,10 @@ ; that it's conditionally evaluated. ; CHECK: foo: -; CHECK-NEXT: divsd -; CHECK: testb $1, %dil -; CHECK-NEXT: jne ; CHECK: divsd +; CHECK-NEXT: testb $1, %dil +; CHECK-NEXT: jne +; CHECK-NEXT: divsd define double @foo(double %x, double %y, i1 %c) nounwind { %a = fdiv double %x, 3.2 diff --git a/test/CodeGen/X86/sse2.ll b/test/CodeGen/X86/sse2.ll index 9f926f2..58fe28b 100644 --- a/test/CodeGen/X86/sse2.ll +++ b/test/CodeGen/X86/sse2.ll @@ -10,10 +10,10 @@ define void @t1(<2 x double>* %r, <2 x double>* %A, double %B) nounwind { ; CHECK: t1: ; CHECK: movl 8(%esp), %eax +; CHECK-NEXT: movl 4(%esp), %ecx ; CHECK-NEXT: movapd (%eax), %xmm0 ; CHECK-NEXT: movlpd 12(%esp), %xmm0 -; CHECK-NEXT: movl 4(%esp), %eax -; CHECK-NEXT: movapd %xmm0, (%eax) +; CHECK-NEXT: movapd %xmm0, (%ecx) ; CHECK-NEXT: ret } @@ -26,9 +26,9 @@ define void @t2(<2 x double>* %r, <2 x double>* %A, double %B) nounwind { ; CHECK: t2: ; CHECK: movl 8(%esp), %eax +; CHECK-NEXT: movl 4(%esp), %ecx ; CHECK-NEXT: movapd (%eax), %xmm0 ; CHECK-NEXT: movhpd 12(%esp), %xmm0 -; CHECK-NEXT: movl 4(%esp), %eax -; CHECK-NEXT: movapd %xmm0, (%eax) +; CHECK-NEXT: movapd %xmm0, (%ecx) ; CHECK-NEXT: ret } diff --git a/test/CodeGen/X86/sse3.ll b/test/CodeGen/X86/sse3.ll index 703635c..6319cb8 100644 --- a/test/CodeGen/X86/sse3.ll +++ b/test/CodeGen/X86/sse3.ll @@ -17,8 +17,8 @@ entry: ; X64: t0: ; X64: movddup (%rsi), %xmm0 -; X64: pshuflw $0, %xmm0, %xmm0 ; X64: xorl %eax, %eax +; X64: pshuflw $0, %xmm0, %xmm0 ; X64: pinsrw $0, %eax, %xmm0 ; X64: movaps %xmm0, (%rdi) ; X64: ret @@ -167,18 +167,12 @@ define internal void @t10() nounwind { store <4 x i16> %6, <4 x i16>* @g2, align 8 ret void ; X64: t10: -; X64: movq _g1@GOTPCREL(%rip), %rax -; X64: movaps (%rax), %xmm0 ; X64: pextrw $4, %xmm0, %eax -; X64: movaps %xmm0, %xmm1 +; X64: pextrw $6, %xmm0, %edx ; X64: movlhps %xmm1, %xmm1 ; X64: pshuflw $8, %xmm1, %xmm1 ; X64: pinsrw $2, %eax, %xmm1 -; X64: pextrw $6, %xmm0, %eax -; X64: pinsrw $3, %eax, %xmm1 -; X64: movq _g2@GOTPCREL(%rip), %rax -; X64: movq %xmm1, (%rax) -; X64: ret +; X64: pinsrw $3, %edx, %xmm1 } @@ -189,8 +183,8 @@ entry: ret <8 x i16> %tmp7 ; X64: t11: -; X64: movd %xmm1, %eax ; X64: movlhps %xmm0, %xmm0 +; X64: movd %xmm1, %eax ; X64: pshuflw $1, %xmm0, %xmm0 ; X64: pinsrw $1, %eax, %xmm0 ; X64: ret @@ -203,8 +197,8 @@ entry: ret <8 x i16> %tmp9 ; X64: t12: -; X64: pextrw $3, %xmm1, %eax ; X64: movlhps %xmm0, %xmm0 +; X64: pextrw $3, %xmm1, %eax ; X64: pshufhw $3, %xmm0, %xmm0 ; X64: pinsrw $5, %eax, %xmm0 ; X64: ret @@ -256,18 +250,12 @@ entry: %tmp9 = shufflevector <16 x i8> %tmp8, <16 x i8> %T0, <16 x i32> < i32 0, i32 1, i32 2, i32 17, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef > ret <16 x i8> %tmp9 ; X64: t16: -; X64: movaps LCPI17_0(%rip), %xmm1 -; X64: movd %xmm1, %eax ; X64: pinsrw $0, %eax, %xmm1 ; X64: pextrw $8, %xmm0, %eax ; X64: pinsrw $1, %eax, %xmm1 ; X64: pextrw $1, %xmm1, %ecx ; X64: movd %xmm1, %edx ; X64: pinsrw $0, %edx, %xmm1 -; X64: movzbl %cl, %ecx -; X64: andw $-256, %ax -; X64: orw %cx, %ax -; X64: movaps %xmm1, %xmm0 ; X64: pinsrw $1, %eax, %xmm0 ; X64: ret } diff --git a/test/CodeGen/X86/stack-color-with-reg.ll b/test/CodeGen/X86/stack-color-with-reg.ll index 672f77e..0f32a50 100644 --- a/test/CodeGen/X86/stack-color-with-reg.ll +++ b/test/CodeGen/X86/stack-color-with-reg.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -relocation-model=pic -disable-fp-elim -color-ss-with-regs -stats -info-output-file - > %t -; RUN: grep stackcoloring %t | grep "stack slot refs replaced with reg refs" | grep 5 -; RUN: grep asm-printer %t | grep 179 +; RUN: grep stackcoloring %t | grep "stack slot refs replaced with reg refs" | grep 6 +; RUN: grep asm-printer %t | grep 177 type { [62 x %struct.Bitvec*] } ; type %0 type { i8* } ; type %1 diff --git a/test/CodeGen/X86/tailcallstack64.ll b/test/CodeGen/X86/tailcallstack64.ll index 73c59bb..69018aa 100644 --- a/test/CodeGen/X86/tailcallstack64.ll +++ b/test/CodeGen/X86/tailcallstack64.ll @@ -3,19 +3,18 @@ ; Check that lowered arguments on the stack do not overwrite each other. ; Add %in1 %p1 to a different temporary register (%eax). ; CHECK: movl %edi, %eax -; CHECK: addl 32(%rsp), %eax ; Move param %in1 to temp register (%r10d). ; CHECK: movl 40(%rsp), %r10d -; Move result of addition to stack. -; CHECK: movl %eax, 40(%rsp) ; Move param %in2 to stack. ; CHECK: movl %r10d, 32(%rsp) +; Move result of addition to stack. +; CHECK: movl %eax, 40(%rsp) ; Eventually, do a TAILCALL ; CHECK: TAILCALL -declare fastcc i32 @tailcallee(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %a, i32 %b) +declare fastcc i32 @tailcallee(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %a, i32 %b) nounwind -define fastcc i32 @tailcaller(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %in1, i32 %in2) { +define fastcc i32 @tailcaller(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %in1, i32 %in2) nounwind { entry: %tmp = add i32 %in1, %p1 %retval = tail call fastcc i32 @tailcallee(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %in2,i32 %tmp) diff --git a/test/CodeGen/X86/vec_shuffle-22.ll b/test/CodeGen/X86/vec_shuffle-22.ll index 5307ced..1cf37d4 100644 --- a/test/CodeGen/X86/vec_shuffle-22.ll +++ b/test/CodeGen/X86/vec_shuffle-22.ll @@ -1,19 +1,15 @@ -; RUN: llc < %s -march=x86 -mcpu=pentium-m -o %t -; RUN: grep movlhps %t | count 1 -; RUN: grep pshufd %t | count 1 -; RUN: llc < %s -march=x86 -mcpu=core2 -o %t -; RUN: grep movlhps %t | count 1 -; RUN: grep movddup %t | count 1 +; RUN: llc < %s -march=x86 -mcpu=pentium-m | FileCheck %s define <4 x float> @t1(<4 x float> %a) nounwind { -entry: - %tmp1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> < i32 0, i32 1, i32 0, i32 1 > ; <<4 x float>> [#uses=1] - ret <4 x float> %tmp1 +; CHECK: movlhps + %tmp1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> < i32 0, i32 1, i32 0, i32 1 > ; <<4 x float>> [#uses=1] + ret <4 x float> %tmp1 } define <4 x i32> @t2(<4 x i32>* %a) nounwind { -entry: - %tmp1 = load <4 x i32>* %a; +; CHECK: pshufd +; CHECK: ret + %tmp1 = load <4 x i32>* %a; %tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> < i32 0, i32 1, i32 0, i32 1 > ; <<4 x i32>> [#uses=1] ret <4 x i32> %tmp2 } diff --git a/test/CodeGen/X86/vec_shuffle-9.ll b/test/CodeGen/X86/vec_shuffle-9.ll index 2bef24d..fc16a26 100644 --- a/test/CodeGen/X86/vec_shuffle-9.ll +++ b/test/CodeGen/X86/vec_shuffle-9.ll @@ -1,9 +1,10 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 -o %t -; RUN: grep punpck %t | count 2 -; RUN: not grep pextrw %t +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s define <4 x i32> @test(i8** %ptr) { -entry: +; CHECK: xorps +; CHECK: punpcklbw +; CHECK: punpcklwd + %tmp = load i8** %ptr ; <i8*> [#uses=1] %tmp.upgrd.1 = bitcast i8* %tmp to float* ; <float*> [#uses=1] %tmp.upgrd.2 = load float* %tmp.upgrd.1 ; <float> [#uses=1] diff --git a/test/CodeGen/X86/widen_arith-1.ll b/test/CodeGen/X86/widen_arith-1.ll index 8f607f5..f8d0690 100644 --- a/test/CodeGen/X86/widen_arith-1.ll +++ b/test/CodeGen/X86/widen_arith-1.ll @@ -1,14 +1,12 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t -; RUN: grep paddb %t | count 1 -; RUN: grep pextrb %t | count 1 -; RUN: not grep pextrw %t +; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s ; Widen a v3i8 to v16i8 to use a vector add -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" - define void @update(<3 x i8>* %dst, <3 x i8>* %src, i32 %n) nounwind { entry: +; CHECK-NOT: pextrw +; CHECK: paddb +; CHECK: pextrb %dst.addr = alloca <3 x i8>* ; <<3 x i8>**> [#uses=2] %src.addr = alloca <3 x i8>* ; <<3 x i8>**> [#uses=2] %n.addr = alloca i32 ; <i32*> [#uses=2] diff --git a/test/CodeGen/X86/widen_arith-2.ll b/test/CodeGen/X86/widen_arith-2.ll index e2420f0..fdecaa3 100644 --- a/test/CodeGen/X86/widen_arith-2.ll +++ b/test/CodeGen/X86/widen_arith-2.ll @@ -1,9 +1,8 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t -; RUN: grep paddb %t | count 1 -; RUN: grep pand %t | count 1 +; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s +; CHECK: paddb +; CHECK: pand ; widen v8i8 to v16i8 (checks even power of 2 widening with add & and) -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" define void @update(i64* %dst_i, i64* %src_i, i32 %n) nounwind { entry: diff --git a/test/CodeGen/X86/widen_arith-3.ll b/test/CodeGen/X86/widen_arith-3.ll index a22d254..a2b8b82 100644 --- a/test/CodeGen/X86/widen_arith-3.ll +++ b/test/CodeGen/X86/widen_arith-3.ll @@ -1,12 +1,10 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t -; RUN: grep paddw %t | count 1 -; RUN: grep movd %t | count 2 -; RUN: grep pextrw %t | count 1 +; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s +; CHECK: paddw +; CHECK: pextrw +; CHECK: movd ; Widen a v3i16 to v8i16 to do a vector add -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" -target triple = "i686-apple-darwin10.0.0d2" @.str = internal constant [4 x i8] c"%d \00" ; <[4 x i8]*> [#uses=1] @.str1 = internal constant [2 x i8] c"\0A\00" ; <[2 x i8]*> [#uses=1] diff --git a/test/CodeGen/X86/widen_arith-4.ll b/test/CodeGen/X86/widen_arith-4.ll index 898bff0..f7506ae 100644 --- a/test/CodeGen/X86/widen_arith-4.ll +++ b/test/CodeGen/X86/widen_arith-4.ll @@ -1,11 +1,9 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t -; RUN: grep psubw %t | count 1 -; RUN: grep pmullw %t | count 1 +; RUN: llc < %s -march=x86-64 -mattr=+sse42 -disable-mmx | FileCheck %s +; CHECK: psubw +; CHECK-NEXT: pmullw ; Widen a v5i16 to v8i16 to do a vector sub and multiple -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" - define void @update(<5 x i16>* %dst, <5 x i16>* %src, i32 %n) nounwind { entry: %dst.addr = alloca <5 x i16>* ; <<5 x i16>**> [#uses=2] diff --git a/test/CodeGen/X86/widen_arith-5.ll b/test/CodeGen/X86/widen_arith-5.ll index 1ecf09d..f7f3408 100644 --- a/test/CodeGen/X86/widen_arith-5.ll +++ b/test/CodeGen/X86/widen_arith-5.ll @@ -1,10 +1,9 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t -; RUN: grep pmulld %t | count 1 -; RUN: grep psubd %t | count 1 -; RUN: grep movaps %t | count 1 +; RUN: llc < %s -march=x86-64 -mattr=+sse42 -disable-mmx | FileCheck %s +; CHECK: movaps +; CHECK: pmulld +; CHECK: psubd ; widen a v3i32 to v4i32 to do a vector multiple and a subtraction -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" define void @update(<3 x i32>* %dst, <3 x i32>* %src, i32 %n) nounwind { entry: diff --git a/test/CodeGen/X86/widen_arith-6.ll b/test/CodeGen/X86/widen_arith-6.ll index 3583258..538123f 100644 --- a/test/CodeGen/X86/widen_arith-6.ll +++ b/test/CodeGen/X86/widen_arith-6.ll @@ -1,9 +1,8 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t -; RUN: grep mulps %t | count 1 -; RUN: grep addps %t | count 1 +; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s +; CHECK: mulps +; CHECK: addps ; widen a v3f32 to vfi32 to do a vector multiple and an add -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" define void @update(<3 x float>* %dst, <3 x float>* %src, i32 %n) nounwind { entry: diff --git a/test/CodeGen/X86/widen_cast-1.ll b/test/CodeGen/X86/widen_cast-1.ll index 441a360..d4ab174 100644 --- a/test/CodeGen/X86/widen_cast-1.ll +++ b/test/CodeGen/X86/widen_cast-1.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t -; RUN: grep paddw %t | count 1 -; RUN: grep movd %t | count 1 -; RUN: grep pextrd %t | count 1 +; RUN: llc -march=x86 -mattr=+sse42 < %s -disable-mmx | FileCheck %s +; CHECK: paddw +; CHECK: pextrd +; CHECK: movd ; bitcast a v4i16 to v2i32 diff --git a/test/CodeGen/X86/widen_cast-2.ll b/test/CodeGen/X86/widen_cast-2.ll index ded5707..e5d2c6a 100644 --- a/test/CodeGen/X86/widen_cast-2.ll +++ b/test/CodeGen/X86/widen_cast-2.ll @@ -1,6 +1,11 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t -; RUN: grep pextrd %t | count 5 -; RUN: grep movd %t | count 3 +; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s +; CHECK: pextrd +; CHECK: pextrd +; CHECK: movd +; CHECK: pextrd +; CHECK: pextrd +; CHECK: pextrd +; CHECK: movd ; bitcast v14i16 to v7i32 diff --git a/test/CodeGen/X86/widen_cast-3.ll b/test/CodeGen/X86/widen_cast-3.ll index 67a760f..02674dd 100644 --- a/test/CodeGen/X86/widen_cast-3.ll +++ b/test/CodeGen/X86/widen_cast-3.ll @@ -1,6 +1,7 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t -; RUN: grep paddd %t | count 1 -; RUN: grep pextrd %t | count 2 +; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s +; CHECK: paddd +; CHECK: pextrd +; CHECK: pextrd ; bitcast v12i8 to v3i32 diff --git a/test/CodeGen/X86/widen_cast-4.ll b/test/CodeGen/X86/widen_cast-4.ll index 614eeed..5f31e56 100644 --- a/test/CodeGen/X86/widen_cast-4.ll +++ b/test/CodeGen/X86/widen_cast-4.ll @@ -1,5 +1,12 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t -; RUN: grep sarb %t | count 8 +; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s +; CHECK: sarb +; CHECK: sarb +; CHECK: sarb +; CHECK: sarb +; CHECK: sarb +; CHECK: sarb +; CHECK: sarb +; CHECK: sarb ; v8i8 that is widen to v16i8 then split ; FIXME: This is widen to v16i8 and split to 16 and we then rebuild the vector. diff --git a/test/CodeGen/X86/widen_cast-5.ll b/test/CodeGen/X86/widen_cast-5.ll index 92618d6..d1d7fec 100644 --- a/test/CodeGen/X86/widen_cast-5.ll +++ b/test/CodeGen/X86/widen_cast-5.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t +; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s +; CHECK: movl +; CHECK: movd ; bitcast a i64 to v2i32 diff --git a/test/CodeGen/X86/widen_cast-6.ll b/test/CodeGen/X86/widen_cast-6.ll index 386f749..08759bf 100644 --- a/test/CodeGen/X86/widen_cast-6.ll +++ b/test/CodeGen/X86/widen_cast-6.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=x86 -mattr=+sse41 -disable-mmx -o %t -; RUN: grep movd %t | count 1 +; RUN: llc < %s -march=x86 -mattr=+sse41 -disable-mmx | FileCheck %s +; CHECK: movd ; Test bit convert that requires widening in the operand. diff --git a/test/CodeGen/X86/widen_conv-1.ll b/test/CodeGen/X86/widen_conv-1.ll index ccc8b4f..a2029dd 100644 --- a/test/CodeGen/X86/widen_conv-1.ll +++ b/test/CodeGen/X86/widen_conv-1.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t -; RUN: grep pshufd %t | count 1 -; RUN: grep paddd %t | count 1 +; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s +; CHECK: pshufd +; CHECK: paddd ; truncate v2i64 to v2i32 diff --git a/test/CodeGen/X86/widen_conv-2.ll b/test/CodeGen/X86/widen_conv-2.ll index 9b7ab74..b24a9b3 100644 --- a/test/CodeGen/X86/widen_conv-2.ll +++ b/test/CodeGen/X86/widen_conv-2.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t +; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s +; CHECK: movswl +; CHECK: movswl ; sign extension v2i32 to v2i16 diff --git a/test/CodeGen/X86/widen_conv-3.ll b/test/CodeGen/X86/widen_conv-3.ll index 4ec76a9..1a40800 100644 --- a/test/CodeGen/X86/widen_conv-3.ll +++ b/test/CodeGen/X86/widen_conv-3.ll @@ -1,5 +1,6 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t -; grep cvtsi2ss %t | count 1 +; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s +; CHECK: cvtsi2ss + ; sign to float v2i16 to v2f32 define void @convert(<2 x float>* %dst.addr, <2 x i16> %src) nounwind { diff --git a/test/CodeGen/X86/widen_conv-4.ll b/test/CodeGen/X86/widen_conv-4.ll index 61a26a8..e505b62 100644 --- a/test/CodeGen/X86/widen_conv-4.ll +++ b/test/CodeGen/X86/widen_conv-4.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t +; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s +; CHECK: cvtsi2ss ; unsigned to float v7i16 to v7f32 diff --git a/test/CodeGen/X86/widen_extract-1.ll b/test/CodeGen/X86/widen_extract-1.ll new file mode 100644 index 0000000..308e6b8 --- /dev/null +++ b/test/CodeGen/X86/widen_extract-1.ll @@ -0,0 +1,12 @@ +; RUN: llc < %s -march=x86-64 -mattr=+sse42 -disable-mmx | FileCheck %s +; widen extract subvector + +define void @convert(<2 x double>* %dst.addr, <3 x double> %src) { +entry: +; CHECK: convert: +; CHECK: unpcklpd {{%xmm[0-7]}}, {{%xmm[0-7]}} +; CHECK-NEXT: movapd + %val = shufflevector <3 x double> %src, <3 x double> undef, <2 x i32> < i32 0, i32 1> + store <2 x double> %val, <2 x double>* %dst.addr + ret void +} diff --git a/test/CodeGen/X86/widen_select-1.ll b/test/CodeGen/X86/widen_select-1.ll index aca0b67..4154433 100644 --- a/test/CodeGen/X86/widen_select-1.ll +++ b/test/CodeGen/X86/widen_select-1.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t +; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s +; CHECK: jne ; widening select v6i32 and then a sub diff --git a/test/CodeGen/X86/widen_shuffle-1.ll b/test/CodeGen/X86/widen_shuffle-1.ll index 15da870..dd02241 100644 --- a/test/CodeGen/X86/widen_shuffle-1.ll +++ b/test/CodeGen/X86/widen_shuffle-1.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t +; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s +; CHECK: insertps +; CHECK: extractps ; widening shuffle v3float and then a add diff --git a/test/CodeGen/X86/widen_shuffle-2.ll b/test/CodeGen/X86/widen_shuffle-2.ll index 617cc1de..d097e41 100644 --- a/test/CodeGen/X86/widen_shuffle-2.ll +++ b/test/CodeGen/X86/widen_shuffle-2.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -o %t +; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s +; CHECK: insertps +; CHECK: extractps ; widening shuffle v3float and then a add diff --git a/test/DebugInfo/2009-10-16-Phi.ll b/test/DebugInfo/2009-10-16-Phi.ll new file mode 100644 index 0000000..fc03751 --- /dev/null +++ b/test/DebugInfo/2009-10-16-Phi.ll @@ -0,0 +1,13 @@ +; RUN: llvm-as %s -disable-output + +define i32 @foo() { +E: + br label %B2 +B1: + br label %B2 +B2: + %0 = phi i32 [ 0, %E ], [ 1, %B1 ], !dbg !0 + ret i32 %0 +} + +!0 = metadata !{i32 42}
\ No newline at end of file diff --git a/test/DebugInfo/2009-10-16-Scope.ll b/test/DebugInfo/2009-10-16-Scope.ll new file mode 100644 index 0000000..ea43249 --- /dev/null +++ b/test/DebugInfo/2009-10-16-Scope.ll @@ -0,0 +1,33 @@ +; RUN: llc %s -O0 -o /dev/null +; PR 5197 +; There is not any llvm instruction assocated with !5. The code generator +; should be able to handle this. + +define void @bar() nounwind ssp { +entry: + %count_ = alloca i32, align 4 ; <i32*> [#uses=2] + br label %do.body, !dbg !0 + +do.body: ; preds = %entry + %0 = bitcast i32* %count_ to { }* ; <{ }*> [#uses=1] + call void @llvm.dbg.declare({ }* %0, metadata !4) + %conv = ptrtoint i32* %count_ to i32, !dbg !0 ; <i32> [#uses=1] + %call = call i32 @foo(i32 %conv) ssp, !dbg !0 ; <i32> [#uses=0] + br label %do.end, !dbg !0 + +do.end: ; preds = %do.body + ret void, !dbg !7 +} + +declare void @llvm.dbg.declare({ }*, metadata) nounwind readnone + +declare i32 @foo(i32) ssp + +!0 = metadata !{i32 5, i32 2, metadata !1, null} +!1 = metadata !{i32 458763, metadata !2}; [DW_TAG_lexical_block ] +!2 = metadata !{i32 458798, i32 0, metadata !3, metadata !"bar", metadata !"bar", metadata !"bar", metadata !3, i32 4, null, i1 false, i1 true}; [DW_TAG_subprogram ] +!3 = metadata !{i32 458769, i32 0, i32 12, metadata !"genmodes.i", metadata !"/Users/yash/Downloads", metadata !"clang 1.1", i1 true, i1 false, metadata !"", i32 0}; [DW_TAG_compile_unit ] +!4 = metadata !{i32 459008, metadata !5, metadata !"count_", metadata !3, i32 5, metadata !6}; [ DW_TAG_auto_variable ] +!5 = metadata !{i32 458763, metadata !1}; [DW_TAG_lexical_block ] +!6 = metadata !{i32 458788, metadata !3, metadata !"int", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5}; [DW_TAG_base_type ] +!7 = metadata !{i32 6, i32 1, metadata !2, null} diff --git a/test/Feature/md_on_instruction.ll b/test/Feature/md_on_instruction.ll index d765cd8..da9e49e 100644 --- a/test/Feature/md_on_instruction.ll +++ b/test/Feature/md_on_instruction.ll @@ -1,5 +1,4 @@ -; RUN: llvm-as < %s -disable-output - +; RUN: llvm-as < %s | llvm-dis | grep " !dbg " | count 4 define i32 @foo() nounwind ssp { entry: %retval = alloca i32 ; <i32*> [#uses=2] diff --git a/test/FrontendAda/negative_field_offset.adb b/test/FrontendAda/negative_field_offset.adb new file mode 100644 index 0000000..f8b8510 --- /dev/null +++ b/test/FrontendAda/negative_field_offset.adb @@ -0,0 +1,16 @@ +-- RUN: %llvmgcc -c %s +with System; +procedure Negative_Field_Offset (N : Integer) is + type String_Pointer is access String; + -- Force use of a thin pointer. + for String_Pointer'Size use System.Word_Size; + P : String_Pointer; + + procedure Q (P : String_Pointer) is + begin + P (1) := 'Z'; + end; +begin + P := new String (1 .. N); + Q (P); +end; diff --git a/test/FrontendC++/alignstack.cpp b/test/FrontendC++/alignstack.cpp new file mode 100644 index 0000000..4f993d6 --- /dev/null +++ b/test/FrontendC++/alignstack.cpp @@ -0,0 +1,23 @@ +// RUN: %llvmgxx %s -fasm-blocks -S -o - | FileCheck %s +// Complicated expression as jump target +// XFAIL: * +// XTARGET: x86,i386,i686,darwin + +void Method3() +{ +// CHECK: Method3 +// CHECK-NOT: alignstack + asm("foo:"); +// CHECK: return +} + +void Method4() +{ +// CHECK: Method4 +// CHECK: alignstack + asm { + bar: + } +// CHECK: return +} + diff --git a/test/FrontendC++/member-alignment.cpp b/test/FrontendC++/member-alignment.cpp index 01c90ca..6afc0aa 100644 --- a/test/FrontendC++/member-alignment.cpp +++ b/test/FrontendC++/member-alignment.cpp @@ -1,5 +1,5 @@ // RUN: %llvmgxx -S -emit-llvm %s -o - | FileCheck %s -// XFAIL: arm +// XFAIL: arm,powerpc // rdar://7268289 diff --git a/test/FrontendC++/varargs.cpp b/test/FrontendC++/varargs.cpp new file mode 100644 index 0000000..1c07aed --- /dev/null +++ b/test/FrontendC++/varargs.cpp @@ -0,0 +1,19 @@ +// RUN: %llvmgxx -S -emit-llvm %s -o - | FileCheck %s +// rdar://7309675 +// PR4678 + +// test1 should be compmiled to be a varargs function in the IR even +// though there is no way to do a va_begin. Otherwise, the optimizer +// will warn about 'dropped arguments' at the call site. + +// CHECK: define i32 @_Z5test1z(...) +int test1(...) { + return -1; +} + +// CHECK: call i32 (...)* @_Z5test1z(i32 0) +void test() { + test1(0); +} + + diff --git a/test/FrontendC/alignstack.c b/test/FrontendC/alignstack.c new file mode 100644 index 0000000..30c00ff --- /dev/null +++ b/test/FrontendC/alignstack.c @@ -0,0 +1,23 @@ +// RUN: %llvmgcc %s -fasm-blocks -S -o - | FileCheck %s +// Complicated expression as jump target +// XFAIL: * +// XTARGET: x86,i386,i686,darwin + +void Method3() +{ +// CHECK: Method3 +// CHECK-NOT: alignstack + asm("foo:"); +// CHECK: return +} + +void Method4() +{ +// CHECK: Method4 +// CHECK: alignstack + asm { + bar: + } +// CHECK: return +} + diff --git a/test/LLVMC/MultiplePluginPriorities.td b/test/LLVMC/MultiplePluginPriorities.td new file mode 100644 index 0000000..721b7cc --- /dev/null +++ b/test/LLVMC/MultiplePluginPriorities.td @@ -0,0 +1,10 @@ +// Check that multiple plugin priorities are not allowed. +// RUN: ignore tblgen -I %p/../../include --gen-llvmc %s |& grep "More than one 'PluginPriority' instance found" + +include "llvm/CompilerDriver/Common.td" + +def Graph : CompilationGraph<[]>; + +def Priority1 : PluginPriority<1>; + +def Priority2 : PluginPriority<2>; diff --git a/test/MC/AsmParser/labels.s b/test/MC/AsmParser/labels.s index 53da7ed..456d61f 100644 --- a/test/MC/AsmParser/labels.s +++ b/test/MC/AsmParser/labels.s @@ -12,21 +12,21 @@ a: .long 0 .text -foo: +foo: // CHECK: addl $24, a$b(%eax) - addl $24, "a$b"(%eax) + addl $24, "a$b"(%eax) // CHECK: addl $24, a$b+10(%eax) addl $24, ("a$b" + 10)(%eax) - + // CHECK: b$c = 10 "b$c" = 10 -// CHECK: addl $b$c, %eax +// CHECK: addl $10, %eax addl "b$c", %eax - + // CHECK: "a 0" = 11 .set "a 0", 11 - -// CHECK: .long "a 0" + +// CHECK: .long 11 .long "a 0" // XXCHCK: .section "a 1,a 2" @@ -48,12 +48,12 @@ foo: .lcomm "a 7", 1 // FIXME: We don't bother to support .lsym. - + // CHECX: .lsym "a 8",1 // .lsym "a 8", 1 // CHECK: "a 9" = a-b .set "a 9", a - b - + // CHECK: .long "a 9" .long "a 9" diff --git a/test/MC/AsmParser/variables-invalid.s b/test/MC/AsmParser/variables-invalid.s new file mode 100644 index 0000000..9656889 --- /dev/null +++ b/test/MC/AsmParser/variables-invalid.s @@ -0,0 +1,17 @@ +// RUN: not llvm-mc -triple i386-unknown-unknown %s 2> %t +// RUN: FileCheck --input-file %t %s + + .data +// CHECK: invalid assignment to 't0_v0' + t0_v0 = t0_v0 + 1 + + t1_v1 = 1 + t1_v1 = 2 + +t2_s0: +// CHECK: redefinition of 't2_s0' + t2_s0 = 2 + + t3_s0 = t2_s0 + 1 +// CHECK: invalid reassignment of non-absolute variable 't3_s0' + t3_s0 = 1 diff --git a/test/MC/AsmParser/variables.s b/test/MC/AsmParser/variables.s new file mode 100644 index 0000000..cb004d7 --- /dev/null +++ b/test/MC/AsmParser/variables.s @@ -0,0 +1,15 @@ +// RUN: llvm-mc -triple i386-unknown-unknown %s + + .data + t0_v0 = 1 + t0_v1 = t0_v0 + .if t0_v1 != 1 + .abort "invalid value" + .endif + + t1_v0 = 1 + t1_v1 = t0_v0 + t1_v0 = 2 + .if t0_v1 != 1 + .abort "invalid value" + .endif diff --git a/test/Transforms/ConstProp/constant-expr.ll b/test/Transforms/ConstProp/constant-expr.ll new file mode 100644 index 0000000..eece37f --- /dev/null +++ b/test/Transforms/ConstProp/constant-expr.ll @@ -0,0 +1,60 @@ +; RUN: llvm-as < %s | llvm-dis | FileCheck %s + +@X = external global i8 +@Y = external global i8 +@Z = external global i8 + +@A = global i1 add (i1 icmp ult (i8* @X, i8* @Y), i1 icmp ult (i8* @X, i8* @Z)) +; CHECK: @A = global i1 xor (i1 icmp ult (i8* @X, i8* @Y), i1 icmp ult (i8* @X, i8* @Z)) +@B = global i1 sub (i1 icmp ult (i8* @X, i8* @Y), i1 icmp ult (i8* @X, i8* @Z)), align 2 +; CHECK: @B = global i1 xor (i1 icmp ult (i8* @X, i8* @Y), i1 icmp ult (i8* @X, i8* @Z)) +@C = global i1 mul (i1 icmp ult (i8* @X, i8* @Y), i1 icmp ult (i8* @X, i8* @Z)) +; CHECK: @C = global i1 and (i1 icmp ult (i8* @X, i8* @Y), i1 icmp ult (i8* @X, i8* @Z)) + +@D = global i1 sdiv (i1 icmp ult (i8* @X, i8* @Y), i1 icmp ult (i8* @X, i8* @Z)) +; CHECK: @D = global i1 icmp ult (i8* @X, i8* @Y) +@E = global i1 udiv (i1 icmp ult (i8* @X, i8* @Y), i1 icmp ult (i8* @X, i8* @Z)) +; CHECK: @E = global i1 icmp ult (i8* @X, i8* @Y) +@F = global i1 srem (i1 icmp ult (i8* @X, i8* @Y), i1 icmp ult (i8* @X, i8* @Z)) +; CHECK: @F = global i1 false ; <i1*> [#uses=0] +@G = global i1 urem (i1 icmp ult (i8* @X, i8* @Y), i1 icmp ult (i8* @X, i8* @Z)) +; CHECK: @G = global i1 false ; <i1*> [#uses=0] + +@H = global i1 icmp ule (i32* bitcast (i8* @X to i32*), i32* bitcast (i8* @Y to i32*)) +; CHECK: @H = global i1 icmp ule (i8* @X, i8* @Y) + +@I = global i1 xor (i1 icmp ult (i8* @X, i8* @Y), i1 false) +; CHECK: @I = global i1 icmp ult (i8* @X, i8* @Y) +@J = global i1 xor (i1 icmp ult (i8* @X, i8* @Y), i1 true) +; CHECK: @J = global i1 icmp uge (i8* @X, i8* @Y) + +@K = global i1 icmp eq (i1 icmp ult (i8* @X, i8* @Y), i1 false) +; CHECK: @K = global i1 icmp uge (i8* @X, i8* @Y) +@L = global i1 icmp eq (i1 icmp ult (i8* @X, i8* @Y), i1 true) +; CHECK: @L = global i1 icmp ult (i8* @X, i8* @Y) +@M = global i1 icmp ne (i1 icmp ult (i8* @X, i8* @Y), i1 true) +; CHECK: @M = global i1 icmp uge (i8* @X, i8* @Y) +@N = global i1 icmp ne (i1 icmp ult (i8* @X, i8* @Y), i1 false) +; CHECK: @N = global i1 icmp ult (i8* @X, i8* @Y) + +@O = global i1 icmp eq (i32 zext (i1 icmp ult (i8* @X, i8* @Y) to i32), i32 0) +; CHECK: @O = global i1 icmp uge (i8* @X, i8* @Y) + + + +; PR5176 + +; CHECK: @T1 = global i1 true +@T1 = global i1 icmp eq (i64 and (i64 trunc (i256 lshr (i256 or (i256 and (i256 and (i256 shl (i256 zext (i64 ptrtoint (i1* @B to i64) to i256), i256 64), i256 -6277101735386680763495507056286727952638980837032266301441), i256 6277101735386680763835789423207666416102355444464034512895), i256 shl (i256 zext (i64 ptrtoint (i1* @A to i64) to i256), i256 192)), i256 64) to i64), i64 1), i64 0) + +; CHECK: @T2 = global i1* @B +@T2 = global i1* inttoptr (i64 add (i64 trunc (i256 lshr (i256 or (i256 and (i256 and (i256 shl (i256 zext (i64 ptrtoint (i1* @A to i64) to i256), i256 64), i256 -6277101735386680763495507056286727952638980837032266301441), i256 6277101735386680763835789423207666416102355444464034512895), i256 shl (i256 zext (i64 ptrtoint (i1* @B to i64) to i256), i256 192)), i256 192) to i64), i64 trunc (i256 lshr (i256 or (i256 and (i256 and (i256 shl (i256 zext (i64 ptrtoint (i1* @A to i64) to i256), i256 64), i256 -6277101735386680763495507056286727952638980837032266301441), i256 6277101735386680763835789423207666416102355444464034512895), i256 shl (i256 zext (i64 ptrtoint (i1* @B to i64) to i256), i256 192)), i256 128) to i64)) to i1*) + +; CHECK: @T3 = global i64 add (i64 ptrtoint (i1* @B to i64), i64 -1) +@T3 = global i64 add (i64 trunc (i256 lshr (i256 or (i256 and (i256 and (i256 shl (i256 zext (i64 ptrtoint (i1* @B to i64) to i256), i256 64), i256 -6277101735386680763495507056286727952638980837032266301441), i256 6277101735386680763835789423207666416102355444464034512895), i256 shl (i256 zext (i64 ptrtoint (i1* @A to i64) to i256), i256 192)), i256 64) to i64), i64 -1) + +; CHECK: @T4 = global i1* @B +@T4 = global i1* inttoptr (i64 trunc (i256 lshr (i256 or (i256 and (i256 and (i256 shl (i256 zext (i64 ptrtoint (i1* @B to i64) to i256), i256 64), i256 -6277101735386680763495507056286727952638980837032266301441), i256 6277101735386680763835789423207666416102355444464034512895), i256 shl (i256 zext (i64 ptrtoint (i1* @A to i64) to i256), i256 192)), i256 64) to i64) to i1*) + +; CHECK: @T5 = global i1* @A +@T5 = global i1* inttoptr (i64 add (i64 trunc (i256 lshr (i256 or (i256 and (i256 and (i256 shl (i256 zext (i64 ptrtoint (i1* @B to i64) to i256), i256 64), i256 -6277101735386680763495507056286727952638980837032266301441), i256 6277101735386680763835789423207666416102355444464034512895), i256 shl (i256 zext (i64 ptrtoint (i1* @A to i64) to i256), i256 192)), i256 192) to i64), i64 trunc (i256 lshr (i256 or (i256 and (i256 and (i256 shl (i256 zext (i64 ptrtoint (i1* @B to i64) to i256), i256 64), i256 -6277101735386680763495507056286727952638980837032266301441), i256 6277101735386680763835789423207666416102355444464034512895), i256 shl (i256 zext (i64 ptrtoint (i1* @A to i64) to i256), i256 192)), i256 128) to i64)) to i1*)
\ No newline at end of file diff --git a/test/Transforms/ConstProp/loads.ll b/test/Transforms/ConstProp/loads.ll new file mode 100644 index 0000000..f3e7f6a --- /dev/null +++ b/test/Transforms/ConstProp/loads.ll @@ -0,0 +1,89 @@ +; RUN: opt < %s -instcombine -S | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" + +@test1 = constant {{i32,i8},i32} {{i32,i8} { i32 -559038737, i8 186 }, i32 -889275714 } +@test2 = constant double 1.0 +@test3 = constant {i64, i64} { i64 123, i64 112312312 } + +; Simple load +define i32 @test1() { + %r = load i32* getelementptr ({{i32,i8},i32}* @test1, i32 0, i32 0, i32 0) + ret i32 %r +; @test1 +; CHECK: ret i32 -559038737 +} + +; PR3152 +; Load of first 16 bits of 32-bit value. +define i16 @test2() { + %r = load i16* bitcast(i32* getelementptr ({{i32,i8},i32}* @test1, i32 0, i32 0, i32 0) to i16*) + ret i16 %r + +; @test2 +; CHECK: ret i16 -16657 +} + +; Load of second 16 bits of 32-bit value. +define i16 @test3() { + %r = load i16* getelementptr(i16* bitcast(i32* getelementptr ({{i32,i8},i32}* @test1, i32 0, i32 0, i32 0) to i16*), i32 1) + ret i16 %r + +; @test3 +; CHECK: ret i16 -8531 +} + +; Load of 8 bit field + tail padding. +define i16 @test4() { + %r = load i16* getelementptr(i16* bitcast(i32* getelementptr ({{i32,i8},i32}* @test1, i32 0, i32 0, i32 0) to i16*), i32 2) + ret i16 %r +; @test4 +; CHECK: ret i16 186 +} + +; Load of double bits. +define i64 @test6() { + %r = load i64* bitcast(double* @test2 to i64*) + ret i64 %r + +; @test6 +; CHECK: ret i64 4607182418800017408 +} + +; Load of double bits. +define i16 @test7() { + %r = load i16* bitcast(double* @test2 to i16*) + ret i16 %r + +; @test7 +; CHECK: ret i16 0 +} + +; Double load. +define double @test8() { + %r = load double* bitcast({{i32,i8},i32}* @test1 to double*) + ret double %r + +; @test8 +; CHECK: ret double 0xDEADBEBA +} + + +; i128 load. +define i128 @test9() { + %r = load i128* bitcast({i64, i64}* @test3 to i128*) + ret i128 %r + +; @test9 +; CHECK: ret i128 112312312 +} + +; vector load. +define <2 x i64> @test10() { + %r = load <2 x i64>* bitcast({i64, i64}* @test3 to <2 x i64>*) + ret <2 x i64> %r + +; @test10 +; CHECK: ret <2 x i64> <i64 112312312, i64 0> +} + diff --git a/test/Transforms/GVN/calls-readonly.ll b/test/Transforms/GVN/calls-readonly.ll index 28b5ff0..97ec915 100644 --- a/test/Transforms/GVN/calls-readonly.ll +++ b/test/Transforms/GVN/calls-readonly.ll @@ -6,22 +6,22 @@ target triple = "i386-apple-darwin7" define i8* @test(i8* %P, i8* %Q, i32 %x, i32 %y) nounwind readonly { entry: - %0 = tail call i32 @strlen(i8* %P) nounwind readonly ; <i32> [#uses=2] - %1 = icmp eq i32 %0, 0 ; <i1> [#uses=1] - br i1 %1, label %bb, label %bb1 + %0 = tail call i32 @strlen(i8* %P) ; <i32> [#uses=2] + %1 = icmp eq i32 %0, 0 ; <i1> [#uses=1] + br i1 %1, label %bb, label %bb1 -bb: ; preds = %entry - %2 = sdiv i32 %x, %y ; <i32> [#uses=1] - br label %bb1 +bb: ; preds = %entry + %2 = sdiv i32 %x, %y ; <i32> [#uses=1] + br label %bb1 -bb1: ; preds = %bb, %entry - %x_addr.0 = phi i32 [ %2, %bb ], [ %x, %entry ] ; <i32> [#uses=1] - %3 = tail call i8* @strchr(i8* %Q, i32 97) nounwind readonly ; <i8*> [#uses=1] - %4 = tail call i32 @strlen(i8* %P) nounwind readonly ; <i32> [#uses=1] - %5 = add i32 %x_addr.0, %0 ; <i32> [#uses=1] - %.sum = sub i32 %5, %4 ; <i32> [#uses=1] - %6 = getelementptr i8* %3, i32 %.sum ; <i8*> [#uses=1] - ret i8* %6 +bb1: ; preds = %bb, %entry + %x_addr.0 = phi i32 [ %2, %bb ], [ %x, %entry ] ; <i32> [#uses=1] + %3 = tail call i8* @strchr(i8* %Q, i32 97) ; <i8*> [#uses=1] + %4 = tail call i32 @strlen(i8* %P) ; <i32> [#uses=1] + %5 = add i32 %x_addr.0, %0 ; <i32> [#uses=1] + %.sum = sub i32 %5, %4 ; <i32> [#uses=1] + %6 = getelementptr i8* %3, i32 %.sum ; <i8*> [#uses=1] + ret i8* %6 } declare i32 @strlen(i8*) nounwind readonly diff --git a/test/Transforms/GlobalOpt/2009-11-16-BrokenPerformHeapAllocSRoA.ll b/test/Transforms/GlobalOpt/2009-11-16-BrokenPerformHeapAllocSRoA.ll new file mode 100644 index 0000000..54e8f90 --- /dev/null +++ b/test/Transforms/GlobalOpt/2009-11-16-BrokenPerformHeapAllocSRoA.ll @@ -0,0 +1,26 @@ +; RUN: opt < %s -globalopt -S | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target triple = "x86_64-apple-darwin10.0" + +%struct.hashheader = type { i16, i16, i16, i16, i16, i16, i32, i32, i32, i32, i32, i32, i32, i32, i32, [5 x i8], [13 x i8], i8, i8, i8, [228 x i16], [228 x i8], [228 x i8], [228 x i8], [228 x i8], [228 x i8], [228 x i8], [128 x i8], [100 x [11 x i8]], [100 x i32], [100 x i32], i16 } +%struct.strchartype = type { i8*, i8*, i8* } + +@hashheader = internal global %struct.hashheader zeroinitializer, align 32 ; <%struct.hashheader*> [#uses=1] +@chartypes = internal global %struct.strchartype* null ; <%struct.strchartype**> [#uses=1] +; CHECK-NOT: @hashheader +; CHECK-NOT: @chartypes + +; based on linit in office-ispell +define void @test() nounwind ssp { + %1 = load i32* getelementptr inbounds (%struct.hashheader* @hashheader, i64 0, i32 13), align 8 ; <i32> [#uses=1] + %2 = sext i32 %1 to i64 ; <i64> [#uses=1] + %3 = mul i64 %2, ptrtoint (%struct.strchartype* getelementptr (%struct.strchartype* null, i64 1) to i64) ; <i64> [#uses=1] + %4 = tail call i8* @malloc(i64 %3) ; <i8*> [#uses=1] +; CHECK: call i8* @malloc(i64 + %5 = bitcast i8* %4 to %struct.strchartype* ; <%struct.strchartype*> [#uses=1] + store %struct.strchartype* %5, %struct.strchartype** @chartypes, align 8 + ret void +} + +declare noalias i8* @malloc(i64) diff --git a/test/Transforms/GlobalOpt/2009-11-16-MallocSingleStoreToGlobalVar.ll b/test/Transforms/GlobalOpt/2009-11-16-MallocSingleStoreToGlobalVar.ll new file mode 100644 index 0000000..c43565a --- /dev/null +++ b/test/Transforms/GlobalOpt/2009-11-16-MallocSingleStoreToGlobalVar.ll @@ -0,0 +1,30 @@ +; Test ensures that non-optimizable array mallocs are not optimized; specifically +; GlobalOpt was treating a non-optimizable array malloc as a non-array malloc +; and optimizing the global object that the malloc was stored to as a single +; element global. The global object @TOP in this test should not be optimized. +; RUN: opt < %s -globalopt -S | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target triple = "x86_64-apple-darwin10.0" + +@TOP = internal global i64* null ; <i64**> [#uses=2] +; CHECK: @TOP = internal global i64* null +@channelColumns = internal global i64 0 ; <i64*> [#uses=2] + +; Derived from @DescribeChannel() in yacr2 +define void @test() nounwind ssp { + store i64 2335, i64* @channelColumns, align 8 + %1 = load i64* @channelColumns, align 8 ; <i64> [#uses=1] + %2 = shl i64 %1, 3 ; <i64> [#uses=1] + %3 = add i64 %2, 8 ; <i64> [#uses=1] + %4 = call noalias i8* @malloc(i64 %3) nounwind ; <i8*> [#uses=1] +; CHECK: call noalias i8* @malloc + %5 = bitcast i8* %4 to i64* ; <i64*> [#uses=1] + store i64* %5, i64** @TOP, align 8 + %6 = load i64** @TOP, align 8 ; <i64*> [#uses=1] + %7 = getelementptr inbounds i64* %6, i64 13 ; <i64*> [#uses=1] + store i64 0, i64* %7, align 8 + ret void +} + +declare noalias i8* @malloc(i64) nounwind diff --git a/test/Transforms/GlobalOpt/malloc-promote-2.ll b/test/Transforms/GlobalOpt/malloc-promote-2.ll index 0d03835..d3d2252 100644 --- a/test/Transforms/GlobalOpt/malloc-promote-2.ll +++ b/test/Transforms/GlobalOpt/malloc-promote-2.ll @@ -1,4 +1,6 @@ -; RUN: opt < %s -globalopt -S | not grep malloc +; RUN: opt < %s -globalopt -globaldce -S | not grep malloc +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" +target triple = "i686-apple-darwin8" @G = internal global i32* null ; <i32**> [#uses=3] diff --git a/test/Transforms/GlobalOpt/malloc-promote-3.ll b/test/Transforms/GlobalOpt/malloc-promote-3.ll index d4ee4e8..a920b61 100644 --- a/test/Transforms/GlobalOpt/malloc-promote-3.ll +++ b/test/Transforms/GlobalOpt/malloc-promote-3.ll @@ -1,4 +1,6 @@ -; RUN: opt < %s -globalopt -S | not grep malloc +; RUN: opt < %s -globalopt -globaldce -S | not grep malloc +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" +target triple = "i686-apple-darwin8" @G = internal global i32* null ; <i32**> [#uses=4] diff --git a/test/Transforms/Inline/crash.ll b/test/Transforms/Inline/crash.ll index 30eae7a..f34b44c 100644 --- a/test/Transforms/Inline/crash.ll +++ b/test/Transforms/Inline/crash.ll @@ -51,7 +51,38 @@ entry: unreachable } +declare fastcc void @list_Rplacd1284() nounwind ssp -declare fastcc void @list_Rplacd1284() nounwind ssp + +;============================ +; PR5208 + +define void @AAA() { +entry: + %A = alloca i8, i32 undef, align 1 + invoke fastcc void @XXX() + to label %invcont98 unwind label %lpad156 + +invcont98: + unreachable + +lpad156: + unreachable +} + +declare fastcc void @YYY() + +define internal fastcc void @XXX() { +entry: + %B = alloca i8, i32 undef, align 1 + invoke fastcc void @YYY() + to label %bb260 unwind label %lpad + +bb260: + ret void + +lpad: + unwind +} diff --git a/test/Transforms/InstCombine/cast.ll b/test/Transforms/InstCombine/cast.ll index 9835d65..c5266f3 100644 --- a/test/Transforms/InstCombine/cast.ll +++ b/test/Transforms/InstCombine/cast.ll @@ -102,8 +102,8 @@ define i32* @test12() { %p = malloc [4 x i8] ; <[4 x i8]*> [#uses=1] %c = bitcast [4 x i8]* %p to i32* ; <i32*> [#uses=1] ret i32* %c -; CHECK: %p = malloc i32 -; CHECK: ret i32* %p +; CHECK: %malloccall = tail call i8* @malloc(i32 ptrtoint ([4 x i8]* getelementptr ([4 x i8]* null, i32 1) to i32)) +; CHECK: ret i32* %c } define i8* @test13(i64 %A) { @@ -274,9 +274,9 @@ define void @test32(double** %tmp) { %tmp8.upgrd.1 = bitcast [16 x i8]* %tmp8 to double* ; <double*> [#uses=1] store double* %tmp8.upgrd.1, double** %tmp ret void -; CHECK: %tmp81 = malloc [2 x double] -; CHECK: %tmp81.sub = getelementptr inbounds [2 x double]* %tmp81, i64 0, i64 0 -; CHECK: store double* %tmp81.sub, double** %tmp +; CHECK: %malloccall = tail call i8* @malloc(i32 ptrtoint ([16 x i8]* getelementptr ([16 x i8]* null, i32 1) to i32)) +; CHECK: %tmp8.upgrd.1 = bitcast i8* %malloccall to double* +; CHECK: store double* %tmp8.upgrd.1, double** %tmp ; CHECK: ret void } diff --git a/test/Transforms/InstCombine/crash.ll b/test/Transforms/InstCombine/crash.ll index d475ab5..fbac472 100644 --- a/test/Transforms/InstCombine/crash.ll +++ b/test/Transforms/InstCombine/crash.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -instcombine | llvm-dis +; RUN: opt < %s -instcombine -S target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i386-apple-darwin10.0" @@ -44,3 +44,84 @@ entry: store i32 %ins, i32* %arrayidx20 ret void } + +; PR5262 +@tmp2 = global i64 0 ; <i64*> [#uses=1] + +declare void @use(i64) nounwind + +define void @foo(i1) nounwind align 2 { +; <label>:1 + br i1 %0, label %2, label %3 + +; <label>:2 ; preds = %1 + br label %3 + +; <label>:3 ; preds = %2, %1 + %4 = phi i8 [ 1, %2 ], [ 0, %1 ] ; <i8> [#uses=1] + %5 = icmp eq i8 %4, 0 ; <i1> [#uses=1] + %6 = load i64* @tmp2, align 8 ; <i64> [#uses=1] + %7 = select i1 %5, i64 0, i64 %6 ; <i64> [#uses=1] + br label %8 + +; <label>:8 ; preds = %3 + call void @use(i64 %7) + ret void +} + +%t0 = type { i32, i32 } +%t1 = type { i32, i32, i32, i32, i32* } + +declare %t0* @bar2(i64) + +define void @bar3(i1, i1) nounwind align 2 { +; <label>:2 + br i1 %1, label %10, label %3 + +; <label>:3 ; preds = %2 + %4 = getelementptr inbounds %t0* null, i64 0, i32 1 ; <i32*> [#uses=0] + %5 = getelementptr inbounds %t1* null, i64 0, i32 4 ; <i32**> [#uses=1] + %6 = load i32** %5, align 8 ; <i32*> [#uses=1] + %7 = icmp ne i32* %6, null ; <i1> [#uses=1] + %8 = zext i1 %7 to i32 ; <i32> [#uses=1] + %9 = add i32 %8, 0 ; <i32> [#uses=1] + br label %10 + +; <label>:10 ; preds = %3, %2 + %11 = phi i32 [ %9, %3 ], [ 0, %2 ] ; <i32> [#uses=1] + br i1 %1, label %12, label %13 + +; <label>:12 ; preds = %10 + br label %13 + +; <label>:13 ; preds = %12, %10 + %14 = zext i32 %11 to i64 ; <i64> [#uses=1] + %15 = tail call %t0* @bar2(i64 %14) nounwind ; <%0*> [#uses=0] + ret void +} + + + + +; PR5262 +; Make sure the PHI node gets put in a place where all of its operands dominate +; it. +define i64 @test4(i1 %c, i64* %P) nounwind align 2 { +BB0: + br i1 %c, label %BB1, label %BB2 + +BB1: + br label %BB2 + +BB2: + %v5_ = phi i1 [ true, %BB0], [false, %BB1] + %v6 = load i64* %P + br label %l8 + +l8: + br label %l10 + +l10: + %v11 = select i1 %v5_, i64 0, i64 %v6 + ret i64 %v11 +} diff --git a/test/Transforms/InstCombine/getelementptr.ll b/test/Transforms/InstCombine/getelementptr.ll index ffaa6af..285e0ba 100644 --- a/test/Transforms/InstCombine/getelementptr.ll +++ b/test/Transforms/InstCombine/getelementptr.ll @@ -58,7 +58,7 @@ define i32* @test6() { %B = getelementptr i32* %A, i64 2 ret i32* %B ; CHECK: @test6 -; CHECK: getelementptr [4 x i32]* %M, i64 0, i64 2 +; CHECK: getelementptr i8* %malloccall, i64 8 } define i32* @test7(i32* %I, i64 %C, i64 %D) { diff --git a/test/Transforms/InstCombine/malloc-free-delete.ll b/test/Transforms/InstCombine/malloc-free-delete.ll index 2ed5ec6..fd91e44 100644 --- a/test/Transforms/InstCombine/malloc-free-delete.ll +++ b/test/Transforms/InstCombine/malloc-free-delete.ll @@ -1,5 +1,5 @@ ; RUN: opt < %s -instcombine -S | grep {ret i32 0} -; RUN: opt < %s -instcombine -S | not grep malloc +; RUN: opt < %s -instcombine -globaldce -S | not grep malloc ; PR1201 define i32 @main(i32 %argc, i8** %argv) { %c_19 = alloca i8* ; <i8**> [#uses=2] diff --git a/test/Transforms/InstCombine/malloc2.ll b/test/Transforms/InstCombine/malloc2.ll index 102422e..8462dac 100644 --- a/test/Transforms/InstCombine/malloc2.ll +++ b/test/Transforms/InstCombine/malloc2.ll @@ -1,19 +1,22 @@ -; RUN: opt < %s -instcombine -S | grep {ret i32 0} -; RUN: opt < %s -instcombine -S | not grep malloc +; RUN: opt < %s -instcombine -S | FileCheck %s ; PR1313 define i32 @test1(i32 %argc, i8* %argv, i8* %envp) { %tmp15.i.i.i23 = malloc [2564 x i32] ; <[2564 x i32]*> [#uses=1] +; CHECK-NOT: call i8* @malloc %c = icmp eq [2564 x i32]* %tmp15.i.i.i23, null ; <i1>:0 [#uses=1] %retval = zext i1 %c to i32 ; <i32> [#uses=1] ret i32 %retval +; CHECK: ret i32 0 } define i32 @test2(i32 %argc, i8* %argv, i8* %envp) { %tmp15.i.i.i23 = malloc [2564 x i32] ; <[2564 x i32]*> [#uses=1] +; CHECK-NOT: call i8* @malloc %X = bitcast [2564 x i32]* %tmp15.i.i.i23 to i32* %c = icmp ne i32* %X, null %retval = zext i1 %c to i32 ; <i32> [#uses=1] ret i32 %retval +; CHECK: ret i32 1 } diff --git a/test/Transforms/InstCombine/malloc3.ll b/test/Transforms/InstCombine/malloc3.ll index cd407ff..f1c0cae 100644 --- a/test/Transforms/InstCombine/malloc3.ll +++ b/test/Transforms/InstCombine/malloc3.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -instcombine -S | grep {malloc.*struct.foo} | count 2 +; RUN: opt < %s -instcombine -S | not grep load ; PR1728 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" diff --git a/test/Transforms/JumpThreading/crash.ll b/test/Transforms/JumpThreading/crash.ll index 0b6cd27..023c7d0 100644 --- a/test/Transforms/JumpThreading/crash.ll +++ b/test/Transforms/JumpThreading/crash.ll @@ -54,3 +54,38 @@ bb15: bb61: ret void } + + +; PR5258 +define i32 @test(i1 %cond, i1 %cond2, i32 %a) { +A: + br i1 %cond, label %F, label %A1 +F: + br label %A1 + +A1: + %d = phi i1 [false, %A], [true, %F] + %e = add i32 %a, %a + br i1 %d, label %B, label %G + +G: + br i1 %cond2, label %B, label %D + +B: + %f = phi i32 [%e, %G], [%e, %A1] + %b = add i32 0, 0 + switch i32 %a, label %C [ + i32 7, label %D + i32 8, label %D + i32 9, label %D + ] + +C: + br label %D + +D: + %c = phi i32 [%e, %B], [%e, %B], [%e, %B], [%f, %C], [%e, %G] + ret i32 %c +E: + ret i32 412 +}
\ No newline at end of file diff --git a/test/Transforms/LoopSimplify/unreachable-loop-pred.ll b/test/Transforms/LoopSimplify/unreachable-loop-pred.ll new file mode 100644 index 0000000..faaaf97 --- /dev/null +++ b/test/Transforms/LoopSimplify/unreachable-loop-pred.ll @@ -0,0 +1,20 @@ +; RUN: opt -S -loopsimplify -disable-output -verify-loop-info -verify-dom-info < %s +; PR5235 + +; When loopsimplify inserts a preheader for this loop, it should add the new +; block to the enclosing loop and not get confused by the unreachable +; bogus loop entry. + +define void @is_extract_cab() nounwind { +entry: + br label %header + +header: ; preds = %if.end206, %cond.end66, %if.end23 + br label %while.body115 + +while.body115: ; preds = %9, %if.end192, %if.end101 + br i1 undef, label %header, label %while.body115 + +foo: + br label %while.body115 +} diff --git a/test/Transforms/SCCP/ipsccp-basic.ll b/test/Transforms/SCCP/ipsccp-basic.ll index 7f0772e..d3584d1 100644 --- a/test/Transforms/SCCP/ipsccp-basic.ll +++ b/test/Transforms/SCCP/ipsccp-basic.ll @@ -1,13 +1,136 @@ -; RUN: opt < %s -ipsccp -S | \ -; RUN: grep -v {ret i32 17} | grep -v {ret i32 undef} | not grep ret +; RUN: opt < %s -ipsccp -S | FileCheck %s -define internal i32 @bar(i32 %A) { - %X = add i32 1, 2 ; <i32> [#uses=0] +;;======================== test1 + +define internal i32 @test1a(i32 %A) { + %X = add i32 1, 2 ret i32 %A } +; CHECK: define internal i32 @test1a +; CHECK: ret i32 undef -define i32 @foo() { - %X = call i32 @bar( i32 17 ) ; <i32> [#uses=1] +define i32 @test1b() { + %X = call i32 @test1a( i32 17 ) ret i32 %X + +; CHECK: define i32 @test1b +; CHECK: ret i32 17 +} + + + +;;======================== test2 + +define internal i32 @test2a(i32 %A) { + %C = icmp eq i32 %A, 0 + br i1 %C, label %T, label %F +T: + %B = call i32 @test2a( i32 0 ) + ret i32 0 +F: + %C.upgrd.1 = call i32 @test2a(i32 1) + ret i32 %C.upgrd.1 +} +; CHECK: define internal i32 @test2a +; CHECK-NEXT: br label %T +; CHECK: ret i32 undef + + +define i32 @test2b() { + %X = call i32 @test2a(i32 0) + ret i32 %X +} +; CHECK: define i32 @test2b +; CHECK-NEXT: %X = call i32 @test2a(i32 0) +; CHECK-NEXT: ret i32 0 + + +;;======================== test3 + +@G = internal global i32 undef + +define void @test3a() { + %X = load i32* @G + store i32 %X, i32* @G + ret void +} +; CHECK: define void @test3a +; CHECK-NEXT: ret void + + +define i32 @test3b() { + %V = load i32* @G + %C = icmp eq i32 %V, 17 + br i1 %C, label %T, label %F +T: + store i32 17, i32* @G + ret i32 %V +F: + store i32 123, i32* @G + ret i32 0 +} +; CHECK: define i32 @test3b +; CHECK-NOT: store +; CHECK: ret i32 0 + + +;;======================== test4 + +define internal {i64,i64} @test4a() { + %a = insertvalue {i64,i64} undef, i64 4, 1 + %b = insertvalue {i64,i64} %a, i64 5, 0 + ret {i64,i64} %b +} + +define i64 @test4b() { + %a = invoke {i64,i64} @test4a() + to label %A unwind label %B +A: + %b = extractvalue {i64,i64} %a, 0 + %c = call i64 @test4c(i64 %b) + ret i64 %c +B: + ret i64 0 +} +; CHECK: define i64 @test4b() +; CHECK: %c = call i64 @test4c(i64 5) +; CHECK-NEXT: ret i64 5 + + +define internal i64 @test4c(i64 %a) { + ret i64 %a +} +; CHECK: define internal i64 @test4c +; CHECK: ret i64 undef + + + +;;======================== test5 + +; PR4313 +define internal {i64,i64} @test5a() { + %a = insertvalue {i64,i64} undef, i64 4, 1 + %b = insertvalue {i64,i64} %a, i64 5, 0 + ret {i64,i64} %b +} + +define i64 @test5b() { + %a = invoke {i64,i64} @test5a() + to label %A unwind label %B +A: + %c = call i64 @test5c({i64,i64} %a) + ret i64 %c +B: + ret i64 0 +} + +; CHECK: define i64 @test5b() +; CHECK: A: +; CHECK-NEXT: %c = call i64 @test5c(%0 %a) +; CHECK-NEXT: ret i64 %c + +define internal i64 @test5c({i64,i64} %a) { + %b = extractvalue {i64,i64} %a, 0 + ret i64 %b } diff --git a/test/Transforms/SCCP/sccptest.ll b/test/Transforms/SCCP/sccptest.ll index 6f422f0..a719f6c 100644 --- a/test/Transforms/SCCP/sccptest.ll +++ b/test/Transforms/SCCP/sccptest.ll @@ -1,31 +1,58 @@ +; RUN: opt < %s -sccp -S | FileCheck %s + +; This is a basic sanity check for constant propagation. The add instruction +; should be eliminated. + +define i32 @test1(i1 %B) { + br i1 %B, label %BB1, label %BB2 +BB1: ; preds = %0 + %Val = add i32 0, 0 ; <i32> [#uses=1] + br label %BB3 +BB2: ; preds = %0 + br label %BB3 +BB3: ; preds = %BB2, %BB1 + %Ret = phi i32 [ %Val, %BB1 ], [ 1, %BB2 ] ; <i32> [#uses=1] + ret i32 %Ret + +; CHECK: @test1 +; CHECK: %Ret = phi i32 [ 0, %BB1 ], [ 1, %BB2 ] +} + ; This is the test case taken from appel's book that illustrates a hard case -; that SCCP gets right. BB3 should be completely eliminated. +; that SCCP gets right. ; -; RUN: opt < %s -sccp -constprop -dce -simplifycfg | \ -; RUN: llvm-dis | not grep BB3 - -define i32 @testfunction(i32 %i0, i32 %j0) { +define i32 @test2(i32 %i0, i32 %j0) { +; CHECK: @test2 BB1: br label %BB2 -BB2: ; preds = %BB7, %BB1 - %j2 = phi i32 [ %j4, %BB7 ], [ 1, %BB1 ] ; <i32> [#uses=2] - %k2 = phi i32 [ %k4, %BB7 ], [ 0, %BB1 ] ; <i32> [#uses=4] - %kcond = icmp slt i32 %k2, 100 ; <i1> [#uses=1] +BB2: + %j2 = phi i32 [ %j4, %BB7 ], [ 1, %BB1 ] + %k2 = phi i32 [ %k4, %BB7 ], [ 0, %BB1 ] + %kcond = icmp slt i32 %k2, 100 br i1 %kcond, label %BB3, label %BB4 -BB3: ; preds = %BB2 - %jcond = icmp slt i32 %j2, 20 ; <i1> [#uses=1] +BB3: + %jcond = icmp slt i32 %j2, 20 br i1 %jcond, label %BB5, label %BB6 -BB4: ; preds = %BB2 +; CHECK: BB3: +; CHECK-NEXT: br i1 true, label %BB5, label %BB6 +BB4: ret i32 %j2 -BB5: ; preds = %BB3 - %k3 = add i32 %k2, 1 ; <i32> [#uses=1] +; CHECK: BB4: +; CHECK-NEXT: ret i32 1 +BB5: + %k3 = add i32 %k2, 1 br label %BB7 -BB6: ; preds = %BB3 - %k5 = add i32 %k2, 1 ; <i32> [#uses=1] +BB6: + %k5 = add i32 %k2, 1 br label %BB7 -BB7: ; preds = %BB6, %BB5 - %j4 = phi i32 [ 1, %BB5 ], [ %k2, %BB6 ] ; <i32> [#uses=1] - %k4 = phi i32 [ %k3, %BB5 ], [ %k5, %BB6 ] ; <i32> [#uses=1] +; CHECK: BB6: +; CHECK-NEXT: br label %BB7 +BB7: + %j4 = phi i32 [ 1, %BB5 ], [ %k2, %BB6 ] + %k4 = phi i32 [ %k3, %BB5 ], [ %k5, %BB6 ] br label %BB2 +; CHECK: BB7: +; CHECK-NEXT: %k4 = phi i32 [ %k3, %BB5 ], [ undef, %BB6 ] +; CHECK-NEXT: br label %BB2 } |
