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| author | dim <dim@FreeBSD.org> | 2012-08-15 19:34:23 +0000 |
|---|---|---|
| committer | dim <dim@FreeBSD.org> | 2012-08-15 19:34:23 +0000 |
| commit | 721c201bd55ffb73cb2ba8d39e0570fa38c44e15 (patch) | |
| tree | eacfc83d988e4b9d11114387ae7dc41243f2a363 /test/MC/Disassembler | |
| parent | 2b2816e083a455f7a656ae88b0fd059d1688bb36 (diff) | |
| download | FreeBSD-src-721c201bd55ffb73cb2ba8d39e0570fa38c44e15.zip FreeBSD-src-721c201bd55ffb73cb2ba8d39e0570fa38c44e15.tar.gz | |
Vendor import of llvm trunk r161861:
http://llvm.org/svn/llvm-project/llvm/trunk@161861
Diffstat (limited to 'test/MC/Disassembler')
91 files changed, 1330 insertions, 1028 deletions
diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index 471076a..0c9aaab 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 -mattr +mp | FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 -mcpu=cortex-a9-mp | FileCheck %s # CHECK: addpl r4, pc, #318767104 0x4c 0x45 0x8f 0x52 diff --git a/test/MC/Disassembler/ARM/basic-arm-instructions.txt b/test/MC/Disassembler/ARM/basic-arm-instructions.txt index fc7eda5..1100ce6 100644 --- a/test/MC/Disassembler/ARM/basic-arm-instructions.txt +++ b/test/MC/Disassembler/ARM/basic-arm-instructions.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple=armv7-apple-darwin -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -disassemble < %s | FileCheck %s #------------------------------------------------------------------------------ # ADC (immediate) @@ -169,9 +169,15 @@ #------------------------------------------------------------------------------ # CHECK: add r2, pc, #3 # CHECK: sub r2, pc, #3 +# CHECK: sub r1, pc, #0 +# CHECK: sub r1, pc, #301989888 +# CHECK: add r1, pc, #301989888 0x03 0x20 0x8f 0xe2 0x03 0x20 0x4f 0xe2 +0x00 0x10 0x4f 0xe2 +0x12 0x14 0x4f 0xe2 +0x12 0x14 0x8f 0xe2 #------------------------------------------------------------------------------ # AND @@ -469,47 +475,77 @@ #------------------------------------------------------------------------------ # DMB #------------------------------------------------------------------------------ -# CHECK: dmb sy -# CHECK: dmb st -# CHECK: dmb ish -# CHECK: dmb ishst -# CHECK: dmb nsh -# CHECK: dmb nshst -# CHECK: dmb osh + +# CHECK: dmb #0x0 +# CHECK: dmb #0x1 # CHECK: dmb oshst -# CHECK: dmb +# CHECK: dmb osh +# CHECK: dmb #0x4 +# CHECK: dmb #0x5 +# CHECK: dmb nshst +# CHECK: dmb nsh +# CHECK: dmb #0x8 +# CHECK: dmb #0x9 +# CHECK: dmb ishst +# CHECK: dmb ish +# CHECK: dmb #0xc +# CHECK: dmb #0xd +# CHECK: dmb st +# CHECK: dmb sy -0x5f 0xf0 0x7f 0xf5 -0x5e 0xf0 0x7f 0xf5 -0x5b 0xf0 0x7f 0xf5 -0x5a 0xf0 0x7f 0xf5 -0x57 0xf0 0x7f 0xf5 -0x56 0xf0 0x7f 0xf5 -0x53 0xf0 0x7f 0xf5 +0x50 0xf0 0x7f 0xf5 +0x51 0xf0 0x7f 0xf5 0x52 0xf0 0x7f 0xf5 +0x53 0xf0 0x7f 0xf5 +0x54 0xf0 0x7f 0xf5 +0x55 0xf0 0x7f 0xf5 +0x56 0xf0 0x7f 0xf5 +0x57 0xf0 0x7f 0xf5 +0x58 0xf0 0x7f 0xf5 +0x59 0xf0 0x7f 0xf5 +0x5a 0xf0 0x7f 0xf5 +0x5b 0xf0 0x7f 0xf5 +0x5c 0xf0 0x7f 0xf5 +0x5d 0xf0 0x7f 0xf5 +0x5e 0xf0 0x7f 0xf5 0x5f 0xf0 0x7f 0xf5 #------------------------------------------------------------------------------ # DSB #------------------------------------------------------------------------------ -# CHECK: dsb sy -# CHECK: dsb st -# CHECK: dsb ish -# CHECK: dsb ishst -# CHECK: dsb nsh -# CHECK: dsb nshst -# CHECK: dsb osh -# CHECK: dsb oshst -# CHECK: dsb -0x4f 0xf0 0x7f 0xf5 -0x4e 0xf0 0x7f 0xf5 -0x4b 0xf0 0x7f 0xf5 -0x4a 0xf0 0x7f 0xf5 -0x47 0xf0 0x7f 0xf5 -0x46 0xf0 0x7f 0xf5 -0x43 0xf0 0x7f 0xf5 +# CHECK: dsb #0x0 +# CHECK: dsb #0x1 +# CHECK: dsb oshst +# CHECK: dsb osh +# CHECK: dsb #0x4 +# CHECK: dsb #0x5 +# CHECK: dsb nshst +# CHECK: dsb nsh +# CHECK: dsb #0x8 +# CHECK: dsb #0x9 +# CHECK: dsb ishst +# CHECK: dsb ish +# CHECK: dsb #0xc +# CHECK: dsb #0xd +# CHECK: dsb st +# CHECK: dsb sy + +0x40 0xf0 0x7f 0xf5 +0x41 0xf0 0x7f 0xf5 0x42 0xf0 0x7f 0xf5 +0x43 0xf0 0x7f 0xf5 +0x44 0xf0 0x7f 0xf5 +0x45 0xf0 0x7f 0xf5 +0x46 0xf0 0x7f 0xf5 +0x47 0xf0 0x7f 0xf5 +0x48 0xf0 0x7f 0xf5 +0x49 0xf0 0x7f 0xf5 +0x4a 0xf0 0x7f 0xf5 +0x4b 0xf0 0x7f 0xf5 +0x4c 0xf0 0x7f 0xf5 +0x4d 0xf0 0x7f 0xf5 +0x4e 0xf0 0x7f 0xf5 0x4f 0xf0 0x7f 0xf5 #------------------------------------------------------------------------------ diff --git a/test/MC/Disassembler/ARM/fp-encoding.txt b/test/MC/Disassembler/ARM/fp-encoding.txt index 9095b84..8dedf80 100644 --- a/test/MC/Disassembler/ARM/fp-encoding.txt +++ b/test/MC/Disassembler/ARM/fp-encoding.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple armv7-apple-darwin -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple armv7-apple-darwin -mcpu=cortex-a8 -disassemble < %s | FileCheck %s 0xa0 0x0b 0x71 0xee # CHECK: vadd.f64 d16, d17, d16 @@ -203,6 +203,33 @@ # CHECK: vstmia r1, {d2, d3, d4, d5, d6, d7} # CHECK: vstmia r1, {s2, s3, s4, s5, s6, s7} +0x05 0x9a 0xc0 0x0c +0x0c 0x0b 0xc7 0x0c +0x06 0x9a 0x93 0x0c +0x0a 0x5b 0xd2 0x0c +# CHECK: vstmiaeq r0, {s19, s20, s21, s22, s23} +# CHECK: vstmiaeq r7, {d16, d17, d18, d19, d20, d21} +# CHECK: vldmiaeq r3, {s18, s19, s20, s21, s22, s23} +# CHECK: vldmiaeq r2, {d21, d22, d23, d24, d25} + +0x04 0xca 0x6c 0x0d +0x06 0x1b 0x69 0x0d +0x03 0xaa 0x75 0x0d +0x08 0xeb 0x37 0x0d +# CHECK: vstmdbeq r12!, {s25, s26, s27, s28} +# CHECK: vstmdbeq r9!, {d17, d18, d19} +# CHECK: vldmdbeq r5!, {s21, s22, s23} +# CHECK: vldmdbeq r7!, {d14, d15, d16, d17} + +0x04 0x7a 0xa6 0x0c +0x0c 0xfb 0xa4 0x0c +0x03 0xaa 0xf8 0x0c +0x0a 0x3b 0xfb 0x0c +# CHECK: vstmiaeq r6!, {s14, s15, s16, s17} +# CHECK: vstmiaeq r4!, {d15, d16, d17, d18, d19, d20} +# CHECK: vldmiaeq r8!, {s21, s22, s23} +# CHECK: vldmiaeq r11!, {d19, d20, d21, d22, d23} + 0x40 0x0b 0xbd 0xee 0x60 0x0a 0xbd 0xee 0x40 0x0b 0xbc 0xee diff --git a/test/MC/Disassembler/ARM/invalid-BFI-arm.txt b/test/MC/Disassembler/ARM/invalid-BFI-arm.txt index a0d5944..f7acce9 100644 --- a/test/MC/Disassembler/ARM/invalid-BFI-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-BFI-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=60 Name=BFI Format=ARM_FORMAT_DPFRM(4) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt b/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt index d2d424c..356c376 100644 --- a/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=2249 Name=tBcc Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt b/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt index 10748e9..bc8b7e1 100644 --- a/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # invalid imod value (0b01) 0xc0 0x67 0x4 0xf1 diff --git a/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt b/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt index 8146b5c..842a52b 100644 --- a/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {potentially undefined instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding" # invalid (imod, M, iflags) combination 0x93 0x00 0x02 0xf1 diff --git a/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt b/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt index b441485..8396156 100644 --- a/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=1908 Name=t2DMB Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-DSB-arm.txt b/test/MC/Disassembler/ARM/invalid-DSB-arm.txt index de042a97..2c6e6a7 100644 --- a/test/MC/Disassembler/ARM/invalid-DSB-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-DSB-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=102 Name=DSB Format=ARM_FORMAT_MISCFRM(26) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt b/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt index 6174e92..4297c01 100644 --- a/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {potentially undefined instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding" # CBZ / CBNZ not allowed in IT block. diff --git a/test/MC/Disassembler/ARM/invalid-IT-CC15.txt b/test/MC/Disassembler/ARM/invalid-IT-CC15.txt index 17e25ea..733895d 100644 --- a/test/MC/Disassembler/ARM/invalid-IT-CC15.txt +++ b/test/MC/Disassembler/ARM/invalid-IT-CC15.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-unknown-unknown |& grep und +# RUN: llvm-mc --disassemble %s -triple=thumbv7-unknown-unknown 2>&1 | grep und # rdar://10841671 0xe3 0xbf diff --git a/test/MC/Disassembler/ARM/invalid-IT-thumb.txt b/test/MC/Disassembler/ARM/invalid-IT-thumb.txt index 9b571b3..1a8ff48 100644 --- a/test/MC/Disassembler/ARM/invalid-IT-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-IT-thumb.txt @@ -1,3 +1,3 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-unknown-unknown |& grep {potentially undefined instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumbv7-unknown-unknown 2>&1 | grep "potentially undefined instruction encoding" 0xff 0xbf 0x6b 0x80 0x00 0x75 diff --git a/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt b/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt index 0b0426b..6cff09e 100644 --- a/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=0 Name=PHI Format=(42) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt b/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt index a42b248..7d8c492 100644 --- a/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {potentially undefined instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding" # Writeback is not allowed is Rn is in the target register list. diff --git a/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt b/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt index 6b695b9..68d22de 100644 --- a/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {potentially undefined instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding" # Opcode=140 Name=LDRB_POST Format=ARM_FORMAT_LDFRM(6) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt b/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt index 7ea1b46..4df5309 100644 --- a/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=1930 Name=t2LDRD_PRE Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt b/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt index eef2c45..0cff28a 100644 --- a/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # XFAIL: * # LDR_PRE/POST has encoding Inst{4} = 0. diff --git a/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt b/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt index e42e0de..30cb727 100644 --- a/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {potentially undefined instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding" # Opcode=165 Name=LDR_PRE Format=ARM_FORMAT_LDFRM(6) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt b/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt index 23a0b85..7b7286a 100644 --- a/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # LDR (register) has encoding Inst{4} = 0. 0xba 0xae 0x9f 0x57 diff --git a/test/MC/Disassembler/ARM/invalid-MCR-arm.txt b/test/MC/Disassembler/ARM/invalid-MCR-arm.txt index 8343d54..bb4b06c 100644 --- a/test/MC/Disassembler/ARM/invalid-MCR-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-MCR-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=171 Name=MCR Format=ARM_FORMAT_BRFRM(2) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt index 235952f..528563a 100644 --- a/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=185 Name=MOVTi16 Format=ARM_FORMAT_DPFRM(4) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt index 01c1466..41ec53f 100644 --- a/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=0 Name=PHI Format=(42) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt index 757d167..e5f2a5e 100644 --- a/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt index ba48877..3f4c1e5 100644 --- a/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=0 Name=PHI Format=(42) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt b/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt index aaae6ce..c20ce54 100644 --- a/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s # CHECK: invalid instruction encoding 0x00 0x1a 0x50 0xfc diff --git a/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt b/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt index 3765b1f..901667a 100644 --- a/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=206 Name=MSRi Format=ARM_FORMAT_BRFRM(2) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt b/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt index cffd86d..499aa86 100644 --- a/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=134 Name=LDMIA Format=ARM_FORMAT_LDSTMULFRM(10) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt b/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt index 9e16536..7bc97d5 100644 --- a/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=271 Name=SBFX Format=ARM_FORMAT_DPFRM(4) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt b/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt index 91f3d58..fe4f43a 100644 --- a/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=284 Name=SMLAD Format=ARM_FORMAT_MULFRM(1) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-SRS-arm.txt b/test/MC/Disassembler/ARM/invalid-SRS-arm.txt index fc5c711..eedd05c 100644 --- a/test/MC/Disassembler/ARM/invalid-SRS-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-SRS-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=0 Name=PHI Format=(42) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt index ca16724..3d5235d 100644 --- a/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=2313 Name=tSTMIA_UPD Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt b/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt index 400d44c..f67f38e 100644 --- a/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=390 Name=SXTBr_rot Format=ARM_FORMAT_EXTFRM(14) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt b/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt index c7cbd84..f57c48f 100644 --- a/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=419 Name=UMAAL Format=ARM_FORMAT_MULFRM(1) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt b/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt index 12da869..5ba7d61 100644 --- a/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | grep "invalid instruction encoding" # XFAIL: * # Opcode=737 Name=VLD1DUPq8_UPD Format=ARM_FORMAT_NLdSt(30) diff --git a/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt index bab32ca..58def05 100644 --- a/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=871 Name=VLD3DUPd32_UPD Format=ARM_FORMAT_NLdSt(30) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt b/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt index 887b983..54fcadb 100644 --- a/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" # core registers out of range 0xa5 0xba 0x72 0xed diff --git a/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt b/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt index a53f940..f961c64 100644 --- a/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | grep "invalid instruction encoding" # XFAIL: * # Opcode=1225 Name=VQADDsv16i8 Format=ARM_FORMAT_N3Reg(37) diff --git a/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt b/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt index 8ff3a2b..2d2a628 100644 --- a/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=1839 Name=VST1d8Twb_register Format=ARM_FORMAT_NLdSt(30) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt b/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt index a12ca95..07a1c7a 100644 --- a/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | grep "invalid instruction encoding" # XFAIL: * # Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) diff --git a/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt index df0a642..c9f1cf1 100644 --- a/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=1894 Name=t2Bcc Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt index e1f841b8..eb415f7 100644 --- a/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=1922 Name=t2LDRBT Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt index 7c0efab..6c13560 100644 --- a/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding" # XFAIL: * # Opcode=1934 Name=t2LDREXD Format=ARM_FORMAT_THUMBFRM(25) diff --git a/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt index a63d121..7f84e08 100644 --- a/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=1953 Name=t2LDRSHi12 Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt index f126ff0..e44cf95 100644 --- a/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=1954 Name=t2LDRSHi8 Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-t2PUSH-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2PUSH-thumb.txt index b3daa9a..8c0d48b 100644 --- a/test/MC/Disassembler/ARM/invalid-t2PUSH-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2PUSH-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding" # SP and PC are not allowed in the register list on STM instructions in Thumb2. diff --git a/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt index 2198efc..64ba368 100644 --- a/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding" # XFAIL: * # Opcode=2124 Name=t2STRD_PRE Format=ARM_FORMAT_THUMBFRM(25) diff --git a/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt index 3f406d4..243c11d 100644 --- a/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding" # XFAIL: * # Opcode=2127 Name=t2STREXB Format=ARM_FORMAT_THUMBFRM(25) diff --git a/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt index 0f9a16e..7a7c4a5 100644 --- a/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=2128 Name=t2STREXD Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt index 548ad05..2ad3e7d 100644 --- a/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" # Opcode=2137 Name=t2STR_POST Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/ldrd-armv4.txt b/test/MC/Disassembler/ARM/ldrd-armv4.txt index bb87ade..f2fff3f 100644 --- a/test/MC/Disassembler/ARM/ldrd-armv4.txt +++ b/test/MC/Disassembler/ARM/ldrd-armv4.txt @@ -1,5 +1,5 @@ -# RUN: llvm-mc --disassemble %s -triple=armv4-linux-gnueabi |& FileCheck %s -check-prefix=V4 -# RUN: llvm-mc --disassemble %s -triple=armv5te-linux-gnueabi |& FileCheck %s -check-prefix=V5TE +# RUN: llvm-mc --disassemble %s -triple=armv4-linux-gnueabi 2>&1 | FileCheck %s -check-prefix=V4 +# RUN: llvm-mc --disassemble %s -triple=armv5te-linux-gnueabi 2>&1 | FileCheck %s -check-prefix=V5TE # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- diff --git a/test/MC/Disassembler/ARM/neon-tests.txt b/test/MC/Disassembler/ARM/neon-tests.txt index f44c2a0..a7b6b1c 100644 --- a/test/MC/Disassembler/ARM/neon-tests.txt +++ b/test/MC/Disassembler/ARM/neon-tests.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 | FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 -mcpu=cortex-a8 | FileCheck %s # CHECK: vbif q15, q7, q0 0x50 0xe1 0x7e 0xf3 diff --git a/test/MC/Disassembler/ARM/neon.txt b/test/MC/Disassembler/ARM/neon.txt index c5dbee3..649424a 100644 --- a/test/MC/Disassembler/ARM/neon.txt +++ b/test/MC/Disassembler/ARM/neon.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple armv7-unknown-unknown -disassemble -mattr +fp16 < %s | FileCheck %s +# RUN: llvm-mc -triple armv7-unknown-unknown -mcpu=cortex-a9 -disassemble < %s | FileCheck %s 0x20 0x03 0xf1 0xf3 # CHECK: vabs.s8 d16, d16 @@ -1734,6 +1734,25 @@ 0xcf 0x1a 0xe0 0xf4 # CHECK: vld3.32 {d17[1], d19[1], d21[1]}, [r0] +# CHECK: vld3.8 {d0[], d1[], d2[]}, [r4] +0x0f 0x0e 0xa4 0xf4 +# CHECK: vld3.8 {d0[], d1[], d2[]}, [r4]! +0x0d 0x0e 0xa4 0xf4 +# CHECK: vld3.8 {d0[], d2[], d4[]}, [r4], r5 +0x25 0x0e 0xa4 0xf4 +# CHECK: vld3.16 {d0[], d2[], d4[]}, [r4] +0x6f 0x0e 0xa4 0xf4 +# CHECK: vld3.16 {d0[], d1[], d2[]}, [r4]! +0x4d 0x0e 0xa4 0xf4 +# CHECK: vld3.16 {d0[], d2[], d4[]}, [r4], r5 +0x65 0x0e 0xa4 0xf4 +# CHECK: vld3.32 {d0[], d1[], d2[]}, [r4] +0x8f 0x0e 0xa4 0xf4 +# CHECK: vld3.32 {d0[], d1[], d2[]}, [r4]! +0x8d 0x0e 0xa4 0xf4 +# CHECK: vld3.32 {d0[], d2[], d4[]}, [r4], r5 +0xa5 0x0e 0xa4 0xf4 + 0x3f 0x03 0xe0 0xf4 # CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] 0x4f 0x07 0xe0 0xf4 @@ -1745,6 +1764,30 @@ 0x4f 0x1b 0xe0 0xf4 # CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] +0x0f 0x0f 0xa4 0xf4 +# CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4] +0x3f 0x0f 0xa4 0xf4 +# CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4, :32] +0x1d 0x0f 0xa4 0xf4 +# CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4, :32]! +0x35 0x0f 0xa4 0xf4 +# CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4, :32], r5 +0x4f 0x0f 0xa4 0xf4 +# CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4] +0x7f 0x0f 0xa4 0xf4 +# CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4, :64] +0x5d 0x0f 0xa4 0xf4 +# CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4, :64]! +0x75 0x0f 0xa4 0xf4 +# CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4, :64], r5 +0x8f 0x0f 0xa4 0xf4 +# CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4] +0xbf 0x0f 0xa4 0xf4 +# CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4, :64] +0xdd 0x0f 0xa4 0xf4 +# CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4, :128]! +0xf5 0x0f 0xa4 0xf4 +# CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4, :128], r5 0x1f 0x07 0x40 0xf4 @@ -1852,7 +1895,26 @@ # CHECK: vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0]! 0x3d 0x2a 0x5e 0x6c -# CHECK: vmovvs r2, lr, s29, s30 +# CHECK: vmovvs r2, lr, s27, s28 + +0x31 0x1a 0x42 0xec +0x11 0x1a 0x42 0xec +0x31 0x1a 0x52 0xec +0x11 0x1a 0x52 0xec +# CHECK: vmov s3, s4, r1, r2 +# CHECK: vmov s2, s3, r1, r2 +# CHECK: vmov r1, r2, s3, s4 +# CHECK: vmov r1, r2, s2, s3 + +0x1f 0x1b 0x42 0xec +0x30 0x1b 0x42 0xec +0x1f 0x1b 0x52 0xec +0x30 0x1b 0x52 0xec +# CHECK: vmov d15, r1, r2 +# CHECK: vmov d16, r1, r2 +# CHECK: vmov r1, r2, d15 +# CHECK: vmov r1, r2, d16 + 0xe9 0x1a 0xb2 0x4e # CHECK: vcvttmi.f32.f16 s2, s19 @@ -1869,14 +1931,6 @@ # CHECK: vmov.f32 d0, #1.600000e+01 # CHECK: vmov.f32 q0, #1.600000e+01 -# rdar://10798451 -0xe7 0xf9 0x32 0x1d -# CHECK vld2.8 {d17[], d19[]}, [r7, :16], r2 -0xe7 0xf9 0x3d 0x1d -# CHECK vld2.8 {d17[], d19[]}, [r7, :16]! -0xe7 0xf9 0x3f 0x1d -# CHECK vld2.8 {d17[], d19[]}, [r7, :16] - # rdar://11034702 0x0d 0x87 0x04 0xf4 # CHECK: vst1.8 {d8}, [r4]! diff --git a/test/MC/Disassembler/ARM/neont2.txt b/test/MC/Disassembler/ARM/neont2.txt index 65cd230..7d7010f 100644 --- a/test/MC/Disassembler/ARM/neont2.txt +++ b/test/MC/Disassembler/ARM/neont2.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple thumbv7-unknown-unknown -disassemble -mattr +fp16 < %s | FileCheck %s +# RUN: llvm-mc -triple thumbv7-unknown-unknown -mcpu=cortex-a9 -disassemble < %s | FileCheck %s 0xf1 0xff 0x20 0x03 # CHECK: vabs.s8 d16, d16 @@ -1475,6 +1475,25 @@ 0xe0 0xf9 0xcf 0x1a # CHECK: vld3.32 {d17[1], d19[1], d21[1]}, [r0] +0xa4 0xf9 0x0f 0x0e +# CHECK: vld3.8 {d0[], d1[], d2[]}, [r4] +0xa4 0xf9 0x0d 0x0e +# CHECK: vld3.8 {d0[], d1[], d2[]}, [r4]! +0xa4 0xf9 0x25 0x0e +# CHECK: vld3.8 {d0[], d2[], d4[]}, [r4], r5 +0xa4 0xf9 0x6f 0x0e +# CHECK: vld3.16 {d0[], d2[], d4[]}, [r4] +0xa4 0xf9 0x4d 0x0e +# CHECK: vld3.16 {d0[], d1[], d2[]}, [r4]! +0xa4 0xf9 0x65 0x0e +# CHECK: vld3.16 {d0[], d2[], d4[]}, [r4], r5 +0xa4 0xf9 0x8f 0x0e +# CHECK: vld3.32 {d0[], d1[], d2[]}, [r4] +0xa4 0xf9 0x8d 0x0e +# CHECK: vld3.32 {d0[], d1[], d2[]}, [r4]! +0xa4 0xf9 0xa5 0x0e +# CHECK: vld3.32 {d0[], d2[], d4[]}, [r4], r5 + 0xe0 0xf9 0x3f 0x03 # CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] 0xe0 0xf9 0x4f 0x07 @@ -1486,6 +1505,31 @@ 0xe0 0xf9 0x4f 0x1b # CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] +0xa4 0xf9 0x0f 0x0f +# CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4] +0xa4 0xf9 0x3f 0x0f +# CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4, :32] +0xa4 0xf9 0x1d 0x0f +# CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4, :32]! +0xa4 0xf9 0x35 0x0f +# CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4, :32], r5 +0xa4 0xf9 0x4f 0x0f +# CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4] +0xa4 0xf9 0x7f 0x0f +# CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4, :64] +0xa4 0xf9 0x5d 0x0f +# CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4, :64]! +0xa4 0xf9 0x75 0x0f +# CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4, :64], r5 +0xa4 0xf9 0x8f 0x0f +# CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4] +0xa4 0xf9 0xbf 0x0f +# CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4, :64] +0xa4 0xf9 0xdd 0x0f +# CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4, :128]! +0xa4 0xf9 0xf5 0x0f +# CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4, :128], r5 + 0x40 0xf9 0x1f 0x07 # CHECK: vst1.8 {d16}, [r0, :64] 0x40 0xf9 0x4f 0x07 @@ -1998,3 +2042,13 @@ # CHECK: vld2.16 {d0[], d2[]}, [r3], r4 0xa3 0xf9 0xa4 0x0d # CHECK: vld2.32 {d0[], d2[]}, [r3], r4 + + +# rdar://10798451 +0xe7 0xf9 0x32 0x1d +# CHECK: vld2.8 {d17[], d19[]}, [r7, :16], r2 +0xe7 0xf9 0x3d 0x1d +# CHECK: vld2.8 {d17[], d19[]}, [r7, :16]! +0xe7 0xf9 0x3f 0x1d +# CHECK: vld2.8 {d17[], d19[]}, [r7, :16] + diff --git a/test/MC/Disassembler/ARM/thumb-tests.txt b/test/MC/Disassembler/ARM/thumb-tests.txt index 18b8f47..c08585a 100644 --- a/test/MC/Disassembler/ARM/thumb-tests.txt +++ b/test/MC/Disassembler/ARM/thumb-tests.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 -mattr +t2xtpk,+mp | FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 -mcpu=cortex-a9-mp | FileCheck %s # CHECK: add r5, sp, #68 0x11 0xad @@ -301,3 +301,11 @@ # CHECK: mrs r0, apsr 0xef 0xf3 0x00 0x80 + +# rdar://11313994 +# CHECK: blx #2313244 +0x34 0xf2 0x0e 0xee + +# rdar://11324693 +# CHECK: bl #-12303196 +0x44 0xf4 0x52 0xda diff --git a/test/MC/Disassembler/ARM/thumb1.txt b/test/MC/Disassembler/ARM/thumb1.txt index 17c4bad..5b70262 100644 --- a/test/MC/Disassembler/ARM/thumb1.txt +++ b/test/MC/Disassembler/ARM/thumb1.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple=thumbv6-apple-darwin -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=thumbv6-apple-darwin -disassemble -show-encoding < %s | FileCheck %s #------------------------------------------------------------------------------ # ADC (register) @@ -83,6 +83,15 @@ 0xb1 0x43 #------------------------------------------------------------------------------ +# B +#------------------------------------------------------------------------------ +# CHECK: bls #128 @ encoding: [0x40,0xd9] +# CHECK: beq #-256 @ encoding: [0x80,0xd0] + +0x40 0xd9 +0x80 0xd0 + +#------------------------------------------------------------------------------ # BKPT #------------------------------------------------------------------------------ # CHECK: bkpt #0 @@ -516,15 +525,3 @@ 0xd7 0xb2 0xa1 0xb2 - - -#------------------------------------------------------------------------------ -# WFE/WFI/YIELD -#------------------------------------------------------------------------------ -# CHECK: wfe -# CHECK: wfi -# CHECK: yield - -0x20 0xbf -0x30 0xbf -0x10 0xbf diff --git a/test/MC/Disassembler/ARM/thumb2.txt b/test/MC/Disassembler/ARM/thumb2.txt index ed8d988..42ebe58 100644 --- a/test/MC/Disassembler/ARM/thumb2.txt +++ b/test/MC/Disassembler/ARM/thumb2.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple=thumbv7-apple-darwin -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -disassemble < %s | FileCheck %s #------------------------------------------------------------------------------ # ADC (immediate) @@ -92,9 +92,11 @@ #------------------------------------------------------------------------------ # CHECK: subw r11, pc, #3270 # CHECK: subw r11, pc, #826 +# CHECK: subw r1, pc, #0 0xaf 0xf6 0xc6 0x4b 0xaf 0xf2 0x3a 0x3b +0xaf 0xf2 0x00 0x01 #------------------------------------------------------------------------------ # AND (immediate) @@ -344,23 +346,37 @@ #------------------------------------------------------------------------------ #CHECK: dmb sy #CHECK: dmb st +#CHECK: dmb #0xd +#CHECK: dmb #0xc #CHECK: dmb ish #CHECK: dmb ishst +#CHECK: dmb #0x9 +#CHECK: dmb #0x8 #CHECK: dmb nsh #CHECK: dmb nshst +#CHECK: dmb #0x5 +#CHECK: dmb #0x4 #CHECK: dmb osh #CHECK: dmb oshst -#CHECK: dmb +#CHECK: dmb #0x1 +#CHECK: dmb #0x0 0xbf 0xf3 0x5f 0x8f 0xbf 0xf3 0x5e 0x8f +0xbf 0xf3 0x5d 0x8f +0xbf 0xf3 0x5c 0x8f 0xbf 0xf3 0x5b 0x8f 0xbf 0xf3 0x5a 0x8f +0xbf 0xf3 0x59 0x8f +0xbf 0xf3 0x58 0x8f 0xbf 0xf3 0x57 0x8f 0xbf 0xf3 0x56 0x8f +0xbf 0xf3 0x55 0x8f +0xbf 0xf3 0x54 0x8f 0xbf 0xf3 0x53 0x8f 0xbf 0xf3 0x52 0x8f -0xbf 0xf3 0x5f 0x8f +0xbf 0xf3 0x51 0x8f +0xbf 0xf3 0x50 0x8f #------------------------------------------------------------------------------ @@ -368,21 +384,37 @@ #------------------------------------------------------------------------------ #CHECK: dsb sy #CHECK: dsb st +#CHECK: dsb #0xd +#CHECK: dsb #0xc #CHECK: dsb ish #CHECK: dsb ishst +#CHECK: dsb #0x9 +#CHECK: dsb #0x8 #CHECK: dsb nsh #CHECK: dsb nshst +#CHECK: dsb #0x5 +#CHECK: dsb #0x4 #CHECK: dsb osh #CHECK: dsb oshst +#CHECK: dsb #0x1 +#CHECK: dsb #0x0 0xbf 0xf3 0x4f 0x8f 0xbf 0xf3 0x4e 0x8f +0xbf 0xf3 0x4d 0x8f +0xbf 0xf3 0x4c 0x8f 0xbf 0xf3 0x4b 0x8f 0xbf 0xf3 0x4a 0x8f +0xbf 0xf3 0x49 0x8f +0xbf 0xf3 0x48 0x8f 0xbf 0xf3 0x47 0x8f 0xbf 0xf3 0x46 0x8f +0xbf 0xf3 0x45 0x8f +0xbf 0xf3 0x44 0x8f 0xbf 0xf3 0x43 0x8f 0xbf 0xf3 0x42 0x8f +0xbf 0xf3 0x41 0x8f +0xbf 0xf3 0x40 0x8f #------------------------------------------------------------------------------ @@ -609,6 +641,9 @@ # CHECK: ldrd r3, r5, [r6], #-8 # CHECK: ldrd r3, r5, [r6] # CHECK: ldrd r8, r1, [r3] +# CHECK: ldrd r0, r1, [r2], #-0 +# CHECK: ldrd r0, r1, [r2, #-0]! +# CHECK: ldrd r0, r1, [r2, #-0] 0xd6 0xe9 0x06 0x35 0xf6 0xe9 0x06 0x35 @@ -616,6 +651,9 @@ 0x76 0xe8 0x02 0x35 0xd6 0xe9 0x00 0x35 0xd3 0xe9 0x00 0x81 +0x72 0xe8 0x00 0x01 +0x72 0xe9 0x00 0x01 +0x52 0xe9 0x00 0x01 #------------------------------------------------------------------------------ @@ -1790,12 +1828,16 @@ # STRD (immediate) #------------------------------------------------------------------------------ # CHECK: strd r6, r3, [r5], #-8 -# CHECK: strd r8, r5, [r5]{{$}} +# CHECK: strd r8, r5, [r5], #-0 # CHECK: strd r7, r4, [r5], #-4 +# CHECK: strd r0, r1, [r2, #-0]! +# CHECK: strd r0, r1, [r2, #-0] 0x65 0xe8 0x02 0x63 0x65 0xe8 0x00 0x85 0x65 0xe8 0x01 0x74 +0x62 0xe9 0x00 0x01 +0x42 0xe9 0x00 0x01 #------------------------------------------------------------------------------ # STREX/STREXB/STREXH/STREXD diff --git a/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt b/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt index 275bae2f..d5c8cbb 100644 --- a/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-ADC-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s # CHECK: potentially undefined # CHECK: 0x1f 0x12 0xb0 0x00 diff --git a/test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt b/test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt index 635b66e..d251eb4 100644 --- a/test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-ADDREXT3-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s # CHECK: potentially undefined # CHECK: 0xd1 0xf1 0x5f 0x01 diff --git a/test/MC/Disassembler/ARM/unpredictable-AExtI-arm.txt b/test/MC/Disassembler/ARM/unpredictable-AExtI-arm.txt new file mode 100644 index 0000000..d0cb520 --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-AExtI-arm.txt @@ -0,0 +1,62 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s -check-prefix=CHECK-WARN +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x03 0xaf 0x06 +# CHECK: sxtb +0x74 0x03 0xaf 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xbf 0x06 +# CHECK: sxth +0x74 0x3f 0xbf 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xa6 0x06 +# CHECK: sxtab +0x74 0x3f 0xa6 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xb7 0x06 +# CHECK: sxtah +0x74 0x3f 0xb7 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0x8f 0x06 +# CHECK: sxtb16 +0x74 0x3f 0x8f 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0x86 0x06 +# CHECK: sxtab16 +0x74 0x3f 0x86 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xef 0x06 +# CHECK: uxtb +0x74 0x3f 0xef 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xff 0x06 +# CHECK: uxth +0x74 0x3f 0xff 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xcf 0x06 +# CHECK: uxtb16 +0x74 0x3f 0xcf 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xe4 0x06 +# CHECK: uxtab +0x74 0x3f 0xe4 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xf2 0x06 +# CHECK: uxtah +0x74 0x3f 0xf2 0x06 + +# CHECK-WARN: potentially undefined +# CHECK-WARN: 0x74 0x3f 0xc4 0x06 +# CHECK: uxtab16 +0x74 0x3f 0xc4 0x06 diff --git a/test/MC/Disassembler/ARM/unpredictable-AI1cmp-arm.txt b/test/MC/Disassembler/ARM/unpredictable-AI1cmp-arm.txt index dac4390..554ae53 100644 --- a/test/MC/Disassembler/ARM/unpredictable-AI1cmp-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-AI1cmp-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s # CHECK: potentially undefined # CHECK: 0x01 0x10 0x50 0x03 diff --git a/test/MC/Disassembler/ARM/unpredictable-LDR-arm.txt b/test/MC/Disassembler/ARM/unpredictable-LDR-arm.txt index ed5e350..66073a8 100644 --- a/test/MC/Disassembler/ARM/unpredictable-LDR-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-LDR-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s # CHECK: potentially undefined # CHECK: 0xff 0x00 0xb9 0x00 diff --git a/test/MC/Disassembler/ARM/unpredictable-LDRD-arm.txt b/test/MC/Disassembler/ARM/unpredictable-LDRD-arm.txt index a8f54f7..572d844 100644 --- a/test/MC/Disassembler/ARM/unpredictable-LDRD-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-LDRD-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- diff --git a/test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt b/test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt index f7d6bc6..9c26953 100644 --- a/test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt +++ b/test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s # Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/unpredictable-MRRC2-arm.txt b/test/MC/Disassembler/ARM/unpredictable-MRRC2-arm.txt index 26b286d..439aaed 100644 --- a/test/MC/Disassembler/ARM/unpredictable-MRRC2-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-MRRC2-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s # CHECK: potentially undefined # CHECK: 0x00 0x10 0x51 0xfc diff --git a/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt b/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt index 3e472cd..d785341 100644 --- a/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s # CHECK: warning: potentially undefined # CHECK: 0x00 0xf0 0x0f 0x01 diff --git a/test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt b/test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt index 3db86cc..472868f 100644 --- a/test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-MUL-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s # CHECK: potentially undefined # CHECK: 0x93 0x12 0x01 0x00 diff --git a/test/MC/Disassembler/ARM/unpredictable-RSC-arm.txt b/test/MC/Disassembler/ARM/unpredictable-RSC-arm.txt index 5b13610..fdfda6d 100644 --- a/test/MC/Disassembler/ARM/unpredictable-RSC-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-RSC-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s # Opcode=261 Name=RSCrs Format=ARM_FORMAT_DPSOREGFRM(5) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/unpredictable-SEL-arm.txt b/test/MC/Disassembler/ARM/unpredictable-SEL-arm.txt new file mode 100644 index 0000000..a2a8770 --- /dev/null +++ b/test/MC/Disassembler/ARM/unpredictable-SEL-arm.txt @@ -0,0 +1,5 @@ +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s + +# CHECK: potentially undefined +# CHECK: 0xb4 0x38 0x80 0x06 +0xb4 0x38 0x80 0x06 diff --git a/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt b/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt index 8ec49ca..741d059 100644 --- a/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-SHADD16-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s # CHECK: warning: potentially undefined # CHECK: shadd16 r5, r7, r0 diff --git a/test/MC/Disassembler/ARM/unpredictable-SSAT-arm.txt b/test/MC/Disassembler/ARM/unpredictable-SSAT-arm.txt index 874378e..832aa3f 100644 --- a/test/MC/Disassembler/ARM/unpredictable-SSAT-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-SSAT-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s # Opcode=322 Name=SSAT Format=ARM_FORMAT_SATFRM(13) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/unpredictable-STRBrs-arm.txt b/test/MC/Disassembler/ARM/unpredictable-STRBrs-arm.txt index fef6125..5e62802 100644 --- a/test/MC/Disassembler/ARM/unpredictable-STRBrs-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-STRBrs-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s # Opcode=355 Name=STRBrs Format=ARM_FORMAT_STFRM(7) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/unpredictable-UQADD8-arm.txt b/test/MC/Disassembler/ARM/unpredictable-UQADD8-arm.txt index 4c4c9ab..85b52dd 100644 --- a/test/MC/Disassembler/ARM/unpredictable-UQADD8-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-UQADD8-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | FileCheck %s # Opcode=426 Name=UQADD8 Format=ARM_FORMAT_DPFRM(4) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt b/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt index 64bb171..eef5d9f 100644 --- a/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt +++ b/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s # CHECK: potentially undefined # CHECK: 0x9f 0x10 0x03 0x01 diff --git a/test/MC/Disassembler/ARM/unpredictables-thumb.txt b/test/MC/Disassembler/ARM/unpredictables-thumb.txt index e7645f0..925dcd3 100644 --- a/test/MC/Disassembler/ARM/unpredictables-thumb.txt +++ b/test/MC/Disassembler/ARM/unpredictables-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7 |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=thumbv7 2>&1 | FileCheck %s 0x01 0x47 # CHECK: 3:1: warning: potentially undefined diff --git a/test/MC/Disassembler/Mips/lit.local.cfg b/test/MC/Disassembler/Mips/lit.local.cfg new file mode 100644 index 0000000..9b698b2 --- /dev/null +++ b/test/MC/Disassembler/Mips/lit.local.cfg @@ -0,0 +1,6 @@ +config.suffixes = ['.txt'] + +targets = set(config.root.targets_to_build.split()) +if not 'Mips' in targets: + config.unsupported = True + diff --git a/test/MC/Disassembler/Mips/mips32.txt b/test/MC/Disassembler/Mips/mips32.txt index 591d8c4..a193319 100644 --- a/test/MC/Disassembler/Mips/mips32.txt +++ b/test/MC/Disassembler/Mips/mips32.txt @@ -1,421 +1,406 @@ -# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux | FileCheck %s +# CHECK: .section __TEXT,__text,regular,pure_instructions +# CHECK: abs.d $f12, $f14 +0x46 0x20 0x73 0x05 -# CHECK: abs.d $f12,$f14 -0x46 0x20 0x39 0x85 - -# CHECK: abs.s $f6,$f7 +# CHECK: abs.s $f6, $f7 0x46 0x00 0x39 0x85 -# CHECK: add t1,a2,a3 +# CHECK: add $9, $6, $7 0x00 0xc7 0x48 0x20 -# CHECK: add.d $f18,$f12,$f14 -0x46 0x27 0x32 0x40 +# CHECK: add.d $f8, $f12, $f14 +0x46 0x2e 0x62 0x00 -# CHECK: add.s $f9,$f6,$f7 +# CHECK: add.s $f9, $f6, $f7 0x46 0x07 0x32 0x40 -# CHECK: addi t1,a2,17767 +# CHECK: addi $9, $6, 17767 0x20 0xc9 0x45 0x67 -# CHECK: addiu t1,a2,-15001 +# CHECK: addiu $9, $6, -15001 0x24 0xc9 0xc5 0x67 -# CHECK: addu t1,a2,a3 +# CHECK: addu $9, $6, $7 0x00 0xc7 0x48 0x21 -# CHECK: and t1,a2,a3 +# CHECK: and $9, $6, $7 0x00 0xc7 0x48 0x24 -# CHECK: andi t1,a2,0x4567 +# CHECK: andi $9, $6, 17767 0x30 0xc9 0x45 0x67 -# CHECK: b 00000534 +# CHECK: b 1332 0x10 0x00 0x01 0x4c -# CHECK: bal 00000534 -0x04 0x11 0x01 0x4c - -# CHECK: bc1f 00000534 +# CHECK: bc1f 1332 0x45 0x00 0x01 0x4c -# CHECK: bc1t 00000534 +# CHECK: bc1t 1332 0x45 0x01 0x01 0x4c -# CHECK: beq t1,a2,00000534 +# CHECK: beq $9, $6, 1332 0x11 0x26 0x01 0x4c -# CHECK: bgez a2,00000534 +# CHECK: bgez $6, 1332 0x04 0xc1 0x01 0x4c -# CHECK: bgezal a2,00000534 +# CHECK: bgezal $6, 1332 0x04 0xd1 0x01 0x4c -# CHECK: bgtz a2,00000534 +# CHECK: bgtz $6, 1332 0x1c 0xc0 0x01 0x4c -# CHECK: blez a2,00000534 +# CHECK: blez $6, 1332 0x18 0xc0 0x01 0x4c -# CHECK: bne t1,a2,00000534 +# CHECK: bne $9, $6, 1332 0x15 0x26 0x01 0x4c -# CHECK: c.eq.d $f12,$f14 -0x46 0x27 0x30 0x32 +# CHECK: c.eq.d $f12, $f14 +0x46 0x2e 0x60 0x32 -# CHECK: c.eq.s $f6,$f7 +# CHECK: c.eq.s $f6, $f7 0x46 0x07 0x30 0x32 -# CHECK: c.f.d $f12,$f14 -0x46 0x27 0x30 0x30 +# CHECK: c.f.d $f12, $f14 +0x46 0x2e 0x60 0x30 -# CHECK: c.f.s $f6,$f7 +# CHECK: c.f.s $f6, $f7 0x46 0x07 0x30 0x30 -# CHECK: c.le.d $f12,$f14 -0x46 0x27 0x30 0x3e +# CHECK: c.le.d $f12, $f14 +0x46 0x2e 0x60 0x3e -# CHECK: c.le.s $f6,$f7 +# CHECK: c.le.s $f6, $f7 0x46 0x07 0x30 0x3e -# CHECK: c.lt.d $f12,$f14 -0x46 0x27 0x30 0x3c +# CHECK: c.lt.d $f12, $f14 +0x46 0x2e 0x60 0x3c -# CHECK: c.lt.s $f6,$f7 +# CHECK: c.lt.s $f6, $f7 0x46 0x07 0x30 0x3c -# CHECK: c.nge.d $f12,$f14 -0x46 0x27 0x30 0x3d +# CHECK: c.nge.d $f12, $f14 +0x46 0x2e 0x60 0x3d -# CHECK: c.nge.s $f6,$f7 +# CHECK: c.nge.s $f6, $f7 0x46 0x07 0x30 0x3d -# CHECK: c.ngl.d $f12,$f14 -0x46 0x27 0x30 0x3b +# CHECK: c.ngl.d $f12, $f14 +0x46 0x2e 0x60 0x3b -# CHECK: c.ngl.s $f6,$f7 +# CHECK: c.ngl.s $f6, $f7 0x46 0x07 0x30 0x3b -# CHECK: c.ngle.d $f12,$f14 -0x46 0x27 0x30 0x39 +# CHECK: c.ngle.d $f12, $f14 +0x46 0x2e 0x60 0x39 -# CHECK: c.ngle.s $f6,$f7 +# CHECK: c.ngle.s $f6, $f7 0x46 0x07 0x30 0x39 -# CHECK: c.ngt.d $f12,$f14 -0x46 0x27 0x30 0x3f +# CHECK: c.ngt.d $f12, $f14 +0x46 0x2e 0x60 0x3f -# CHECK: c.ngt.s $f6,$f7 +# CHECK: c.ngt.s $f6, $f7 0x46 0x07 0x30 0x3f -# CHECK: c.ole.d $f12,$f14 -0x46 0x27 0x30 0x36 +# CHECK: c.ole.d $f12, $f14 +0x46 0x2e 0x60 0x36 -# CHECK: c.ole.s $f6,$f7 +# CHECK: c.ole.s $f6, $f7 0x46 0x07 0x30 0x36 -# CHECK: c.olt.d $f12,$f14 -0x46 0x27 0x30 0x34 +# CHECK: c.olt.d $f12, $f14 +0x46 0x2e 0x60 0x34 -# CHECK: c.olt.s $f6,$f7 +# CHECK: c.olt.s $f6, $f7 0x46 0x07 0x30 0x34 -# CHECK: c.seq.d $f12,$f14 -0x46 0x27 0x30 0x3a +# CHECK: c.seq.d $f12, $f14 +0x46 0x2e 0x60 0x3a -# CHECK: c.seq.s $f6,$f7 +# CHECK: c.seq.s $f6, $f7 0x46 0x07 0x30 0x3a -# CHECK: c.sf.d $f12,$f14 -0x46 0x27 0x30 0x38 +# CHECK: c.sf.d $f12, $f14 +0x46 0x2e 0x60 0x38 -# CHECK: c.sf.s $f6,$f7 +# CHECK: c.sf.s $f6, $f7 0x46 0x07 0x30 0x38 -# CHECK: c.ueq.d $f12,$f14 -0x46 0x27 0x30 0x33 +# CHECK: c.ueq.d $f12, $f14 +0x46 0x2e 0x60 0x33 -# CHECK: c.ueq.s $f28,$f18 +# CHECK: c.ueq.s $f28, $f18 0x46 0x12 0xe0 0x33 -# CHECK: c.ule.d $f12,$f14 -0x46 0x27 0x30 0x37 +# CHECK: c.ule.d $f12, $f14 +0x46 0x2e 0x60 0x37 -# CHECK: c.ule.s $f6,$f7 +# CHECK: c.ule.s $f6, $f7 0x46 0x07 0x30 0x37 -# CHECK: c.ult.d $f12,$f14 -0x46 0x27 0x30 0x35 +# CHECK: c.ult.d $f12, $f14 +0x46 0x2e 0x60 0x35 -# CHECK: c.ult.s $f6,$f7 +# CHECK: c.ult.s $f6, $f7 0x46 0x07 0x30 0x35 -# CHECK: c.un.d $f12,$f14 -0x46 0x27 0x30 0x31 +# CHECK: c.un.d $f12, $f14 +0x46 0x2e 0x60 0x31 -# CHECK: c.un.s $f6,$f7 +# CHECK: c.un.s $f6, $f7 0x46 0x07 0x30 0x31 -# CHECK: ceil.w.d $f12,$f14 -0x46 0x20 0x39 0x8e +# CHECK: ceil.w.d $f12, $f14 +0x46 0x20 0x73 0x0e -# CHECK: ceil.w.s $f6,$f7 +# CHECK: ceil.w.s $f6, $f7 0x46 0x00 0x39 0x8e -# CHECK: cfc1 a2,$7 +# CHECK: cfc1 $6, $7 0x44 0x46 0x38 0x00 -# CHECK: clo a2,a3 +# CHECK: clo $6, $7 0x70 0xe6 0x30 0x21 -# CHECK: clz a2,a3 +# CHECK: clz $6, $7 0x70 0xe6 0x30 0x20 -# CHECK: ctc1 a2,$7 +# CHECK: ctc1 $6, $7 0x44 0xc6 0x38 0x00 -# CHECK: cvt.d.s $f6,$f7 -0x46 0x00 0x38 0xa1 - -# CHECK: cvt.d.w $f12,$f14 -0x46 0x80 0x38 0xa1 - -# CHECK: cvt.l.d $f12,$f14 -0x46 0x20 0x39 0xa5 +# CHECK: cvt.d.s $f6, $f7 +0x46 0x00 0x39 0xa1 -# CHECK: cvt.l.s $f6,$f7 -0x46 0x00 0x39 0xa5 +# CHECK: cvt.d.w $f12, $f14 +0x46 0x80 0x73 0x21 -# CHECK: cvt.s.d $f12,$f14 -0x46 0x20 0x39 0xa0 +# CHECK: cvt.s.d $f12, $f14 +0x46 0x20 0x73 0x20 -# CHECK: cvt.s.w $f6,$f7 +# CHECK: cvt.s.w $f6, $f7 0x46 0x80 0x39 0xa0 -# CHECK: cvt.w.d $f12,$f14 -0x46 0x20 0x39 0xa4 +# CHECK: cvt.w.d $f12, $f14 +0x46 0x20 0x73 0x24 -# CHECK: cvt.w.s $f6,$f7 +# CHECK: cvt.w.s $f6, $f7 0x46 0x00 0x39 0xa4 -# CHECK: floor.w.d $f12,$f14 -0x46 0x20 0x39 0x8f +# CHECK: floor.w.d $f12, $f14 +0x46 0x20 0x73 0x0f -# CHECK: floor.w.s $f6,$f7 +# CHECK: floor.w.s $f6, $f7 0x46 0x00 0x39 0x8f -# CHECK: j 00000530 +# CHECK: j 1328 0x08 0x00 0x01 0x4c -# CHECK: jal 00000530 +# CHECK: jal 1328 0x0c 0x00 0x01 0x4c -# CHECK: jalr a2,a3 +# CHECK: jalr $7 0x00 0xe0 0xf8 0x09 -# CHECK: jr a3 +# CHECK: jr $7 0x00 0xe0 0x00 0x08 -# CHECK: lb a0,9158(a1) +# CHECK: lb $4, 9158($5) 0x80 0xa4 0x23 0xc6 -# CHECK: lbu a0,6(a1) +# CHECK: lbu $4, 6($5) 0x90 0xa4 0x00 0x06 -# CHECK: ldc1 $f9,9158(a3) +# CHECK: ldc1 $f9, 9158($7) 0xd4 0xe9 0x23 0xc6 -# CHECK: lh a0,12(a1) +# CHECK: lh $4, 12($5) 0x84 0xa4 0x00 0x0c -# CHECK: lh a0,12(a1) +# CHECK: lh $4, 12($5) 0x84 0xa4 0x00 0x0c -# CHECK: li v1,17767 -0x24 0x03 0x45 0x67 - -# CHECK: ll t1,9158(a3) +# CHECK: ll $9, 9158($7) 0xc0 0xe9 0x23 0xc6 -# CHECK: lui a2,0x4567 +# CHECK: lui $6, 17767 0x3c 0x06 0x45 0x67 -# CHECK: lw a0,24(a1) +# CHECK: lw $4, 24($5) 0x8c 0xa4 0x00 0x18 -# CHECK: lwc1 $f9,9158(a3) +# CHECK: lwc1 $f9, 9158($7) 0xc4 0xe9 0x23 0xc6 -# CHECK: madd a2,a3 +# CHECK: lwl $2, 3($4) +0x88 0x82 0x00 0x03 + +# CHECK: lwr $3, 16($5) +0x98 0xa3 0x00 0x10 + +# CHECK: madd $6, $7 0x70 0xc7 0x00 0x00 -# CHECK: maddu a2,a3 +# CHECK: maddu $6, $7 0x70 0xc7 0x00 0x01 -# CHECK: mfc1 a2,$f7 +# CHECK: mfc1 $6, $f7 0x44 0x06 0x38 0x00 -# CHECK: mfhi a1 +# CHECK: mfhi $5 0x00 0x00 0x28 0x10 -# CHECK: mflo a1 +# CHECK: mflo $5 0x00 0x00 0x28 0x12 -# CHECK: mov.d $f6,$f7 -0x46 0x20 0x39 0x86 +# CHECK: mov.d $f6, $f8 +0x46 0x20 0x41 0x86 -# CHECK: mov.s $f6,$f7 +# CHECK: mov.s $f6, $f7 0x46 0x00 0x39 0x86 -# CHECK: move a2,a1 -0x00 0xa0 0x30 0x21 - -# CHECK: msub a2,a3 +# CHECK: msub $6, $7 0x70 0xc7 0x00 0x04 -# CHECK: msubu a2,a3 +# CHECK: msubu $6, $7 0x70 0xc7 0x00 0x05 -# CHECK: mtc1 a2,$f7 +# CHECK: mtc1 $6, $f7 0x44 0x86 0x38 0x00 -# CHECK: mthi a3 +# CHECK: mthi $7 0x00 0xe0 0x00 0x11 -# CHECK: mtlo a3 +# CHECK: mtlo $7 0x00 0xe0 0x00 0x13 -# CHECK: mul.d $f9,$f12,$f14 -0x46 0x27 0x32 0x42 +# CHECK: mul.d $f8, $f12, $f14 +0x46 0x2e 0x62 0x02 -# CHECK: mul.s $f9,$f6,$f7 +# CHECK: mul.s $f9, $f6, $f7 0x46 0x07 0x32 0x42 -# CHECK: mul t1,a2,a3 +# CHECK: mul $9, $6, $7 0x70 0xc7 0x48 0x02 -# CHECK: mult v1,a1 +# CHECK: mult $3, $5 0x00 0x65 0x00 0x18 -# CHECK: multu v1,a1 +# CHECK: multu $3, $5 0x00 0x65 0x00 0x19 -# CHECK: neg.d $f12,$f14 -0x46 0x20 0x39 0x87 +# CHECK: neg.d $f12, $f14 +0x46 0x20 0x73 0x07 -# CHECK: neg.s $f6,$f7 +# CHECK: neg.s $f6, $f7 0x46 0x00 0x39 0x87 -# CHECK: neg v1,a1 -0x00 0x05 0x18 0x22 - # CHECK: nop 0x00 0x00 0x00 0x00 -# CHECK: nor t1,a2,a3 +# CHECK: nor $9, $6, $7 0x00 0xc7 0x48 0x27 -# CHECK: not v1,a1 -0x00 0xa0 0x18 0x27 - -# CHECK: or v1,v1,a1 +# CHECK: or $3, $3, $5 0x00 0x65 0x18 0x25 -# CHECK: ori t1,a2,0x4567 +# CHECK: ori $9, $6, 17767 0x34 0xc9 0x45 0x67 -# CHECK: rdhwr a2,$29 -0x7c 0x06 0xe8 0x3b +# CHECK: round.w.d $f12, $f14 +0x46 0x20 0x73 0x0c -# CHECK: round.w.d $f12,$f14 -0x46 0x20 0x39 0x8c - -# CHECK: round.w.s $f6,$f7 +# CHECK: round.w.s $f6, $f7 0x46 0x00 0x39 0x8c -# CHECK: sb a0,9158(a1) +# CHECK: sb $4, 9158($5) 0xa0 0xa4 0x23 0xc6 -# CHECK: sb a0,6(a1) +# CHECK: sb $4, 6($5) 0xa0 0xa4 0x00 0x06 -# CHECK: sc t1,9158(a3) +# CHECK: sc $9, 9158($7) 0xe0 0xe9 0x23 0xc6 -# CHECK: sdc1 $f9,9158(a3) +# CHECK: sdc1 $f9, 9158($7) 0xf4 0xe9 0x23 0xc6 -# CHECK: sh a0,9158(a1) +# CHECK: sh $4, 9158($5) 0xa4 0xa4 0x23 0xc6 -# CHECK: sll a0,v1,0x7 +# CHECK: sll $4, $3, 7 0x00 0x03 0x21 0xc0 -# CHECK: sllv v0,v1,a1 +# CHECK: sllv $2, $3, $5 0x00 0xa3 0x10 0x04 -# CHECK: slt v1,v1,a1 +# CHECK: slt $3, $3, $5 0x00 0x65 0x18 0x2a -# CHECK: slti v1,v1,103 +# CHECK: slti $3, $3, 103 0x28 0x63 0x00 0x67 -# CHECK: sltiu v1,v1,103 +# CHECK: sltiu $3, $3, 103 0x2c 0x63 0x00 0x67 -# CHECK: sltu v1,v1,a1 +# CHECK: sltu $3, $3, $5 0x00 0x65 0x18 0x2b -# CHECK: sqrt.d $f12,$f14 -0x46 0x20 0x39 0x84 +# CHECK: sqrt.d $f12, $f14 +0x46 0x20 0x73 0x04 -# CHECK: sqrt.s $f6,$f7 +# CHECK: sqrt.s $f6, $f7 0x46 0x00 0x39 0x84 -# CHECK: sra a0,v1,0x7 +# CHECK: sra $4, $3, 7 0x00 0x03 0x21 0xc3 -# CHECK: sra a0,v1,0x7 -0x00 0x03 0x21 0xc3 - -# CHECK: srav v0,v1,a1 +# CHECK: srav $2, $3, $5 0x00 0xa3 0x10 0x07 -# CHECK: srl a0,v1,0x7 +# CHECK: srl $4, $3, 7 0x00 0x03 0x21 0xc2 -# CHECK: srlv v0,v1,a1 +# CHECK: srlv $2, $3, $5 0x00 0xa3 0x10 0x06 -# CHECK: sub.d $f9,$f12,$f14 -0x46 0x27 0x32 0x41 +# CHECK: sub.d $f8, $f12, $f14 +0x46 0x2e 0x62 0x01 -# CHECK: sub.s $f9,$f6,$f7 +# CHECK: sub.s $f9, $f6, $f7 0x46 0x07 0x32 0x41 -# CHECK: sub t1,a2,a3 +# CHECK: sub $9, $6, $7 0x00 0xc7 0x48 0x22 -# CHECK: subu a0,v1,a1 +# CHECK: subu $4, $3, $5 0x00 0x65 0x20 0x23 -# CHECK: sw a0,24(a1) +# CHECK: sw $4, 24($5) 0xac 0xa4 0x00 0x18 -# CHECK: swc1 $f9,9158(a3) +# CHECK: swc1 $f9, 9158($7) 0xe4 0xe9 0x23 0xc6 -# CHECK: sync 0x7 +# CHECK: swl $4, 16($5) +0xa8 0xa4 0x00 0x10 + +# CHECK: swr $6, 16($7) +0xb8 0xe6 0x00 0x10 + +# CHECK: sync 7 0x00 0x00 0x01 0xcf -# CHECK: trunc.w.d $f12,$f14 -0x46 0x20 0x39 0x8d +# CHECK: trunc.w.d $f12, $f14 +0x46 0x20 0x73 0x0d -# CHECK: trunc.w.s $f6,$f7 +# CHECK: trunc.w.s $f6, $f7 0x46 0x00 0x39 0x8d -# CHECK: xor v1,v1,a1 +# CHECK: xor $3, $3, $5 0x00 0x65 0x18 0x26 -# CHECK: xori t1,a2,0x4567 +# CHECK: xori $9, $6, 17767 0x38 0xc9 0x45 0x67 diff --git a/test/MC/Disassembler/Mips/mips32_le.txt b/test/MC/Disassembler/Mips/mips32_le.txt index a5a3cfd..08b3672 100644 --- a/test/MC/Disassembler/Mips/mips32_le.txt +++ b/test/MC/Disassembler/Mips/mips32_le.txt @@ -1,424 +1,406 @@ -# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux +# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux | FileCheck %s +# CHECK: .section __TEXT,__text,regular,pure_instructions +# CHECK: abs.d $f12, $f14 +0x05 0x73 0x20 0x46 -# CHECK: abs.d $f12,$f14 -0x85 0x39 0x20 0x46 - -# CHECK: abs.s $f6,$f7 +# CHECK: abs.s $f6, $f7 0x85 0x39 0x00 0x46 -# CHECK: add t1,a2,a3 +# CHECK: add $9, $6, $7 0x20 0x48 0xc7 0x00 -# CHECK: add.d $f18,$f12,$f14 -0x40 0x32 0x27 0x46 +# CHECK: add.d $f8, $f12, $f14 +0x00 0x62 0x2e 0x46 -# CHECK: add.s $f9,$f6,$f7 +# CHECK: add.s $f9, $f6, $f7 0x40 0x32 0x07 0x46 -# CHECK: addi t1,a2,17767 +# CHECK: addi $9, $6, 17767 0x67 0x45 0xc9 0x20 -# CHECK: addiu t1,a2,-15001 +# CHECK: addiu $9, $6, -15001 0x67 0xc5 0xc9 0x24 -# CHECK: addu t1,a2,a3 +# CHECK: addu $9, $6, $7 0x21 0x48 0xc7 0x00 -# CHECK: and t1,a2,a3 +# CHECK: and $9, $6, $7 0x24 0x48 0xc7 0x00 -# CHECK: andi t1,a2,0x4567 +# CHECK: andi $9, $6, 17767 0x67 0x45 0xc9 0x30 -# CHECK: b 00000534 +# CHECK: b 1332 0x4c 0x01 0x00 0x10 -# CHECK: bal 00000534 -0x4c 0x01 0x11 0x04 - -# CHECK: bc1f 00000534 +# CHECK: bc1f 1332 0x4c 0x01 0x00 0x45 -# CHECK: bc1t 00000534 +# CHECK: bc1t 1332 0x4c 0x01 0x01 0x45 -# CHECK: beq t1,a2,00000534 +# CHECK: beq $9, $6, 1332 0x4c 0x01 0x26 0x11 -# CHECK: bgez a2,00000534 +# CHECK: bgez $6, 1332 0x4c 0x01 0xc1 0x04 -# CHECK: bgezal a2,00000534 +# CHECK: bgezal $6, 1332 0x4c 0x01 0xd1 0x04 -# CHECK: bgtz a2,00000534 +# CHECK: bgtz $6, 1332 0x4c 0x01 0xc0 0x1c -# CHECK: blez a2,00000534 +# CHECK: blez $6, 1332 0x4c 0x01 0xc0 0x18 -# CHECK: bne t1,a2,00000534 +# CHECK: bne $9, $6, 1332 0x4c 0x01 0x26 0x15 -# CHECK: c.eq.d $f12,$f14 -0x32 0x30 0x27 0x46 +# CHECK: c.eq.d $f12, $f14 +0x32 0x60 0x2e 0x46 -# CHECK: c.eq.s $f6,$f7 +# CHECK: c.eq.s $f6, $f7 0x32 0x30 0x07 0x46 -# CHECK: c.f.d $f12,$f14 -0x30 0x30 0x27 0x46 +# CHECK: c.f.d $f12, $f14 +0x30 0x60 0x2e 0x46 -# CHECK: c.f.s $f6,$f7 +# CHECK: c.f.s $f6, $f7 0x30 0x30 0x07 0x46 -# CHECK: c.le.d $f12,$f14 -0x3e 0x30 0x27 0x46 +# CHECK: c.le.d $f12, $f14 +0x3e 0x60 0x2e 0x46 -# CHECK: c.le.s $f6,$f7 +# CHECK: c.le.s $f6, $f7 0x3e 0x30 0x07 0x46 -# CHECK: c.lt.d $f12,$f14 -0x3c 0x30 0x27 0x46 +# CHECK: c.lt.d $f12, $f14 +0x3c 0x60 0x2e 0x46 -# CHECK: c.lt.s $f6,$f7 +# CHECK: c.lt.s $f6, $f7 0x3c 0x30 0x07 0x46 -# CHECK: c.nge.d $f12,$f14 -0x3d 0x30 0x27 0x46 +# CHECK: c.nge.d $f12, $f14 +0x3d 0x60 0x2e 0x46 -# CHECK: c.nge.s $f6,$f7 +# CHECK: c.nge.s $f6, $f7 0x3d 0x30 0x07 0x46 -# CHECK: c.ngl.d $f12,$f14 -0x3b 0x30 0x27 0x46 +# CHECK: c.ngl.d $f12, $f14 +0x3b 0x60 0x2e 0x46 -# CHECK: c.ngl.s $f6,$f7 +# CHECK: c.ngl.s $f6, $f7 0x3b 0x30 0x07 0x46 -# CHECK: c.ngle.d $f12,$f14 -0x39 0x30 0x27 0x46 +# CHECK: c.ngle.d $f12, $f14 +0x39 0x60 0x2e 0x46 -# CHECK: c.ngle.s $f6,$f7 +# CHECK: c.ngle.s $f6, $f7 0x39 0x30 0x07 0x46 -# CHECK: c.ngt.d $f12,$f14 -0x3f 0x30 0x27 0x46 +# CHECK: c.ngt.d $f12, $f14 +0x3f 0x60 0x2e 0x46 -# CHECK: c.ngt.s $f6,$f7 +# CHECK: c.ngt.s $f6, $f7 0x3f 0x30 0x07 0x46 -# CHECK: c.ole.d $f12,$f14 -0x36 0x30 0x27 0x46 +# CHECK: c.ole.d $f12, $f14 +0x36 0x60 0x2e 0x46 -# CHECK: c.ole.s $f6,$f7 +# CHECK: c.ole.s $f6, $f7 0x36 0x30 0x07 0x46 -# CHECK: c.olt.d $f12,$f14 -0x34 0x30 0x27 0x46 +# CHECK: c.olt.d $f12, $f14 +0x34 0x60 0x2e 0x46 -# CHECK: c.olt.s $f6,$f7 +# CHECK: c.olt.s $f6, $f7 0x34 0x30 0x07 0x46 -# CHECK: c.seq.d $f12,$f14 -0x3a 0x30 0x27 0x46 +# CHECK: c.seq.d $f12, $f14 +0x3a 0x60 0x2e 0x46 -# CHECK: c.seq.s $f6,$f7 +# CHECK: c.seq.s $f6, $f7 0x3a 0x30 0x07 0x46 -# CHECK: c.sf.d $f12,$f14 -0x38 0x30 0x27 0x46 +# CHECK: c.sf.d $f12, $f14 +0x38 0x60 0x2e 0x46 -# CHECK: c.sf.s $f6,$f7 +# CHECK: c.sf.s $f6, $f7 0x38 0x30 0x07 0x46 -# CHECK: c.ueq.d $f12,$f14 -0x33 0x30 0x27 0x46 +# CHECK: c.ueq.d $f12, $f14 +0x33 0x60 0x2e 0x46 -# CHECK: c.ueq.s $f28,$f18 +# CHECK: c.ueq.s $f28, $f18 0x33 0xe0 0x12 0x46 -# CHECK: c.ule.d $f12,$f14 -0x37 0x30 0x27 0x46 +# CHECK: c.ule.d $f12, $f14 +0x37 0x60 0x2e 0x46 -# CHECK: c.ule.s $f6,$f7 +# CHECK: c.ule.s $f6, $f7 0x37 0x30 0x07 0x46 -# CHECK: c.ult.d $f12,$f14 -0x35 0x30 0x27 0x46 +# CHECK: c.ult.d $f12, $f14 +0x35 0x60 0x2e 0x46 -# CHECK: c.ult.s $f6,$f7 +# CHECK: c.ult.s $f6, $f7 0x35 0x30 0x07 0x46 -# CHECK: c.un.d $f12,$f14 -0x31 0x30 0x27 0x46 +# CHECK: c.un.d $f12, $f14 +0x31 0x60 0x2e 0x46 -# CHECK: c.un.s $f6,$f7 +# CHECK: c.un.s $f6, $f7 0x31 0x30 0x07 0x46 -# CHECK: ceil.w.d $f12,$f14 -0x8e 0x38 0x20 0x46 +# CHECK: ceil.w.d $f12, $f14 +0x0e 0x73 0x20 0x46 -# CHECK: ceil.w.s $f6,$f7 -0x8e 0x38 0x00 0x46 +# CHECK: ceil.w.s $f6, $f7 +0x8e 0x39 0x00 0x46 -# CHECK: cfc1 a2,$7 +# CHECK: cfc1 $6, $7 0x00 0x38 0x46 0x44 -# CHECK: clo a2,a3 +# CHECK: clo $6, $7 0x21 0x30 0xe6 0x70 -# CHECK: clz a2,a3 +# CHECK: clz $6, $7 0x20 0x30 0xe6 0x70 -# CHECK: ctc1 a2,$7 +# CHECK: ctc1 $6, $7 0x00 0x38 0xc6 0x44 -# CHECK: cvt.d.s $f6,$f7 +# CHECK: cvt.d.s $f6, $f7 0xa1 0x39 0x00 0x46 -# CHECK: cvt.d.w $f12,$f14 -0xa1 0x39 0x80 0x46 - -# CHECK: cvt.l.d $f12,$f14 -0xa5 0x39 0x20 0x46 - -# CHECK: cvt.l.s $f6,$f7 -0xa5 0x39 0x00 0x46 +# CHECK: cvt.d.w $f12, $f14 +0x21 0x73 0x80 0x46 -# CHECK: cvt.s.d $f12,$f14 -0xa0 0x39 0x20 0x46 +# CHECK: cvt.s.d $f12, $f14 +0x20 0x73 0x20 0x46 -# CHECK: cvt.s.w $f6,$f7 +# CHECK: cvt.s.w $f6, $f7 0xa0 0x39 0x80 0x46 -# CHECK: cvt.w.d $f12,$f14 -0xa4 0x39 0x20 0x46 +# CHECK: cvt.w.d $f12, $f14 +0x24 0x73 0x20 0x46 -# CHECK: cvt.w.s $f6,$f7 +# CHECK: cvt.w.s $f6, $f7 0xa4 0x39 0x00 0x46 -# CHECK: floor.w.d $f12,$f14 -0x8f 0x39 0x20 0x46 +# CHECK: floor.w.d $f12, $f14 +0x0f 0x73 0x20 0x46 -# CHECK: floor.w.s $f6,$f7 +# CHECK: floor.w.s $f6, $f7 0x8f 0x39 0x00 0x46 -# CHECK: j 00000530 +# CHECK: j 1328 0x4c 0x01 0x00 0x08 -# CHECK: jal 00000530 +# CHECK: jal 1328 0x4c 0x01 0x00 0x0c -# CHECK: jalr a2,a3 +# CHECK: jalr $7 0x09 0xf8 0xe0 0x00 -# CHECK: jr a3 +# CHECK: jr $7 0x08 0x00 0xe0 0x00 -# CHECK: lb a0,9158(a1) +# CHECK: lb $4, 9158($5) 0xc6 0x23 0xa4 0x80 -# CHECK: lbu a0,6(a1) +# CHECK: lbu $4, 6($5) 0x06 0x00 0xa4 0x90 -# CHECK: ldc1 $f9,9158(a3) +# CHECK: ldc1 $f9, 9158($7) 0xc6 0x23 0xe9 0xd4 -# CHECK: lh a0,12(a1) +# CHECK: lh $4, 12($5) 0x0c 0x00 0xa4 0x84 -# CHECK: lh a0,12(a1) +# CHECK: lh $4, 12($5) 0x0c 0x00 0xa4 0x84 -# CHECK: li v1,17767 -0x67 0x45 0x03 0x24 - -# CHECK: ll t1,9158(a3) +# CHECK: ll $9, 9158($7) 0xc6 0x23 0xe9 0xc0 -# CHECK: lui a2,0x4567 +# CHECK: lui $6, 17767 0x67 0x45 0x06 0x3c -# CHECK: lw a0,24(a1) +# CHECK: lw $4, 24($5) 0x18 0x00 0xa4 0x8c -# CHECK lw at,-18316(v0) -0x74 0xb8 0x41 0x8c - -# CHECK: lwc1 $f9,9158(a3) +# CHECK: lwc1 $f9, 9158($7) 0xc6 0x23 0xe9 0xc4 -# CHECK: madd a2,a3 +# CHECK: lwl $2, 3($4) +0x03 0x00 0x82 0x88 + +# CHECK: lwr $3, 16($5) +0x10 0x00 0xa3 0x98 + +# CHECK: madd $6, $7 0x00 0x00 0xc7 0x70 -# CHECK: maddu a2,a3 +# CHECK: maddu $6, $7 0x01 0x00 0xc7 0x70 -# CHECK: mfc1 a2,$f7 +# CHECK: mfc1 $6, $f7 0x00 0x38 0x06 0x44 -# CHECK: mfhi a1 +# CHECK: mfhi $5 0x10 0x28 0x00 0x00 -# CHECK: mflo a1 +# CHECK: mflo $5 0x12 0x28 0x00 0x00 -# CHECK: mov.d $f12,$f14 -0x86 0x39 0x20 0x46 +# CHECK: mov.d $f6, $f8 +0x86 0x41 0x20 0x46 -# CHECK: mov.s $f6,$f7 +# CHECK: mov.s $f6, $f7 0x86 0x39 0x00 0x46 -# CHECK: move a2,a1 -0x21 0x30 0xa0 0x00 - -# CHECK: msub a2,a3 +# CHECK: msub $6, $7 0x04 0x00 0xc7 0x70 -# CHECK: msubu a2,a3 +# CHECK: msubu $6, $7 0x05 0x00 0xc7 0x70 -# CHECK: mtc1 a2,$f7 +# CHECK: mtc1 $6, $f7 0x00 0x38 0x86 0x44 -# CHECK: mthi a3 +# CHECK: mthi $7 0x11 0x00 0xe0 0x00 -# CHECK: mtlo a3 +# CHECK: mtlo $7 0x13 0x00 0xe0 0x00 -# CHECK: mul.d $f9,$f12,$f14 -0x42 0x32 0x27 0x46 +# CHECK: mul.d $f8, $f12, $f14 +0x02 0x62 0x2e 0x46 -# CHECK: mul.s $f9,$f6,$f7 +# CHECK: mul.s $f9, $f6, $f7 0x42 0x32 0x07 0x46 -# CHECK: mul t1,a2,a3 +# CHECK: mul $9, $6, $7 0x02 0x48 0xc7 0x70 -# CHECK: mult v1,a1 +# CHECK: mult $3, $5 0x18 0x00 0x65 0x00 -# CHECK: multu v1,a1 +# CHECK: multu $3, $5 0x19 0x00 0x65 0x00 -# CHECK: neg.d $f12,$f14 -0x87 0x39 0x20 0x46 +# CHECK: neg.d $f12, $f14 +0x07 0x73 0x20 0x46 -# CHECK: neg.s $f6,$f7 +# CHECK: neg.s $f6, $f7 0x87 0x39 0x00 0x46 -# CHECK: neg v1,a1 -0x22 0x18 0x05 0x00 - # CHECK: nop 0x00 0x00 0x00 0x00 -# CHECK: nor t1,a2,a3 +# CHECK: nor $9, $6, $7 0x27 0x48 0xc7 0x00 -# CHECK: not v1,a1 -0x27 0x18 0xa0 0x00 - -# CHECK: or v1,v1,a1 +# CHECK: or $3, $3, $5 0x25 0x18 0x65 0x00 -# CHECK: ori t1,a2,0x4567 +# CHECK: ori $9, $6, 17767 0x67 0x45 0xc9 0x34 -# CHECK: rdhwr a2,$29 -0x3b 0xe8 0x06 0x7c - -# CHECK: round.w.d $f12,$f14 -0x8c 0x39 0x20 0x46 +# CHECK: round.w.d $f12, $f14 +0x0c 0x73 0x20 0x46 -# CHECK: round.w.s $f6,$f7 +# CHECK: round.w.s $f6, $f7 0x8c 0x39 0x00 0x46 -# CHECK: sb a0,9158(a1) +# CHECK: sb $4, 9158($5) 0xc6 0x23 0xa4 0xa0 -# CHECK: sb a0,6(a1) +# CHECK: sb $4, 6($5) 0x06 0x00 0xa4 0xa0 -# CHECK: sc t1,9158(a3) +# CHECK: sc $9, 9158($7) 0xc6 0x23 0xe9 0xe0 -# CHECK: sdc1 $f9,9158(a3) +# CHECK: sdc1 $f9, 9158($7) 0xc6 0x23 0xe9 0xf4 -# CHECK: sh a0,9158(a1) +# CHECK: sh $4, 9158($5) 0xc6 0x23 0xa4 0xa4 -# CHECK: sll a0,v1,0x7 +# CHECK: sll $4, $3, 7 0xc0 0x21 0x03 0x00 -# CHECK: sllv v0,v1,a1 +# CHECK: sllv $2, $3, $5 0x04 0x10 0xa3 0x00 -# CHECK: slt v1,v1,a1 +# CHECK: slt $3, $3, $5 0x2a 0x18 0x65 0x00 -# CHECK: slti v1,v1,103 +# CHECK: slti $3, $3, 103 0x67 0x00 0x63 0x28 -# CHECK: sltiu v1,v1,103 +# CHECK: sltiu $3, $3, 103 0x67 0x00 0x63 0x2c -# CHECK: sltu v1,v1,a1 +# CHECK: sltu $3, $3, $5 0x2b 0x18 0x65 0x00 -# CHECK: sqrt.d $f12,$f14 -0x84 0x39 0x20 0x46 +# CHECK: sqrt.d $f12, $f14 +0x04 0x73 0x20 0x46 -# CHECK: sqrt.s $f6,$f7 +# CHECK: sqrt.s $f6, $f7 0x84 0x39 0x00 0x46 -# CHECK: sra a0,v1,0x7 +# CHECK: sra $4, $3, 7 0xc3 0x21 0x03 0x00 -# CHECK: sra a0,v1,0x7 -0xc3 0x21 0x03 0x00 - -# CHECK: srav v0,v1,a1 +# CHECK: srav $2, $3, $5 0x07 0x10 0xa3 0x00 -# CHECK: srl a0,v1,0x7 +# CHECK: srl $4, $3, 7 0xc2 0x21 0x03 0x00 -# CHECK: srlv v0,v1,a1 +# CHECK: srlv $2, $3, $5 0x06 0x10 0xa3 0x00 -# CHECK: sub.d $f9,$f12,$f14 -0x41 0x32 0x27 0x46 +# CHECK: sub.d $f8, $f12, $f14 +0x01 0x62 0x2e 0x46 -# CHECK: sub.s $f9,$f6,$f7 +# CHECK: sub.s $f9, $f6, $f7 0x41 0x32 0x07 0x46 -# CHECK: sub t1,a2,a3 +# CHECK: sub $9, $6, $7 0x22 0x48 0xc7 0x00 -# CHECK: subu a0,v1,a1 +# CHECK: subu $4, $3, $5 0x23 0x20 0x65 0x00 -# CHECK: sw a0,24(a1) +# CHECK: sw $4, 24($5) 0x18 0x00 0xa4 0xac -# CHECK: swc1 $f9,9158(a3) +# CHECK: swc1 $f9, 9158($7) 0xc6 0x23 0xe9 0xe4 -# CHECK: sync 0x7 +# CHECK: swl $4, 16($5) +0x10 0x00 0xa4 0xa8 + +# CHECK: swr $6, 16($7) +0x10 0x00 0xe6 0xb8 + +# CHECK: sync 7 0xcf 0x01 0x00 0x00 -# CHECK: trunc.w.d $f12,$f14 -0x8d 0x39 0x20 0x46 +# CHECK: trunc.w.d $f12, $f14 +0x0d 0x73 0x20 0x46 -# CHECK: trunc.w.s $f6,$f7 +# CHECK: trunc.w.s $f6, $f7 0x8d 0x39 0x00 0x46 -# CHECK: xor v1,v1,a1 +# CHECK: xor $3, $3, $5 0x26 0x18 0x65 0x00 -# CHECK: xori t1,a2,0x4567 +# CHECK: xori $9, $6, 17767 0x67 0x45 0xc9 0x38 diff --git a/test/MC/Disassembler/Mips/mips32r2.txt b/test/MC/Disassembler/Mips/mips32r2.txt index 295ffd0..3b70db3 100644 --- a/test/MC/Disassembler/Mips/mips32r2.txt +++ b/test/MC/Disassembler/Mips/mips32r2.txt @@ -1,439 +1,430 @@ -# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 | FileCheck %s +# CHECK: .section __TEXT,__text,regular,pure_instructions +# CHECK: abs.d $f12, $f14 +0x46 0x20 0x73 0x05 -# CHECK: abs.d $f12,$f14 -0x46 0x20 0x39 0x85 - -# CHECK: abs.s $f6,$f7 +# CHECK: abs.s $f6, $f7 0x46 0x00 0x39 0x85 -# CHECK: add t1,a2,a3 +# CHECK: add $9, $6, $7 0x00 0xc7 0x48 0x20 -# CHECK: add.d $f18,$f12,$f14 -0x46 0x27 0x32 0x40 +# CHECK: add.d $f8, $f12, $f14 +0x46 0x2e 0x62 0x00 -# CHECK: add.s $f9,$f6,$f7 +# CHECK: add.s $f9, $f6, $f7 0x46 0x07 0x32 0x40 -# CHECK: addi t1,a2,17767 +# CHECK: addi $9, $6, 17767 0x20 0xc9 0x45 0x67 -# CHECK: addiu t1,a2,-15001 +# CHECK: addiu $9, $6, -15001 0x24 0xc9 0xc5 0x67 -# CHECK: addu t1,a2,a3 +# CHECK: addu $9, $6, $7 0x00 0xc7 0x48 0x21 -# CHECK: and t1,a2,a3 +# CHECK: and $9, $6, $7 0x00 0xc7 0x48 0x24 -# CHECK: andi t1,a2,0x4567 +# CHECK: andi $9, $6, 17767 0x30 0xc9 0x45 0x67 -# CHECK: b 00000534 +# CHECK: b 1332 0x10 0x00 0x01 0x4c -# CHECK: bal 00000534 -0x04 0x11 0x01 0x4c - -# CHECK: bc1f 00000534 +# CHECK: bc1f 1332 0x45 0x00 0x01 0x4c -# CHECK: bc1t 00000534 +# CHECK: bc1t 1332 0x45 0x01 0x01 0x4c -# CHECK: beq t1,a2,00000534 +# CHECK: beq $9, $6, 1332 0x11 0x26 0x01 0x4c -# CHECK: bgez a2,00000534 +# CHECK: bgez $6, 1332 0x04 0xc1 0x01 0x4c -# CHECK: bgezal a2,00000534 +# CHECK: bgezal $6, 1332 0x04 0xd1 0x01 0x4c -# CHECK: bgtz a2,00000534 +# CHECK: bgtz $6, 1332 0x1c 0xc0 0x01 0x4c -# CHECK: blez a2,00000534 +# CHECK: blez $6, 1332 0x18 0xc0 0x01 0x4c -# CHECK: bne t1,a2,00000534 +# CHECK: bne $9, $6, 1332 0x15 0x26 0x01 0x4c -# CHECK: c.eq.d $f12,$f14 -0x46 0x27 0x30 0x32 +# CHECK: c.eq.d $f12, $f14 +0x46 0x2e 0x60 0x32 -# CHECK: c.eq.s $f6,$f7 +# CHECK: c.eq.s $f6, $f7 0x46 0x07 0x30 0x32 -# CHECK: c.f.d $f12,$f14 -0x46 0x27 0x30 0x30 +# CHECK: c.f.d $f12, $f14 +0x46 0x2e 0x60 0x30 -# CHECK: c.f.s $f6,$f7 +# CHECK: c.f.s $f6, $f7 0x46 0x07 0x30 0x30 -# CHECK: c.le.d $f12,$f14 -0x46 0x27 0x30 0x3e +# CHECK: c.le.d $f12, $f14 +0x46 0x2e 0x60 0x3e -# CHECK: c.le.s $f6,$f7 +# CHECK: c.le.s $f6, $f7 0x46 0x07 0x30 0x3e -# CHECK: c.lt.d $f12,$f14 -0x46 0x27 0x30 0x3c +# CHECK: c.lt.d $f12, $f14 +0x46 0x2e 0x60 0x3c -# CHECK: c.lt.s $f6,$f7 +# CHECK: c.lt.s $f6, $f7 0x46 0x07 0x30 0x3c -# CHECK: c.nge.d $f12,$f14 -0x46 0x27 0x30 0x3d +# CHECK: c.nge.d $f12, $f14 +0x46 0x2e 0x60 0x3d -# CHECK: c.nge.s $f6,$f7 +# CHECK: c.nge.s $f6, $f7 0x46 0x07 0x30 0x3d -# CHECK: c.ngl.d $f12,$f14 -0x46 0x27 0x30 0x3b +# CHECK: c.ngl.d $f12, $f14 +0x46 0x2e 0x60 0x3b -# CHECK: c.ngl.s $f6,$f7 +# CHECK: c.ngl.s $f6, $f7 0x46 0x07 0x30 0x3b -# CHECK: c.ngle.d $f12,$f14 -0x46 0x27 0x30 0x39 +# CHECK: c.ngle.d $f12, $f14 +0x46 0x2e 0x60 0x39 -# CHECK: c.ngle.s $f6,$f7 +# CHECK: c.ngle.s $f6, $f7 0x46 0x07 0x30 0x39 -# CHECK: c.ngt.d $f12,$f14 -0x46 0x27 0x30 0x3f +# CHECK: c.ngt.d $f12, $f14 +0x46 0x2e 0x60 0x3f -# CHECK: c.ngt.s $f6,$f7 +# CHECK: c.ngt.s $f6, $f7 0x46 0x07 0x30 0x3f -# CHECK: c.ole.d $f12,$f14 -0x46 0x27 0x30 0x36 +# CHECK: c.ole.d $f12, $f14 +0x46 0x2e 0x60 0x36 -# CHECK: c.ole.s $f6,$f7 +# CHECK: c.ole.s $f6, $f7 0x46 0x07 0x30 0x36 -# CHECK: c.olt.d $f12,$f14 -0x46 0x27 0x30 0x34 +# CHECK: c.olt.d $f12, $f14 +0x46 0x2e 0x60 0x34 -# CHECK: c.olt.s $f6,$f7 +# CHECK: c.olt.s $f6, $f7 0x46 0x07 0x30 0x34 -# CHECK: c.seq.d $f12,$f14 -0x46 0x27 0x30 0x3a +# CHECK: c.seq.d $f12, $f14 +0x46 0x2e 0x60 0x3a -# CHECK: c.seq.s $f6,$f7 +# CHECK: c.seq.s $f6, $f7 0x46 0x07 0x30 0x3a -# CHECK: c.sf.d $f12,$f14 -0x46 0x27 0x30 0x38 +# CHECK: c.sf.d $f12, $f14 +0x46 0x2e 0x60 0x38 -# CHECK: c.sf.s $f6,$f7 +# CHECK: c.sf.s $f6, $f7 0x46 0x07 0x30 0x38 -# CHECK: c.ueq.d $f12,$f14 -0x46 0x27 0x30 0x33 +# CHECK: c.ueq.d $f12, $f14 +0x46 0x2e 0x60 0x33 -# CHECK: c.ueq.s $f28,$f18 +# CHECK: c.ueq.s $f28, $f18 0x46 0x12 0xe0 0x33 -# CHECK: c.ule.d $f12,$f14 -0x46 0x27 0x30 0x37 +# CHECK: c.ule.d $f12, $f14 +0x46 0x2e 0x60 0x37 -# CHECK: c.ule.s $f6,$f7 +# CHECK: c.ule.s $f6, $f7 0x46 0x07 0x30 0x37 -# CHECK: c.ult.d $f12,$f14 -0x46 0x27 0x30 0x35 +# CHECK: c.ult.d $f12, $f14 +0x46 0x2e 0x60 0x35 -# CHECK: c.ult.s $f6,$f7 +# CHECK: c.ult.s $f6, $f7 0x46 0x07 0x30 0x35 -# CHECK: c.un.d $f12,$f14 -0x46 0x27 0x30 0x31 +# CHECK: c.un.d $f12, $f14 +0x46 0x2e 0x60 0x31 -# CHECK: c.un.s $f6,$f7 +# CHECK: c.un.s $f6, $f7 0x46 0x07 0x30 0x31 -# CHECK: ceil.w.d $f12,$f14 -0x46 0x20 0x39 0x8e +# CHECK: ceil.w.d $f12, $f14 +0x46 0x20 0x73 0x0e -# CHECK: ceil.w.s $f6,$f7 +# CHECK: ceil.w.s $f6, $f7 0x46 0x00 0x39 0x8e -# CHECK: cfc1 a2,$7 +# CHECK: cfc1 $6, $7 0x44 0x46 0x38 0x00 -# CHECK: clo a2,a3 +# CHECK: clo $6, $7 0x70 0xe6 0x30 0x21 -# CHECK: clz a2,a3 +# CHECK: clz $6, $7 0x70 0xe6 0x30 0x20 -# CHECK: ctc1 a2,$7 +# CHECK: ctc1 $6, $7 0x44 0xc6 0x38 0x00 -# CHECK: cvt.d.s $f6,$f7 -0x46 0x00 0x38 0xa1 +# CHECK: cvt.d.s $f6, $f7 +0x46 0x00 0x39 0xa1 -# CHECK: cvt.d.w $f12,$f14 -0x46 0x80 0x38 0xa1 +# CHECK: cvt.d.w $f12, $f14 +0x46 0x80 0x73 0x21 -# CHECK: cvt.l.d $f12,$f14 -0x46 0x20 0x39 0xa5 +# CHECK: cvt.l.d $f12, $f14 +0x46 0x20 0x73 0x25 -# CHECK: cvt.l.s $f6,$f7 +# CHECK: cvt.l.s $f6, $f7 0x46 0x00 0x39 0xa5 -# CHECK: cvt.s.d $f12,$f14 -0x46 0x20 0x39 0xa0 +# CHECK: cvt.s.d $f12, $f14 +0x46 0x20 0x73 0x20 -# CHECK: cvt.s.w $f6,$f7 +# CHECK: cvt.s.w $f6, $f7 0x46 0x80 0x39 0xa0 -# CHECK: cvt.w.d $f12,$f14 -0x46 0x20 0x39 0xa4 +# CHECK: cvt.w.d $f12, $f14 +0x46 0x20 0x73 0x24 -# CHECK: cvt.w.s $f6,$f7 +# CHECK: cvt.w.s $f6, $f7 0x46 0x00 0x39 0xa4 -# CHECK: floor.w.d $f12,$f14 -0x46 0x20 0x39 0x8f +# CHECK: floor.w.d $f12, $f14 +0x46 0x20 0x73 0x0f -# CHECK: floor.w.s $f6,$f7 +# CHECK: floor.w.s $f6, $f7 0x46 0x00 0x39 0x8f -# CHECK: ins s3,t1,0x6,0x7 +# CHECK: ins $19, $9, 6, 7 0x7d 0x33 0x61 0x84 -# CHECK: j 00000530 +# CHECK: j 1328 0x08 0x00 0x01 0x4c -# CHECK: jal 00000530 +# CHECK: jal 1328 0x0c 0x00 0x01 0x4c -# CHECK: jalr a2,a3 +# CHECK: jalr $7 0x00 0xe0 0xf8 0x09 -# CHECK: jr a3 +# CHECK: jr $7 0x00 0xe0 0x00 0x08 -# CHECK: lb a0,9158(a1) +# CHECK: lb $4, 9158($5) 0x80 0xa4 0x23 0xc6 -# CHECK: lbu a0,6(a1) +# CHECK: lbu $4, 6($5) 0x90 0xa4 0x00 0x06 -# CHECK: ldc1 $f9,9158(a3) +# CHECK: ldc1 $f9, 9158($7) 0xd4 0xe9 0x23 0xc6 -# CHECK: lh a0,12(a1) +# CHECK: lh $4, 12($5) 0x84 0xa4 0x00 0x0c -# CHECK: lh a0,12(a1) +# CHECK: lh $4, 12($5) 0x84 0xa4 0x00 0x0c -# CHECK: li v1,17767 -0x24 0x03 0x45 0x67 - -# CHECK: ll t1,9158(a3) +# CHECK: ll $9, 9158($7) 0xc0 0xe9 0x23 0xc6 -# CHECK: lui a2,0x4567 +# CHECK: lui $6, 17767 0x3c 0x06 0x45 0x67 -# CHECK: lw a0,24(a1) +# CHECK: lw $4, 24($5) 0x8c 0xa4 0x00 0x18 -# CHECK: lwc1 $f9,9158(a3) +# CHECK: lwc1 $f9, 9158($7) 0xc4 0xe9 0x23 0xc6 -# CHECK: madd a2,a3 +# CHECK: lwl $2, 3($4) +0x88 0x82 0x00 0x03 + +# CHECK: lwr $3, 16($5) +0x98 0xa3 0x00 0x10 + +# CHECK: madd $6, $7 0x70 0xc7 0x00 0x00 -# CHECK: maddu a2,a3 +# CHECK: maddu $6, $7 0x70 0xc7 0x00 0x01 -# CHECK: mfc1 a2,$f7 +# CHECK: mfc1 $6, $f7 0x44 0x06 0x38 0x00 -# CHECK: mfhi a1 +# CHECK: mfhi $5 0x00 0x00 0x28 0x10 -# CHECK: mflo a1 +# CHECK: mflo $5 0x00 0x00 0x28 0x12 -# CHECK: mov.d $f6,$f7 -0x46 0x20 0x39 0x86 +# CHECK: mov.d $f6, $f8 +0x46 0x20 0x41 0x86 -# CHECK: mov.s $f6,$f7 +# CHECK: mov.s $f6, $f7 0x46 0x00 0x39 0x86 -# CHECK: move a2,a1 -0x00 0xa0 0x30 0x21 - -# CHECK: msub a2,a3 +# CHECK: msub $6, $7 0x70 0xc7 0x00 0x04 -# CHECK: msubu a2,a3 +# CHECK: msubu $6, $7 0x70 0xc7 0x00 0x05 -# CHECK: mtc1 a2,$f7 +# CHECK: mtc1 $6, $f7 0x44 0x86 0x38 0x00 -# CHECK: mthi a3 +# CHECK: mthi $7 0x00 0xe0 0x00 0x11 -# CHECK: mtlo a3 +# CHECK: mtlo $7 0x00 0xe0 0x00 0x13 -# CHECK: mul.d $f9,$f12,$f14 -0x46 0x27 0x32 0x42 +# CHECK: mul.d $f8, $f12, $f14 +0x46 0x2e 0x62 0x02 -# CHECK: mul.s $f9,$f6,$f7 +# CHECK: mul.s $f9, $f6, $f7 0x46 0x07 0x32 0x42 -# CHECK: mul t1,a2,a3 +# CHECK: mul $9, $6, $7 0x70 0xc7 0x48 0x02 -# CHECK: mult v1,a1 +# CHECK: mult $3, $5 0x00 0x65 0x00 0x18 -# CHECK: multu v1,a1 +# CHECK: multu $3, $5 0x00 0x65 0x00 0x19 -# CHECK: neg.d $f12,$f14 -0x46 0x20 0x39 0x87 +# CHECK: neg.d $f12, $f14 +0x46 0x20 0x73 0x07 -# CHECK: neg.s $f6,$f7 +# CHECK: neg.s $f6, $f7 0x46 0x00 0x39 0x87 -# CHECK: neg v1,a1 -0x00 0x05 0x18 0x22 - # CHECK: nop 0x00 0x00 0x00 0x00 -# CHECK: nor t1,a2,a3 +# CHECK: nor $9, $6, $7 0x00 0xc7 0x48 0x27 -# CHECK: not v1,a1 -0x00 0xa0 0x18 0x27 - -# CHECK: or v1,v1,a1 +# CHECK: or $3, $3, $5 0x00 0x65 0x18 0x25 -# CHECK: ori t1,a2,0x4567 +# CHECK: ori $9, $6, 17767 0x34 0xc9 0x45 0x67 -# CHECK: rdhwr a2,$29 -0x7c 0x06 0xe8 0x3b - -# CHECK: ror t1,a2,0x7 +# CHECK: rotr $9, $6, 7 0x00 0x26 0x49 0xc2 -# CHECK: rorv t1,a2,a3 +# CHECK: rotrv $9, $6, $7 0x00 0xe6 0x48 0x46 -# CHECK: round.w.d $f12,$f14 -0x46 0x20 0x39 0x8c +# CHECK: round.w.d $f12, $f14 +0x46 0x20 0x73 0x0c -# CHECK: round.w.s $f6,$f7 +# CHECK: round.w.s $f6, $f7 0x46 0x00 0x39 0x8c -# CHECK: sb a0,9158(a1) +# CHECK: sb $4, 9158($5) 0xa0 0xa4 0x23 0xc6 -# CHECK: sb a0,6(a1) +# CHECK: sb $4, 6($5) 0xa0 0xa4 0x00 0x06 -# CHECK: sc t1,9158(a3) +# CHECK: sc $9, 9158($7) 0xe0 0xe9 0x23 0xc6 -# CHECK: sdc1 $f9,9158(a3) +# CHECK: sdc1 $f9, 9158($7) 0xf4 0xe9 0x23 0xc6 -# CHECK: seb a2,a3 +# CHECK: seb $6, $7 0x7c 0x07 0x34 0x20 -# CHECK: seh a2,a3 +# CHECK: seh $6, $7 0x7c 0x07 0x36 0x20 -# CHECK: sh a0,9158(a1) +# CHECK: sh $4, 9158($5) 0xa4 0xa4 0x23 0xc6 -# CHECK: sll a0,v1,0x7 +# CHECK: sll $4, $3, 7 0x00 0x03 0x21 0xc0 -# CHECK: sllv v0,v1,a1 +# CHECK: sllv $2, $3, $5 0x00 0xa3 0x10 0x04 -# CHECK: slt v1,v1,a1 +# CHECK: slt $3, $3, $5 0x00 0x65 0x18 0x2a -# CHECK: slti v1,v1,103 +# CHECK: slti $3, $3, 103 0x28 0x63 0x00 0x67 -# CHECK: sltiu v1,v1,103 +# CHECK: sltiu $3, $3, 103 0x2c 0x63 0x00 0x67 -# CHECK: sltu v1,v1,a1 +# CHECK: sltu $3, $3, $5 0x00 0x65 0x18 0x2b -# CHECK: sqrt.d $f12,$f14 -0x46 0x20 0x39 0x84 +# CHECK: sqrt.d $f12, $f14 +0x46 0x20 0x73 0x04 -# CHECK: sqrt.s $f6,$f7 +# CHECK: sqrt.s $f6, $f7 0x46 0x00 0x39 0x84 -# CHECK: sra a0,v1,0x7 -0x00 0x03 0x21 0xc3 - -# CHECK: sra a0,v1,0x7 +# CHECK: sra $4, $3, 7 0x00 0x03 0x21 0xc3 -# CHECK: srav v0,v1,a1 +# CHECK: srav $2, $3, $5 0x00 0xa3 0x10 0x07 -# CHECK: srl a0,v1,0x7 +# CHECK: srl $4, $3, 7 0x00 0x03 0x21 0xc2 -# CHECK: srlv v0,v1,a1 +# CHECK: srlv $2, $3, $5 0x00 0xa3 0x10 0x06 -# CHECK: sub.d $f9,$f12,$f14 -0x46 0x27 0x32 0x41 +# CHECK: sub.d $f8, $f12, $f14 +0x46 0x2e 0x62 0x01 -# CHECK: sub.s $f9,$f6,$f7 +# CHECK: sub.s $f9, $f6, $f7 0x46 0x07 0x32 0x41 -# CHECK: sub t1,a2,a3 +# CHECK: sub $9, $6, $7 0x00 0xc7 0x48 0x22 -# CHECK: subu a0,v1,a1 +# CHECK: subu $4, $3, $5 0x00 0x65 0x20 0x23 -# CHECK: sw a0,24(a1) +# CHECK: sw $4, 24($5) 0xac 0xa4 0x00 0x18 -# CHECK: swc1 $f9,9158(a3) +# CHECK: swc1 $f9, 9158($7) 0xe4 0xe9 0x23 0xc6 -# CHECK: sync 0x7 +# CHECK: swl $4, 16($5) +0xa8 0xa4 0x00 0x10 + +# CHECK: swr $6, 16($7) +0xb8 0xe6 0x00 0x10 + +# CHECK: sync 7 0x00 0x00 0x01 0xcf -# CHECK: trunc.w.d $f12,$f14 -0x46 0x20 0x39 0x8d +# CHECK: trunc.w.d $f12, $f14 +0x46 0x20 0x73 0x0d -# CHECK: trunc.w.s $f6,$f7 +# CHECK: trunc.w.s $f6, $f7 0x46 0x00 0x39 0x8d -# CHECK: wsbh a2,a3 +# CHECK: wsbh $6, $7 0x7c 0x07 0x30 0xa0 -# CHECK: xor v1,v1,a1 +# CHECK: xor $3, $3, $5 0x00 0x65 0x18 0x26 -# CHECK: xori t1,a2,0x4567 +# CHECK: xori $9, $6, 17767 0x38 0xc9 0x45 0x67 diff --git a/test/MC/Disassembler/Mips/mips32r2_le.txt b/test/MC/Disassembler/Mips/mips32r2_le.txt index 6d8be79..ecfde7a 100644 --- a/test/MC/Disassembler/Mips/mips32r2_le.txt +++ b/test/MC/Disassembler/Mips/mips32r2_le.txt @@ -1,442 +1,430 @@ -# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r2 +# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r2 | FileCheck %s +# CHECK: .section __TEXT,__text,regular,pure_instructions +# CHECK: abs.d $f12, $f14 +0x05 0x73 0x20 0x46 -# CHECK: abs.d $f12,$f14 -0x85 0x39 0x20 0x46 - -# CHECK: abs.s $f6,$f7 +# CHECK: abs.s $f6, $f7 0x85 0x39 0x00 0x46 -# CHECK: add t1,a2,a3 +# CHECK: add $9, $6, $7 0x20 0x48 0xc7 0x00 -# CHECK: add.d $f18,$f12,$f14 -0x40 0x32 0x27 0x46 +# CHECK: add.d $f8, $f12, $f14 +0x00 0x62 0x2e 0x46 -# CHECK: add.s $f9,$f6,$f7 +# CHECK: add.s $f9, $f6, $f7 0x40 0x32 0x07 0x46 -# CHECK: addi t1,a2,17767 +# CHECK: addi $9, $6, 17767 0x67 0x45 0xc9 0x20 -# CHECK: addiu t1,a2,-15001 +# CHECK: addiu $9, $6, -15001 0x67 0xc5 0xc9 0x24 -# CHECK: addu t1,a2,a3 +# CHECK: addu $9, $6, $7 0x21 0x48 0xc7 0x00 -# CHECK: and t1,a2,a3 +# CHECK: and $9, $6, $7 0x24 0x48 0xc7 0x00 -# CHECK: andi t1,a2,0x4567 +# CHECK: andi $9, $6, 17767 0x67 0x45 0xc9 0x30 -# CHECK: b 00000534 +# CHECK: b 1332 0x4c 0x01 0x00 0x10 -# CHECK: bal 00000534 -0x4c 0x01 0x11 0x04 - -# CHECK: bc1f 00000534 +# CHECK: bc1f 1332 0x4c 0x01 0x00 0x45 -# CHECK: bc1t 00000534 +# CHECK: bc1t 1332 0x4c 0x01 0x01 0x45 -# CHECK: beq t1,a2,00000534 +# CHECK: beq $9, $6, 1332 0x4c 0x01 0x26 0x11 -# CHECK: bgez a2,00000534 +# CHECK: bgez $6, 1332 0x4c 0x01 0xc1 0x04 -# CHECK: bgezal a2,00000534 +# CHECK: bgezal $6, 1332 0x4c 0x01 0xd1 0x04 -# CHECK: bgtz a2,00000534 +# CHECK: bgtz $6, 1332 0x4c 0x01 0xc0 0x1c -# CHECK: blez a2,00000534 +# CHECK: blez $6, 1332 0x4c 0x01 0xc0 0x18 -# CHECK: bne t1,a2,00000534 +# CHECK: bne $9, $6, 1332 0x4c 0x01 0x26 0x15 -# CHECK: c.eq.d $f12,$f14 -0x32 0x30 0x27 0x46 +# CHECK: c.eq.d $f12, $f14 +0x32 0x60 0x2e 0x46 -# CHECK: c.eq.s $f6,$f7 +# CHECK: c.eq.s $f6, $f7 0x32 0x30 0x07 0x46 -# CHECK: c.f.d $f12,$f14 -0x30 0x30 0x27 0x46 +# CHECK: c.f.d $f12, $f14 +0x30 0x60 0x2e 0x46 -# CHECK: c.f.s $f6,$f7 +# CHECK: c.f.s $f6, $f7 0x30 0x30 0x07 0x46 -# CHECK: c.le.d $f12,$f14 -0x3e 0x30 0x27 0x46 +# CHECK: c.le.d $f12, $f14 +0x3e 0x60 0x2e 0x46 -# CHECK: c.le.s $f6,$f7 +# CHECK: c.le.s $f6, $f7 0x3e 0x30 0x07 0x46 -# CHECK: c.lt.d $f12,$f14 -0x3c 0x30 0x27 0x46 +# CHECK: c.lt.d $f12, $f14 +0x3c 0x60 0x2e 0x46 -# CHECK: c.lt.s $f6,$f7 +# CHECK: c.lt.s $f6, $f7 0x3c 0x30 0x07 0x46 -# CHECK: c.nge.d $f12,$f14 -0x3d 0x30 0x27 0x46 +# CHECK: c.nge.d $f12, $f14 +0x3d 0x60 0x2e 0x46 -# CHECK: c.nge.s $f6,$f7 +# CHECK: c.nge.s $f6, $f7 0x3d 0x30 0x07 0x46 -# CHECK: c.ngl.d $f12,$f14 -0x3b 0x30 0x27 0x46 +# CHECK: c.ngl.d $f12, $f14 +0x3b 0x60 0x2e 0x46 -# CHECK: c.ngl.s $f6,$f7 +# CHECK: c.ngl.s $f6, $f7 0x3b 0x30 0x07 0x46 -# CHECK: c.ngle.d $f12,$f14 -0x39 0x30 0x27 0x46 +# CHECK: c.ngle.d $f12, $f14 +0x39 0x60 0x2e 0x46 -# CHECK: c.ngle.s $f6,$f7 +# CHECK: c.ngle.s $f6, $f7 0x39 0x30 0x07 0x46 -# CHECK: c.ngt.d $f12,$f14 -0x3f 0x30 0x27 0x46 +# CHECK: c.ngt.d $f12, $f14 +0x3f 0x60 0x2e 0x46 -# CHECK: c.ngt.s $f6,$f7 +# CHECK: c.ngt.s $f6, $f7 0x3f 0x30 0x07 0x46 -# CHECK: c.ole.d $f12,$f14 -0x36 0x30 0x27 0x46 +# CHECK: c.ole.d $f12, $f14 +0x36 0x60 0x2e 0x46 -# CHECK: c.ole.s $f6,$f7 +# CHECK: c.ole.s $f6, $f7 0x36 0x30 0x07 0x46 -# CHECK: c.olt.d $f12,$f14 -0x34 0x30 0x27 0x46 +# CHECK: c.olt.d $f12, $f14 +0x34 0x60 0x2e 0x46 -# CHECK: c.olt.s $f6,$f7 +# CHECK: c.olt.s $f6, $f7 0x34 0x30 0x07 0x46 -# CHECK: c.seq.d $f12,$f14 -0x3a 0x30 0x27 0x46 +# CHECK: c.seq.d $f12, $f14 +0x3a 0x60 0x2e 0x46 -# CHECK: c.seq.s $f6,$f7 +# CHECK: c.seq.s $f6, $f7 0x3a 0x30 0x07 0x46 -# CHECK: c.sf.d $f12,$f14 -0x38 0x30 0x27 0x46 +# CHECK: c.sf.d $f12, $f14 +0x38 0x60 0x2e 0x46 -# CHECK: c.sf.s $f6,$f7 +# CHECK: c.sf.s $f6, $f7 0x38 0x30 0x07 0x46 -# CHECK: c.ueq.d $f12,$f14 -0x33 0x30 0x27 0x46 +# CHECK: c.ueq.d $f12, $f14 +0x33 0x60 0x2e 0x46 -# CHECK: c.ueq.s $f28,$f18 +# CHECK: c.ueq.s $f28, $f18 0x33 0xe0 0x12 0x46 -# CHECK: c.ule.d $f12,$f14 -0x37 0x30 0x27 0x46 +# CHECK: c.ule.d $f12, $f14 +0x37 0x60 0x2e 0x46 -# CHECK: c.ule.s $f6,$f7 +# CHECK: c.ule.s $f6, $f7 0x37 0x30 0x07 0x46 -# CHECK: c.ult.d $f12,$f14 -0x35 0x30 0x27 0x46 +# CHECK: c.ult.d $f12, $f14 +0x35 0x60 0x2e 0x46 -# CHECK: c.ult.s $f6,$f7 +# CHECK: c.ult.s $f6, $f7 0x35 0x30 0x07 0x46 -# CHECK: c.un.d $f12,$f14 -0x31 0x30 0x27 0x46 +# CHECK: c.un.d $f12, $f14 +0x31 0x60 0x2e 0x46 -# CHECK: c.un.s $f6,$f7 +# CHECK: c.un.s $f6, $f7 0x31 0x30 0x07 0x46 -# CHECK: ceil.w.d $f12,$f14 -0x8e 0x38 0x20 0x46 +# CHECK: ceil.w.d $f12, $f14 +0x0e 0x73 0x20 0x46 -# CHECK: ceil.w.s $f6,$f7 -0x8e 0x38 0x00 0x46 +# CHECK: ceil.w.s $f6, $f7 +0x8e 0x39 0x00 0x46 -# CHECK: cfc1 a2,$7 +# CHECK: cfc1 $6, $7 0x00 0x38 0x46 0x44 -# CHECK: clo a2,a3 +# CHECK: clo $6, $7 0x21 0x30 0xe6 0x70 -# CHECK: clz a2,a3 +# CHECK: clz $6, $7 0x20 0x30 0xe6 0x70 -# CHECK: ctc1 a2,$7 +# CHECK: ctc1 $6, $7 0x00 0x38 0xc6 0x44 -# CHECK: cvt.d.s $f6,$f7 +# CHECK: cvt.d.s $f6, $f7 0xa1 0x39 0x00 0x46 -# CHECK: cvt.d.w $f12,$f14 -0xa1 0x39 0x80 0x46 +# CHECK: cvt.d.w $f12, $f14 +0x21 0x73 0x80 0x46 -# CHECK: cvt.l.d $f12,$f14 -0xa5 0x39 0x20 0x46 +# CHECK: cvt.l.d $f12, $f14 +0x25 0x73 0x20 0x46 -# CHECK: cvt.l.s $f6,$f7 +# CHECK: cvt.l.s $f6, $f7 0xa5 0x39 0x00 0x46 -# CHECK: cvt.s.d $f12,$f14 -0xa0 0x39 0x20 0x46 +# CHECK: cvt.s.d $f12, $f14 +0x20 0x73 0x20 0x46 -# CHECK: cvt.s.w $f6,$f7 +# CHECK: cvt.s.w $f6, $f7 0xa0 0x39 0x80 0x46 -# CHECK: cvt.w.d $f12,$f14 -0xa4 0x39 0x20 0x46 +# CHECK: cvt.w.d $f12, $f14 +0x24 0x73 0x20 0x46 -# CHECK: cvt.w.s $f6,$f7 +# CHECK: cvt.w.s $f6, $f7 0xa4 0x39 0x00 0x46 -# CHECK: floor.w.d $f12,$f14 -0x8f 0x39 0x20 0x46 +# CHECK: floor.w.d $f12, $f14 +0x0f 0x73 0x20 0x46 -# CHECK: floor.w.s $f6,$f7 +# CHECK: floor.w.s $f6, $f7 0x8f 0x39 0x00 0x46 -# CHECK: ins s3,t1,0x6,0x7 +# CHECK: ins $19, $9, 6, 7 0x84 0x61 0x33 0x7d -# CHECK: j 00000530 +# CHECK: j 1328 0x4c 0x01 0x00 0x08 -# CHECK: jal 00000530 +# CHECK: jal 1328 0x4c 0x01 0x00 0x0c -# CHECK: jalr a2,a3 +# CHECK: jalr $7 0x09 0xf8 0xe0 0x00 -# CHECK: jr a3 +# CHECK: jr $7 0x08 0x00 0xe0 0x00 -# CHECK: lb a0,9158(a1) +# CHECK: lb $4, 9158($5) 0xc6 0x23 0xa4 0x80 -# CHECK: lbu a0,6(a1) +# CHECK: lbu $4, 6($5) 0x06 0x00 0xa4 0x90 -# CHECK: ldc1 $f9,9158(a3) +# CHECK: ldc1 $f9, 9158($7) 0xc6 0x23 0xe9 0xd4 -# CHECK: lh a0,12(a1) +# CHECK: lh $4, 12($5) 0x0c 0x00 0xa4 0x84 -# CHECK: lh a0,12(a1) +# CHECK: lh $4, 12($5) 0x0c 0x00 0xa4 0x84 -# CHECK: li v1,17767 -0x67 0x45 0x03 0x24 - -# CHECK: ll t1,9158(a3) +# CHECK: ll $9, 9158($7) 0xc6 0x23 0xe9 0xc0 -# CHECK: lui a2,0x4567 +# CHECK: lui $6, 17767 0x67 0x45 0x06 0x3c -# CHECK: lw a0,24(a1) +# CHECK: lw $4, 24($5) 0x18 0x00 0xa4 0x8c -# CHECK lw at,-18316(v0) -0x74 0xb8 0x41 0x8c - -# CHECK: lwc1 $f9,9158(a3) +# CHECK: lwc1 $f9, 9158($7) 0xc6 0x23 0xe9 0xc4 -# CHECK: madd a2,a3 +# CHECK: lwl $2, 3($4) +0x03 0x00 0x82 0x88 + +# CHECK: lwr $3, 16($5) +0x10 0x00 0xa3 0x98 + +# CHECK: madd $6, $7 0x00 0x00 0xc7 0x70 -# CHECK: maddu a2,a3 +# CHECK: maddu $6, $7 0x01 0x00 0xc7 0x70 -# CHECK: mfc1 a2,$f7 +# CHECK: mfc1 $6, $f7 0x00 0x38 0x06 0x44 -# CHECK: mfhi a1 +# CHECK: mfhi $5 0x10 0x28 0x00 0x00 -# CHECK: mflo a1 +# CHECK: mflo $5 0x12 0x28 0x00 0x00 -# CHECK: mov.d $f12,$f14 -0x86 0x39 0x20 0x46 +# CHECK: mov.d $f6, $f8 +0x86 0x41 0x20 0x46 -# CHECK: mov.s $f6,$f7 +# CHECK: mov.s $f6, $f7 0x86 0x39 0x00 0x46 -# CHECK: move a2,a1 -0x21 0x30 0xa0 0x00 - -# CHECK: msub a2,a3 +# CHECK: msub $6, $7 0x04 0x00 0xc7 0x70 -# CHECK: msubu a2,a3 +# CHECK: msubu $6, $7 0x05 0x00 0xc7 0x70 -# CHECK: mtc1 a2,$f7 +# CHECK: mtc1 $6, $f7 0x00 0x38 0x86 0x44 -# CHECK: mthi a3 +# CHECK: mthi $7 0x11 0x00 0xe0 0x00 -# CHECK: mtlo a3 +# CHECK: mtlo $7 0x13 0x00 0xe0 0x00 -# CHECK: mul.d $f9,$f12,$f14 -0x42 0x32 0x27 0x46 +# CHECK: mul.d $f8, $f12, $f14 +0x02 0x62 0x2e 0x46 -# CHECK: mul.s $f9,$f6,$f7 +# CHECK: mul.s $f9, $f6, $f7 0x42 0x32 0x07 0x46 -# CHECK: mul t1,a2,a3 +# CHECK: mul $9, $6, $7 0x02 0x48 0xc7 0x70 -# CHECK: mult v1,a1 +# CHECK: mult $3, $5 0x18 0x00 0x65 0x00 -# CHECK: multu v1,a1 +# CHECK: multu $3, $5 0x19 0x00 0x65 0x00 -# CHECK: neg.d $f12,$f14 -0x87 0x39 0x20 0x46 +# CHECK: neg.d $f12, $f14 +0x07 0x73 0x20 0x46 -# CHECK: neg.s $f6,$f7 +# CHECK: neg.s $f6, $f7 0x87 0x39 0x00 0x46 -# CHECK: neg v1,a1 -0x22 0x18 0x05 0x00 - # CHECK: nop 0x00 0x00 0x00 0x00 -# CHECK: nor t1,a2,a3 +# CHECK: nor $9, $6, $7 0x27 0x48 0xc7 0x00 -# CHECK: not v1,a1 -0x27 0x18 0xa0 0x00 - -# CHECK: or v1,v1,a1 +# CHECK: or $3, $3, $5 0x25 0x18 0x65 0x00 -# CHECK: ori t1,a2,0x4567 +# CHECK: ori $9, $6, 17767 0x67 0x45 0xc9 0x34 -# CHECK: rdhwr a2,$29 -0x3b 0xe8 0x06 0x7c - -# CHECK: ror t1,a2,0x7 +# CHECK: rotr $9, $6, 7 0xc2 0x49 0x26 0x00 -# CHECK: rorv t1,a2,a3 +# CHECK: rotrv $9, $6, $7 0x46 0x48 0xe6 0x00 -# CHECK: round.w.d $f12,$f14 -0x8c 0x39 0x20 0x46 +# CHECK: round.w.d $f12, $f14 +0x0c 0x73 0x20 0x46 -# CHECK: round.w.s $f6,$f7 +# CHECK: round.w.s $f6, $f7 0x8c 0x39 0x00 0x46 -# CHECK: sb a0,9158(a1) +# CHECK: sb $4, 9158($5) 0xc6 0x23 0xa4 0xa0 -# CHECK: sb a0,6(a1) +# CHECK: sb $4, 6($5) 0x06 0x00 0xa4 0xa0 -# CHECK: sc t1,9158(a3) +# CHECK: sc $9, 9158($7) 0xc6 0x23 0xe9 0xe0 -# CHECK: sdc1 $f9,9158(a3) +# CHECK: sdc1 $f9, 9158($7) 0xc6 0x23 0xe9 0xf4 -# CHECK: seb a2,a3 +# CHECK: seb $6, $7 0x20 0x34 0x07 0x7c -# CHECK: seh a2,a3 +# CHECK: seh $6, $7 0x20 0x36 0x07 0x7c -# CHECK: sh a0,9158(a1) +# CHECK: sh $4, 9158($5) 0xc6 0x23 0xa4 0xa4 -# CHECK: sll a0,v1,0x7 +# CHECK: sll $4, $3, 7 0xc0 0x21 0x03 0x00 -# CHECK: sllv v0,v1,a1 +# CHECK: sllv $2, $3, $5 0x04 0x10 0xa3 0x00 -# CHECK: slt v1,v1,a1 +# CHECK: slt $3, $3, $5 0x2a 0x18 0x65 0x00 -# CHECK: slti v1,v1,103 +# CHECK: slti $3, $3, 103 0x67 0x00 0x63 0x28 -# CHECK: sltiu v1,v1,103 +# CHECK: sltiu $3, $3, 103 0x67 0x00 0x63 0x2c -# CHECK: sltu v1,v1,a1 +# CHECK: sltu $3, $3, $5 0x2b 0x18 0x65 0x00 -# CHECK: sqrt.d $f12,$f14 -0x84 0x39 0x20 0x46 +# CHECK: sqrt.d $f12, $f14 +0x04 0x73 0x20 0x46 -# CHECK: sqrt.s $f6,$f7 +# CHECK: sqrt.s $f6, $f7 0x84 0x39 0x00 0x46 -# CHECK: sra a0,v1,0x7 +# CHECK: sra $4, $3, 7 0xc3 0x21 0x03 0x00 -# CHECK: sra a0,v1,0x7 -0xc3 0x21 0x03 0x00 - -# CHECK: srav v0,v1,a1 +# CHECK: srav $2, $3, $5 0x07 0x10 0xa3 0x00 -# CHECK: srl a0,v1,0x7 +# CHECK: srl $4, $3, 7 0xc2 0x21 0x03 0x00 -# CHECK: srlv v0,v1,a1 +# CHECK: srlv $2, $3, $5 0x06 0x10 0xa3 0x00 -# CHECK: sub.d $f9,$f12,$f14 -0x41 0x32 0x27 0x46 +# CHECK: sub.d $f8, $f12, $f14 +0x01 0x62 0x2e 0x46 -# CHECK: sub.s $f9,$f6,$f7 +# CHECK: sub.s $f9, $f6, $f7 0x41 0x32 0x07 0x46 -# CHECK: sub t1,a2,a3 +# CHECK: sub $9, $6, $7 0x22 0x48 0xc7 0x00 -# CHECK: subu a0,v1,a1 +# CHECK: subu $4, $3, $5 0x23 0x20 0x65 0x00 -# CHECK: sw a0,24(a1) +# CHECK: sw $4, 24($5) 0x18 0x00 0xa4 0xac -# CHECK: swc1 $f9,9158(a3) +# CHECK: swc1 $f9, 9158($7) 0xc6 0x23 0xe9 0xe4 -# CHECK: sync 0x7 +# CHECK: swl $4, 16($5) +0x10 0x00 0xa4 0xa8 + +# CHECK: swr $6, 16($7) +0x10 0x00 0xe6 0xb8 + +# CHECK: sync 7 0xcf 0x01 0x00 0x00 -# CHECK: trunc.w.d $f12,$f14 -0x8d 0x39 0x20 0x46 +# CHECK: trunc.w.d $f12, $f14 +0x0d 0x73 0x20 0x46 -# CHECK: trunc.w.s $f6,$f7 +# CHECK: trunc.w.s $f6, $f7 0x8d 0x39 0x00 0x46 -# CHECK: wsbh a2,a3 +# CHECK: wsbh $6, $7 0xa0 0x30 0x07 0x7c -# CHECK: xor v1,v1,a1 +# CHECK: xor $3, $3, $5 0x26 0x18 0x65 0x00 -# CHECK: xori t1,a2,0x4567 +# CHECK: xori $9, $6, 17767 0x67 0x45 0xc9 0x38 diff --git a/test/MC/Disassembler/Mips/mips64.txt b/test/MC/Disassembler/Mips/mips64.txt index 1c7447a..095ed18 100644 --- a/test/MC/Disassembler/Mips/mips64.txt +++ b/test/MC/Disassembler/Mips/mips64.txt @@ -1,67 +1,67 @@ -# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux
-
-# CHECK: daddiu t3,k0,31949
+# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux | FileCheck %s
+# CHECK: .section __TEXT,__text,regular,pure_instructions
+# CHECK: daddiu $11, $26, 31949
0x67 0x4b 0x7c 0xcd
-# CHECK: daddu k0,at,t3
+# CHECK: daddu $26, $at, $11
0x00 0x2b 0xd0 0x2d
-# CHECK: ddiv zero,k0,s6
+# CHECK: ddiv $zero, $26, $22
0x03 0x56 0x00 0x1e
-# CHECK: ddivu zero,t1,t8
+# CHECK: ddivu $zero, $9, $24
0x01 0x38 0x00 0x1f
-# CHECK: dmfc1 v0,$f14
+# CHECK: dmfc1 $2, $f14
0x44 0x22 0x70 0x00
-# CHECK: dmtc1 s7,$f5
+# CHECK: dmtc1 $23, $f5
0x44 0xb7 0x28 0x00
-# CHECK: dmult t3,k0
+# CHECK: dmult $11, $26
0x01 0x7a 0x00 0x1c
-# CHECK: dmultu s7,t5
+# CHECK: dmultu $23, $13
0x02 0xed 0x00 0x1d
-# CHECK: dsll v1,t8,0x11
+# CHECK: dsll $3, $24, 17
0x00 0x18 0x1c 0x78
-# CHECK: dsllv gp,k1,t8
+# CHECK: dsllv $gp, $27, $24
0x03 0x1b 0xe0 0x14
-# CHECK: dsra at,at,0x1e
+# CHECK: dsra $at, $at, 30
0x00 0x01 0x0f 0xbb
-# CHECK: dsrav at,at,s8
+# CHECK: dsrav $at, $at, $fp
0x03 0xc1 0x08 0x17
-# CHECK: dsrl t2,gp,0x18
+# CHECK: dsrl $10, $gp, 24
0x00 0x1c 0x56 0x3a
-# CHECK: dsrlv gp,t2,s7
+# CHECK: dsrlv $gp, $10, $23
0x02 0xea 0xe0 0x16
-# CHECK: dsubu gp,k1,t8
+# CHECK: dsubu $gp, $27, $24
0x03 0x78 0xe0 0x2f
-# CHECK: lw k1,-15155(at)
+# CHECK: lw $27, -15155($at)
0x8c 0x3b 0xc4 0xcd
-# CHECK: lui at,0x1
+# CHECK: lui $at, 1
0x3c 0x01 0x00 0x01
-# CHECK: lwu v1,-1746(v1)
+# CHECK: lwu $3, -1746($3)
0x9c 0x63 0xf9 0x2e
-# CHECK: lui ra,0x1
+# CHECK: lui $ra, 1
0x3c 0x1f 0x00 0x01
-# CHECK: sw k0,-15159(at)
+# CHECK: sw $26, -15159($at)
0xac 0x3a 0xc4 0xc9
-# CHECK: ld k0,3958(zero)
+# CHECK: ld $26, 3958($zero)
0xdc 0x1a 0x0f 0x76
-# CHECK: sd a2,17767(zero)
+# CHECK: sd $6, 17767($zero)
0xfc 0x06 0x45 0x67
diff --git a/test/MC/Disassembler/Mips/mips64_le.txt b/test/MC/Disassembler/Mips/mips64_le.txt index dd87522..c4e5591 100644 --- a/test/MC/Disassembler/Mips/mips64_le.txt +++ b/test/MC/Disassembler/Mips/mips64_le.txt @@ -1,67 +1,67 @@ -# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux
-
-# CHECK: daddiu t3,k0,31949
+# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux | FileCheck %s
+# CHECK: .section __TEXT,__text,regular,pure_instructions
+# CHECK: daddiu $11, $26, 31949
0xcd 0x7c 0x4b 0x67
-# CHECK: daddu k0,at,t3
+# CHECK: daddu $26, $at, $11
0x2d 0xd0 0x2b 0x00
-# CHECK: ddiv zero,k0,s6
+# CHECK: ddiv $zero, $26, $22
0x1e 0x00 0x56 0x03
-# CHECK: ddivu zero,t1,t8
+# CHECK: ddivu $zero, $9, $24
0x1f 0x00 0x38 0x01
-# CHECK: dmfc1 v0,$f14
+# CHECK: dmfc1 $2, $f14
0x00 0x70 0x22 0x44
-# CHECK: dmtc1 s7,$f5
+# CHECK: dmtc1 $23, $f5
0x00 0x28 0xb7 0x44
-# CHECK: dmult t3,k0
+# CHECK: dmult $11, $26
0x1c 0x00 0x7a 0x01
-# CHECK: dmultu s7,t5
+# CHECK: dmultu $23, $13
0x1d 0x00 0xed 0x02
-# CHECK: dsll v1,t8,0x11
+# CHECK: dsll $3, $24, 17
0x78 0x1c 0x18 0x00
-# CHECK: dsllv gp,k1,t8
+# CHECK: dsllv $gp, $27, $24
0x14 0xe0 0x1b 0x03
-# CHECK: dsra at,at,0x1e
+# CHECK: dsra $at, $at, 30
0xbb 0x0f 0x01 0x00
-# CHECK: dsrav at,at,s8
+# CHECK: dsrav $at, $at, $fp
0x17 0x08 0xc1 0x03
-# CHECK: dsrl t2,gp,0x18
+# CHECK: dsrl $10, $gp, 24
0x3a 0x56 0x1c 0x00
-# CHECK: dsrlv gp,t2,s7
+# CHECK: dsrlv $gp, $10, $23
0x16 0xe0 0xea 0x02
-# CHECK: dsubu gp,k1,t8
+# CHECK: dsubu $gp, $27, $24
0x2f 0xe0 0x78 0x03
-# CHECK: lw k1,-15155(at)
+# CHECK: lw $27, -15155($at)
0xcd 0xc4 0x3b 0x8c
-# CHECK: lui at,0x1
+# CHECK: lui $at, 1
0x01 0x00 0x01 0x3c
-# CHECK: lwu v1,-1746(v1)
+# CHECK: lwu $3, -1746($3)
0x2e 0xf9 0x63 0x9c
-# CHECK: lui ra,0x1
+# CHECK: lui $ra, 1
0x01 0x00 0x1f 0x3c
-# CHECK: sw k0,-15159(at)
+# CHECK: sw $26, -15159($at)
0xc9 0xc4 0x3a 0xac
-# CHECK: ld k0,3958(zero)
+# CHECK: ld $26, 3958($zero)
0x76 0x0f 0x1a 0xdc
-# CHECK: sd a2,17767(zero)
+# CHECK: sd $6, 17767($zero)
0x67 0x45 0x06 0xfc
diff --git a/test/MC/Disassembler/Mips/mips64r2.txt b/test/MC/Disassembler/Mips/mips64r2.txt index 26bc94d..41808c7 100644 --- a/test/MC/Disassembler/Mips/mips64r2.txt +++ b/test/MC/Disassembler/Mips/mips64r2.txt @@ -1,91 +1,91 @@ -# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mattr +mips64r2
-
-# CHECK: daddiu t3,k0,31949
+# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mattr +mips64r2 | FileCheck %s
+# CHECK: .section __TEXT,__text,regular,pure_instructions
+# CHECK: daddiu $11, $26, 31949
0x67 0x4b 0x7c 0xcd
-# CHECK: daddu k0,at,t3
+# CHECK: daddu $26, $at, $11
0x00 0x2b 0xd0 0x2d
-# CHECK: ddiv zero,k0,s6
+# CHECK: ddiv $zero, $26, $22
0x03 0x56 0x00 0x1e
-# CHECK: ddivu zero,t1,t8
+# CHECK: ddivu $zero, $9, $24
0x01 0x38 0x00 0x1f
-# CHECK: dmfc1 v0,$f14
+# CHECK: dmfc1 $2, $f14
0x44 0x22 0x70 0x00
-# CHECK: dmtc1 s7,$f5
+# CHECK: dmtc1 $23, $f5
0x44 0xb7 0x28 0x00
-# CHECK: dmult t3,k0
+# CHECK: dmult $11, $26
0x01 0x7a 0x00 0x1c
-# CHECK: dmultu s7,t5
+# CHECK: dmultu $23, $13
0x02 0xed 0x00 0x1d
-# CHECK: dsll v1,t8,0x11
+# CHECK: dsll $3, $24, 17
0x00 0x18 0x1c 0x78
-# CHECK: dsllv gp,k1,t8
+# CHECK: dsllv $gp, $27, $24
0x03 0x1b 0xe0 0x14
-# CHECK: dsra at,at,0x1e
+# CHECK: dsra $at, $at, 30
0x00 0x01 0x0f 0xbb
-# CHECK: dsrav at,at,s8
+# CHECK: dsrav $at, $at, $fp
0x03 0xc1 0x08 0x17
-# CHECK: dsrl t2,gp,0x18
+# CHECK: dsrl $10, $gp, 24
0x00 0x1c 0x56 0x3a
-# CHECK: dsrlv gp,t2,s7
+# CHECK: dsrlv $gp, $10, $23
0x02 0xea 0xe0 0x16
-# CHECK: dsubu gp,k1,t8
+# CHECK: dsubu $gp, $27, $24
0x03 0x78 0xe0 0x2f
-# CHECK: lw k1,-15155(at)
+# CHECK: lw $27, -15155($at)
0x8c 0x3b 0xc4 0xcd
-# CHECK: lui at,0x1
+# CHECK: lui $at, 1
0x3c 0x01 0x00 0x01
-# CHECK: lwu v1,-1746(v1)
+# CHECK: lwu $3, -1746($3)
0x9c 0x63 0xf9 0x2e
-# CHECK: lui ra,0x1
+# CHECK: lui $ra, 1
0x3c 0x1f 0x00 0x01
-# CHECK: sw k0,-15159(at)
+# CHECK: sw $26, -15159($at)
0xac 0x3a 0xc4 0xc9
-# CHECK: ld k0,3958(zero)
+# CHECK: ld $26, 3958($zero)
0xdc 0x1a 0x0f 0x76
-# CHECK: sd a2,17767(zero)
+# CHECK: sd $6, 17767($zero)
0xfc 0x06 0x45 0x67
-# CHECK: dclo t1,t8
+# CHECK: dclo $9, $24
0x73 0x09 0x48 0x25
-# CHECK: dclz k0,t1
+# CHECK: dclz $26, $9
0x71 0x3a 0xd0 0x24
-# CHECK: dext a3,gp,0x1d,0x1f
+# CHECK: dext $7, $gp, 29, 31
0x7f 0x87 0xf7 0x43
-# CHECK: dins s4,gp,0xf,0x1
+# CHECK: dins $20, $gp, 15, 1
0x7f 0x94 0x7b 0xc7
-# CHECK: dsbh a3,gp
+# CHECK: dsbh $7, $gp
0x7c 0x1c 0x38 0xa4
-# CHECK: dshd v1,t6
+# CHECK: dshd $3, $14
0x7c 0x0e 0x19 0x64
-# CHECK: drotr s4,k1,0x6
+# CHECK: drotr $20, $27, 6
0x00 0x3b 0xa1 0xba
-# CHECK: drotrv t8,s7,a1
+# CHECK: drotrv $24, $23, $5
0x00 0xb7 0xc0 0x56
diff --git a/test/MC/Disassembler/Mips/mips64r2_le.txt b/test/MC/Disassembler/Mips/mips64r2_le.txt index 81a7c66..4987f80 100644 --- a/test/MC/Disassembler/Mips/mips64r2_le.txt +++ b/test/MC/Disassembler/Mips/mips64r2_le.txt @@ -1,91 +1,91 @@ -# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux -mattr +mips64r2
-
-# CHECK: daddiu t3,k0,31949
+# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux -mattr +mips64r2 | FileCheck %s
+# CHECK: .section __TEXT,__text,regular,pure_instructions
+# CHECK: daddiu $11, $26, 31949
0xcd 0x7c 0x4b 0x67
-# CHECK: daddu k0,at,t3
+# CHECK: daddu $26, $at, $11
0x2d 0xd0 0x2b 0x00
-# CHECK: ddiv zero,k0,s6
+# CHECK: ddiv $zero, $26, $22
0x1e 0x00 0x56 0x03
-# CHECK: ddivu zero,t1,t8
+# CHECK: ddivu $zero, $9, $24
0x1f 0x00 0x38 0x01
-# CHECK: dmfc1 v0,$f14
+# CHECK: dmfc1 $2, $f14
0x00 0x70 0x22 0x44
-# CHECK: dmtc1 s7,$f5
+# CHECK: dmtc1 $23, $f5
0x00 0x28 0xb7 0x44
-# CHECK: dmult t3,k0
+# CHECK: dmult $11, $26
0x1c 0x00 0x7a 0x01
-# CHECK: dmultu s7,t5
+# CHECK: dmultu $23, $13
0x1d 0x00 0xed 0x02
-# CHECK: dsll v1,t8,0x11
+# CHECK: dsll $3, $24, 17
0x78 0x1c 0x18 0x00
-# CHECK: dsllv gp,k1,t8
+# CHECK: dsllv $gp, $27, $24
0x14 0xe0 0x1b 0x03
-# CHECK: dsra at,at,0x1e
+# CHECK: dsra $at, $at, 30
0xbb 0x0f 0x01 0x00
-# CHECK: dsrav at,at,s8
+# CHECK: dsrav $at, $at, $fp
0x17 0x08 0xc1 0x03
-# CHECK: dsrl t2,gp,0x18
+# CHECK: dsrl $10, $gp, 24
0x3a 0x56 0x1c 0x00
-# CHECK: dsrlv gp,t2,s7
+# CHECK: dsrlv $gp, $10, $23
0x16 0xe0 0xea 0x02
-# CHECK: dsubu gp,k1,t8
+# CHECK: dsubu $gp, $27, $24
0x2f 0xe0 0x78 0x03
-# CHECK: lw k1,-15155(at)
+# CHECK: lw $27, -15155($at)
0xcd 0xc4 0x3b 0x8c
-# CHECK: lui at,0x1
+# CHECK: lui $at, 1
0x01 0x00 0x01 0x3c
-# CHECK: lwu v1,-1746(v1)
+# CHECK: lwu $3, -1746($3)
0x2e 0xf9 0x63 0x9c
-# CHECK: lui ra,0x1
+# CHECK: lui $ra, 1
0x01 0x00 0x1f 0x3c
-# CHECK: sw k0,-15159(at)
+# CHECK: sw $26, -15159($at)
0xc9 0xc4 0x3a 0xac
-# CHECK: ld k0,3958(zero)
+# CHECK: ld $26, 3958($zero)
0x76 0x0f 0x1a 0xdc
-# CHECK: sd a2,17767(zero)
+# CHECK: sd $6, 17767($zero)
0x67 0x45 0x06 0xfc
-# CHECK: dclo t1,t8
+# CHECK: dclo $9, $24
0x25 0x48 0x09 0x73
-# CHECK: dclz k0,t1
+# CHECK: dclz $26, $9
0x24 0xd0 0x3a 0x71
-# CHECK: dext a3,gp,0x1d,0x1f
+# CHECK: dext $7, $gp, 29, 31
0x43 0xf7 0x87 0x7f
-# CHECK: dins s4,gp,0xf,0x1
+# CHECK: dins $20, $gp, 15, 1
0xc7 0x7b 0x94 0x7f
-# CHECK: dsbh a3,gp
+# CHECK: dsbh $7, $gp
0xa4 0x38 0x1c 0x7c
-# CHECK: dshd v1,t6
+# CHECK: dshd $3, $14
0x64 0x19 0x0e 0x7c
-# CHECK: drotr s4,k1,0x6
+# CHECK: drotr $20, $27, 6
0xba 0xa1 0x3b 0x00
-# CHECK: drotrv t8,s7,a1
+# CHECK: drotrv $24, $23, $5
0x56 0xc0 0xb7 0x00
diff --git a/test/MC/Disassembler/X86/enhanced.txt b/test/MC/Disassembler/X86/enhanced.txt index 752ab17..deff735 100644 --- a/test/MC/Disassembler/X86/enhanced.txt +++ b/test/MC/Disassembler/X86/enhanced.txt @@ -1,10 +1,10 @@ -# RUN: llvm-mc --edis %s -triple=x86_64-apple-darwin9 |& FileCheck %s +# RUN: llvm-mc --edis %s -triple=x86_64-apple-darwin9 2>&1 | FileCheck %s -# CHECK: [o:jne][w: ][0-p:-][0-l:10=10] <br> 0:[RIP/111](pc)=18446744073709551606 +# CHECK: [o:jne][w: ][0-p:-][0-l:10=10] <br> 0:[RIP/112](pc)=18446744073709551606 0x0f 0x85 0xf6 0xff 0xff 0xff -# CHECK: [o:movq][w: ][1-r:%gs=r63][1-p::][1-l:8=8][p:,][w: ][0-r:%rcx=r108] <mov> 0:[RCX/108]=0 1:[GS/63]=8 +# CHECK: [o:movq][w: ][1-r:%gs=r64][1-p::][1-l:8=8][p:,][w: ][0-r:%rcx=r109] <mov> 0:[RCX/109]=0 1:[GS/64]=8 0x65 0x48 0x8b 0x0c 0x25 0x08 0x00 0x00 0x00 -# CHECK: [o:xorps][w: ][2-r:%xmm1=r129][p:,][w: ][0-r:%xmm2=r130] 0:[XMM2/130]=0 1:[XMM2/130]=0 2:[XMM1/129]=0 +# CHECK: [o:xorps][w: ][2-r:%xmm1=r130][p:,][w: ][0-r:%xmm2=r131] 0:[XMM2/131]=0 1:[XMM2/131]=0 2:[XMM1/130]=0 0x0f 0x57 0xd1 -# CHECK: [o:andps][w: ][2-r:%xmm1=r129][p:,][w: ][0-r:%xmm2=r130] 0:[XMM2/130]=0 1:[XMM2/130]=0 2:[XMM1/129]=0 +# CHECK: [o:andps][w: ][2-r:%xmm1=r130][p:,][w: ][0-r:%xmm2=r131] 0:[XMM2/131]=0 1:[XMM2/131]=0 2:[XMM1/130]=0 0x0f 0x54 0xd1 diff --git a/test/MC/Disassembler/X86/intel-syntax.txt b/test/MC/Disassembler/X86/intel-syntax.txt index a5dbcf2..27694cd 100644 --- a/test/MC/Disassembler/X86/intel-syntax.txt +++ b/test/MC/Disassembler/X86/intel-syntax.txt @@ -105,3 +105,8 @@ # CHECK: retf 0x66 0xcb +# CHECK: vpgatherqq YMM2, QWORD PTR [RDI + 2*YMM1], YMM0 +0xc4 0xe2 0xfd 0x91 0x14 0x4f + +# CHECK: vpgatherdd XMM10, DWORD PTR [R15 + 2*XMM9], XMM8 +0xc4 0x02 0x39 0x90 0x14 0x4f diff --git a/test/MC/Disassembler/X86/invalid-VEX-vvvv.txt b/test/MC/Disassembler/X86/invalid-VEX-vvvv.txt index 9feb54c..31a3804 100644 --- a/test/MC/Disassembler/X86/invalid-VEX-vvvv.txt +++ b/test/MC/Disassembler/X86/invalid-VEX-vvvv.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 2>&1 | grep "invalid instruction encoding" # This instruction would decode as movmskps if the vvvv field in the VEX prefix was all 1s. 0xc5 0xf0 0x50 0xc0 diff --git a/test/MC/Disassembler/X86/invalid-cmp-imm.txt b/test/MC/Disassembler/X86/invalid-cmp-imm.txt index bf8699b..7b2ea2a 100644 --- a/test/MC/Disassembler/X86/invalid-cmp-imm.txt +++ b/test/MC/Disassembler/X86/invalid-cmp-imm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 2>&1 | grep "invalid instruction encoding" # This instruction would decode as cmpordps if the immediate byte was less than 8. 0x0f 0xc2 0xc7 0x08 diff --git a/test/MC/Disassembler/X86/simple-tests.txt b/test/MC/Disassembler/X86/simple-tests.txt index c0e77d06..672d239 100644 --- a/test/MC/Disassembler/X86/simple-tests.txt +++ b/test/MC/Disassembler/X86/simple-tests.txt @@ -123,10 +123,10 @@ # CHECK: vcvtss2sil %xmm0, %eax 0xc5 0xfa 0x2d 0xc0 -# CHECK: vcvtsd2si %xmm0, %eax +# CHECK: vcvtsd2sil %xmm0, %eax 0xc5 0xfb 0x2d 0xc0 -# CHECK: vcvtsd2si %xmm0, %rax +# CHECK: vcvtsd2siq %xmm0, %rax 0xc4 0xe1 0xfb 0x2d 0xc0 # CHECK: vmaskmovpd %xmm0, %xmm1, (%rax) @@ -437,10 +437,10 @@ # CHECK: vroundsd $0, %xmm0, %xmm0, %xmm0 0xc4 0xe3 0x7d 0x0b 0xc0 0x00 -# CHECK: vcvtsd2si %xmm0, %eax +# CHECK: vcvtsd2sil %xmm0, %eax 0xc4 0xe1 0x7f 0x2d 0xc0 -# CHECK: vcvtsd2si %xmm0, %rax +# CHECK: vcvtsd2siq %xmm0, %rax 0xc4 0xe1 0xff 0x2d 0xc0 # CHECK: vucomisd %xmm1, %xmm0 @@ -725,6 +725,30 @@ # CHECK: vpermil2ps $1, 4(%rax), %xmm2, %xmm3, %xmm0 0xc4 0xe3 0xe1 0x48 0x40 0x04 0x21 +# CHECK: vgatherdpd %xmm0, (%rdi,%xmm1,2), %xmm2 +0xc4 0xe2 0xf9 0x92 0x14 0x4f + +# CHECK: vgatherdpd %ymm0, (%rdi,%xmm1,2), %ymm2 +0xc4 0xe2 0xfd 0x92 0x14 0x4f + +# CHECK: vgatherqps %xmm8, (%r15,%xmm9,2), %xmm10 +0xc4 0x02 0x39 0x93 0x14 0x4f + +# CHECK: vgatherqps %xmm8, (%r15,%ymm9,2), %xmm10 +0xc4 0x02 0x3d 0x93 0x14 0x4f + +# CHECK: vpgatherdq %xmm0, (%rdi,%xmm1,2), %xmm2 +0xc4 0xe2 0xf9 0x90 0x14 0x4f + +# CHECK: vpgatherdq %ymm0, (%rdi,%xmm1,2), %ymm2 +0xc4 0xe2 0xfd 0x90 0x14 0x4f + +# CHECK: vpgatherqd %xmm8, (%r15,%xmm9,2), %xmm10 +0xc4 0x02 0x39 0x91 0x14 0x4f + +# CHECK: vpgatherqd %xmm8, (%r15,%ymm9,2), %xmm10 +0xc4 0x02 0x3d 0x91 0x14 0x4f + # rdar://8812056 lldb doesn't print the x86 lock prefix when disassembling # CHECK: lock # CHECK-NEXT: xaddq %rcx, %rbx diff --git a/test/MC/Disassembler/X86/truncated-input.txt b/test/MC/Disassembler/X86/truncated-input.txt index 34cf038..83be1ca 100644 --- a/test/MC/Disassembler/X86/truncated-input.txt +++ b/test/MC/Disassembler/X86/truncated-input.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 |& FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 2>&1 | FileCheck %s # CHECK: warning 0x00 diff --git a/test/MC/Disassembler/X86/x86-32.txt b/test/MC/Disassembler/X86/x86-32.txt index 739fa6a..899657b 100644 --- a/test/MC/Disassembler/X86/x86-32.txt +++ b/test/MC/Disassembler/X86/x86-32.txt @@ -159,10 +159,10 @@ # CHECK: vcvtss2sil %xmm0, %eax 0xc5 0xfa 0x2d 0xc0 -# CHECK: vcvtsd2si %xmm0, %eax +# CHECK: vcvtsd2sil %xmm0, %eax 0xc5 0xfb 0x2d 0xc0 -# CHECK: vcvtsd2si %xmm0, %eax +# CHECK: vcvtsd2sil %xmm0, %eax 0xc4 0xe1 0x7b 0x2d 0xc0 # CHECK: vmaskmovpd %xmm0, %xmm1, (%eax) @@ -460,10 +460,10 @@ # CHECK: vroundsd $0, %xmm0, %xmm0, %xmm0 0xc4 0xe3 0x7d 0x0b 0xc0 0x00 -# CHECK: vcvtsd2si %xmm0, %eax +# CHECK: vcvtsd2sil %xmm0, %eax 0xc4 0xe1 0x7f 0x2d 0xc0 -# CHECK: vcvtsd2si %xmm0, %eax +# CHECK: vcvtsd2sil %xmm0, %eax 0xc4 0xe1 0xff 0x2d 0xc0 # CHECK: vucomisd %xmm1, %xmm0 @@ -612,3 +612,21 @@ # CHECK: shrxl %esi, %ebx, %edx 0xc4 0xe2 0x0b 0xf7 0xd3 + +# CHECK: extrq $2, $3, %xmm0 +0x66 0x0f 0x78 0xc0 0x03 0x02 + +# CHECK: extrq %xmm1, %xmm0 +0x66 0x0f 0x79 0xc1 + +# CHECK: insertq $6, $5, %xmm1, %xmm0 +0xf2 0x0f 0x78 0xc1 0x05 0x06 + +# CHECK: insertq %xmm1, %xmm0 +0xf2 0x0f 0x79 0xc1 + +# CHECK: movntsd %xmm0, (%edi) +0xf2 0x0f 0x2b 0x07 + +# CHECK: movntss %xmm0, (%edi) +0xf3 0x0f 0x2b 0x07 diff --git a/test/MC/Disassembler/X86/x86-64.txt b/test/MC/Disassembler/X86/x86-64.txt index f4b8f46..df449a4 100644 --- a/test/MC/Disassembler/X86/x86-64.txt +++ b/test/MC/Disassembler/X86/x86-64.txt @@ -61,3 +61,21 @@ # CHECK: cmpordsd 0xf2 0x0f 0xc2 0xc7 0x07 + +# CHECK: extrq $2, $3, %xmm0 +0x66 0x0f 0x78 0xc0 0x03 0x02 + +# CHECK: extrq %xmm1, %xmm0 +0x66 0x0f 0x79 0xc1 + +# CHECK: insertq $6, $5, %xmm1, %xmm0 +0xf2 0x0f 0x78 0xc1 0x05 0x06 + +# CHECK: insertq %xmm1, %xmm0 +0xf2 0x0f 0x79 0xc1 + +# CHECK: movntsd %xmm0, (%rdi) +0xf2 0x0f 0x2b 0x07 + +# CHECK: movntss %xmm0, (%rdi) +0xf3 0x0f 0x2b 0x07 |
