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| author | dim <dim@FreeBSD.org> | 2011-10-20 21:10:27 +0000 |
|---|---|---|
| committer | dim <dim@FreeBSD.org> | 2011-10-20 21:10:27 +0000 |
| commit | 7b3392326c40c3c20697816acae597ba7b3144eb (patch) | |
| tree | 2cbcf22585e99f8a87d12d5ff94f392c0d266819 /test/MC/ARM | |
| parent | 1176aa52646fe641a4243a246aa7f960c708a274 (diff) | |
| download | FreeBSD-src-7b3392326c40c3c20697816acae597ba7b3144eb.zip FreeBSD-src-7b3392326c40c3c20697816acae597ba7b3144eb.tar.gz | |
Vendor import of llvm release_30 branch r142614:
http://llvm.org/svn/llvm-project/llvm/branches/release_30@142614
Diffstat (limited to 'test/MC/ARM')
43 files changed, 7802 insertions, 1626 deletions
diff --git a/test/MC/ARM/arm-memory-instructions.s b/test/MC/ARM/arm-memory-instructions.s new file mode 100644 index 0000000..783ac28 --- /dev/null +++ b/test/MC/ARM/arm-memory-instructions.s @@ -0,0 +1,479 @@ +@ RUN: llvm-mc -triple=armv7-apple-darwin -show-encoding < %s | FileCheck %s + .syntax unified + .globl _func + +@ Check that the assembler can handle the documented syntax from the ARM ARM +@ for loads and stores. + +_func: +@ CHECK: _func + +@------------------------------------------------------------------------------ +@ LDR (immediate) +@------------------------------------------------------------------------------ + ldr r5, [r7] + ldr r6, [r3, #63] + ldr r2, [r4, #4095]! + ldr r1, [r2], #30 + ldr r3, [r1], #-30 + +@ CHECK: ldr r5, [r7] @ encoding: [0x00,0x50,0x97,0xe5] +@ CHECK: ldr r6, [r3, #63] @ encoding: [0x3f,0x60,0x93,0xe5] +@ CHECK: ldr r2, [r4, #4095]! @ encoding: [0xff,0x2f,0xb4,0xe5] +@ CHECK: ldr r1, [r2], #30 @ encoding: [0x1e,0x10,0x92,0xe4] +@ CHECK: ldr r3, [r1], #-30 @ encoding: [0x1e,0x30,0x11,0xe4] + +@------------------------------------------------------------------------------ +@ FIXME: LDR (literal) +@------------------------------------------------------------------------------ +@ label operands currently assert the show-encoding asm comment helper due +@ to the use of non-contiguous bit ranges for fixups in ARM. Once that's +@ cleaned up, we can write useful assembly testcases for these sorts of +@ instructions. + +@------------------------------------------------------------------------------ +@ LDR (register) +@------------------------------------------------------------------------------ + ldr r3, [r8, r1] + ldr r2, [r5, -r3] + ldr r1, [r5, r9]! + ldr r6, [r7, -r8]! + ldr r1, [r0, r2, lsr #3]! + ldr r5, [r9], r2 + ldr r4, [r3], -r6 + ldr r3, [r8, -r2, lsl #15] + ldr r1, [r5], r3, asr #15 + +@ CHECK: ldr r3, [r8, r1] @ encoding: [0x01,0x30,0x98,0xe7] +@ CHECK: ldr r2, [r5, -r3] @ encoding: [0x03,0x20,0x15,0xe7] +@ CHECK: ldr r1, [r5, r9]! @ encoding: [0x09,0x10,0xb5,0xe7] +@ CHECK: ldr r6, [r7, -r8]! @ encoding: [0x08,0x60,0x37,0xe7] +@ CHECK: ldr r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xb0,0xe7] +@ CHECK: ldr r5, [r9], r2 @ encoding: [0x02,0x50,0x99,0xe6] +@ CHECK: ldr r4, [r3], -r6 @ encoding: [0x06,0x40,0x13,0xe6] +@ CHECK: ldr r3, [r8, -r2, lsl #15] @ encoding: [0x82,0x37,0x18,0xe7] +@ CHECK: ldr r1, [r5], r3, asr #15 @ encoding: [0xc3,0x17,0x95,0xe6] + + +@------------------------------------------------------------------------------ +@ LDRB (immediate) +@------------------------------------------------------------------------------ + ldrb r3, [r8] + ldrb r1, [sp, #63] + ldrb r9, [r3, #4095]! + ldrb r8, [r1], #22 + ldrb r2, [r7], #-19 + +@ CHECK: ldrb r3, [r8] @ encoding: [0x00,0x30,0xd8,0xe5] +@ CHECK: ldrb r1, [sp, #63] @ encoding: [0x3f,0x10,0xdd,0xe5] +@ CHECK: ldrb r9, [r3, #4095]! @ encoding: [0xff,0x9f,0xf3,0xe5] +@ CHECK: ldrb r8, [r1], #22 @ encoding: [0x16,0x80,0xd1,0xe4] +@ CHECK: ldrb r2, [r7], #-19 @ encoding: [0x13,0x20,0x57,0xe4] + + +@------------------------------------------------------------------------------ +@ LDRB (register) +@------------------------------------------------------------------------------ + ldrb r9, [r8, r5] + ldrb r1, [r5, -r1] + ldrb r3, [r5, r2]! + ldrb r6, [r9, -r3]! + ldrb r2, [r1], r4 + ldrb r8, [r4], -r5 + ldrb r7, [r12, -r1, lsl #15] + ldrb r5, [r2], r9, asr #15 + +@ CHECK: ldrb r9, [r8, r5] @ encoding: [0x05,0x90,0xd8,0xe7] +@ CHECK: ldrb r1, [r5, -r1] @ encoding: [0x01,0x10,0x55,0xe7] +@ CHECK: ldrb r3, [r5, r2]! @ encoding: [0x02,0x30,0xf5,0xe7] +@ CHECK: ldrb r6, [r9, -r3]! @ encoding: [0x03,0x60,0x79,0xe7] +@ CHECK: ldrb r2, [r1], r4 @ encoding: [0x04,0x20,0xd1,0xe6] +@ CHECK: ldrb r8, [r4], -r5 @ encoding: [0x05,0x80,0x54,0xe6] +@ CHECK: ldrb r7, [r12, -r1, lsl #15] @ encoding: [0x81,0x77,0x5c,0xe7] +@ CHECK: ldrb r5, [r2], r9, asr #15 @ encoding: [0xc9,0x57,0xd2,0xe6] + + +@------------------------------------------------------------------------------ +@ LDRBT +@------------------------------------------------------------------------------ +@ FIXME: Optional offset operand. + ldrbt r3, [r1], #4 + ldrbt r2, [r8], #-8 + ldrbt r8, [r7], r6 + ldrbt r1, [r2], -r6, lsl #12 + + +@ CHECK: ldrbt r3, [r1], #4 @ encoding: [0x04,0x30,0xf1,0xe4] +@ CHECK: ldrbt r2, [r8], #-8 @ encoding: [0x08,0x20,0x78,0xe4] +@ CHECK: ldrbt r8, [r7], r6 @ encoding: [0x06,0x80,0xf7,0xe6] +@ CHECK: ldrbt r1, [r2], -r6, lsl #12 @ encoding: [0x06,0x16,0x72,0xe6] + + +@------------------------------------------------------------------------------ +@ LDRD (immediate) +@------------------------------------------------------------------------------ + ldrd r3, r4, [r5] + ldrd r7, r8, [r2, #15] + ldrd r1, r2, [r9, #32]! + ldrd r6, r7, [r1], #8 + ldrd r1, r2, [r8], #0 + ldrd r1, r2, [r8], #+0 + ldrd r1, r2, [r8], #-0 + +@ CHECK: ldrd r3, r4, [r5] @ encoding: [0xd0,0x30,0xc5,0xe1] +@ CHECK: ldrd r7, r8, [r2, #15] @ encoding: [0xdf,0x70,0xc2,0xe1] +@ CHECK: ldrd r1, r2, [r9, #32]! @ encoding: [0xd0,0x12,0xe9,0xe1] +@ CHECK: ldrd r6, r7, [r1], #8 @ encoding: [0xd8,0x60,0xc1,0xe0] +@ CHECK: ldrd r1, r2, [r8], #0 @ encoding: [0xd0,0x10,0xc8,0xe0] +@ CHECK: ldrd r1, r2, [r8], #0 @ encoding: [0xd0,0x10,0xc8,0xe0] +@ CHECK: ldrd r1, r2, [r8], #-0 @ encoding: [0xd0,0x10,0x48,0xe0] + + +@------------------------------------------------------------------------------ +@ FIXME: LDRD (label) +@------------------------------------------------------------------------------ + +@------------------------------------------------------------------------------ +@ LDRD (register) +@------------------------------------------------------------------------------ + ldrd r3, r4, [r1, r3] + ldrd r4, r5, [r7, r2]! + ldrd r1, r2, [r8], r12 + ldrd r1, r2, [r8], -r12 + +@ CHECK: ldrd r3, r4, [r1, r3] @ encoding: [0xd3,0x30,0x81,0xe1] +@ CHECK: ldrd r4, r5, [r7, r2]! @ encoding: [0xd2,0x40,0xa7,0xe1] +@ CHECK: ldrd r1, r2, [r8], r12 @ encoding: [0xdc,0x10,0x88,0xe0] +@ CHECK: ldrd r1, r2, [r8], -r12 @ encoding: [0xdc,0x10,0x08,0xe0] + + +@------------------------------------------------------------------------------ +@ LDRH (immediate) +@------------------------------------------------------------------------------ + ldrh r3, [r4] + ldrh r2, [r7, #4] + ldrh r1, [r8, #64]! + ldrh r12, [sp], #4 + +@ CHECK: ldrh r3, [r4] @ encoding: [0xb0,0x30,0xd4,0xe1] +@ CHECK: ldrh r2, [r7, #4] @ encoding: [0xb4,0x20,0xd7,0xe1] +@ CHECK: ldrh r1, [r8, #64]! @ encoding: [0xb0,0x14,0xf8,0xe1] +@ CHECK: ldrh r12, [sp], #4 @ encoding: [0xb4,0xc0,0xdd,0xe0] + + +@------------------------------------------------------------------------------ +@ FIXME: LDRH (label) +@------------------------------------------------------------------------------ + + +@------------------------------------------------------------------------------ +@ LDRH (register) +@------------------------------------------------------------------------------ + ldrh r6, [r5, r4] + ldrh r3, [r8, r11]! + ldrh r1, [r2, -r1]! + ldrh r9, [r7], r2 + ldrh r4, [r3], -r2 + +@ CHECK: ldrh r6, [r5, r4] @ encoding: [0xb4,0x60,0x95,0xe1] +@ CHECK: ldrh r3, [r8, r11]! @ encoding: [0xbb,0x30,0xb8,0xe1] +@ CHECK: ldrh r1, [r2, -r1]! @ encoding: [0xb1,0x10,0x32,0xe1] +@ CHECK: ldrh r9, [r7], r2 @ encoding: [0xb2,0x90,0x97,0xe0] +@ CHECK: ldrh r4, [r3], -r2 @ encoding: [0xb2,0x40,0x13,0xe0] + + +@------------------------------------------------------------------------------ +@ LDRHT +@------------------------------------------------------------------------------ + ldrht r9, [r7], #128 + ldrht r4, [r3], #-75 + ldrht r9, [r7], r2 + ldrht r4, [r3], -r2 + +@ CHECK: ldrht r9, [r7], #128 @ encoding: [0xb0,0x98,0xf7,0xe0] +@ CHECK: ldrht r4, [r3], #-75 @ encoding: [0xbb,0x44,0x73,0xe0] +@ CHECK: ldrht r9, [r7], r2 @ encoding: [0xb2,0x90,0xb7,0xe0] +@ CHECK: ldrht r4, [r3], -r2 @ encoding: [0xb2,0x40,0x33,0xe0] + + +@------------------------------------------------------------------------------ +@ LDRSB (immediate) +@------------------------------------------------------------------------------ + ldrsb r3, [r4] + ldrsb r2, [r7, #17] + ldrsb r1, [r8, #255]! + ldrsb r12, [sp], #9 + +@ CHECK: ldrsb r3, [r4] @ encoding: [0xd0,0x30,0xd4,0xe1] +@ CHECK: ldrsb r2, [r7, #17] @ encoding: [0xd1,0x21,0xd7,0xe1] +@ CHECK: ldrsb r1, [r8, #255]! @ encoding: [0xdf,0x1f,0xf8,0xe1] +@ CHECK: ldrsb r12, [sp], #9 @ encoding: [0xd9,0xc0,0xdd,0xe0] + + +@------------------------------------------------------------------------------ +@ FIXME: LDRSB (label) +@------------------------------------------------------------------------------ + + +@------------------------------------------------------------------------------ +@ LDRSB (register) +@------------------------------------------------------------------------------ + ldrsb r6, [r5, r4] + ldrsb r3, [r8, r11]! + ldrsb r1, [r2, -r1]! + ldrsb r9, [r7], r2 + ldrsb r4, [r3], -r2 + + +@ CHECK: ldrsb r6, [r5, r4] @ encoding: [0xd4,0x60,0x95,0xe1] +@ CHECK: ldrsb r3, [r8, r11]! @ encoding: [0xdb,0x30,0xb8,0xe1] +@ CHECK: ldrsb r1, [r2, -r1]! @ encoding: [0xd1,0x10,0x32,0xe1] +@ CHECK: ldrsb r9, [r7], r2 @ encoding: [0xd2,0x90,0x97,0xe0] +@ CHECK: ldrsb r4, [r3], -r2 @ encoding: [0xd2,0x40,0x13,0xe0] + + +@------------------------------------------------------------------------------ +@ LDRSBT +@------------------------------------------------------------------------------ + ldrsbt r5, [r6], #1 + ldrsbt r3, [r8], #-12 + ldrsbt r8, [r9], r5 + ldrsbt r2, [r1], -r4 + +@ CHECK: ldrsbt r5, [r6], #1 @ encoding: [0xd1,0x50,0xf6,0xe0] +@ CHECK: ldrsbt r3, [r8], #-12 @ encoding: [0xdc,0x30,0x78,0xe0] +@ CHECK: ldrsbt r8, [r9], r5 @ encoding: [0xd5,0x80,0xb9,0xe0] +@ CHECK: ldrsbt r2, [r1], -r4 @ encoding: [0xd4,0x20,0x31,0xe0] + + +@------------------------------------------------------------------------------ +@ LDRSH (immediate) +@------------------------------------------------------------------------------ + ldrsh r5, [r9] + ldrsh r4, [r5, #7] + ldrsh r3, [r6, #55]! + ldrsh r2, [r7], #-9 + +@ CHECK: ldrsh r5, [r9] @ encoding: [0xf0,0x50,0xd9,0xe1] +@ CHECK: ldrsh r4, [r5, #7] @ encoding: [0xf7,0x40,0xd5,0xe1] +@ CHECK: ldrsh r3, [r6, #55]! @ encoding: [0xf7,0x33,0xf6,0xe1] +@ CHECK: ldrsh r2, [r7], #-9 @ encoding: [0xf9,0x20,0x57,0xe0] + + +@------------------------------------------------------------------------------ +@ FIXME: LDRSH (label) +@------------------------------------------------------------------------------ + + +@------------------------------------------------------------------------------ +@ LDRSH (register) +@------------------------------------------------------------------------------ + ldrsh r3, [r1, r5] + ldrsh r4, [r6, r1]! + ldrsh r5, [r3, -r6]! + ldrsh r6, [r9], r8 + ldrsh r7, [r8], -r3 + +@ CHECK: ldrsh r3, [r1, r5] @ encoding: [0xf5,0x30,0x91,0xe1] +@ CHECK: ldrsh r4, [r6, r1]! @ encoding: [0xf1,0x40,0xb6,0xe1] +@ CHECK: ldrsh r5, [r3, -r6]! @ encoding: [0xf6,0x50,0x33,0xe1] +@ CHECK: ldrsh r6, [r9], r8 @ encoding: [0xf8,0x60,0x99,0xe0] +@ CHECK: ldrsh r7, [r8], -r3 @ encoding: [0xf3,0x70,0x18,0xe0] + + +@------------------------------------------------------------------------------ +@ LDRSHT +@------------------------------------------------------------------------------ + ldrsht r5, [r6], #1 + ldrsht r3, [r8], #-12 + ldrsht r8, [r9], r5 + ldrsht r2, [r1], -r4 + +@ CHECK: ldrsht r5, [r6], #1 @ encoding: [0xf1,0x50,0xf6,0xe0] +@ CHECK: ldrsht r3, [r8], #-12 @ encoding: [0xfc,0x30,0x78,0xe0] +@ CHECK: ldrsht r8, [r9], r5 @ encoding: [0xf5,0x80,0xb9,0xe0] +@ CHECK: ldrsht r2, [r1], -r4 @ encoding: [0xf4,0x20,0x31,0xe0] + + +@------------------------------------------------------------------------------ +@ STR (immediate) +@------------------------------------------------------------------------------ + str r8, [r12] + str r7, [r1, #12] + str r3, [r5, #40]! + str r9, [sp], #4095 + str r1, [r7], #-128 + +@ CHECK: str r8, [r12] @ encoding: [0x00,0x80,0x8c,0xe5] +@ CHECK: str r7, [r1, #12] @ encoding: [0x0c,0x70,0x81,0xe5] +@ CHECK: str r3, [r5, #40]! @ encoding: [0x28,0x30,0xa5,0xe5] +@ CHECK: str r9, [sp], #4095 @ encoding: [0xff,0x9f,0x8d,0xe4] +@ CHECK: str r1, [r7], #-128 @ encoding: [0x80,0x10,0x07,0xe4] + + +@------------------------------------------------------------------------------ +@ FIXME: STR (literal) +@------------------------------------------------------------------------------ + +@------------------------------------------------------------------------------ +@ STR (register) +@------------------------------------------------------------------------------ + str r9, [r6, r3] + str r8, [r0, -r2] + str r7, [r1, r6]! + str r6, [sp, -r1]! + str r5, [r3], r9 + str r4, [r2], -r5 + str r3, [r4, -r2, lsl #2] + str r2, [r7], r3, asr #24 + +@ CHECK: str r9, [r6, r3] @ encoding: [0x03,0x90,0x86,0xe7] +@ CHECK: str r8, [r0, -r2] @ encoding: [0x02,0x80,0x00,0xe7] +@ CHECK: str r7, [r1, r6]! @ encoding: [0x06,0x70,0xa1,0xe7] +@ CHECK: str r6, [sp, -r1]! @ encoding: [0x01,0x60,0x2d,0xe7] +@ CHECK: str r5, [r3], r9 @ encoding: [0x09,0x50,0x83,0xe6] +@ CHECK: str r4, [r2], -r5 @ encoding: [0x05,0x40,0x02,0xe6] +@ CHECK: str r3, [r4, -r2, lsl #2] @ encoding: [0x02,0x31,0x04,0xe7] +@ CHECK: str r2, [r7], r3, asr #24 @ encoding: [0x43,0x2c,0x87,0xe6] + + +@------------------------------------------------------------------------------ +@ STRB (immediate) +@------------------------------------------------------------------------------ + strb r9, [r2] + strb r7, [r1, #3] + strb r6, [r4, #405]! + strb r5, [r7], #72 + strb r1, [sp], #-1 + +@ CHECK: strb r9, [r2] @ encoding: [0x00,0x90,0xc2,0xe5] +@ CHECK: strb r7, [r1, #3] @ encoding: [0x03,0x70,0xc1,0xe5] +@ CHECK: strb r6, [r4, #405]! @ encoding: [0x95,0x61,0xe4,0xe5] +@ CHECK: strb r5, [r7], #72 @ encoding: [0x48,0x50,0xc7,0xe4] +@ CHECK: strb r1, [sp], #-1 @ encoding: [0x01,0x10,0x4d,0xe4] + +@------------------------------------------------------------------------------ +@ FIXME: STRB (literal) +@------------------------------------------------------------------------------ + +@------------------------------------------------------------------------------ +@ STRB (register) +@------------------------------------------------------------------------------ + strb r1, [r2, r9] + strb r2, [r3, -r8] + strb r3, [r4, r7]! + strb r4, [r5, -r6]! + strb r5, [r6], r5 + strb r6, [r2], -r4 + strb r7, [r12, -r3, lsl #5] + strb sp, [r7], r2, asr #12 + +@ CHECK: strb r1, [r2, r9] @ encoding: [0x09,0x10,0xc2,0xe7] +@ CHECK: strb r2, [r3, -r8] @ encoding: [0x08,0x20,0x43,0xe7] +@ CHECK: strb r3, [r4, r7]! @ encoding: [0x07,0x30,0xe4,0xe7] +@ CHECK: strb r4, [r5, -r6]! @ encoding: [0x06,0x40,0x65,0xe7] +@ CHECK: strb r5, [r6], r5 @ encoding: [0x05,0x50,0xc6,0xe6] +@ CHECK: strb r6, [r2], -r4 @ encoding: [0x04,0x60,0x42,0xe6] +@ CHECK: strb r7, [r12, -r3, lsl #5] @ encoding: [0x83,0x72,0x4c,0xe7] +@ CHECK: strb sp, [r7], r2, asr #12 @ encoding: [0x42,0xd6,0xc7,0xe6] + + +@------------------------------------------------------------------------------ +@ STRBT +@------------------------------------------------------------------------------ +@ FIXME: Optional offset operand. + strbt r6, [r2], #12 + strbt r5, [r6], #-13 + strbt r4, [r9], r5 + strbt r3, [r8], -r2, lsl #3 + +@ CHECK: strbt r6, [r2], #12 @ encoding: [0x0c,0x60,0xe2,0xe4] +@ CHECK: strbt r5, [r6], #-13 @ encoding: [0x0d,0x50,0x66,0xe4] +@ CHECK: strbt r4, [r9], r5 @ encoding: [0x05,0x40,0xe9,0xe6] +@ CHECK: strbt r3, [r8], -r2, lsl #3 @ encoding: [0x82,0x31,0x68,0xe6] + + +@------------------------------------------------------------------------------ +@ STRD (immediate) +@------------------------------------------------------------------------------ + strd r1, r2, [r4] + strd r2, r3, [r6, #1] + strd r3, r4, [r7, #22]! + strd r4, r5, [r8], #7 + strd r5, r6, [sp], #0 + strd r6, r7, [lr], #+0 + strd r7, r8, [r9], #-0 + +@ CHECK: strd r1, r2, [r4] @ encoding: [0xf0,0x10,0xc4,0xe1] +@ CHECK: strd r2, r3, [r6, #1] @ encoding: [0xf1,0x20,0xc6,0xe1] +@ CHECK: strd r3, r4, [r7, #22]! @ encoding: [0xf6,0x31,0xe7,0xe1] +@ CHECK: strd r4, r5, [r8], #7 @ encoding: [0xf7,0x40,0xc8,0xe0] +@ CHECK: strd r5, r6, [sp], #0 @ encoding: [0xf0,0x50,0xcd,0xe0] +@ CHECK: strd r6, r7, [lr], #0 @ encoding: [0xf0,0x60,0xce,0xe0] +@ CHECK: strd r7, r8, [r9], #-0 @ encoding: [0xf0,0x70,0x49,0xe0] + + +@------------------------------------------------------------------------------ +@ FIXME: STRD (label) +@------------------------------------------------------------------------------ + +@------------------------------------------------------------------------------ +@ STRD (register) +@------------------------------------------------------------------------------ + strd r8, r9, [r4, r1] + strd r7, r8, [r3, r9]! + strd r6, r7, [r5], r8 + strd r5, r6, [r12], -r10 + +@ CHECK: strd r8, r9, [r4, r1] @ encoding: [0xf1,0x80,0x84,0xe1] +@ CHECK: strd r7, r8, [r3, r9]! @ encoding: [0xf9,0x70,0xa3,0xe1] +@ CHECK: strd r6, r7, [r5], r8 @ encoding: [0xf8,0x60,0x85,0xe0] +@ CHECK: strd r5, r6, [r12], -r10 @ encoding: [0xfa,0x50,0x0c,0xe0] + + +@------------------------------------------------------------------------------ +@ STRH (immediate) +@------------------------------------------------------------------------------ + strh r3, [r4] + strh r2, [r7, #4] + strh r1, [r8, #64]! + strh r12, [sp], #4 + +@ CHECK: strh r3, [r4] @ encoding: [0xb0,0x30,0xc4,0xe1] +@ CHECK: strh r2, [r7, #4] @ encoding: [0xb4,0x20,0xc7,0xe1] +@ CHECK: strh r1, [r8, #64]! @ encoding: [0xb0,0x14,0xe8,0xe1] +@ CHECK: strh r12, [sp], #4 @ encoding: [0xb4,0xc0,0xcd,0xe0] + + +@------------------------------------------------------------------------------ +@ FIXME: STRH (label) +@------------------------------------------------------------------------------ + + +@------------------------------------------------------------------------------ +@ STRH (register) +@------------------------------------------------------------------------------ + strh r6, [r5, r4] + strh r3, [r8, r11]! + strh r1, [r2, -r1]! + strh r9, [r7], r2 + strh r4, [r3], -r2 + +@ CHECK: strh r6, [r5, r4] @ encoding: [0xb4,0x60,0x85,0xe1] +@ CHECK: strh r3, [r8, r11]! @ encoding: [0xbb,0x30,0xa8,0xe1] +@ CHECK: strh r1, [r2, -r1]! @ encoding: [0xb1,0x10,0x22,0xe1] +@ CHECK: strh r9, [r7], r2 @ encoding: [0xb2,0x90,0x87,0xe0] +@ CHECK: strh r4, [r3], -r2 @ encoding: [0xb2,0x40,0x03,0xe0] + +@------------------------------------------------------------------------------ +@ STRHT +@------------------------------------------------------------------------------ + strht r2, [r5], #76 + strht r8, [r1], #-25 + strht r5, [r3], r4 + strht r6, [r8], -r0 + +@ CHECK: strht r2, [r5], #76 @ encoding: [0xbc,0x24,0xe5,0xe0] +@ CHECK: strht r8, [r1], #-25 @ encoding: [0xb9,0x81,0x61,0xe0] +@ CHECK: strht r5, [r3], r4 @ encoding: [0xb4,0x50,0xa3,0xe0] +@ CHECK: strht r6, [r8], -r0 @ encoding: [0xb0,0x60,0x28,0xe0] diff --git a/test/MC/ARM/arm_addrmode3.s b/test/MC/ARM/arm_addrmode3.s index 0b9639e..e1dc020 100644 --- a/test/MC/ARM/arm_addrmode3.s +++ b/test/MC/ARM/arm_addrmode3.s @@ -1,12 +1,12 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s -@ CHECK: ldrsbt r1, [r0], +r2 @ encoding: [0xd2,0x10,0xb0,0xe0] +@ CHECK: ldrsbt r1, [r0], r2 @ encoding: [0xd2,0x10,0xb0,0xe0] @ CHECK: ldrsbt r1, [r0], #4 @ encoding: [0xd4,0x10,0xf0,0xe0] -@ CHECK: ldrsht r1, [r0], +r2 @ encoding: [0xf2,0x10,0xb0,0xe0] +@ CHECK: ldrsht r1, [r0], r2 @ encoding: [0xf2,0x10,0xb0,0xe0] @ CHECK: ldrsht r1, [r0], #4 @ encoding: [0xf4,0x10,0xf0,0xe0] -@ CHECK: ldrht r1, [r0], +r2 @ encoding: [0xb2,0x10,0xb0,0xe0] +@ CHECK: ldrht r1, [r0], r2 @ encoding: [0xb2,0x10,0xb0,0xe0] @ CHECK: ldrht r1, [r0], #4 @ encoding: [0xb4,0x10,0xf0,0xe0] -@ CHECK: strht r1, [r0], +r2 @ encoding: [0xb2,0x10,0xa0,0xe0] +@ CHECK: strht r1, [r0], r2 @ encoding: [0xb2,0x10,0xa0,0xe0] @ CHECK: strht r1, [r0], #4 @ encoding: [0xb4,0x10,0xe0,0xe0] ldrsbt r1, [r0], r2 ldrsbt r1, [r0], #4 diff --git a/test/MC/ARM/arm_fixups.s b/test/MC/ARM/arm_fixups.s index 0dceb83..aba0cd8 100644 --- a/test/MC/ARM/arm_fixups.s +++ b/test/MC/ARM/arm_fixups.s @@ -1,7 +1,17 @@ -// RUN: llvm-mc -triple arm-unknown-unknown %s --show-encoding > %t -// RUN: FileCheck < %t %s +@ RUN: llvm-mc -triple armv7-unknown-unknown %s --show-encoding > %t +@ RUN: FileCheck < %t %s -// CHECK: bl _printf @ encoding: [A,A,A,0xeb] -// CHECK: @ fixup A - offset: 0, value: _printf, kind: fixup_arm_uncondbranch -bl _printf -
\ No newline at end of file + bl _printf +@ CHECK: bl _printf @ encoding: [A,A,A,0xeb] +@ CHECK: @ fixup A - offset: 0, value: _printf, kind: fixup_arm_uncondbranch + + mov r9, :lower16:(_foo) + movw r9, :lower16:(_foo) + movt r9, :upper16:(_foo) + +@ CHECK: movw r9, :lower16:_foo @ encoding: [A,0x90'A',0b0000AAAA,0xe3] +@ CHECK: @ fixup A - offset: 0, value: _foo, kind: fixup_arm_movw_lo16 +@ CHECK: movw r9, :lower16:_foo @ encoding: [A,0x90'A',0b0000AAAA,0xe3] +@ CHECK: @ fixup A - offset: 0, value: _foo, kind: fixup_arm_movw_lo16 +@ CHECK: movt r9, :upper16:_foo @ encoding: [A,0x90'A',0b0100AAAA,0xe3] +@ CHECK: @ fixup A - offset: 0, value: _foo, kind: fixup_arm_movt_hi16 diff --git a/test/MC/ARM/arm_instructions.s b/test/MC/ARM/arm_instructions.s index 650fcd2..186954c 100644 --- a/test/MC/ARM/arm_instructions.s +++ b/test/MC/ARM/arm_instructions.s @@ -1,13 +1,5 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s -@ CHECK: nop -@ CHECK: encoding: [0x00,0xf0,0x20,0xe3] - nop - -@ CHECK: nopeq -@ CHECK: encoding: [0x00,0xf0,0x20,0x03] - nopeq - @ CHECK: trap @ CHECK: encoding: [0xfe,0xde,0xff,0xe7] trap @@ -47,15 +39,6 @@ @ CHECK: adc r1, r2, r3 @ encoding: [0x03,0x10,0xa2,0xe0] adc r1,r2,r3 -@ CHECK: sbc r1, r2, r3 @ encoding: [0x03,0x10,0xc2,0xe0] - sbc r1,r2,r3 - -@ CHECK: orr r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe1] - orr r1,r2,r3 - -@ CHECK: orrs r1, r2, r3 @ encoding: [0x03,0x10,0x92,0xe1] - orrs r1,r2,r3 - @ CHECK: bic r1, r2, r3 @ encoding: [0x03,0x10,0xc2,0xe1] bic r1,r2,r3 @@ -71,135 +54,23 @@ @ CHECK: mvns r1, r2 @ encoding: [0x02,0x10,0xf0,0xe1] mvns r1,r2 -@ CHECK: rsb r1, r2, r3 @ encoding: [0x03,0x10,0x62,0xe0] - rsb r1,r2,r3 - -@ CHECK: rsc r1, r2, r3 @ encoding: [0x03,0x10,0xe2,0xe0] - rsc r1,r2,r3 - @ CHECK: bfi r0, r0, #5, #7 @ encoding: [0x90,0x02,0xcb,0xe7] bfi r0, r0, #5, #7 @ CHECK: bkpt #10 @ encoding: [0x7a,0x00,0x20,0xe1] bkpt #10 -@ CHECK: mrs r8, cpsr @ encoding: [0x00,0x80,0x0f,0xe1] - mrs r8, cpsr - -@ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xee] - mrc p14, #0, r1, c1, c2, #4 -@ CHECK: mrrc p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xec] - mrrc p7, #1, r5, r4, c1 - -@ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xfe] - mrc2 p14, #0, r1, c1, c2, #4 -@ CHECK: mrrc2 p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xfc] - mrrc2 p7, #1, r5, r4, c1 - @ CHECK: cdp p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xee] cdp p7, #1, c1, c1, c1, #4 @ CHECK: cdp2 p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xfe] cdp2 p7, #1, c1, c1, c1, #4 -@ CHECK: qadd r1, r2, r3 @ encoding: [0x52,0x10,0x03,0xe1] - qadd r1, r2, r3 - -@ CHECK: qsub r1, r2, r3 @ encoding: [0x52,0x10,0x23,0xe1] - qsub r1, r2, r3 - -@ CHECK: qdadd r1, r2, r3 @ encoding: [0x52,0x10,0x43,0xe1] - qdadd r1, r2, r3 - -@ CHECK: qdsub r1, r2, r3 @ encoding: [0x52,0x10,0x63,0xe1] - qdsub r1, r2, r3 - -@ CHECK: wfe @ encoding: [0x02,0xf0,0x20,0xe3] - wfe - -@ CHECK: wfi @ encoding: [0x03,0xf0,0x20,0xe3] - wfi - -@ CHECK: yield @ encoding: [0x01,0xf0,0x20,0xe3] - yield - -@ CHECK: nop @ encoding: [0x00,0xf0,0x20,0xe3] - nop - -@ CHECK: cpsie aif @ encoding: [0xc0,0x01,0x08,0xf1] - cpsie aif - -@ CHECK: cps #15 @ encoding: [0x0f,0x00,0x02,0xf1] - cps #15 - -@ CHECK: cpsie if, #10 @ encoding: [0xca,0x00,0x0a,0xf1] - cpsie if, #10 - -@ CHECK: msr cpsr_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] - msr apsr, r0 - -@ CHECK: msr cpsr_s, r0 @ encoding: [0x00,0xf0,0x24,0xe1] - msr apsr_g, r0 - -@ CHECK: msr cpsr_f, r0 @ encoding: [0x00,0xf0,0x28,0xe1] - msr apsr_nzcvq, r0 - -@ CHECK: msr cpsr_fs, r0 @ encoding: [0x00,0xf0,0x2c,0xe1] - msr apsr_nzcvqg, r0 - -@ CHECK: msr cpsr_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] - msr cpsr_fc, r0 - -@ CHECK: msr cpsr_c, r0 @ encoding: [0x00,0xf0,0x21,0xe1] - msr cpsr_c, r0 - -@ CHECK: msr cpsr_x, r0 @ encoding: [0x00,0xf0,0x22,0xe1] - msr cpsr_x, r0 - -@ CHECK: msr cpsr_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] - msr cpsr_fc, r0 - -@ CHECK: msr cpsr_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] - msr cpsr_all, r0 - -@ CHECK: msr cpsr_fsx, r0 @ encoding: [0x00,0xf0,0x2e,0xe1] - msr cpsr_fsx, r0 - -@ CHECK: msr spsr_fc, r0 @ encoding: [0x00,0xf0,0x69,0xe1] - msr spsr_fc, r0 - -@ CHECK: msr spsr_fsxc, r0 @ encoding: [0x00,0xf0,0x6f,0xe1] - msr spsr_fsxc, r0 - -@ CHECK: msr cpsr_fsxc, r0 @ encoding: [0x00,0xf0,0x2f,0xe1] - msr cpsr_fsxc, r0 - @ CHECK: add r1, r2, r3, lsl r4 @ encoding: [0x13,0x14,0x82,0xe0] add r1, r2, r3, lsl r4 -@ CHECK: strexb r0, r1, [r2] @ encoding: [0x91,0x0f,0xc2,0xe1] - strexb r0, r1, [r2] - -@ CHECK: strexh r0, r1, [r2] @ encoding: [0x91,0x0f,0xe2,0xe1] - strexh r0, r1, [r2] - -@ CHECK: strex r0, r1, [r2] @ encoding: [0x91,0x0f,0x82,0xe1] - strex r0, r1, [r2] - -@ CHECK: strexd r0, r2, r3, [r1] @ encoding: [0x92,0x0f,0xa1,0xe1] - strexd r0, r2, r3, [r1] - -@ CHECK: ldrexb r0, [r0] @ encoding: [0x9f,0x0f,0xd0,0xe1] - ldrexb r0, [r0] - -@ CHECK: ldrexh r0, [r0] @ encoding: [0x9f,0x0f,0xf0,0xe1] - ldrexh r0, [r0] - -@ CHECK: ldrex r0, [r0] @ encoding: [0x9f,0x0f,0x90,0xe1] - ldrex r0, [r0] - -@ CHECK: ldrexd r0, r1, [r0] @ encoding: [0x9f,0x0f,0xb0,0xe1] - ldrexd r0, r1, [r0] - @ CHECK: ssat16 r0, #7, r0 @ encoding: [0x30,0x0f,0xa6,0xe6] ssat16 r0, #7, r0 +@ CHECK: cpsie none, #0 @ encoding: [0x00,0x00,0x0a,0xf1] + cpsie none, #0 + diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s index 0b728bc..55d9f02 100644 --- a/test/MC/ARM/basic-arm-instructions.s +++ b/test/MC/ARM/basic-arm-instructions.s @@ -14,18 +14,18 @@ _func: @------------------------------------------------------------------------------ @ ADC (immediate) @------------------------------------------------------------------------------ - adc r1, r2, #0xf - adc r1, r2, #0xf0 - adc r1, r2, #0xf00 - adc r1, r2, #0xf000 - adc r1, r2, #0xf0000 - adc r1, r2, #0xf00000 - adc r1, r2, #0xf000000 - adc r1, r2, #0xf0000000 - adc r1, r2, #0xf000000f - adcs r1, r2, #0xf00 - adcseq r1, r2, #0xf00 - adceq r1, r2, #0xf00 + adc r1, r2, #0xf + adc r1, r2, #0xf0 + adc r1, r2, #0xf00 + adc r1, r2, #0xf000 + adc r1, r2, #0xf0000 + adc r1, r2, #0xf00000 + adc r1, r2, #0xf000000 + adc r1, r2, #0xf0000000 + adc r1, r2, #0xf000000f + adcs r1, r2, #0xf00 + adcseq r1, r2, #0xf00 + adceq r1, r2, #0xf00 @ CHECK: adc r1, r2, #15 @ encoding: [0x0f,0x10,0xa2,0xe2] @ CHECK: adc r1, r2, #240 @ encoding: [0xf0,0x10,0xa2,0xe2] @@ -45,44 +45,44 @@ _func: @ ADC (register) @ ADC (shifted register) @------------------------------------------------------------------------------ - adc r4, r5, r6 - @ Constant shifts - adc r4, r5, r6, lsl #1 - adc r4, r5, r6, lsl #31 - adc r4, r5, r6, lsr #1 - adc r4, r5, r6, lsr #31 - adc r4, r5, r6, lsr #32 - adc r4, r5, r6, asr #1 - adc r4, r5, r6, asr #31 - adc r4, r5, r6, asr #32 - adc r4, r5, r6, ror #1 - adc r4, r5, r6, ror #31 - - @ Register shifts - adc r6, r7, r8, lsl r9 - adc r6, r7, r8, lsr r9 - adc r6, r7, r8, asr r9 - adc r6, r7, r8, ror r9 - adc r4, r5, r6, rrx - - @ Destination register is optional - adc r5, r6 - adc r4, r5, lsl #1 - adc r4, r5, lsl #31 - adc r4, r5, lsr #1 - adc r4, r5, lsr #31 - adc r4, r5, lsr #32 - adc r4, r5, asr #1 - adc r4, r5, asr #31 - adc r4, r5, asr #32 - adc r4, r5, ror #1 - adc r4, r5, ror #31 - adc r4, r5, rrx - adc r6, r7, lsl r9 - adc r6, r7, lsr r9 - adc r6, r7, asr r9 - adc r6, r7, ror r9 - adc r4, r5, rrx + adc r4, r5, r6 + @ Constant shifts + adc r4, r5, r6, lsl #1 + adc r4, r5, r6, lsl #31 + adc r4, r5, r6, lsr #1 + adc r4, r5, r6, lsr #31 + adc r4, r5, r6, lsr #32 + adc r4, r5, r6, asr #1 + adc r4, r5, r6, asr #31 + adc r4, r5, r6, asr #32 + adc r4, r5, r6, ror #1 + adc r4, r5, r6, ror #31 + + @ Register shifts + adc r6, r7, r8, lsl r9 + adc r6, r7, r8, lsr r9 + adc r6, r7, r8, asr r9 + adc r6, r7, r8, ror r9 + adc r4, r5, r6, rrx + + @ Destination register is optional + adc r5, r6 + adc r4, r5, lsl #1 + adc r4, r5, lsl #31 + adc r4, r5, lsr #1 + adc r4, r5, lsr #31 + adc r4, r5, lsr #32 + adc r4, r5, asr #1 + adc r4, r5, asr #31 + adc r4, r5, asr #32 + adc r4, r5, ror #1 + adc r4, r5, ror #31 + adc r4, r5, rrx + adc r6, r7, lsl r9 + adc r6, r7, lsr r9 + adc r6, r7, asr r9 + adc r6, r7, ror r9 + adc r4, r5, rrx @ CHECK: adc r4, r5, r6 @ encoding: [0x06,0x40,0xa5,0xe0] @@ -123,38 +123,54 @@ _func: @------------------------------------------------------------------------------ -@ FIXME: ADR +@ ADR @------------------------------------------------------------------------------ +Lback: + adr r2, Lback + adr r3, Lforward +Lforward: + adr r2, #3 + adr r2, #-3 + +@ CHECK: Lback: +@ CHECK: adr r2, Lback @ encoding: [0bAAAAAAA0,0x20'A',0x0f'A',0b1110001A] +@ CHECK: @ fixup A - offset: 0, value: Lback, kind: fixup_arm_adr_pcrel_12 +@ CHECK: adr r3, Lforward @ encoding: [0bAAAAAAA0,0x30'A',0x0f'A',0b1110001A] +@ CHECK: @ fixup A - offset: 0, value: Lforward, kind: fixup_arm_adr_pcrel_12 +@ CHECK: Lforward: +@ CHECK: adr r2, #3 @ encoding: [0x03,0x20,0x8f,0xe2] +@ CHECK: adr r2, #-3 @ encoding: [0x03,0x20,0x4f,0xe2] + @------------------------------------------------------------------------------ @ ADD @------------------------------------------------------------------------------ - add r4, r5, #0xf000 - add r4, r5, r6 - add r4, r5, r6, lsl #5 - add r4, r5, r6, lsr #5 - add r4, r5, r6, lsr #5 - add r4, r5, r6, asr #5 - add r4, r5, r6, ror #5 - add r6, r7, r8, lsl r9 - add r6, r7, r8, lsr r9 - add r6, r7, r8, asr r9 - add r6, r7, r8, ror r9 - add r4, r5, r6, rrx - - @ destination register is optional - add r5, #0xf000 - add r4, r5 - add r4, r5, lsl #5 - add r4, r5, lsr #5 - add r4, r5, lsr #5 - add r4, r5, asr #5 - add r4, r5, ror #5 - add r6, r7, lsl r9 - add r6, r7, lsr r9 - add r6, r7, asr r9 - add r6, r7, ror r9 - add r4, r5, rrx + add r4, r5, #0xf000 + add r4, r5, r6 + add r4, r5, r6, lsl #5 + add r4, r5, r6, lsr #5 + add r4, r5, r6, lsr #5 + add r4, r5, r6, asr #5 + add r4, r5, r6, ror #5 + add r6, r7, r8, lsl r9 + add r6, r7, r8, lsr r9 + add r6, r7, r8, asr r9 + add r6, r7, r8, ror r9 + add r4, r5, r6, rrx + + @ destination register is optional + add r5, #0xf000 + add r4, r5 + add r4, r5, lsl #5 + add r4, r5, lsr #5 + add r4, r5, lsr #5 + add r4, r5, asr #5 + add r4, r5, ror #5 + add r6, r7, lsl r9 + add r6, r7, lsr r9 + add r6, r7, asr r9 + add r6, r7, ror r9 + add r4, r5, rrx @ CHECK: add r4, r5, #61440 @ encoding: [0x0f,0x4a,0x85,0xe2] @ CHECK: add r4, r5, r6 @ encoding: [0x06,0x40,0x85,0xe0] @@ -187,32 +203,32 @@ _func: @------------------------------------------------------------------------------ @ AND @------------------------------------------------------------------------------ - and r10, r1, #0xf - and r10, r1, r6 - and r10, r1, r6, lsl #10 - and r10, r1, r6, lsr #10 - and r10, r1, r6, lsr #10 - and r10, r1, r6, asr #10 - and r10, r1, r6, ror #10 - and r6, r7, r8, lsl r2 - and r6, r7, r8, lsr r2 - and r6, r7, r8, asr r2 - and r6, r7, r8, ror r2 - and r10, r1, r6, rrx - - @ destination register is optional - and r1, #0xf - and r10, r1 - and r10, r1, lsl #10 - and r10, r1, lsr #10 - and r10, r1, lsr #10 - and r10, r1, asr #10 - and r10, r1, ror #10 - and r6, r7, lsl r2 - and r6, r7, lsr r2 - and r6, r7, asr r2 - and r6, r7, ror r2 - and r10, r1, rrx + and r10, r1, #0xf + and r10, r1, r6 + and r10, r1, r6, lsl #10 + and r10, r1, r6, lsr #10 + and r10, r1, r6, lsr #10 + and r10, r1, r6, asr #10 + and r10, r1, r6, ror #10 + and r6, r7, r8, lsl r2 + and r6, r7, r8, lsr r2 + and r6, r7, r8, asr r2 + and r6, r7, r8, ror r2 + and r10, r1, r6, rrx + + @ destination register is optional + and r1, #0xf + and r10, r1 + and r10, r1, lsl #10 + and r10, r1, lsr #10 + and r10, r1, lsr #10 + and r10, r1, asr #10 + and r10, r1, ror #10 + and r6, r7, lsl r2 + and r6, r7, lsr r2 + and r6, r7, asr r2 + and r6, r7, ror r2 + and r10, r1, rrx @ CHECK: and r10, r1, #15 @ encoding: [0x0f,0xa0,0x01,0xe2] @ CHECK: and r10, r1, r6 @ encoding: [0x06,0xa0,0x01,0xe0] @@ -244,44 +260,66 @@ _func: @ FIXME: ASR @------------------------------------------------------------------------------ @------------------------------------------------------------------------------ -@ FIXME: B +@ B @------------------------------------------------------------------------------ + b _bar + beq _baz + +@ CHECK: b _bar @ encoding: [A,A,A,0xea] + @ fixup A - offset: 0, value: _bar, kind: fixup_arm_uncondbranch +@ CHECK: beq _baz @ encoding: [A,A,A,0x0a] + @ fixup A - offset: 0, value: _baz, kind: fixup_arm_condbranch + + @------------------------------------------------------------------------------ -@ FIXME: BFC +@ BFC @------------------------------------------------------------------------------ + bfc r5, #3, #17 + bfccc r5, #3, #17 + +@ CHECK: bfc r5, #3, #17 @ encoding: [0x9f,0x51,0xd3,0xe7] +@ CHECK: bfclo r5, #3, #17 @ encoding: [0x9f,0x51,0xd3,0x37] + + @------------------------------------------------------------------------------ -@ FIXME: BFI +@ BFI @------------------------------------------------------------------------------ + bfi r5, r2, #3, #17 + bfine r5, r2, #3, #17 + +@ CHECK: bfi r5, r2, #3, #17 @ encoding: [0x92,0x51,0xd3,0xe7] +@ CHECK: bfine r5, r2, #3, #17 @ encoding: [0x92,0x51,0xd3,0x17] + @------------------------------------------------------------------------------ @ BIC @------------------------------------------------------------------------------ - bic r10, r1, #0xf - bic r10, r1, r6 - bic r10, r1, r6, lsl #10 - bic r10, r1, r6, lsr #10 - bic r10, r1, r6, lsr #10 - bic r10, r1, r6, asr #10 - bic r10, r1, r6, ror #10 - bic r6, r7, r8, lsl r2 - bic r6, r7, r8, lsr r2 - bic r6, r7, r8, asr r2 - bic r6, r7, r8, ror r2 - bic r10, r1, r6, rrx - - @ destination register is optional - bic r1, #0xf - bic r10, r1 - bic r10, r1, lsl #10 - bic r10, r1, lsr #10 - bic r10, r1, lsr #10 - bic r10, r1, asr #10 - bic r10, r1, ror #10 - bic r6, r7, lsl r2 - bic r6, r7, lsr r2 - bic r6, r7, asr r2 - bic r6, r7, ror r2 - bic r10, r1, rrx + bic r10, r1, #0xf + bic r10, r1, r6 + bic r10, r1, r6, lsl #10 + bic r10, r1, r6, lsr #10 + bic r10, r1, r6, lsr #10 + bic r10, r1, r6, asr #10 + bic r10, r1, r6, ror #10 + bic r6, r7, r8, lsl r2 + bic r6, r7, r8, lsr r2 + bic r6, r7, r8, asr r2 + bic r6, r7, r8, ror r2 + bic r10, r1, r6, rrx + + @ destination register is optional + bic r1, #0xf + bic r10, r1 + bic r10, r1, lsl #10 + bic r10, r1, lsr #10 + bic r10, r1, lsr #10 + bic r10, r1, asr #10 + bic r10, r1, ror #10 + bic r6, r7, lsl r2 + bic r6, r7, lsr r2 + bic r6, r7, asr r2 + bic r6, r7, ror r2 + bic r10, r1, rrx @ CHECK: bic r10, r1, #15 @ encoding: [0x0f,0xa0,0xc1,0xe3] @ CHECK: bic r10, r1, r6 @ encoding: [0x06,0xa0,0xc1,0xe1] @@ -313,8 +351,8 @@ _func: @------------------------------------------------------------------------------ @ BKPT @------------------------------------------------------------------------------ - bkpt #10 - bkpt #65535 + bkpt #10 + bkpt #65535 @ CHECK: bkpt #10 @ encoding: [0x7a,0x00,0x20,0xe1] @ CHECK: bkpt #65535 @ encoding: [0x7f,0xff,0x2f,0xe1] @@ -323,17 +361,24 @@ _func: @ BL/BLX (immediate) @------------------------------------------------------------------------------ - bl _bar - @ FIXME: blx _bar + bl _bar + blx _bar + blls #28634268 + blx #32424576 + blx #16212288 @ CHECK: bl _bar @ encoding: [A,A,A,0xeb] @ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_uncondbranch - +@ CHECK: blx _bar @ encoding: [A,A,A,0xfa] + @ fixup A - offset: 0, value: _bar, kind: fixup_arm_uncondbranch +@ CHECK: blls #28634268 @ encoding: [0x27,0x3b,0x6d,0x9b] +@ CHECK: blx #32424576 @ encoding: [0xa0,0xb0,0x7b,0xfa] +@ CHECK: blx #16212288 @ encoding: [0x50,0xd8,0x3d,0xfa] @------------------------------------------------------------------------------ @ BLX (register) @------------------------------------------------------------------------------ - blx r2 - blxne r2 + blx r2 + blxne r2 @ CHECK: blx r2 @ encoding: [0x32,0xff,0x2f,0xe1] @ CHECK: blxne r2 @ encoding: [0x32,0xff,0x2f,0x11] @@ -341,9 +386,8 @@ _func: @------------------------------------------------------------------------------ @ BX @------------------------------------------------------------------------------ - - bx r2 - bxne r2 + bx r2 + bxne r2 @ CHECK: bx r2 @ encoding: [0x12,0xff,0x2f,0xe1] @ CHECK: bxne r2 @ encoding: [0x12,0xff,0x2f,0x11] @@ -351,23 +395,18 @@ _func: @------------------------------------------------------------------------------ @ BXJ @------------------------------------------------------------------------------ - - bxj r2 - bxjne r2 + bxj r2 + bxjne r2 @ CHECK: bxj r2 @ encoding: [0x22,0xff,0x2f,0xe1] @ CHECK: bxjne r2 @ encoding: [0x22,0xff,0x2f,0x11] -@------------------------------------------------------------------------------ -@ FIXME: CBNZ/CBZ -@------------------------------------------------------------------------------ - @------------------------------------------------------------------------------ @ CDP/CDP2 @------------------------------------------------------------------------------ - cdp p7, #1, c1, c1, c1, #4 - cdp2 p7, #1, c1, c1, c1, #4 + cdp p7, #1, c1, c1, c1, #4 + cdp2 p7, #1, c1, c1, c1, #4 @ CHECK: cdp p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xee] @ CHECK: cdp2 p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xfe] @@ -376,7 +415,7 @@ _func: @------------------------------------------------------------------------------ @ CLREX @------------------------------------------------------------------------------ - clrex + clrex @ CHECK: clrex @ encoding: [0x1f,0xf0,0x7f,0xf5] @@ -384,8 +423,8 @@ _func: @------------------------------------------------------------------------------ @ CLZ @------------------------------------------------------------------------------ - clz r1, r2 - clzeq r1, r2 + clz r1, r2 + clzeq r1, r2 @ CHECK: clz r1, r2 @ encoding: [0x12,0x1f,0x6f,0xe1] @ CHECK: clzeq r1, r2 @ encoding: [0x12,0x1f,0x6f,0x01] @@ -393,18 +432,18 @@ _func: @------------------------------------------------------------------------------ @ CMN @------------------------------------------------------------------------------ - cmn r1, #0xf - cmn r1, r6 - cmn r1, r6, lsl #10 - cmn r1, r6, lsr #10 - cmn sp, r6, lsr #10 - cmn r1, r6, asr #10 - cmn r1, r6, ror #10 - cmn r7, r8, lsl r2 - cmn sp, r8, lsr r2 - cmn r7, r8, asr r2 - cmn r7, r8, ror r2 - cmn r1, r6, rrx + cmn r1, #0xf + cmn r1, r6 + cmn r1, r6, lsl #10 + cmn r1, r6, lsr #10 + cmn sp, r6, lsr #10 + cmn r1, r6, asr #10 + cmn r1, r6, ror #10 + cmn r7, r8, lsl r2 + cmn sp, r8, lsr r2 + cmn r7, r8, asr r2 + cmn r7, r8, ror r2 + cmn r1, r6, rrx @ CHECK: cmn r1, #15 @ encoding: [0x0f,0x00,0x71,0xe3] @ CHECK: cmn r1, r6 @ encoding: [0x06,0x00,0x71,0xe1] @@ -422,18 +461,18 @@ _func: @------------------------------------------------------------------------------ @ CMP @------------------------------------------------------------------------------ - cmp r1, #0xf - cmp r1, r6 - cmp r1, r6, lsl #10 - cmp r1, r6, lsr #10 - cmp sp, r6, lsr #10 - cmp r1, r6, asr #10 - cmp r1, r6, ror #10 - cmp r7, r8, lsl r2 - cmp sp, r8, lsr r2 - cmp r7, r8, asr r2 - cmp r7, r8, ror r2 - cmp r1, r6, rrx + cmp r1, #0xf + cmp r1, r6 + cmp r1, r6, lsl #10 + cmp r1, r6, lsr #10 + cmp sp, r6, lsr #10 + cmp r1, r6, asr #10 + cmp r1, r6, ror #10 + cmp r7, r8, lsl r2 + cmp sp, r8, lsr r2 + cmp r7, r8, asr r2 + cmp r7, r8, ror r2 + cmp r1, r6, rrx @ CHECK: cmp r1, #15 @ encoding: [0x0f,0x00,0x51,0xe3] @ CHECK: cmp r1, r6 @ encoding: [0x06,0x00,0x51,0xe1] @@ -448,12 +487,25 @@ _func: @ CHECK: cmp r7, r8, ror r2 @ encoding: [0x78,0x02,0x57,0xe1] @ CHECK: cmp r1, r6, rrx @ encoding: [0x66,0x00,0x51,0xe1] + +@------------------------------------------------------------------------------ +@ CPS +@------------------------------------------------------------------------------ + cpsie aif + cps #15 + cpsid if, #10 + +@ CHECK: cpsie aif @ encoding: [0xc0,0x01,0x08,0xf1] +@ CHECK: cps #15 @ encoding: [0x0f,0x00,0x02,0xf1] +@ CHECK: cpsid if, #10 @ encoding: [0xca,0x00,0x0e,0xf1] + + @------------------------------------------------------------------------------ @ DBG @------------------------------------------------------------------------------ - dbg #0 - dbg #5 - dbg #15 + dbg #0 + dbg #5 + dbg #15 @ CHECK: dbg #0 @ encoding: [0xf0,0xf0,0x20,0xe3] @ CHECK: dbg #5 @ encoding: [0xf5,0xf0,0x20,0xe3] @@ -463,19 +515,19 @@ _func: @------------------------------------------------------------------------------ @ DMB @------------------------------------------------------------------------------ - dmb sy - dmb st - dmb sh - dmb ish - dmb shst - dmb ishst - dmb un - dmb nsh - dmb unst - dmb nshst - dmb osh - dmb oshst - dmb + dmb sy + dmb st + dmb sh + dmb ish + dmb shst + dmb ishst + dmb un + dmb nsh + dmb unst + dmb nshst + dmb osh + dmb oshst + dmb @ CHECK: dmb sy @ encoding: [0x5f,0xf0,0x7f,0xf5] @ CHECK: dmb st @ encoding: [0x5e,0xf0,0x7f,0xf5] @@ -494,19 +546,19 @@ _func: @------------------------------------------------------------------------------ @ DSB @------------------------------------------------------------------------------ - dsb sy - dsb st - dsb sh - dsb ish - dsb shst - dsb ishst - dsb un - dsb nsh - dsb unst - dsb nshst - dsb osh - dsb oshst - dsb + dsb sy + dsb st + dsb sh + dsb ish + dsb shst + dsb ishst + dsb un + dsb nsh + dsb unst + dsb nshst + dsb osh + dsb oshst + dsb @ CHECK: dsb sy @ encoding: [0x4f,0xf0,0x7f,0xf5] @ CHECK: dsb st @ encoding: [0x4e,0xf0,0x7f,0xf5] @@ -525,32 +577,32 @@ _func: @------------------------------------------------------------------------------ @ EOR @------------------------------------------------------------------------------ - eor r4, r5, #0xf000 - eor r4, r5, r6 - eor r4, r5, r6, lsl #5 - eor r4, r5, r6, lsr #5 - eor r4, r5, r6, lsr #5 - eor r4, r5, r6, asr #5 - eor r4, r5, r6, ror #5 - eor r6, r7, r8, lsl r9 - eor r6, r7, r8, lsr r9 - eor r6, r7, r8, asr r9 - eor r6, r7, r8, ror r9 - eor r4, r5, r6, rrx - - @ destination register is optional - eor r5, #0xf000 - eor r4, r5 - eor r4, r5, lsl #5 - eor r4, r5, lsr #5 - eor r4, r5, lsr #5 - eor r4, r5, asr #5 - eor r4, r5, ror #5 - eor r6, r7, lsl r9 - eor r6, r7, lsr r9 - eor r6, r7, asr r9 - eor r6, r7, ror r9 - eor r4, r5, rrx + eor r4, r5, #0xf000 + eor r4, r5, r6 + eor r4, r5, r6, lsl #5 + eor r4, r5, r6, lsr #5 + eor r4, r5, r6, lsr #5 + eor r4, r5, r6, asr #5 + eor r4, r5, r6, ror #5 + eor r6, r7, r8, lsl r9 + eor r6, r7, r8, lsr r9 + eor r6, r7, r8, asr r9 + eor r6, r7, r8, ror r9 + eor r4, r5, r6, rrx + + @ destination register is optional + eor r5, #0xf000 + eor r4, r5 + eor r4, r5, lsl #5 + eor r4, r5, lsr #5 + eor r4, r5, lsr #5 + eor r4, r5, asr #5 + eor r4, r5, ror #5 + eor r6, r7, lsl r9 + eor r6, r7, lsr r9 + eor r6, r7, asr r9 + eor r6, r7, ror r9 + eor r4, r5, rrx @ CHECK: eor r4, r5, #61440 @ encoding: [0x0f,0x4a,0x25,0xe2] @ CHECK: eor r4, r5, r6 @ encoding: [0x06,0x40,0x25,0xe0] @@ -590,6 +642,91 @@ _func: @ CHECK: isb sy @ encoding: [0x6f,0xf0,0x7f,0xf5] +@------------------------------------------------------------------------------ +@ LDC{L}/LDC2{L} +@------------------------------------------------------------------------------ + ldc2 p0, c8, [r1, #4] + ldc2 p1, c7, [r2] + ldc2 p2, c6, [r3, #-224] + ldc2 p3, c5, [r4, #-120]! + ldc2 p4, c4, [r5], #16 + ldc2 p5, c3, [r6], #-72 + ldc2l p6, c2, [r7, #4] + ldc2l p7, c1, [r8] + ldc2l p8, c0, [r9, #-224] + ldc2l p9, c1, [r10, #-120]! + ldc2l p10, c2, [r11], #16 + ldc2l p11, c3, [r12], #-72 + + ldc p12, c4, [r0, #4] + ldc p13, c5, [r1] + ldc p14, c6, [r2, #-224] + ldc p15, c7, [r3, #-120]! + ldc p5, c8, [r4], #16 + ldc p4, c9, [r5], #-72 + ldcl p3, c10, [r6, #4] + ldcl p2, c11, [r7] + ldcl p1, c12, [r8, #-224] + ldcl p0, c13, [r9, #-120]! + ldcl p6, c14, [r10], #16 + ldcl p7, c15, [r11], #-72 + + ldclo p12, c4, [r0, #4] + ldchi p13, c5, [r1] + ldccs p14, c6, [r2, #-224] + ldccc p15, c7, [r3, #-120]! + ldceq p5, c8, [r4], #16 + ldcgt p4, c9, [r5], #-72 + ldcllt p3, c10, [r6, #4] + ldclge p2, c11, [r7] + ldclle p1, c12, [r8, #-224] + ldclne p0, c13, [r9, #-120]! + ldcleq p6, c14, [r10], #16 + ldclhi p7, c15, [r11], #-72 + + ldc2 p2, c8, [r1], { 25 } + +@ CHECK: ldc2 p0, c8, [r1, #4] @ encoding: [0x01,0x80,0x91,0xfd] +@ CHECK: ldc2 p1, c7, [r2] @ encoding: [0x00,0x71,0x92,0xfd] +@ CHECK: ldc2 p2, c6, [r3, #-224] @ encoding: [0x38,0x62,0x13,0xfd] +@ CHECK: ldc2 p3, c5, [r4, #-120]! @ encoding: [0x1e,0x53,0x34,0xfd] +@ CHECK: ldc2 p4, c4, [r5], #16 @ encoding: [0x04,0x44,0xb5,0xfc] +@ CHECK: ldc2 p5, c3, [r6], #-72 @ encoding: [0x12,0x35,0x36,0xfc] +@ CHECK: ldc2l p6, c2, [r7, #4] @ encoding: [0x01,0x26,0xd7,0xfd] +@ CHECK: ldc2l p7, c1, [r8] @ encoding: [0x00,0x17,0xd8,0xfd] +@ CHECK: ldc2l p8, c0, [r9, #-224] @ encoding: [0x38,0x08,0x59,0xfd] +@ CHECK: ldc2l p9, c1, [r10, #-120]! @ encoding: [0x1e,0x19,0x7a,0xfd] +@ CHECK: ldc2l p10, c2, [r11], #16 @ encoding: [0x04,0x2a,0xfb,0xfc] +@ CHECK: ldc2l p11, c3, [r12], #-72 @ encoding: [0x12,0x3b,0x7c,0xfc] + +@ CHECK: ldc p12, c4, [r0, #4] @ encoding: [0x01,0x4c,0x90,0xed] +@ CHECK: ldc p13, c5, [r1] @ encoding: [0x00,0x5d,0x91,0xed] +@ CHECK: ldc p14, c6, [r2, #-224] @ encoding: [0x38,0x6e,0x12,0xed] +@ CHECK: ldc p15, c7, [r3, #-120]! @ encoding: [0x1e,0x7f,0x33,0xed] +@ CHECK: ldc p5, c8, [r4], #16 @ encoding: [0x04,0x85,0xb4,0xec] +@ CHECK: ldc p4, c9, [r5], #-72 @ encoding: [0x12,0x94,0x35,0xec] +@ CHECK: ldcl p3, c10, [r6, #4] @ encoding: [0x01,0xa3,0xd6,0xed] +@ CHECK: ldcl p2, c11, [r7] @ encoding: [0x00,0xb2,0xd7,0xed] +@ CHECK: ldcl p1, c12, [r8, #-224] @ encoding: [0x38,0xc1,0x58,0xed] +@ CHECK: ldcl p0, c13, [r9, #-120]! @ encoding: [0x1e,0xd0,0x79,0xed] +@ CHECK: ldcl p6, c14, [r10], #16 @ encoding: [0x04,0xe6,0xfa,0xec] +@ CHECK: ldcl p7, c15, [r11], #-72 @ encoding: [0x12,0xf7,0x7b,0xec] + +@ CHECK: ldclo p12, c4, [r0, #4] @ encoding: [0x01,0x4c,0x90,0x3d] +@ CHECK: ldchi p13, c5, [r1] @ encoding: [0x00,0x5d,0x91,0x8d] +@ CHECK: ldchs p14, c6, [r2, #-224] @ encoding: [0x38,0x6e,0x12,0x2d] +@ CHECK: ldclo p15, c7, [r3, #-120]! @ encoding: [0x1e,0x7f,0x33,0x3d] +@ CHECK: ldceq p5, c8, [r4], #16 @ encoding: [0x04,0x85,0xb4,0x0c] +@ CHECK: ldcgt p4, c9, [r5], #-72 @ encoding: [0x12,0x94,0x35,0xcc] +@ CHECK: ldcllt p3, c10, [r6, #4] @ encoding: [0x01,0xa3,0xd6,0xbd] +@ CHECK: ldclge p2, c11, [r7] @ encoding: [0x00,0xb2,0xd7,0xad] +@ CHECK: ldclle p1, c12, [r8, #-224] @ encoding: [0x38,0xc1,0x58,0xdd] +@ CHECK: ldclne p0, c13, [r9, #-120]! @ encoding: [0x1e,0xd0,0x79,0x1d] +@ CHECK: ldcleq p6, c14, [r10], #16 @ encoding: [0x04,0xe6,0xfa,0x0c] +@ CHECK: ldclhi p7, c15, [r11], #-72 @ encoding: [0x12,0xf7,0x7b,0x8c] + +@ CHECK: ldc2 p2, c8, [r1], {25} @ encoding: [0x19,0x82,0x91,0xfc] + @------------------------------------------------------------------------------ @ LDM* @@ -619,9 +756,29 @@ _func: @ CHECK: ldmda r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x32,0xe8] @ CHECK: ldmdb r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x32,0xe9] + +@------------------------------------------------------------------------------ +@ LDREX/LDREXB/LDREXH/LDREXD +@------------------------------------------------------------------------------ + ldrexb r3, [r4] + ldrexh r2, [r5] + ldrex r1, [r7] + ldrexd r6, r7, [r8] + +@ CHECK: ldrexb r3, [r4] @ encoding: [0x9f,0x3f,0xd4,0xe1] +@ CHECK: ldrexh r2, [r5] @ encoding: [0x9f,0x2f,0xf5,0xe1] +@ CHECK: ldrex r1, [r7] @ encoding: [0x9f,0x1f,0x97,0xe1] +@ CHECK: ldrexd r6, r7, [r8] @ encoding: [0x9f,0x6f,0xb8,0xe1] + @------------------------------------------------------------------------------ -@ FIXME: LDR* +@ LDRHT @------------------------------------------------------------------------------ + ldrhthi r8, [r11], #-0 + ldrhthi r8, [r11], #0 + +@ CHECK: ldrhthi r8, [r11], #-0 @ encoding: [0xb0,0x80,0x7b,0x80] +@ CHECK: ldrhthi r8, [r11], #0 @ encoding: [0xb0,0x80,0xfb,0x80] + @------------------------------------------------------------------------------ @ FIXME: LSL @------------------------------------------------------------------------------ @@ -635,8 +792,8 @@ _func: mcr p7, #1, r5, c1, c1, #4 mcr2 p7, #1, r5, c1, c1, #4 -@ CHECK: mcr p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0xee] -@ CHECK: mcr2 p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0xfe] +@ CHECK: mcr p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0xee] +@ CHECK: mcr2 p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0xfe] @------------------------------------------------------------------------------ @ MCRR/MCRR2 @@ -644,8 +801,8 @@ _func: mcrr p7, #15, r5, r4, c1 mcrr2 p7, #15, r5, r4, c1 -@ CHECK: mcrr p7, #15, r5, r4, c1 @ encoding: [0xf1,0x57,0x44,0xec] -@ CHECK: mcrr2 p7, #15, r5, r4, c1 @ encoding: [0xf1,0x57,0x44,0xfc] +@ CHECK: mcrr p7, #15, r5, r4, c1 @ encoding: [0xf1,0x57,0x44,0xec] +@ CHECK: mcrr2 p7, #15, r5, r4, c1 @ encoding: [0xf1,0x57,0x44,0xfc] @------------------------------------------------------------------------------ @@ -656,10 +813,10 @@ _func: mlane r1,r2,r3,r4 mlasne r1,r2,r3,r4 -@ CHECK: mla r1, r2, r3, r4 @ encoding: [0x92,0x43,0x21,0xe0] -@ CHECK: mlas r1, r2, r3, r4 @ encoding: [0x92,0x43,0x31,0xe0] -@ CHECK: mlane r1, r2, r3, r4 @ encoding: [0x92,0x43,0x21,0x10] -@ CHECK: mlasne r1, r2, r3, r4 @ encoding: [0x92,0x43,0x31,0x10] +@ CHECK: mla r1, r2, r3, r4 @ encoding: [0x92,0x43,0x21,0xe0] +@ CHECK: mlas r1, r2, r3, r4 @ encoding: [0x92,0x43,0x31,0xe0] +@ CHECK: mlane r1, r2, r3, r4 @ encoding: [0x92,0x43,0x21,0x10] +@ CHECK: mlasne r1, r2, r3, r4 @ encoding: [0x92,0x43,0x31,0x10] @------------------------------------------------------------------------------ @ MLS @@ -671,28 +828,1799 @@ _func: @ CHECK: mlsne r2, r5, r6, r3 @ encoding: [0x95,0x36,0x62,0x10] @------------------------------------------------------------------------------ +@ MOV (immediate) +@------------------------------------------------------------------------------ + mov r3, #7 + mov r4, #0xff0 + mov r5, #0xff0000 + mov r6, #0xffff + movw r9, #0xffff + movs r3, #7 + moveq r4, #0xff0 + movseq r5, #0xff0000 + +@ CHECK: mov r3, #7 @ encoding: [0x07,0x30,0xa0,0xe3] +@ CHECK: mov r4, #4080 @ encoding: [0xff,0x4e,0xa0,0xe3] +@ CHECK: mov r5, #16711680 @ encoding: [0xff,0x58,0xa0,0xe3] +@ CHECK: movw r6, #65535 @ encoding: [0xff,0x6f,0x0f,0xe3] +@ CHECK: movw r9, #65535 @ encoding: [0xff,0x9f,0x0f,0xe3] +@ CHECK: movs r3, #7 @ encoding: [0x07,0x30,0xb0,0xe3] +@ CHECK: moveq r4, #4080 @ encoding: [0xff,0x4e,0xa0,0x03] +@ CHECK: movseq r5, #16711680 @ encoding: [0xff,0x58,0xb0,0x03] + +@------------------------------------------------------------------------------ +@ MOV (register) +@------------------------------------------------------------------------------ + mov r2, r3 + movs r2, r3 + moveq r2, r3 + movseq r2, r3 + +@ CHECK: mov r2, r3 @ encoding: [0x03,0x20,0xa0,0xe1] +@ CHECK: movs r2, r3 @ encoding: [0x03,0x20,0xb0,0xe1] +@ CHECK: moveq r2, r3 @ encoding: [0x03,0x20,0xa0,0x01] +@ CHECK: movseq r2, r3 @ encoding: [0x03,0x20,0xb0,0x01] + +@------------------------------------------------------------------------------ +@ MOVT +@------------------------------------------------------------------------------ + movt r3, #7 + movt r6, #0xffff + movteq r4, #0xff0 + +@ CHECK: movt r3, #7 @ encoding: [0x07,0x30,0x40,0xe3] +@ CHECK: movt r6, #65535 @ encoding: [0xff,0x6f,0x4f,0xe3] +@ CHECK: movteq r4, #4080 @ encoding: [0xf0,0x4f,0x40,0x03] + + +@------------------------------------------------------------------------------ +@ MRC/MRC2 +@------------------------------------------------------------------------------ + mrc p14, #0, r1, c1, c2, #4 + mrc2 p14, #0, r1, c1, c2, #4 + +@ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xee] +@ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xfe] + +@------------------------------------------------------------------------------ +@ MRRC/MRRC2 +@------------------------------------------------------------------------------ + mrrc p7, #1, r5, r4, c1 + mrrc2 p7, #1, r5, r4, c1 + +@ CHECK: mrrc p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xec] +@ CHECK: mrrc2 p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xfc] + + +@------------------------------------------------------------------------------ +@ MRS +@------------------------------------------------------------------------------ + mrs r8, apsr + mrs r8, cpsr + mrs r8, spsr +@ CHECK: mrs r8, apsr @ encoding: [0x00,0x80,0x0f,0xe1] +@ CHECK: mrs r8, apsr @ encoding: [0x00,0x80,0x0f,0xe1] +@ CHECK: mrs r8, spsr @ encoding: [0x00,0x80,0x4f,0xe1] + + + +@------------------------------------------------------------------------------ +@ MSR +@------------------------------------------------------------------------------ + + msr apsr, #5 + msr apsr_g, #5 + msr apsr_nzcvq, #5 + msr APSR_nzcvq, #5 + msr apsr_nzcvqg, #5 + msr cpsr_fc, #5 + msr cpsr_c, #5 + msr cpsr_x, #5 + msr cpsr_fc, #5 + msr cpsr_all, #5 + msr cpsr_fsx, #5 + msr spsr_fc, #5 + msr SPSR_fsxc, #5 + msr cpsr_fsxc, #5 + +@ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3] +@ CHECK: msr APSR_g, #5 @ encoding: [0x05,0xf0,0x24,0xe3] +@ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3] +@ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3] +@ CHECK: msr APSR_nzcvqg, #5 @ encoding: [0x05,0xf0,0x2c,0xe3] +@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x29,0xe3] +@ CHECK: msr CPSR_c, #5 @ encoding: [0x05,0xf0,0x21,0xe3] +@ CHECK: msr CPSR_x, #5 @ encoding: [0x05,0xf0,0x22,0xe3] +@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x29,0xe3] +@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x29,0xe3] +@ CHECK: msr CPSR_fsx, #5 @ encoding: [0x05,0xf0,0x2e,0xe3] +@ CHECK: msr SPSR_fc, #5 @ encoding: [0x05,0xf0,0x69,0xe3] +@ CHECK: msr SPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x6f,0xe3] +@ CHECK: msr CPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x2f,0xe3] + + msr apsr, r0 + msr apsr_g, r0 + msr apsr_nzcvq, r0 + msr APSR_nzcvq, r0 + msr apsr_nzcvqg, r0 + msr cpsr_fc, r0 + msr cpsr_c, r0 + msr cpsr_x, r0 + msr cpsr_fc, r0 + msr cpsr_all, r0 + msr cpsr_fsx, r0 + msr spsr_fc, r0 + msr SPSR_fsxc, r0 + msr cpsr_fsxc, r0 + +@ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1] +@ CHECK: msr APSR_g, r0 @ encoding: [0x00,0xf0,0x24,0xe1] +@ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1] +@ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1] +@ CHECK: msr APSR_nzcvqg, r0 @ encoding: [0x00,0xf0,0x2c,0xe1] +@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] +@ CHECK: msr CPSR_c, r0 @ encoding: [0x00,0xf0,0x21,0xe1] +@ CHECK: msr CPSR_x, r0 @ encoding: [0x00,0xf0,0x22,0xe1] +@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] +@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] +@ CHECK: msr CPSR_fsx, r0 @ encoding: [0x00,0xf0,0x2e,0xe1] +@ CHECK: msr SPSR_fc, r0 @ encoding: [0x00,0xf0,0x69,0xe1] +@ CHECK: msr SPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x6f,0xe1] +@ CHECK: msr CPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x2f,0xe1] + +@------------------------------------------------------------------------------ +@ MUL +@------------------------------------------------------------------------------ + mul r5, r6, r7 + muls r5, r6, r7 + mulgt r5, r6, r7 + mulsle r5, r6, r7 + +@ CHECK: mul r5, r6, r7 @ encoding: [0x96,0x07,0x05,0xe0] +@ CHECK: muls r5, r6, r7 @ encoding: [0x96,0x07,0x15,0xe0] +@ CHECK: mulgt r5, r6, r7 @ encoding: [0x96,0x07,0x05,0xc0] +@ CHECK: mulsle r5, r6, r7 @ encoding: [0x96,0x07,0x15,0xd0] + + +@------------------------------------------------------------------------------ +@ MVN (immediate) +@------------------------------------------------------------------------------ + mvn r3, #7 + mvn r4, #0xff0 + mvn r5, #0xff0000 + mvns r3, #7 + mvneq r4, #0xff0 + mvnseq r5, #0xff0000 + +@ CHECK: mvn r3, #7 @ encoding: [0x07,0x30,0xe0,0xe3] +@ CHECK: mvn r4, #4080 @ encoding: [0xff,0x4e,0xe0,0xe3] +@ CHECK: mvn r5, #16711680 @ encoding: [0xff,0x58,0xe0,0xe3] +@ CHECK: mvns r3, #7 @ encoding: [0x07,0x30,0xf0,0xe3] +@ CHECK: mvneq r4, #4080 @ encoding: [0xff,0x4e,0xe0,0x03] +@ CHECK: mvnseq r5, #16711680 @ encoding: [0xff,0x58,0xf0,0x03] + + +@------------------------------------------------------------------------------ +@ MVN (register) +@------------------------------------------------------------------------------ + mvn r2, r3 + mvns r2, r3 + mvn r5, r6, lsl #19 + mvn r5, r6, lsr #9 + mvn r5, r6, asr #4 + mvn r5, r6, ror #6 + mvn r5, r6, rrx + mvneq r2, r3 + mvnseq r2, r3, lsl #10 + +@ CHECK: mvn r2, r3 @ encoding: [0x03,0x20,0xe0,0xe1] +@ CHECK: mvns r2, r3 @ encoding: [0x03,0x20,0xf0,0xe1] +@ CHECK: mvn r5, r6, lsl #19 @ encoding: [0x86,0x59,0xe0,0xe1] +@ CHECK: mvn r5, r6, lsr #9 @ encoding: [0xa6,0x54,0xe0,0xe1] +@ CHECK: mvn r5, r6, asr #4 @ encoding: [0x46,0x52,0xe0,0xe1] +@ CHECK: mvn r5, r6, ror #6 @ encoding: [0x66,0x53,0xe0,0xe1] +@ CHECK: mvn r5, r6, rrx @ encoding: [0x66,0x50,0xe0,0xe1] +@ CHECK: mvneq r2, r3 @ encoding: [0x03,0x20,0xe0,0x01] +@ CHECK: mvnseq r2, r3, lsl #10 @ encoding: [0x03,0x25,0xf0,0x01] + + +@------------------------------------------------------------------------------ +@ MVN (shifted register) +@------------------------------------------------------------------------------ + mvn r5, r6, lsl r7 + mvns r5, r6, lsr r7 + mvngt r5, r6, asr r7 + mvnslt r5, r6, ror r7 + +@ CHECK: mvn r5, r6, lsl r7 @ encoding: [0x16,0x57,0xe0,0xe1] +@ CHECK: mvns r5, r6, lsr r7 @ encoding: [0x36,0x57,0xf0,0xe1] +@ CHECK: mvngt r5, r6, asr r7 @ encoding: [0x56,0x57,0xe0,0xc1] +@ CHECK: mvnslt r5, r6, ror r7 @ encoding: [0x76,0x57,0xf0,0xb1] + +@------------------------------------------------------------------------------ +@ NOP +@------------------------------------------------------------------------------ + nop + nopgt + +@ CHECK: nop @ encoding: [0x00,0xf0,0x20,0xe3] +@ CHECK: nopgt @ encoding: [0x00,0xf0,0x20,0xc3] + + +@------------------------------------------------------------------------------ +@ ORR +@------------------------------------------------------------------------------ + orr r4, r5, #0xf000 + orr r4, r5, r6 + orr r4, r5, r6, lsl #5 + orr r4, r5, r6, lsr #5 + orr r4, r5, r6, lsr #5 + orr r4, r5, r6, asr #5 + orr r4, r5, r6, ror #5 + orr r6, r7, r8, lsl r9 + orr r6, r7, r8, lsr r9 + orr r6, r7, r8, asr r9 + orr r6, r7, r8, ror r9 + orr r4, r5, r6, rrx + + @ destination register is optional + orr r5, #0xf000 + orr r4, r5 + orr r4, r5, lsl #5 + orr r4, r5, lsr #5 + orr r4, r5, lsr #5 + orr r4, r5, asr #5 + orr r4, r5, ror #5 + orr r6, r7, lsl r9 + orr r6, r7, lsr r9 + orr r6, r7, asr r9 + orr r6, r7, ror r9 + orr r4, r5, rrx + +@ CHECK: orr r4, r5, #61440 @ encoding: [0x0f,0x4a,0x85,0xe3] +@ CHECK: orr r4, r5, r6 @ encoding: [0x06,0x40,0x85,0xe1] +@ CHECK: orr r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x85,0xe1] +@ CHECK: orr r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x85,0xe1] +@ CHECK: orr r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x85,0xe1] +@ CHECK: orr r4, r5, r6, asr #5 @ encoding: [0xc6,0x42,0x85,0xe1] +@ CHECK: orr r4, r5, r6, ror #5 @ encoding: [0xe6,0x42,0x85,0xe1] +@ CHECK: orr r6, r7, r8, lsl r9 @ encoding: [0x18,0x69,0x87,0xe1] +@ CHECK: orr r6, r7, r8, lsr r9 @ encoding: [0x38,0x69,0x87,0xe1] +@ CHECK: orr r6, r7, r8, asr r9 @ encoding: [0x58,0x69,0x87,0xe1] +@ CHECK: orr r6, r7, r8, ror r9 @ encoding: [0x78,0x69,0x87,0xe1] +@ CHECK: orr r4, r5, r6, rrx @ encoding: [0x66,0x40,0x85,0xe1] + +@ CHECK: orr r5, r5, #61440 @ encoding: [0x0f,0x5a,0x85,0xe3] +@ CHECK: orr r4, r4, r5 @ encoding: [0x05,0x40,0x84,0xe1] +@ CHECK: orr r4, r4, r5, lsl #5 @ encoding: [0x85,0x42,0x84,0xe1] +@ CHECK: orr r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x84,0xe1] +@ CHECK: orr r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x84,0xe1] +@ CHECK: orr r4, r4, r5, asr #5 @ encoding: [0xc5,0x42,0x84,0xe1] +@ CHECK: orr r4, r4, r5, ror #5 @ encoding: [0xe5,0x42,0x84,0xe1] +@ CHECK: orr r6, r6, r7, lsl r9 @ encoding: [0x17,0x69,0x86,0xe1] +@ CHECK: orr r6, r6, r7, lsr r9 @ encoding: [0x37,0x69,0x86,0xe1] +@ CHECK: orr r6, r6, r7, asr r9 @ encoding: [0x57,0x69,0x86,0xe1] +@ CHECK: orr r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0x86,0xe1] +@ CHECK: orr r4, r4, r5, rrx @ encoding: [0x65,0x40,0x84,0xe1] + + orrseq r4, r5, #0xf000 + orrne r4, r5, r6 + orrseq r4, r5, r6, lsl #5 + orrlo r6, r7, r8, ror r9 + orrshi r4, r5, r6, rrx + orrcs r5, #0xf000 + orrseq r4, r5 + orrne r6, r7, asr r9 + orrslt r6, r7, ror r9 + orrsgt r4, r5, rrx + +@ CHECK: orrseq r4, r5, #61440 @ encoding: [0x0f,0x4a,0x95,0x03] +@ CHECK: orrne r4, r5, r6 @ encoding: [0x06,0x40,0x85,0x11] +@ CHECK: orrseq r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x95,0x01] +@ CHECK: orrlo r6, r7, r8, ror r9 @ encoding: [0x78,0x69,0x87,0x31] +@ CHECK: orrshi r4, r5, r6, rrx @ encoding: [0x66,0x40,0x95,0x81] +@ CHECK: orrhs r5, r5, #61440 @ encoding: [0x0f,0x5a,0x85,0x23] +@ CHECK: orrseq r4, r4, r5 @ encoding: [0x05,0x40,0x94,0x01] +@ CHECK: orrne r6, r6, r7, asr r9 @ encoding: [0x57,0x69,0x86,0x11] +@ CHECK: orrslt r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0x96,0xb1] +@ CHECK: orrsgt r4, r4, r5, rrx @ encoding: [0x65,0x40,0x94,0xc1] + +@------------------------------------------------------------------------------ +@ PKH +@------------------------------------------------------------------------------ + pkhbt r2, r2, r3 + pkhbt r2, r2, r3, lsl #31 + pkhbt r2, r2, r3, lsl #0 + pkhbt r2, r2, r3, lsl #15 + + pkhtb r2, r2, r3 + pkhtb r2, r2, r3, asr #31 + pkhtb r2, r2, r3, asr #15 + +@ CHECK: pkhbt r2, r2, r3 @ encoding: [0x13,0x20,0x82,0xe6] +@ CHECK: pkhbt r2, r2, r3, lsl #31 @ encoding: [0x93,0x2f,0x82,0xe6] +@ CHECK: pkhbt r2, r2, r3 @ encoding: [0x13,0x20,0x82,0xe6] +@ CHECK: pkhbt r2, r2, r3, lsl #15 @ encoding: [0x93,0x27,0x82,0xe6] + +@ CHECK: pkhbt r2, r2, r3 @ encoding: [0x13,0x20,0x82,0xe6] +@ CHECK: pkhtb r2, r2, r3, asr #31 @ encoding: [0xd3,0x2f,0x82,0xe6] +@ CHECK: pkhtb r2, r2, r3, asr #15 @ encoding: [0xd3,0x27,0x82,0xe6] + +@------------------------------------------------------------------------------ +@ FIXME: PLD +@------------------------------------------------------------------------------ +@------------------------------------------------------------------------------ +@ FIXME: PLI +@------------------------------------------------------------------------------ + + +@------------------------------------------------------------------------------ +@ POP +@------------------------------------------------------------------------------ + pop {r7} + pop {r7, r8, r9, r10} + +@ CHECK: pop {r7} @ encoding: [0x04,0x70,0x9d,0xe4] +@ CHECK: pop {r7, r8, r9, r10} @ encoding: [0x80,0x07,0xbd,0xe8] + + +@------------------------------------------------------------------------------ +@ PUSH +@------------------------------------------------------------------------------ + push {r7} + push {r7, r8, r9, r10} + +@ CHECK: push {r7} @ encoding: [0x04,0x70,0x2d,0xe5] +@ CHECK: push {r7, r8, r9, r10} @ encoding: [0x80,0x07,0x2d,0xe9] + + +@------------------------------------------------------------------------------ +@ QADD/QADD16/QADD8 +@------------------------------------------------------------------------------ + qadd r1, r2, r3 + qaddne r1, r2, r3 + qadd16 r1, r2, r3 + qadd16gt r1, r2, r3 + qadd8 r1, r2, r3 + qadd8le r1, r2, r3 + +@ CHECK: qadd r1, r2, r3 @ encoding: [0x52,0x10,0x03,0xe1] +@ CHECK: qaddne r1, r2, r3 @ encoding: [0x52,0x10,0x03,0x11] +@ CHECK: qadd16 r1, r2, r3 @ encoding: [0x13,0x1f,0x22,0xe6] +@ CHECK: qadd16gt r1, r2, r3 @ encoding: [0x13,0x1f,0x22,0xc6] +@ CHECK: qadd8 r1, r2, r3 @ encoding: [0x93,0x1f,0x22,0xe6] +@ CHECK: qadd8le r1, r2, r3 @ encoding: [0x93,0x1f,0x22,0xd6] + + +@------------------------------------------------------------------------------ +@ QDADD/QDSUB +@------------------------------------------------------------------------------ + qdadd r6, r7, r8 + qdaddhi r6, r7, r8 + qdsub r6, r7, r8 + qdsubhi r6, r7, r8 + +@ CHECK: qdadd r6, r7, r8 @ encoding: [0x57,0x60,0x48,0xe1] +@ CHECK: qdaddhi r6, r7, r8 @ encoding: [0x57,0x60,0x48,0x81] +@ CHECK: qdsub r6, r7, r8 @ encoding: [0x57,0x60,0x68,0xe1] +@ CHECK: qdsubhi r6, r7, r8 @ encoding: [0x57,0x60,0x68,0x81] + + +@------------------------------------------------------------------------------ +@ QSAX +@------------------------------------------------------------------------------ + qsax r9, r12, r0 + qsaxeq r9, r12, r0 + +@ CHECK: qsax r9, r12, r0 @ encoding: [0x50,0x9f,0x2c,0xe6] +@ CHECK: qsaxeq r9, r12, r0 @ encoding: [0x50,0x9f,0x2c,0x06] + + +@------------------------------------------------------------------------------ +@ QSUB/QSUB16/QSUB8 +@------------------------------------------------------------------------------ + qsub r1, r2, r3 + qsubne r1, r2, r3 + qsub16 r1, r2, r3 + qsub16gt r1, r2, r3 + qsub8 r1, r2, r3 + qsub8le r1, r2, r3 + +@ CHECK: qsub r1, r2, r3 @ encoding: [0x52,0x10,0x23,0xe1] +@ CHECK: qsubne r1, r2, r3 @ encoding: [0x52,0x10,0x23,0x11] +@ CHECK: qsub16 r1, r2, r3 @ encoding: [0x73,0x1f,0x22,0xe6] +@ CHECK: qsub16gt r1, r2, r3 @ encoding: [0x73,0x1f,0x22,0xc6] +@ CHECK: qsub8 r1, r2, r3 @ encoding: [0xf3,0x1f,0x22,0xe6] +@ CHECK: qsub8le r1, r2, r3 @ encoding: [0xf3,0x1f,0x22,0xd6] + + +@------------------------------------------------------------------------------ +@ RBIT +@------------------------------------------------------------------------------ + rbit r1, r2 + rbitne r1, r2 + +@ CHECK: rbit r1, r2 @ encoding: [0x32,0x1f,0xff,0xe6] +@ CHECK: rbitne r1, r2 @ encoding: [0x32,0x1f,0xff,0x16] + + +@------------------------------------------------------------------------------ +@ REV/REV16/REVSH +@------------------------------------------------------------------------------ + rev r1, r9 + revne r1, r5 + rev16 r8, r3 + rev16ne r12, r4 + revsh r4, r9 + revshne r9, r1 + +@ CHECK: rev r1, r9 @ encoding: [0x39,0x1f,0xbf,0xe6] +@ CHECK: revne r1, r5 @ encoding: [0x35,0x1f,0xbf,0x16] +@ CHECK: rev16 r8, r3 @ encoding: [0xb3,0x8f,0xbf,0xe6] +@ CHECK: rev16ne r12, r4 @ encoding: [0xb4,0xcf,0xbf,0x16] +@ CHECK: revsh r4, r9 @ encoding: [0xb9,0x4f,0xff,0xe6] +@ CHECK: revshne r9, r1 @ encoding: [0xb1,0x9f,0xff,0x16] + + +@------------------------------------------------------------------------------ +@ RFE +@------------------------------------------------------------------------------ + rfeda r2 + rfedb r3 + rfeia r5 + rfeib r6 + + rfeda r4! + rfedb r7! + rfeia r9! + rfeib r8! + + rfefa r2 + rfeea r3 + rfefd r5 + rfeed r6 + + rfefa r4! + rfeea r7! + rfefd r9! + rfeed r8! + + rfe r1 + rfe r1! + +@ CHECK: rfeda r2 @ encoding: [0x00,0x0a,0x12,0xf8] +@ CHECK: rfedb r3 @ encoding: [0x00,0x0a,0x13,0xf9] +@ CHECK: rfeia r5 @ encoding: [0x00,0x0a,0x95,0xf8] +@ CHECK: rfeib r6 @ encoding: [0x00,0x0a,0x96,0xf9] + +@ CHECK: rfeda r4! @ encoding: [0x00,0x0a,0x34,0xf8] +@ CHECK: rfedb r7! @ encoding: [0x00,0x0a,0x37,0xf9] +@ CHECK: rfeia r9! @ encoding: [0x00,0x0a,0xb9,0xf8] +@ CHECK: rfeib r8! @ encoding: [0x00,0x0a,0xb8,0xf9] + +@ CHECK: rfeda r2 @ encoding: [0x00,0x0a,0x12,0xf8] +@ CHECK: rfedb r3 @ encoding: [0x00,0x0a,0x13,0xf9] +@ CHECK: rfeia r5 @ encoding: [0x00,0x0a,0x95,0xf8] +@ CHECK: rfeib r6 @ encoding: [0x00,0x0a,0x96,0xf9] + +@ CHECK: rfeda r4! @ encoding: [0x00,0x0a,0x34,0xf8] +@ CHECK: rfedb r7! @ encoding: [0x00,0x0a,0x37,0xf9] +@ CHECK: rfeia r9! @ encoding: [0x00,0x0a,0xb9,0xf8] +@ CHECK: rfeib r8! @ encoding: [0x00,0x0a,0xb8,0xf9] + +@ CHECK: rfeia r1 @ encoding: [0x00,0x0a,0x91,0xf8] +@ CHECK: rfeia r1! @ encoding: [0x00,0x0a,0xb1,0xf8] + + +@------------------------------------------------------------------------------ +@ RSB +@------------------------------------------------------------------------------ + rsb r4, r5, #0xf000 + rsb r4, r5, r6 + rsb r4, r5, r6, lsl #5 + rsblo r4, r5, r6, lsr #5 + rsb r4, r5, r6, lsr #5 + rsb r4, r5, r6, asr #5 + rsb r4, r5, r6, ror #5 + rsb r6, r7, r8, lsl r9 + rsb r6, r7, r8, lsr r9 + rsb r6, r7, r8, asr r9 + rsble r6, r7, r8, ror r9 + rsb r4, r5, r6, rrx + + @ destination register is optional + rsb r5, #0xf000 + rsb r4, r5 + rsb r4, r5, lsl #5 + rsb r4, r5, lsr #5 + rsbne r4, r5, lsr #5 + rsb r4, r5, asr #5 + rsb r4, r5, ror #5 + rsbgt r6, r7, lsl r9 + rsb r6, r7, lsr r9 + rsb r6, r7, asr r9 + rsb r6, r7, ror r9 + rsb r4, r5, rrx + +@ CHECK: rsb r4, r5, #61440 @ encoding: [0x0f,0x4a,0x65,0xe2] +@ CHECK: rsb r4, r5, r6 @ encoding: [0x06,0x40,0x65,0xe0] +@ CHECK: rsb r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x65,0xe0] +@ CHECK: rsblo r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x65,0x30] +@ CHECK: rsb r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x65,0xe0] +@ CHECK: rsb r4, r5, r6, asr #5 @ encoding: [0xc6,0x42,0x65,0xe0] +@ CHECK: rsb r4, r5, r6, ror #5 @ encoding: [0xe6,0x42,0x65,0xe0] +@ CHECK: rsb r6, r7, r8, lsl r9 @ encoding: [0x18,0x69,0x67,0xe0] +@ CHECK: rsb r6, r7, r8, lsr r9 @ encoding: [0x38,0x69,0x67,0xe0] +@ CHECK: rsb r6, r7, r8, asr r9 @ encoding: [0x58,0x69,0x67,0xe0] +@ CHECK: rsble r6, r7, r8, ror r9 @ encoding: [0x78,0x69,0x67,0xd0] +@ CHECK: rsb r4, r5, r6, rrx @ encoding: [0x66,0x40,0x65,0xe0] + +@ CHECK: rsb r5, r5, #61440 @ encoding: [0x0f,0x5a,0x65,0xe2] +@ CHECK: rsb r4, r4, r5 @ encoding: [0x05,0x40,0x64,0xe0] +@ CHECK: rsb r4, r4, r5, lsl #5 @ encoding: [0x85,0x42,0x64,0xe0] +@ CHECK: rsb r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x64,0xe0] +@ CHECK: rsbne r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x64,0x10] +@ CHECK: rsb r4, r4, r5, asr #5 @ encoding: [0xc5,0x42,0x64,0xe0] +@ CHECK: rsb r4, r4, r5, ror #5 @ encoding: [0xe5,0x42,0x64,0xe0] +@ CHECK: rsbgt r6, r6, r7, lsl r9 @ encoding: [0x17,0x69,0x66,0xc0] +@ CHECK: rsb r6, r6, r7, lsr r9 @ encoding: [0x37,0x69,0x66,0xe0] +@ CHECK: rsb r6, r6, r7, asr r9 @ encoding: [0x57,0x69,0x66,0xe0] +@ CHECK: rsb r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0x66,0xe0] +@ CHECK: rsb r4, r4, r5, rrx @ encoding: [0x65,0x40,0x64,0xe0] + +@------------------------------------------------------------------------------ +@ RSC +@------------------------------------------------------------------------------ + rsc r4, r5, #0xf000 + rsc r4, r5, r6 + rsc r4, r5, r6, lsl #5 + rsclo r4, r5, r6, lsr #5 + rsc r4, r5, r6, lsr #5 + rsc r4, r5, r6, asr #5 + rsc r4, r5, r6, ror #5 + rsc r6, r7, r8, lsl r9 + rsc r6, r7, r8, lsr r9 + rsc r6, r7, r8, asr r9 + rscle r6, r7, r8, ror r9 + rscs r1, r8, #4064 + + @ destination register is optional + rsc r5, #0xf000 + rsc r4, r5 + rsc r4, r5, lsl #5 + rsc r4, r5, lsr #5 + rscne r4, r5, lsr #5 + rsc r4, r5, asr #5 + rsc r4, r5, ror #5 + rscgt r6, r7, lsl r9 + rsc r6, r7, lsr r9 + rsc r6, r7, asr r9 + rsc r6, r7, ror r9 + +@ CHECK: rsc r4, r5, #61440 @ encoding: [0x0f,0x4a,0xe5,0xe2] +@ CHECK: rsc r4, r5, r6 @ encoding: [0x06,0x40,0xe5,0xe0] +@ CHECK: rsc r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0xe5,0xe0] +@ CHECK: rsclo r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0xe5,0x30] +@ CHECK: rsc r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0xe5,0xe0] +@ CHECK: rsc r4, r5, r6, asr #5 @ encoding: [0xc6,0x42,0xe5,0xe0] +@ CHECK: rsc r4, r5, r6, ror #5 @ encoding: [0xe6,0x42,0xe5,0xe0] +@ CHECK: rsc r6, r7, r8, lsl r9 @ encoding: [0x18,0x69,0xe7,0xe0] +@ CHECK: rsc r6, r7, r8, lsr r9 @ encoding: [0x38,0x69,0xe7,0xe0] +@ CHECK: rsc r6, r7, r8, asr r9 @ encoding: [0x58,0x69,0xe7,0xe0] +@ CHECK: rscle r6, r7, r8, ror r9 @ encoding: [0x78,0x69,0xe7,0xd0] +@ CHECK: rscs r1, r8, #4064 @ encoding: [0xfe,0x1e,0xf8,0xe2] + +@ CHECK: rsc r5, r5, #61440 @ encoding: [0x0f,0x5a,0xe5,0xe2] +@ CHECK: rsc r4, r4, r5 @ encoding: [0x05,0x40,0xe4,0xe0] +@ CHECK: rsc r4, r4, r5, lsl #5 @ encoding: [0x85,0x42,0xe4,0xe0] +@ CHECK: rsc r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0xe4,0xe0] +@ CHECK: rscne r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0xe4,0x10] +@ CHECK: rsc r4, r4, r5, asr #5 @ encoding: [0xc5,0x42,0xe4,0xe0] +@ CHECK: rsc r4, r4, r5, ror #5 @ encoding: [0xe5,0x42,0xe4,0xe0] +@ CHECK: rscgt r6, r6, r7, lsl r9 @ encoding: [0x17,0x69,0xe6,0xc0] +@ CHECK: rsc r6, r6, r7, lsr r9 @ encoding: [0x37,0x69,0xe6,0xe0] +@ CHECK: rsc r6, r6, r7, asr r9 @ encoding: [0x57,0x69,0xe6,0xe0] +@ CHECK: rsc r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0xe6,0xe0] + +@------------------------------------------------------------------------------ +@ SADD16/SADD8 +@------------------------------------------------------------------------------ + sadd16 r1, r2, r3 + sadd16gt r1, r2, r3 + sadd8 r1, r2, r3 + sadd8le r1, r2, r3 + +@ CHECK: sadd16 r1, r2, r3 @ encoding: [0x13,0x1f,0x12,0xe6] +@ CHECK: sadd16gt r1, r2, r3 @ encoding: [0x13,0x1f,0x12,0xc6] +@ CHECK: sadd8 r1, r2, r3 @ encoding: [0x93,0x1f,0x12,0xe6] +@ CHECK: sadd8le r1, r2, r3 @ encoding: [0x93,0x1f,0x12,0xd6] + + +@------------------------------------------------------------------------------ +@ SASX +@------------------------------------------------------------------------------ + sasx r9, r12, r0 + sasxeq r9, r12, r0 + +@ CHECK: sasx r9, r12, r0 @ encoding: [0x30,0x9f,0x1c,0xe6] +@ CHECK: sasxeq r9, r12, r0 @ encoding: [0x30,0x9f,0x1c,0x06] + + +@------------------------------------------------------------------------------ +@ SBC +@------------------------------------------------------------------------------ + sbc r4, r5, #0xf000 + sbc r4, r5, r6 + sbc r4, r5, r6, lsl #5 + sbc r4, r5, r6, lsr #5 + sbc r4, r5, r6, lsr #5 + sbc r4, r5, r6, asr #5 + sbc r4, r5, r6, ror #5 + sbc r6, r7, r8, lsl r9 + sbc r6, r7, r8, lsr r9 + sbc r6, r7, r8, asr r9 + sbc r6, r7, r8, ror r9 + + @ destination register is optional + sbc r5, #0xf000 + sbc r4, r5 + sbc r4, r5, lsl #5 + sbc r4, r5, lsr #5 + sbc r4, r5, lsr #5 + sbc r4, r5, asr #5 + sbc r4, r5, ror #5 + sbc r6, r7, lsl r9 + sbc r6, r7, lsr r9 + sbc r6, r7, asr r9 + sbc r6, r7, ror r9 + +@ CHECK: sbc r4, r5, #61440 @ encoding: [0x0f,0x4a,0xc5,0xe2] +@ CHECK: sbc r4, r5, r6 @ encoding: [0x06,0x40,0xc5,0xe0] +@ CHECK: sbc r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0xc5,0xe0] +@ CHECK: sbc r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0xc5,0xe0] +@ CHECK: sbc r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0xc5,0xe0] +@ CHECK: sbc r4, r5, r6, asr #5 @ encoding: [0xc6,0x42,0xc5,0xe0] +@ CHECK: sbc r4, r5, r6, ror #5 @ encoding: [0xe6,0x42,0xc5,0xe0] +@ CHECK: sbc r6, r7, r8, lsl r9 @ encoding: [0x18,0x69,0xc7,0xe0] +@ CHECK: sbc r6, r7, r8, lsr r9 @ encoding: [0x38,0x69,0xc7,0xe0] +@ CHECK: sbc r6, r7, r8, asr r9 @ encoding: [0x58,0x69,0xc7,0xe0] +@ CHECK: sbc r6, r7, r8, ror r9 @ encoding: [0x78,0x69,0xc7,0xe0] + +@ CHECK: sbc r5, r5, #61440 @ encoding: [0x0f,0x5a,0xc5,0xe2] +@ CHECK: sbc r4, r4, r5 @ encoding: [0x05,0x40,0xc4,0xe0] +@ CHECK: sbc r4, r4, r5, lsl #5 @ encoding: [0x85,0x42,0xc4,0xe0] +@ CHECK: sbc r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0xc4,0xe0] +@ CHECK: sbc r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0xc4,0xe0] +@ CHECK: sbc r4, r4, r5, asr #5 @ encoding: [0xc5,0x42,0xc4,0xe0] +@ CHECK: sbc r4, r4, r5, ror #5 @ encoding: [0xe5,0x42,0xc4,0xe0] +@ CHECK: sbc r6, r6, r7, lsl r9 @ encoding: [0x17,0x69,0xc6,0xe0] +@ CHECK: sbc r6, r6, r7, lsr r9 @ encoding: [0x37,0x69,0xc6,0xe0] +@ CHECK: sbc r6, r6, r7, asr r9 @ encoding: [0x57,0x69,0xc6,0xe0] +@ CHECK: sbc r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0xc6,0xe0] + + +@------------------------------------------------------------------------------ +@ SBFX +@------------------------------------------------------------------------------ + sbfx r4, r5, #16, #1 + sbfxgt r4, r5, #16, #16 + +@ CHECK: sbfx r4, r5, #16, #1 @ encoding: [0x55,0x48,0xa0,0xe7] +@ CHECK: sbfxgt r4, r5, #16, #16 @ encoding: [0x55,0x48,0xaf,0xc7] + + +@------------------------------------------------------------------------------ +@ SEL +@------------------------------------------------------------------------------ + sel r9, r2, r1 + selne r9, r2, r1 + +@ CHECK: sel r9, r2, r1 @ encoding: [0xb1,0x9f,0x82,0xe6] +@ CHECK: selne r9, r2, r1 @ encoding: [0xb1,0x9f,0x82,0x16] + + +@------------------------------------------------------------------------------ +@ SETEND +@------------------------------------------------------------------------------ + setend be + setend le + +@ CHECK: setend be @ encoding: [0x00,0x02,0x01,0xf1] +@ CHECK: setend le @ encoding: [0x00,0x00,0x01,0xf1] + + +@------------------------------------------------------------------------------ +@ SEV +@------------------------------------------------------------------------------ + sev + seveq + +@ CHECK: sev @ encoding: [0x04,0xf0,0x20,0xe3] +@ CHECK: seveq @ encoding: [0x04,0xf0,0x20,0x03] + + +@------------------------------------------------------------------------------ +@ SHADD16/SHADD8 +@------------------------------------------------------------------------------ + shadd16 r4, r8, r2 + shadd16gt r4, r8, r2 + shadd8 r4, r8, r2 + shadd8gt r4, r8, r2 + +@ CHECK: shadd16 r4, r8, r2 @ encoding: [0x12,0x4f,0x38,0xe6] +@ CHECK: shadd16gt r4, r8, r2 @ encoding: [0x12,0x4f,0x38,0xc6] +@ CHECK: shadd8 r4, r8, r2 @ encoding: [0x92,0x4f,0x38,0xe6] +@ CHECK: shadd8gt r4, r8, r2 @ encoding: [0x92,0x4f,0x38,0xc6] + + +@------------------------------------------------------------------------------ +@ SHASX +@------------------------------------------------------------------------------ + shasx r4, r8, r2 + shasxgt r4, r8, r2 + +@ CHECK: shasx r4, r8, r2 @ encoding: [0x32,0x4f,0x38,0xe6] +@ CHECK: shasxgt r4, r8, r2 @ encoding: [0x32,0x4f,0x38,0xc6] + + +@------------------------------------------------------------------------------ +@ SHSUB16/SHSUB8 +@------------------------------------------------------------------------------ + shsub16 r4, r8, r2 + shsub16gt r4, r8, r2 + shsub8 r4, r8, r2 + shsub8gt r4, r8, r2 + +@ CHECK: shsub16 r4, r8, r2 @ encoding: [0x72,0x4f,0x38,0xe6] +@ CHECK: shsub16gt r4, r8, r2 @ encoding: [0x72,0x4f,0x38,0xc6] +@ CHECK: shsub8 r4, r8, r2 @ encoding: [0xf2,0x4f,0x38,0xe6] +@ CHECK: shsub8gt r4, r8, r2 @ encoding: [0xf2,0x4f,0x38,0xc6] + +@------------------------------------------------------------------------------ +@ SMC +@------------------------------------------------------------------------------ + smc #0xf + smceq #0 + +@ CHECK: smc #15 @ encoding: [0x7f,0x00,0x60,0xe1] +@ CHECK: smceq #0 @ encoding: [0x70,0x00,0x60,0x01] + +@------------------------------------------------------------------------------ +@ SMLABB/SMLABT/SMLATB/SMLATT +@------------------------------------------------------------------------------ + smlabb r3, r1, r9, r0 + smlabt r5, r6, r4, r1 + smlatb r4, r2, r3, r2 + smlatt r8, r3, r8, r4 + smlabbge r3, r1, r9, r0 + smlabtle r5, r6, r4, r1 + smlatbne r4, r2, r3, r2 + smlatteq r8, r3, r8, r4 + +@ CHECK: smlabb r3, r1, r9, r0 @ encoding: [0x81,0x09,0x03,0xe1] +@ CHECK: smlabt r5, r6, r4, r1 @ encoding: [0xc6,0x14,0x05,0xe1] +@ CHECK: smlatb r4, r2, r3, r2 @ encoding: [0xa2,0x23,0x04,0xe1] +@ CHECK: smlatt r8, r3, r8, r4 @ encoding: [0xe3,0x48,0x08,0xe1] +@ CHECK: smlabbge r3, r1, r9, r0 @ encoding: [0x81,0x09,0x03,0xa1] +@ CHECK: smlabtle r5, r6, r4, r1 @ encoding: [0xc6,0x14,0x05,0xd1] +@ CHECK: smlatbne r4, r2, r3, r2 @ encoding: [0xa2,0x23,0x04,0x11] +@ CHECK: smlatteq r8, r3, r8, r4 @ encoding: [0xe3,0x48,0x08,0x01] + +@------------------------------------------------------------------------------ +@ SMLAD/SMLADX +@------------------------------------------------------------------------------ + smlad r2, r3, r5, r8 + smladx r2, r3, r5, r8 + smladeq r2, r3, r5, r8 + smladxhi r2, r3, r5, r8 + +@ CHECK: smlad r2, r3, r5, r8 @ encoding: [0x13,0x85,0x02,0xe7] +@ CHECK: smladx r2, r3, r5, r8 @ encoding: [0x33,0x85,0x02,0xe7] +@ CHECK: smladeq r2, r3, r5, r8 @ encoding: [0x13,0x85,0x02,0x07] +@ CHECK: smladxhi r2, r3, r5, r8 @ encoding: [0x33,0x85,0x02,0x87] + + +@------------------------------------------------------------------------------ +@ SMLAL +@------------------------------------------------------------------------------ + smlal r2, r3, r5, r8 + smlals r2, r3, r5, r8 + smlaleq r2, r3, r5, r8 + smlalshi r2, r3, r5, r8 + +@ CHECK: smlal r2, r3, r5, r8 @ encoding: [0x95,0x28,0xe3,0xe0] +@ CHECK: smlals r2, r3, r5, r8 @ encoding: [0x95,0x28,0xf3,0xe0] +@ CHECK: smlaleq r2, r3, r5, r8 @ encoding: [0x95,0x28,0xe3,0x00] +@ CHECK: smlalshi r2, r3, r5, r8 @ encoding: [0x95,0x28,0xf3,0x80] + + +@------------------------------------------------------------------------------ +@ SMLALBB/SMLALBT/SMLALTB/SMLALTT +@------------------------------------------------------------------------------ + smlalbb r3, r1, r9, r0 + smlalbt r5, r6, r4, r1 + smlaltb r4, r2, r3, r2 + smlaltt r8, r3, r8, r4 + smlalbbge r3, r1, r9, r0 + smlalbtle r5, r6, r4, r1 + smlaltbne r4, r2, r3, r2 + smlaltteq r8, r3, r8, r4 + +@ CHECK: smlalbb r3, r1, r9, r0 @ encoding: [0x89,0x30,0x41,0xe1] +@ CHECK: smlalbt r5, r6, r4, r1 @ encoding: [0xc4,0x51,0x46,0xe1] +@ CHECK: smlaltb r4, r2, r3, r2 @ encoding: [0xa3,0x42,0x42,0xe1] +@ CHECK: smlaltt r8, r3, r8, r4 @ encoding: [0xe8,0x84,0x43,0xe1] +@ CHECK: smlalbbge r3, r1, r9, r0 @ encoding: [0x89,0x30,0x41,0xa1] +@ CHECK: smlalbtle r5, r6, r4, r1 @ encoding: [0xc4,0x51,0x46,0xd1] +@ CHECK: smlaltbne r4, r2, r3, r2 @ encoding: [0xa3,0x42,0x42,0x11] +@ CHECK: smlaltteq r8, r3, r8, r4 @ encoding: [0xe8,0x84,0x43,0x01] + + +@------------------------------------------------------------------------------ +@ SMLALD/SMLALDX +@------------------------------------------------------------------------------ + smlald r2, r3, r5, r8 + smlaldx r2, r3, r5, r8 + smlaldeq r2, r3, r5, r8 + smlaldxhi r2, r3, r5, r8 + +@ CHECK: smlald r2, r3, r5, r8 @ encoding: [0x15,0x28,0x43,0xe7] +@ CHECK: smlaldx r2, r3, r5, r8 @ encoding: [0x35,0x28,0x43,0xe7] +@ CHECK: smlaldeq r2, r3, r5, r8 @ encoding: [0x15,0x28,0x43,0x07] +@ CHECK: smlaldxhi r2, r3, r5, r8 @ encoding: [0x35,0x28,0x43,0x87] + + +@------------------------------------------------------------------------------ +@ SMLAWB/SMLAWT +@------------------------------------------------------------------------------ + smlawb r2, r3, r10, r8 + smlawt r8, r3, r5, r9 + smlawbeq r2, r7, r5, r8 + smlawthi r1, r3, r0, r8 + +@ CHECK: smlawb r2, r3, r10, r8 @ encoding: [0x83,0x8a,0x22,0xe1] +@ CHECK: smlawt r8, r3, r5, r9 @ encoding: [0xc3,0x95,0x28,0xe1] +@ CHECK: smlawbeq r2, r7, r5, r8 @ encoding: [0x87,0x85,0x22,0x01] +@ CHECK: smlawthi r1, r3, r0, r8 @ encoding: [0xc3,0x80,0x21,0x81] + + +@------------------------------------------------------------------------------ +@ SMLSD/SMLSDX +@------------------------------------------------------------------------------ + smlsd r2, r3, r5, r8 + smlsdx r2, r3, r5, r8 + smlsdeq r2, r3, r5, r8 + smlsdxhi r2, r3, r5, r8 + +@ CHECK: smlsd r2, r3, r5, r8 @ encoding: [0x53,0x85,0x02,0xe7] +@ CHECK: smlsdx r2, r3, r5, r8 @ encoding: [0x73,0x85,0x02,0xe7] +@ CHECK: smlsdeq r2, r3, r5, r8 @ encoding: [0x53,0x85,0x02,0x07] +@ CHECK: smlsdxhi r2, r3, r5, r8 @ encoding: [0x73,0x85,0x02,0x87] + + +@------------------------------------------------------------------------------ +@ SMLSLD/SMLSLDX +@------------------------------------------------------------------------------ + smlsld r2, r9, r5, r1 + smlsldx r4, r11, r2, r8 + smlsldeq r8, r2, r5, r6 + smlsldxhi r1, r0, r3, r8 + +@ CHECK: smlsld r2, r9, r5, r1 @ encoding: [0x55,0x21,0x49,0xe7] +@ CHECK: smlsldx r4, r11, r2, r8 @ encoding: [0x72,0x48,0x4b,0xe7] +@ CHECK: smlsldeq r8, r2, r5, r6 @ encoding: [0x55,0x86,0x42,0x07] +@ CHECK: smlsldxhi r1, r0, r3, r8 @ encoding: [0x73,0x18,0x40,0x87] + + +@------------------------------------------------------------------------------ +@ SMMLA/SMMLAR +@------------------------------------------------------------------------------ + smmla r1, r2, r3, r4 + smmlar r4, r3, r2, r1 + smmlalo r1, r2, r3, r4 + smmlarcs r4, r3, r2, r1 + +@ CHECK: smmla r1, r2, r3, r4 @ encoding: [0x12,0x43,0x51,0xe7] +@ CHECK: smmlar r4, r3, r2, r1 @ encoding: [0x33,0x12,0x54,0xe7] +@ CHECK: smmlalo r1, r2, r3, r4 @ encoding: [0x12,0x43,0x51,0x37] +@ CHECK: smmlarhs r4, r3, r2, r1 @ encoding: [0x33,0x12,0x54,0x27] + + +@------------------------------------------------------------------------------ +@ SMMLS/SMMLSR +@------------------------------------------------------------------------------ + smmls r1, r2, r3, r4 + smmlsr r4, r3, r2, r1 + smmlslo r1, r2, r3, r4 + smmlsrcs r4, r3, r2, r1 + +@ CHECK: smmls r1, r2, r3, r4 @ encoding: [0xd2,0x43,0x51,0xe7] +@ CHECK: smmlsr r4, r3, r2, r1 @ encoding: [0xf3,0x12,0x54,0xe7] +@ CHECK: smmlslo r1, r2, r3, r4 @ encoding: [0xd2,0x43,0x51,0x37] +@ CHECK: smmlsrhs r4, r3, r2, r1 @ encoding: [0xf3,0x12,0x54,0x27] + + +@------------------------------------------------------------------------------ +@ SMMUL/SMMULR +@------------------------------------------------------------------------------ + smmul r2, r3, r4 + smmulr r3, r2, r1 + smmulcc r2, r3, r4 + smmulrhs r3, r2, r1 + +@ CHECK: smmul r2, r3, r4 @ encoding: [0x13,0xf4,0x52,0xe7] +@ CHECK: smmulr r3, r2, r1 @ encoding: [0x32,0xf1,0x53,0xe7] +@ CHECK: smmullo r2, r3, r4 @ encoding: [0x13,0xf4,0x52,0x37] +@ CHECK: smmulrhs r3, r2, r1 @ encoding: [0x32,0xf1,0x53,0x27] + + +@------------------------------------------------------------------------------ +@ SMUAD/SMUADX +@------------------------------------------------------------------------------ + smuad r2, r3, r4 + smuadx r3, r2, r1 + smuadlt r2, r3, r4 + smuadxge r3, r2, r1 + +@ CHECK: smuad r2, r3, r4 @ encoding: [0x13,0xf4,0x02,0xe7] +@ CHECK: smuadx r3, r2, r1 @ encoding: [0x32,0xf1,0x03,0xe7] +@ CHECK: smuadlt r2, r3, r4 @ encoding: [0x13,0xf4,0x02,0xb7] +@ CHECK: smuadxge r3, r2, r1 @ encoding: [0x32,0xf1,0x03,0xa7] + + +@------------------------------------------------------------------------------ +@ SMULBB/SMULBT/SMULTB/SMULTT +@------------------------------------------------------------------------------ + smulbb r3, r9, r0 + smulbt r5, r4, r1 + smultb r4, r2, r2 + smultt r8, r3, r4 + smulbbge r1, r9, r0 + smulbtle r5, r6, r4 + smultbne r2, r3, r2 + smultteq r8, r3, r4 + +@ CHECK: smulbb r3, r9, r0 @ encoding: [0x89,0x00,0x63,0xe1] +@ CHECK: smulbt r5, r4, r1 @ encoding: [0xc4,0x01,0x65,0xe1] +@ CHECK: smultb r4, r2, r2 @ encoding: [0xa2,0x02,0x64,0xe1] +@ CHECK: smultt r8, r3, r4 @ encoding: [0xe3,0x04,0x68,0xe1] +@ CHECK: smulbbge r1, r9, r0 @ encoding: [0x89,0x00,0x61,0xa1] +@ CHECK: smulbtle r5, r6, r4 @ encoding: [0xc6,0x04,0x65,0xd1] +@ CHECK: smultbne r2, r3, r2 @ encoding: [0xa3,0x02,0x62,0x11] +@ CHECK: smultteq r8, r3, r4 @ encoding: [0xe3,0x04,0x68,0x01] + + +@------------------------------------------------------------------------------ +@ SMULL +@------------------------------------------------------------------------------ + smull r3, r9, r0, r1 + smulls r3, r9, r0, r2 + smulleq r8, r3, r4, r5 + smullseq r8, r3, r4, r3 + +@ CHECK: smull r3, r9, r0, r1 @ encoding: [0x90,0x31,0xc9,0xe0] +@ CHECK: smulls r3, r9, r0, r2 @ encoding: [0x90,0x32,0xd9,0xe0] +@ CHECK: smulleq r8, r3, r4, r5 @ encoding: [0x94,0x85,0xc3,0x00] +@ CHECK: smullseq r8, r3, r4, r3 @ encoding: [0x94,0x83,0xd3,0x00] + + +@------------------------------------------------------------------------------ +@ SMULWB/SMULWT +@------------------------------------------------------------------------------ + smulwb r3, r9, r0 + smulwt r3, r9, r2 + +@ CHECK: smulwb r3, r9, r0 @ encoding: [0xa9,0x00,0x23,0xe1] +@ CHECK: smulwt r3, r9, r2 @ encoding: [0xe9,0x02,0x23,0xe1] + + +@------------------------------------------------------------------------------ +@ SMUSD/SMUSDX +@------------------------------------------------------------------------------ + smusd r3, r0, r1 + smusdx r3, r9, r2 + smusdeq r8, r3, r2 + smusdxne r7, r4, r3 + +@ CHECK: smusd r3, r0, r1 @ encoding: [0x50,0xf1,0x03,0xe7] +@ CHECK: smusdx r3, r9, r2 @ encoding: [0x79,0xf2,0x03,0xe7] +@ CHECK: smusdeq r8, r3, r2 @ encoding: [0x53,0xf2,0x08,0x07] +@ CHECK: smusdxne r7, r4, r3 @ encoding: [0x74,0xf3,0x07,0x17] + + +@------------------------------------------------------------------------------ +@ SRS +@------------------------------------------------------------------------------ + srsda sp, #5 + srsdb sp, #1 + srsia sp, #0 + srsib sp, #15 + + srsda sp!, #31 + srsdb sp!, #19 + srsia sp!, #2 + srsib sp!, #14 + + srsfa sp, #11 + srsea sp, #10 + srsfd sp, #9 + srsed sp, #5 + + srsfa sp!, #5 + srsea sp!, #5 + srsfd sp!, #5 + srsed sp!, #5 + + srs sp, #5 + srs sp!, #5 + +@ CHECK: srsda sp, #5 @ encoding: [0x05,0x05,0x4d,0xf8] +@ CHECK: srsdb sp, #1 @ encoding: [0x01,0x05,0x4d,0xf9] +@ CHECK: srsia sp, #0 @ encoding: [0x00,0x05,0xcd,0xf8] +@ CHECK: srsib sp, #15 @ encoding: [0x0f,0x05,0xcd,0xf9] + +@ CHECK: srsda sp!, #31 @ encoding: [0x1f,0x05,0x6d,0xf8] +@ CHECK: srsdb sp!, #19 @ encoding: [0x13,0x05,0x6d,0xf9] +@ CHECK: srsia sp!, #2 @ encoding: [0x02,0x05,0xed,0xf8] +@ CHECK: srsib sp!, #14 @ encoding: [0x0e,0x05,0xed,0xf9] + +@ CHECK: srsda sp, #11 @ encoding: [0x0b,0x05,0x4d,0xf8] +@ CHECK: srsdb sp, #10 @ encoding: [0x0a,0x05,0x4d,0xf9] +@ CHECK: srsia sp, #9 @ encoding: [0x09,0x05,0xcd,0xf8] +@ CHECK: srsib sp, #5 @ encoding: [0x05,0x05,0xcd,0xf9] + +@ CHECK: srsda sp!, #5 @ encoding: [0x05,0x05,0x6d,0xf8] +@ CHECK: srsdb sp!, #5 @ encoding: [0x05,0x05,0x6d,0xf9] +@ CHECK: srsia sp!, #5 @ encoding: [0x05,0x05,0xed,0xf8] +@ CHECK: srsib sp!, #5 @ encoding: [0x05,0x05,0xed,0xf9] + +@ CHECK: srsia sp, #5 @ encoding: [0x05,0x05,0xcd,0xf8] +@ CHECK: srsia sp!, #5 @ encoding: [0x05,0x05,0xed,0xf8] + + +@------------------------------------------------------------------------------ +@ SSAT +@------------------------------------------------------------------------------ + ssat r8, #1, r10 + ssat r8, #1, r10, lsl #0 + ssat r8, #1, r10, lsl #31 + ssat r8, #1, r10, asr #32 + ssat r8, #1, r10, asr #1 + +@ CHECK: ssat r8, #1, r10 @ encoding: [0x1a,0x80,0xa0,0xe6] +@ CHECK: ssat r8, #1, r10 @ encoding: [0x1a,0x80,0xa0,0xe6] +@ CHECK: ssat r8, #1, r10, lsl #31 @ encoding: [0x9a,0x8f,0xa0,0xe6] +@ CHECK: ssat r8, #1, r10, asr #32 @ encoding: [0x5a,0x80,0xa0,0xe6] +@ CHECK: ssat r8, #1, r10, asr #1 @ encoding: [0xda,0x80,0xa0,0xe6] + + +@------------------------------------------------------------------------------ +@ SSAT16 +@------------------------------------------------------------------------------ + ssat16 r2, #1, r7 + ssat16 r3, #16, r5 + +@ CHECK: ssat16 r2, #1, r7 @ encoding: [0x37,0x2f,0xa0,0xe6] +@ CHECK: ssat16 r3, #16, r5 @ encoding: [0x35,0x3f,0xaf,0xe6] + + +@------------------------------------------------------------------------------ +@ SSAX +@------------------------------------------------------------------------------ + ssax r2, r3, r4 + ssaxlt r2, r3, r4 + +@ CHECK: ssax r2, r3, r4 @ encoding: [0x54,0x2f,0x13,0xe6] +@ CHECK: ssaxlt r2, r3, r4 @ encoding: [0x54,0x2f,0x13,0xb6] + +@------------------------------------------------------------------------------ +@ SSUB16/SSUB8 +@------------------------------------------------------------------------------ + ssub16 r1, r0, r6 + ssub16ne r5, r3, r2 + ssub8 r9, r2, r4 + ssub8eq r5, r1, r2 + +@ CHECK: ssub16 r1, r0, r6 @ encoding: [0x76,0x1f,0x10,0xe6] +@ CHECK: ssub16ne r5, r3, r2 @ encoding: [0x72,0x5f,0x13,0x16] +@ CHECK: ssub8 r9, r2, r4 @ encoding: [0xf4,0x9f,0x12,0xe6] +@ CHECK: ssub8eq r5, r1, r2 @ encoding: [0xf2,0x5f,0x11,0x06] + +@------------------------------------------------------------------------------ +@ STC{L}/STC2{L} +@------------------------------------------------------------------------------ + stc2 p0, c8, [r1, #4] + stc2 p1, c7, [r2] + stc2 p2, c6, [r3, #-224] + stc2 p3, c5, [r4, #-120]! + stc2 p4, c4, [r5], #16 + stc2 p5, c3, [r6], #-72 + stc2l p6, c2, [r7, #4] + stc2l p7, c1, [r8] + stc2l p8, c0, [r9, #-224] + stc2l p9, c1, [r10, #-120]! + stc2l p10, c2, [r11], #16 + stc2l p11, c3, [r12], #-72 + + stc p12, c4, [r0, #4] + stc p13, c5, [r1] + stc p14, c6, [r2, #-224] + stc p15, c7, [r3, #-120]! + stc p5, c8, [r4], #16 + stc p4, c9, [r5], #-72 + stcl p3, c10, [r6, #4] + stcl p2, c11, [r7] + stcl p1, c12, [r8, #-224] + stcl p0, c13, [r9, #-120]! + stcl p6, c14, [r10], #16 + stcl p7, c15, [r11], #-72 + + stclo p12, c4, [r0, #4] + stchi p13, c5, [r1] + stccs p14, c6, [r2, #-224] + stccc p15, c7, [r3, #-120]! + stceq p5, c8, [r4], #16 + stcgt p4, c9, [r5], #-72 + stcllt p3, c10, [r6, #4] + stclge p2, c11, [r7] + stclle p1, c12, [r8, #-224] + stclne p0, c13, [r9, #-120]! + stcleq p6, c14, [r10], #16 + stclhi p7, c15, [r11], #-72 + + stc2 p2, c8, [r1], { 25 } + +@ CHECK: stc2 p0, c8, [r1, #4] @ encoding: [0x01,0x80,0x81,0xfd] +@ CHECK: stc2 p1, c7, [r2] @ encoding: [0x00,0x71,0x82,0xfd] +@ CHECK: stc2 p2, c6, [r3, #-224] @ encoding: [0x38,0x62,0x03,0xfd] +@ CHECK: stc2 p3, c5, [r4, #-120]! @ encoding: [0x1e,0x53,0x24,0xfd] +@ CHECK: stc2 p4, c4, [r5], #16 @ encoding: [0x04,0x44,0xa5,0xfc] +@ CHECK: stc2 p5, c3, [r6], #-72 @ encoding: [0x12,0x35,0x26,0xfc] +@ CHECK: stc2l p6, c2, [r7, #4] @ encoding: [0x01,0x26,0xc7,0xfd] +@ CHECK: stc2l p7, c1, [r8] @ encoding: [0x00,0x17,0xc8,0xfd] +@ CHECK: stc2l p8, c0, [r9, #-224] @ encoding: [0x38,0x08,0x49,0xfd] +@ CHECK: stc2l p9, c1, [r10, #-120]! @ encoding: [0x1e,0x19,0x6a,0xfd] +@ CHECK: stc2l p10, c2, [r11], #16 @ encoding: [0x04,0x2a,0xeb,0xfc] +@ CHECK: stc2l p11, c3, [r12], #-72 @ encoding: [0x12,0x3b,0x6c,0xfc] + +@ CHECK: stc p12, c4, [r0, #4] @ encoding: [0x01,0x4c,0x80,0xed] +@ CHECK: stc p13, c5, [r1] @ encoding: [0x00,0x5d,0x81,0xed] +@ CHECK: stc p14, c6, [r2, #-224] @ encoding: [0x38,0x6e,0x02,0xed] +@ CHECK: stc p15, c7, [r3, #-120]! @ encoding: [0x1e,0x7f,0x23,0xed] +@ CHECK: stc p5, c8, [r4], #16 @ encoding: [0x04,0x85,0xa4,0xec] +@ CHECK: stc p4, c9, [r5], #-72 @ encoding: [0x12,0x94,0x25,0xec] +@ CHECK: stcl p3, c10, [r6, #4] @ encoding: [0x01,0xa3,0xc6,0xed] +@ CHECK: stcl p2, c11, [r7] @ encoding: [0x00,0xb2,0xc7,0xed] +@ CHECK: stcl p1, c12, [r8, #-224] @ encoding: [0x38,0xc1,0x48,0xed] +@ CHECK: stcl p0, c13, [r9, #-120]! @ encoding: [0x1e,0xd0,0x69,0xed] +@ CHECK: stcl p6, c14, [r10], #16 @ encoding: [0x04,0xe6,0xea,0xec] +@ CHECK: stcl p7, c15, [r11], #-72 @ encoding: [0x12,0xf7,0x6b,0xec] + +@ CHECK: stclo p12, c4, [r0, #4] @ encoding: [0x01,0x4c,0x80,0x3d] +@ CHECK: stchi p13, c5, [r1] @ encoding: [0x00,0x5d,0x81,0x8d] +@ CHECK: stchs p14, c6, [r2, #-224] @ encoding: [0x38,0x6e,0x02,0x2d] +@ CHECK: stclo p15, c7, [r3, #-120]! @ encoding: [0x1e,0x7f,0x23,0x3d] +@ CHECK: stceq p5, c8, [r4], #16 @ encoding: [0x04,0x85,0xa4,0x0c] +@ CHECK: stcgt p4, c9, [r5], #-72 @ encoding: [0x12,0x94,0x25,0xcc] +@ CHECK: stcllt p3, c10, [r6, #4] @ encoding: [0x01,0xa3,0xc6,0xbd] +@ CHECK: stclge p2, c11, [r7] @ encoding: [0x00,0xb2,0xc7,0xad] +@ CHECK: stclle p1, c12, [r8, #-224] @ encoding: [0x38,0xc1,0x48,0xdd] +@ CHECK: stclne p0, c13, [r9, #-120]! @ encoding: [0x1e,0xd0,0x69,0x1d] +@ CHECK: stcleq p6, c14, [r10], #16 @ encoding: [0x04,0xe6,0xea,0x0c] +@ CHECK: stclhi p7, c15, [r11], #-72 @ encoding: [0x12,0xf7,0x6b,0x8c] + +@ CHECK: stc2 p2, c8, [r1], {25} @ encoding: [0x19,0x82,0x81,0xfc] + + +@------------------------------------------------------------------------------ @ STM* @------------------------------------------------------------------------------ stm r2, {r1,r3-r6,sp} - stmia r2, {r1,r3-r6,sp} - stmib r2, {r1,r3-r6,sp} - stmda r2, {r1,r3-r6,sp} - stmdb r2, {r1,r3-r6,sp} - stmfd r2, {r1,r3-r6,sp} + stmia r3, {r1,r3-r6,lr} + stmib r4, {r1,r3-r6,sp} + stmda r5, {r1,r3-r6,sp} + stmdb r6, {r1,r3-r6,r8} + stmfd sp, {r1,r3-r6,sp} @ with update - stmia r2!, {r1,r3-r6,sp} - stmib r2!, {r1,r3-r6,sp} - stmda r2!, {r1,r3-r6,sp} - stmdb r2!, {r1,r3-r6,sp} -@ CHECK: stm r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe8] -@ CHECK: stm r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe8] -@ CHECK: stmib r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe9] -@ CHECK: stmda r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x02,0xe8] -@ CHECK: stmdb r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x02,0xe9] -@ CHECK: stmdb r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x02,0xe9] - -@ CHECK: stm r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa2,0xe8] -@ CHECK: stmib r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa2,0xe9] -@ CHECK: stmda r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x22,0xe8] -@ CHECK: stmdb r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x22,0xe9] + stm r8!, {r1,r3-r6,sp} + stmib r9!, {r1,r3-r6,sp} + stmda sp!, {r1,r3-r6} + stmdb r0!, {r1,r5,r7,sp} + +@ CHECK: stm r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe8] +@ CHECK: stm r3, {lr, r1, r3, r4, r5, r6} @ encoding: [0x7a,0x40,0x83,0xe8] +@ CHECK: stmib r4, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x84,0xe9] +@ CHECK: stmda r5, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x05,0xe8] +@ CHECK: stmdb r6, {r1, r3, r4, r5, r6, r8} @ encoding: [0x7a,0x01,0x06,0xe9] +@ CHECK: stmdb sp, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x0d,0xe9] + +@ CHECK: stm r8!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa8,0xe8] +@ CHECK: stmib r9!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa9,0xe9] +@ CHECK: stmda sp!, {r1, r3, r4, r5, r6} @ encoding: [0x7a,0x00,0x2d,0xe8] +@ CHECK: stmdb r0!, {r1, r5, r7, sp} @ encoding: [0xa2,0x20,0x20,0xe9] + + +@------------------------------------------------------------------------------ +@ STREX/STREXB/STREXH/STREXD +@------------------------------------------------------------------------------ + strexb r1, r3, [r4] + strexh r4, r2, [r5] + strex r2, r1, [r7] + strexd r6, r2, r3, [r8] + +@ CHECK: strexb r1, r3, [r4] @ encoding: [0x93,0x1f,0xc4,0xe1] +@ CHECK: strexh r4, r2, [r5] @ encoding: [0x92,0x4f,0xe5,0xe1] +@ CHECK: strex r2, r1, [r7] @ encoding: [0x91,0x2f,0x87,0xe1] +@ CHECK: strexd r6, r2, r3, [r8] @ encoding: [0x92,0x6f,0xa8,0xe1] + +@------------------------------------------------------------------------------ +@ STR +@------------------------------------------------------------------------------ + strpl r3, [r10, #-0]! + strpl r3, [r10, #0]! + +@ CHECK: strpl r3, [r10, #-0]! @ encoding: [0x00,0x30,0x2a,0x55] +@ CHECK: strpl r3, [r10]! @ encoding: [0x00,0x30,0xaa,0x55] + +@------------------------------------------------------------------------------ +@ SUB +@------------------------------------------------------------------------------ + sub r4, r5, #0xf000 + sub r4, r5, r6 + sub r4, r5, r6, lsl #5 + sub r4, r5, r6, lsr #5 + sub r4, r5, r6, lsr #5 + sub r4, r5, r6, asr #5 + sub r4, r5, r6, ror #5 + sub r6, r7, r8, lsl r9 + sub r6, r7, r8, lsr r9 + sub r6, r7, r8, asr r9 + sub r6, r7, r8, ror r9 + + @ destination register is optional + sub r5, #0xf000 + sub r4, r5 + sub r4, r5, lsl #5 + sub r4, r5, lsr #5 + sub r4, r5, lsr #5 + sub r4, r5, asr #5 + sub r4, r5, ror #5 + sub r6, r7, lsl r9 + sub r6, r7, lsr r9 + sub r6, r7, asr r9 + sub r6, r7, ror r9 + +@ CHECK: sub r4, r5, #61440 @ encoding: [0x0f,0x4a,0x45,0xe2] +@ CHECK: sub r4, r5, r6 @ encoding: [0x06,0x40,0x45,0xe0] +@ CHECK: sub r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x45,0xe0] +@ CHECK: sub r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x45,0xe0] +@ CHECK: sub r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x45,0xe0] +@ CHECK: sub r4, r5, r6, asr #5 @ encoding: [0xc6,0x42,0x45,0xe0] +@ CHECK: sub r4, r5, r6, ror #5 @ encoding: [0xe6,0x42,0x45,0xe0] +@ CHECK: sub r6, r7, r8, lsl r9 @ encoding: [0x18,0x69,0x47,0xe0] +@ CHECK: sub r6, r7, r8, lsr r9 @ encoding: [0x38,0x69,0x47,0xe0] +@ CHECK: sub r6, r7, r8, asr r9 @ encoding: [0x58,0x69,0x47,0xe0] +@ CHECK: sub r6, r7, r8, ror r9 @ encoding: [0x78,0x69,0x47,0xe0] + + +@ CHECK: sub r5, r5, #61440 @ encoding: [0x0f,0x5a,0x45,0xe2] +@ CHECK: sub r4, r4, r5 @ encoding: [0x05,0x40,0x44,0xe0] +@ CHECK: sub r4, r4, r5, lsl #5 @ encoding: [0x85,0x42,0x44,0xe0] +@ CHECK: sub r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x44,0xe0] +@ CHECK: sub r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x44,0xe0] +@ CHECK: sub r4, r4, r5, asr #5 @ encoding: [0xc5,0x42,0x44,0xe0] +@ CHECK: sub r4, r4, r5, ror #5 @ encoding: [0xe5,0x42,0x44,0xe0] +@ CHECK: sub r6, r6, r7, lsl r9 @ encoding: [0x17,0x69,0x46,0xe0] +@ CHECK: sub r6, r6, r7, lsr r9 @ encoding: [0x37,0x69,0x46,0xe0] +@ CHECK: sub r6, r6, r7, asr r9 @ encoding: [0x57,0x69,0x46,0xe0] +@ CHECK: sub r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0x46,0xe0] + + +@------------------------------------------------------------------------------ +@ SVC +@------------------------------------------------------------------------------ + svc #16 + svc #0 + svc #0xffffff + +@ CHECK: svc #16 @ encoding: [0x10,0x00,0x00,0xef] +@ CHECK: svc #0 @ encoding: [0x00,0x00,0x00,0xef] +@ CHECK: svc #16777215 @ encoding: [0xff,0xff,0xff,0xef] + + +@------------------------------------------------------------------------------ +@ SWP/SWPB +@------------------------------------------------------------------------------ + swp r1, r2, [r3] + swp r4, r4, [r6] + swpb r5, r1, [r9] + +@ CHECK: swp r1, r2, [r3] @ encoding: [0x92,0x10,0x03,0xe1] +@ CHECK: swp r4, r4, [r6] @ encoding: [0x94,0x40,0x06,0xe1] +@ CHECK: swpb r5, r1, [r9] @ encoding: [0x91,0x50,0x49,0xe1] + + +@------------------------------------------------------------------------------ +@ SXTAB +@------------------------------------------------------------------------------ + sxtab r2, r3, r4 + sxtab r4, r5, r6, ror #0 + sxtablt r6, r2, r9, ror #8 + sxtab r5, r1, r4, ror #16 + sxtab r7, r8, r3, ror #24 + +@ CHECK: sxtab r2, r3, r4 @ encoding: [0x74,0x20,0xa3,0xe6] +@ CHECK: sxtab r4, r5, r6 @ encoding: [0x76,0x40,0xa5,0xe6] +@ CHECK: sxtablt r6, r2, r9, ror #8 @ encoding: [0x79,0x64,0xa2,0xb6] +@ CHECK: sxtab r5, r1, r4, ror #16 @ encoding: [0x74,0x58,0xa1,0xe6] +@ CHECK: sxtab r7, r8, r3, ror #24 @ encoding: [0x73,0x7c,0xa8,0xe6] + + +@------------------------------------------------------------------------------ +@ SXTAB16 +@------------------------------------------------------------------------------ + sxtab16ge r0, r1, r4 + sxtab16 r6, r2, r7, ror #0 + sxtab16 r3, r5, r8, ror #8 + sxtab16 r3, r2, r1, ror #16 + sxtab16eq r1, r2, r3, ror #24 + +@ CHECK: sxtab16ge r0, r1, r4 @ encoding: [0x74,0x00,0x81,0xa6] +@ CHECK: sxtab16 r6, r2, r7 @ encoding: [0x77,0x60,0x82,0xe6] +@ CHECK: sxtab16 r3, r5, r8, ror #8 @ encoding: [0x78,0x34,0x85,0xe6] +@ CHECK: sxtab16 r3, r2, r1, ror #16 @ encoding: [0x71,0x38,0x82,0xe6] +@ CHECK: sxtab16eq r1, r2, r3, ror #24 @ encoding: [0x73,0x1c,0x82,0x06] + +@------------------------------------------------------------------------------ +@ SXTAH +@------------------------------------------------------------------------------ + sxtah r1, r3, r9 + sxtahhi r6, r1, r6, ror #0 + sxtah r3, r8, r3, ror #8 + sxtahlo r2, r2, r4, ror #16 + sxtah r9, r3, r3, ror #24 + +@ CHECK: sxtah r1, r3, r9 @ encoding: [0x79,0x10,0xb3,0xe6] +@ CHECK: sxtahhi r6, r1, r6 @ encoding: [0x76,0x60,0xb1,0x86] +@ CHECK: sxtah r3, r8, r3, ror #8 @ encoding: [0x73,0x34,0xb8,0xe6] +@ CHECK: sxtahlo r2, r2, r4, ror #16 @ encoding: [0x74,0x28,0xb2,0x36] +@ CHECK: sxtah r9, r3, r3, ror #24 @ encoding: [0x73,0x9c,0xb3,0xe6] + +@------------------------------------------------------------------------------ +@ SXTB +@------------------------------------------------------------------------------ + sxtbge r2, r4 + sxtb r5, r6, ror #0 + sxtb r6, r9, ror #8 + sxtbcc r5, r1, ror #16 + sxtb r8, r3, ror #24 + +@ CHECK: sxtbge r2, r4 @ encoding: [0x74,0x20,0xaf,0xa6] +@ CHECK: sxtb r5, r6 @ encoding: [0x76,0x50,0xaf,0xe6] +@ CHECK: sxtb r6, r9, ror #8 @ encoding: [0x79,0x64,0xaf,0xe6] +@ CHECK: sxtblo r5, r1, ror #16 @ encoding: [0x71,0x58,0xaf,0x36] +@ CHECK: sxtb r8, r3, ror #24 @ encoding: [0x73,0x8c,0xaf,0xe6] + + +@------------------------------------------------------------------------------ +@ SXTB16 +@------------------------------------------------------------------------------ + sxtb16 r1, r4 + sxtb16 r6, r7, ror #0 + sxtb16cs r3, r5, ror #8 + sxtb16 r3, r1, ror #16 + sxtb16ge r2, r3, ror #24 + +@ CHECK: sxtb16 r1, r4 @ encoding: [0x74,0x10,0x8f,0xe6] +@ CHECK: sxtb16 r6, r7 @ encoding: [0x77,0x60,0x8f,0xe6] +@ CHECK: sxtb16hs r3, r5, ror #8 @ encoding: [0x75,0x34,0x8f,0x26] +@ CHECK: sxtb16 r3, r1, ror #16 @ encoding: [0x71,0x38,0x8f,0xe6] +@ CHECK: sxtb16ge r2, r3, ror #24 @ encoding: [0x73,0x2c,0x8f,0xa6] + + +@------------------------------------------------------------------------------ +@ SXTH +@------------------------------------------------------------------------------ + sxthne r3, r9 + sxth r1, r6, ror #0 + sxth r3, r8, ror #8 + sxthle r2, r2, ror #16 + sxth r9, r3, ror #24 + +@ CHECK: sxthne r3, r9 @ encoding: [0x79,0x30,0xbf,0x16] +@ CHECK: sxth r1, r6 @ encoding: [0x76,0x10,0xbf,0xe6] +@ CHECK: sxth r3, r8, ror #8 @ encoding: [0x78,0x34,0xbf,0xe6] +@ CHECK: sxthle r2, r2, ror #16 @ encoding: [0x72,0x28,0xbf,0xd6] +@ CHECK: sxth r9, r3, ror #24 @ encoding: [0x73,0x9c,0xbf,0xe6] + + +@------------------------------------------------------------------------------ +@ TEQ +@------------------------------------------------------------------------------ + teq r5, #0xf000 + teq r4, r5 + teq r4, r5, lsl #5 + teq r4, r5, lsr #5 + teq r4, r5, lsr #5 + teq r4, r5, asr #5 + teq r4, r5, ror #5 + teq r6, r7, lsl r9 + teq r6, r7, lsr r9 + teq r6, r7, asr r9 + teq r6, r7, ror r9 + +@ CHECK: teq r5, #61440 @ encoding: [0x0f,0x0a,0x35,0xe3] +@ CHECK: teq r4, r5 @ encoding: [0x05,0x00,0x34,0xe1] +@ CHECK: teq r4, r5, lsl #5 @ encoding: [0x85,0x02,0x34,0xe1] +@ CHECK: teq r4, r5, lsr #5 @ encoding: [0xa5,0x02,0x34,0xe1] +@ CHECK: teq r4, r5, lsr #5 @ encoding: [0xa5,0x02,0x34,0xe1] +@ CHECK: teq r4, r5, asr #5 @ encoding: [0xc5,0x02,0x34,0xe1] +@ CHECK: teq r4, r5, ror #5 @ encoding: [0xe5,0x02,0x34,0xe1] +@ CHECK: teq r6, r7, lsl r9 @ encoding: [0x17,0x09,0x36,0xe1] +@ CHECK: teq r6, r7, lsr r9 @ encoding: [0x37,0x09,0x36,0xe1] +@ CHECK: teq r6, r7, asr r9 @ encoding: [0x57,0x09,0x36,0xe1] +@ CHECK: teq r6, r7, ror r9 @ encoding: [0x77,0x09,0x36,0xe1] + + +@------------------------------------------------------------------------------ +@ TST +@------------------------------------------------------------------------------ + tst r5, #0xf000 + tst r4, r5 + tst r4, r5, lsl #5 + tst r4, r5, lsr #5 + tst r4, r5, lsr #5 + tst r4, r5, asr #5 + tst r4, r5, ror #5 + tst r6, r7, lsl r9 + tst r6, r7, lsr r9 + tst r6, r7, asr r9 + tst r6, r7, ror r9 + +@ CHECK: tst r5, #61440 @ encoding: [0x0f,0x0a,0x15,0xe3] +@ CHECK: tst r4, r5 @ encoding: [0x05,0x00,0x14,0xe1] +@ CHECK: tst r4, r5, lsl #5 @ encoding: [0x85,0x02,0x14,0xe1] +@ CHECK: tst r4, r5, lsr #5 @ encoding: [0xa5,0x02,0x14,0xe1] +@ CHECK: tst r4, r5, lsr #5 @ encoding: [0xa5,0x02,0x14,0xe1] +@ CHECK: tst r4, r5, asr #5 @ encoding: [0xc5,0x02,0x14,0xe1] +@ CHECK: tst r4, r5, ror #5 @ encoding: [0xe5,0x02,0x14,0xe1] +@ CHECK: tst r6, r7, lsl r9 @ encoding: [0x17,0x09,0x16,0xe1] +@ CHECK: tst r6, r7, lsr r9 @ encoding: [0x37,0x09,0x16,0xe1] +@ CHECK: tst r6, r7, asr r9 @ encoding: [0x57,0x09,0x16,0xe1] +@ CHECK: tst r6, r7, ror r9 @ encoding: [0x77,0x09,0x16,0xe1] + + +@------------------------------------------------------------------------------ +@ UADD16/UADD8 +@------------------------------------------------------------------------------ + uadd16 r1, r2, r3 + uadd16gt r1, r2, r3 + uadd8 r1, r2, r3 + uadd8le r1, r2, r3 + +@ CHECK: uadd16 r1, r2, r3 @ encoding: [0x13,0x1f,0x52,0xe6] +@ CHECK: uadd16gt r1, r2, r3 @ encoding: [0x13,0x1f,0x52,0xc6] +@ CHECK: uadd8 r1, r2, r3 @ encoding: [0x93,0x1f,0x52,0xe6] +@ CHECK: uadd8le r1, r2, r3 @ encoding: [0x93,0x1f,0x52,0xd6] + + +@------------------------------------------------------------------------------ +@ UASX +@------------------------------------------------------------------------------ + uasx r9, r12, r0 + uasxeq r9, r12, r0 + +@ CHECK: uasx r9, r12, r0 @ encoding: [0x30,0x9f,0x5c,0xe6] +@ CHECK: uasxeq r9, r12, r0 @ encoding: [0x30,0x9f,0x5c,0x06] + + +@------------------------------------------------------------------------------ +@ UBFX +@------------------------------------------------------------------------------ + ubfx r4, r5, #16, #1 + ubfxgt r4, r5, #16, #16 + +@ CHECK: ubfx r4, r5, #16, #1 @ encoding: [0x55,0x48,0xe0,0xe7] +@ CHECK: ubfxgt r4, r5, #16, #16 @ encoding: [0x55,0x48,0xef,0xc7] + + +@------------------------------------------------------------------------------ +@ UHADD16/UHADD8 +@------------------------------------------------------------------------------ + uhadd16 r4, r8, r2 + uhadd16gt r4, r8, r2 + uhadd8 r4, r8, r2 + uhadd8gt r4, r8, r2 + +@ CHECK: uhadd16 r4, r8, r2 @ encoding: [0x12,0x4f,0x78,0xe6] +@ CHECK: uhadd16gt r4, r8, r2 @ encoding: [0x12,0x4f,0x78,0xc6] +@ CHECK: uhadd8 r4, r8, r2 @ encoding: [0x92,0x4f,0x78,0xe6] +@ CHECK: uhadd8gt r4, r8, r2 @ encoding: [0x92,0x4f,0x78,0xc6] + + +@------------------------------------------------------------------------------ +@ UHASX +@------------------------------------------------------------------------------ + uhasx r4, r8, r2 + uhasxgt r4, r8, r2 + +@ CHECK: uhasx r4, r8, r2 @ encoding: [0x32,0x4f,0x78,0xe6] +@ CHECK: uhasxgt r4, r8, r2 @ encoding: [0x32,0x4f,0x78,0xc6] + + +@------------------------------------------------------------------------------ +@ UHSUB16/UHSUB8 +@------------------------------------------------------------------------------ + uhsub16 r4, r8, r2 + uhsub16gt r4, r8, r2 + uhsub8 r4, r8, r2 + uhsub8gt r4, r8, r2 + +@ CHECK: uhsub16 r4, r8, r2 @ encoding: [0x72,0x4f,0x78,0xe6] +@ CHECK: uhsub16gt r4, r8, r2 @ encoding: [0x72,0x4f,0x78,0xc6] +@ CHECK: uhsub8 r4, r8, r2 @ encoding: [0xf2,0x4f,0x78,0xe6] +@ CHECK: uhsub8gt r4, r8, r2 @ encoding: [0xf2,0x4f,0x78,0xc6] + + +@------------------------------------------------------------------------------ +@ UMAAL +@------------------------------------------------------------------------------ + umaal r3, r4, r5, r6 + umaallt r3, r4, r5, r6 + +@ CHECK: umaal r3, r4, r5, r6 @ encoding: [0x95,0x36,0x44,0xe0] +@ CHECK: umaallt r3, r4, r5, r6 @ encoding: [0x95,0x36,0x44,0xb0] + + +@------------------------------------------------------------------------------ +@ UMLAL +@------------------------------------------------------------------------------ + umlal r2, r4, r6, r8 + umlalgt r6, r1, r2, r6 + umlals r2, r9, r2, r3 + umlalseq r3, r5, r1, r2 + +@ CHECK: umlal r2, r4, r6, r8 @ encoding: [0x96,0x28,0xa4,0xe0] +@ CHECK: umlalgt r6, r1, r2, r6 @ encoding: [0x92,0x66,0xa1,0xc0] +@ CHECK: umlals r2, r9, r2, r3 @ encoding: [0x92,0x23,0xb9,0xe0] +@ CHECK: umlalseq r3, r5, r1, r2 @ encoding: [0x91,0x32,0xb5,0x00] + + +@------------------------------------------------------------------------------ +@ UMULL +@------------------------------------------------------------------------------ + umull r2, r4, r6, r8 + umullgt r6, r1, r2, r6 + umulls r2, r9, r2, r3 + umullseq r3, r5, r1, r2 + +@ CHECK: umull r2, r4, r6, r8 @ encoding: [0x96,0x28,0x84,0xe0] +@ CHECK: umullgt r6, r1, r2, r6 @ encoding: [0x92,0x66,0x81,0xc0] +@ CHECK: umulls r2, r9, r2, r3 @ encoding: [0x92,0x23,0x99,0xe0] +@ CHECK: umullseq r3, r5, r1, r2 @ encoding: [0x91,0x32,0x95,0x00] + + +@------------------------------------------------------------------------------ +@ UQADD16/UQADD8 +@------------------------------------------------------------------------------ + uqadd16 r1, r2, r3 + uqadd16gt r4, r7, r9 + uqadd8 r3, r4, r8 + uqadd8le r8, r1, r2 + + +@ CHECK: uqadd16 r1, r2, r3 @ encoding: [0x13,0x1f,0x62,0xe6] +@ CHECK: uqadd16gt r4, r7, r9 @ encoding: [0x19,0x4f,0x67,0xc6] +@ CHECK: uqadd8 r3, r4, r8 @ encoding: [0x98,0x3f,0x64,0xe6] +@ CHECK: uqadd8le r8, r1, r2 @ encoding: [0x92,0x8f,0x61,0xd6] + + +@------------------------------------------------------------------------------ +@ UQASX +@------------------------------------------------------------------------------ + uqasx r2, r4, r1 + uqasxhi r5, r2, r9 + +@ CHECK: uqasx r2, r4, r1 @ encoding: [0x31,0x2f,0x64,0xe6] +@ CHECK: uqasxhi r5, r2, r9 @ encoding: [0x39,0x5f,0x62,0x86] + + +@------------------------------------------------------------------------------ +@ UQSAX +@------------------------------------------------------------------------------ + uqsax r1, r3, r7 + uqsaxal r3, r6, r2 + +@ CHECK: uqsax r1, r3, r7 @ encoding: [0x57,0x1f,0x63,0xe6] +@ CHECK: uqsax r3, r6, r2 @ encoding: [0x52,0x3f,0x66,0xe6] + + +@------------------------------------------------------------------------------ +@ UQSUB16/UQSUB8 +@------------------------------------------------------------------------------ + uqsub16 r1, r5, r3 + uqsub16gt r3, r2, r5 + uqsub8 r2, r1, r4 + uqsub8le r4, r6, r9 + +@ CHECK: uqsub16 r1, r5, r3 @ encoding: [0x73,0x1f,0x65,0xe6] +@ CHECK: uqsub16gt r3, r2, r5 @ encoding: [0x75,0x3f,0x62,0xc6] +@ CHECK: uqsub8 r2, r1, r4 @ encoding: [0xf4,0x2f,0x61,0xe6] +@ CHECK: uqsub8le r4, r6, r9 @ encoding: [0xf9,0x4f,0x66,0xd6] + + +@------------------------------------------------------------------------------ +@ USADA8/USAD8 +@------------------------------------------------------------------------------ + usad8 r2, r1, r4 + usad8le r4, r6, r9 + usada8 r1, r5, r3, r7 + usada8gt r3, r2, r5, r1 + +@ CHECK: usad8 r2, r1, r4 @ encoding: [0x11,0xf4,0x82,0xe7] +@ CHECK: usad8le r4, r6, r9 @ encoding: [0x16,0xf9,0x84,0xd7] +@ CHECK: usada8 r1, r5, r3, r7 @ encoding: [0x15,0x73,0x81,0xe7] +@ CHECK: usada8gt r3, r2, r5, r1 @ encoding: [0x12,0x15,0x83,0xc7] + + +@------------------------------------------------------------------------------ +@ USAT +@------------------------------------------------------------------------------ + usat r8, #1, r10 + usat r8, #4, r10, lsl #0 + usat r8, #5, r10, lsl #31 + usat r8, #31, r10, asr #32 + usat r8, #16, r10, asr #1 + +@ CHECK: usat r8, #1, r10 @ encoding: [0x1a,0x80,0xe1,0xe6] +@ CHECK: usat r8, #4, r10 @ encoding: [0x1a,0x80,0xe4,0xe6] +@ CHECK: usat r8, #5, r10, lsl #31 @ encoding: [0x9a,0x8f,0xe5,0xe6] +@ CHECK: usat r8, #31, r10, asr #32 @ encoding: [0x5a,0x80,0xff,0xe6] +@ CHECK: usat r8, #16, r10, asr #1 @ encoding: [0xda,0x80,0xf0,0xe6] + + +@------------------------------------------------------------------------------ +@ USAT16 +@------------------------------------------------------------------------------ + usat16 r2, #2, r7 + usat16 r3, #15, r5 + +@ CHECK: usat16 r2, #2, r7 @ encoding: [0x37,0x2f,0xe2,0xe6] +@ CHECK: usat16 r3, #15, r5 @ encoding: [0x35,0x3f,0xef,0xe6] + + +@------------------------------------------------------------------------------ +@ USAX +@------------------------------------------------------------------------------ + usax r2, r3, r4 + usaxne r2, r3, r4 + +@ CHECK: usax r2, r3, r4 @ encoding: [0x54,0x2f,0x53,0xe6] +@ CHECK: usaxne r2, r3, r4 @ encoding: [0x54,0x2f,0x53,0x16] + +@------------------------------------------------------------------------------ +@ USUB16/USUB8 +@------------------------------------------------------------------------------ + usub16 r4, r2, r7 + usub16hi r1, r1, r3 + usub8 r1, r8, r5 + usub8le r9, r2, r3 + +@ CHECK: usub16 r4, r2, r7 @ encoding: [0x77,0x4f,0x52,0xe6] +@ CHECK: usub16hi r1, r1, r3 @ encoding: [0x73,0x1f,0x51,0x86] +@ CHECK: usub8 r1, r8, r5 @ encoding: [0xf5,0x1f,0x58,0xe6] +@ CHECK: usub8le r9, r2, r3 @ encoding: [0xf3,0x9f,0x52,0xd6] + + +@------------------------------------------------------------------------------ +@ UXTAB +@------------------------------------------------------------------------------ + uxtab r2, r3, r4 + uxtab r4, r5, r6, ror #0 + uxtablt r6, r2, r9, ror #8 + uxtab r5, r1, r4, ror #16 + uxtab r7, r8, r3, ror #24 + +@ CHECK: uxtab r2, r3, r4 @ encoding: [0x74,0x20,0xe3,0xe6] +@ CHECK: uxtab r4, r5, r6 @ encoding: [0x76,0x40,0xe5,0xe6] +@ CHECK: uxtablt r6, r2, r9, ror #8 @ encoding: [0x79,0x64,0xe2,0xb6] +@ CHECK: uxtab r5, r1, r4, ror #16 @ encoding: [0x74,0x58,0xe1,0xe6] +@ CHECK: uxtab r7, r8, r3, ror #24 @ encoding: [0x73,0x7c,0xe8,0xe6] + + +@------------------------------------------------------------------------------ +@ UXTAB16 +@------------------------------------------------------------------------------ + uxtab16ge r0, r1, r4 + uxtab16 r6, r2, r7, ror #0 + uxtab16 r3, r5, r8, ror #8 + uxtab16 r3, r2, r1, ror #16 + uxtab16eq r1, r2, r3, ror #24 + +@ CHECK: uxtab16ge r0, r1, r4 @ encoding: [0x74,0x00,0xc1,0xa6] +@ CHECK: uxtab16 r6, r2, r7 @ encoding: [0x77,0x60,0xc2,0xe6] +@ CHECK: uxtab16 r3, r5, r8, ror #8 @ encoding: [0x78,0x34,0xc5,0xe6] +@ CHECK: uxtab16 r3, r2, r1, ror #16 @ encoding: [0x71,0x38,0xc2,0xe6] +@ CHECK: uxtab16eq r1, r2, r3, ror #24 @ encoding: [0x73,0x1c,0xc2,0x06] + + +@------------------------------------------------------------------------------ +@ UXTAH +@------------------------------------------------------------------------------ + uxtah r1, r3, r9 + uxtahhi r6, r1, r6, ror #0 + uxtah r3, r8, r3, ror #8 + uxtahlo r2, r2, r4, ror #16 + uxtah r9, r3, r3, ror #24 + +@ CHECK: uxtah r1, r3, r9 @ encoding: [0x79,0x10,0xf3,0xe6] +@ CHECK: uxtahhi r6, r1, r6 @ encoding: [0x76,0x60,0xf1,0x86] +@ CHECK: uxtah r3, r8, r3, ror #8 @ encoding: [0x73,0x34,0xf8,0xe6] +@ CHECK: uxtahlo r2, r2, r4, ror #16 @ encoding: [0x74,0x28,0xf2,0x36] +@ CHECK: uxtah r9, r3, r3, ror #24 @ encoding: [0x73,0x9c,0xf3,0xe6] + +@------------------------------------------------------------------------------ +@ UXTB +@------------------------------------------------------------------------------ + uxtbge r2, r4 + uxtb r5, r6, ror #0 + uxtb r6, r9, ror #8 + uxtbcc r5, r1, ror #16 + uxtb r8, r3, ror #24 + +@ CHECK: uxtbge r2, r4 @ encoding: [0x74,0x20,0xef,0xa6] +@ CHECK: uxtb r5, r6 @ encoding: [0x76,0x50,0xef,0xe6] +@ CHECK: uxtb r6, r9, ror #8 @ encoding: [0x79,0x64,0xef,0xe6] +@ CHECK: uxtblo r5, r1, ror #16 @ encoding: [0x71,0x58,0xef,0x36] +@ CHECK: uxtb r8, r3, ror #24 @ encoding: [0x73,0x8c,0xef,0xe6] + + +@------------------------------------------------------------------------------ +@ UXTB16 +@------------------------------------------------------------------------------ + uxtb16 r1, r4 + uxtb16 r6, r7, ror #0 + uxtb16cs r3, r5, ror #8 + uxtb16 r3, r1, ror #16 + uxtb16ge r2, r3, ror #24 + +@ CHECK: uxtb16 r1, r4 @ encoding: [0x74,0x10,0xcf,0xe6] +@ CHECK: uxtb16 r6, r7 @ encoding: [0x77,0x60,0xcf,0xe6] +@ CHECK: uxtb16hs r3, r5, ror #8 @ encoding: [0x75,0x34,0xcf,0x26] +@ CHECK: uxtb16 r3, r1, ror #16 @ encoding: [0x71,0x38,0xcf,0xe6] +@ CHECK: uxtb16ge r2, r3, ror #24 @ encoding: [0x73,0x2c,0xcf,0xa6] + + +@------------------------------------------------------------------------------ +@ UXTH +@------------------------------------------------------------------------------ + uxthne r3, r9 + uxth r1, r6, ror #0 + uxth r3, r8, ror #8 + uxthle r2, r2, ror #16 + uxth r9, r3, ror #24 + +@ CHECK: uxthne r3, r9 @ encoding: [0x79,0x30,0xff,0x16] +@ CHECK: uxth r1, r6 @ encoding: [0x76,0x10,0xff,0xe6] +@ CHECK: uxth r3, r8, ror #8 @ encoding: [0x78,0x34,0xff,0xe6] +@ CHECK: uxthle r2, r2, ror #16 @ encoding: [0x72,0x28,0xff,0xd6] +@ CHECK: uxth r9, r3, ror #24 @ encoding: [0x73,0x9c,0xff,0xe6] + + +@------------------------------------------------------------------------------ +@ WFE/WFI/YIELD +@------------------------------------------------------------------------------ + wfe + wfehi + wfi + wfilt + yield + yieldne + +@ CHECK: wfe @ encoding: [0x02,0xf0,0x20,0xe3] +@ CHECK: wfehi @ encoding: [0x02,0xf0,0x20,0x83] +@ CHECK: wfi @ encoding: [0x03,0xf0,0x20,0xe3] +@ CHECK: wfilt @ encoding: [0x03,0xf0,0x20,0xb3] +@ CHECK: yield @ encoding: [0x01,0xf0,0x20,0xe3] +@ CHECK: yieldne @ encoding: [0x01,0xf0,0x20,0x13] diff --git a/test/MC/ARM/basic-thumb-instructions.s b/test/MC/ARM/basic-thumb-instructions.s new file mode 100644 index 0000000..0fa52b0 --- /dev/null +++ b/test/MC/ARM/basic-thumb-instructions.s @@ -0,0 +1,623 @@ +@--- +@ Run these test in both Thumb1 and Thumb2 modes, as all of the encodings +@ should be valid, and parse the same, in both. +@--- +@ RUN: llvm-mc -triple=thumbv6-apple-darwin -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -triple=thumbv7-apple-darwin -show-encoding < %s | FileCheck %s + .syntax unified + .globl _func + +@ Check that the assembler can handle the documented syntax from the ARM ARM. +@ For complex constructs like shifter operands, check more thoroughly for them +@ once then spot check that following instructions accept the form generally. +@ This gives us good coverage while keeping the overall size of the test +@ more reasonable. + + +@ FIXME: Some 3-operand instructions have a 2-operand assembly syntax. + +_func: +@ CHECK: _func + +@------------------------------------------------------------------------------ +@ ADC (register) +@------------------------------------------------------------------------------ + adcs r4, r6 + +@ CHECK: adcs r4, r6 @ encoding: [0x74,0x41] + + +@------------------------------------------------------------------------------ +@ ADD (immediate) +@------------------------------------------------------------------------------ + adds r1, r2, #3 +@ When Rd is not explicitly specified, encoding T2 is preferred even though +@ the literal is in the range [0,7] which would allow encoding T1. + adds r2, #3 + adds r2, #8 + +@ CHECK: adds r1, r2, #3 @ encoding: [0xd1,0x1c] +@ CHECK: adds r2, #3 @ encoding: [0x03,0x32] +@ CHECK: adds r2, #8 @ encoding: [0x08,0x32] + + +@------------------------------------------------------------------------------ +@ ADD (register) +@------------------------------------------------------------------------------ + adds r1, r2, r3 + add r2, r8 + +@ CHECK: adds r1, r2, r3 @ encoding: [0xd1,0x18] +@ CHECK: add r2, r8 @ encoding: [0x42,0x44] + + +@------------------------------------------------------------------------------ +@ ADD (SP plus immediate) +@------------------------------------------------------------------------------ + add sp, #4 + add sp, #508 + add sp, sp, #4 + add r2, sp, #8 + add r2, sp, #1020 + +@ CHECK: add sp, #4 @ encoding: [0x01,0xb0] +@ CHECK: add sp, #508 @ encoding: [0x7f,0xb0] +@ CHECK: add sp, #4 @ encoding: [0x01,0xb0] +@ CHECK: add r2, sp, #8 @ encoding: [0x02,0xaa] +@ CHECK: add r2, sp, #1020 @ encoding: [0xff,0xaa] + + +@------------------------------------------------------------------------------ +@ ADD (SP plus register) +@------------------------------------------------------------------------------ + add sp, r3 + add r2, sp, r2 + +@ CHECK: add sp, r3 @ encoding: [0x9d,0x44] +@ CHECK: add r2, sp, r2 @ encoding: [0x6a,0x44] + + +@------------------------------------------------------------------------------ +@ ADR +@------------------------------------------------------------------------------ + adr r2, _baz + adr r2, #3 + +@ CHECK: adr r2, _baz @ encoding: [A,0xa2] + @ fixup A - offset: 0, value: _baz, kind: fixup_thumb_adr_pcrel_10 +@ CHECK: adr r2, #3 @ encoding: [0x03,0xa2] + +@------------------------------------------------------------------------------ +@ ASR (immediate) +@------------------------------------------------------------------------------ + asrs r2, r3, #32 + asrs r2, r3, #5 + asrs r2, r3, #1 + +@ CHECK: asrs r2, r3, #32 @ encoding: [0x1a,0x10] +@ CHECK: asrs r2, r3, #5 @ encoding: [0x5a,0x11] +@ CHECK: asrs r2, r3, #1 @ encoding: [0x5a,0x10] + + +@------------------------------------------------------------------------------ +@ ASR (register) +@------------------------------------------------------------------------------ + asrs r5, r2 + +@ CHECK: asrs r5, r2 @ encoding: [0x15,0x41] + + +@------------------------------------------------------------------------------ +@ B +@------------------------------------------------------------------------------ + b _baz + beq _bar + b #1838 + b #-420 + beq #336 + beq #160 + +@ CHECK: b _baz @ encoding: [A,0xe0'A'] + @ fixup A - offset: 0, value: _baz, kind: fixup_arm_thumb_br +@ CHECK: beq _bar @ encoding: [A,0xd0] + @ fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_bcc +@ CHECK: b #1838 @ encoding: [0x97,0xe3] +@ CHECK: b #-420 @ encoding: [0x2e,0xe7] +@ CHECK: beq #336 @ encoding: [0xa8,0xd0] +@ CHECK: beq #160 @ encoding: [0x50,0xd0] + +@------------------------------------------------------------------------------ +@ BL/BLX +@------------------------------------------------------------------------------ + blx #884800 + blx #1769600 + +@ CHECK: blx #884800 @ encoding: [0xd8,0xf0,0x20,0xe8] +@ CHECK: blx #1769600 @ encoding: [0xb0,0xf1,0x40,0xe8] + +@------------------------------------------------------------------------------ +@ BICS +@------------------------------------------------------------------------------ + bics r1, r6 + +@ CHECK: bics r1, r6 @ encoding: [0xb1,0x43] + + +@------------------------------------------------------------------------------ +@ BKPT +@------------------------------------------------------------------------------ + bkpt #0 + bkpt #255 + +@ CHECK: bkpt #0 @ encoding: [0x00,0xbe] +@ CHECK: bkpt #255 @ encoding: [0xff,0xbe] + + +@------------------------------------------------------------------------------ +@ BL/BLX (immediate) +@------------------------------------------------------------------------------ + bl _bar + blx _baz + +@ CHECK: bl _bar @ encoding: [A,0xf0'A',A,0xf8'A'] + @ fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_bl +@ CHECK: blx _baz @ encoding: [A,0xf0'A',A,0xe8'A'] + @ fixup A - offset: 0, value: _baz, kind: fixup_arm_thumb_blx + + +@------------------------------------------------------------------------------ +@ BLX (register) +@------------------------------------------------------------------------------ + blx r4 + +@ CHECK: blx r4 @ encoding: [0xa0,0x47] + + +@------------------------------------------------------------------------------ +@ BX +@------------------------------------------------------------------------------ + bx r2 + +@ CHECK: bx r2 @ encoding: [0x10,0x47] + + +@------------------------------------------------------------------------------ +@ CMN +@------------------------------------------------------------------------------ + + cmn r5, r1 + +@ CHECK: cmn r5, r1 @ encoding: [0xcd,0x42] + + +@------------------------------------------------------------------------------ +@ CMP +@------------------------------------------------------------------------------ + cmp r6, #32 + cmp r3, r4 + cmp r8, r1 + +@ CHECK: cmp r6, #32 @ encoding: [0x20,0x2e] +@ CHECK: cmp r3, r4 @ encoding: [0xa3,0x42] +@ CHECK: cmp r8, r1 @ encoding: [0x88,0x45] + +@------------------------------------------------------------------------------ +@ EOR +@------------------------------------------------------------------------------ + eors r4, r5 + +@ CHECK: eors r4, r5 @ encoding: [0x6c,0x40] + + +@------------------------------------------------------------------------------ +@ LDM +@------------------------------------------------------------------------------ + ldm r3, {r0, r1, r2, r3, r4, r5, r6, r7} + ldm r2!, {r1, r3, r4, r5, r7} + ldm r1, {r1} + +@ CHECK: ldm r3, {r0, r1, r2, r3, r4, r5, r6, r7} @ encoding: [0xff,0xcb] +@ CHECK: ldm r2!, {r1, r3, r4, r5, r7} @ encoding: [0xba,0xca] +@ CHECK: ldm r1, {r1} @ encoding: [0x02,0xc9] + + +@------------------------------------------------------------------------------ +@ LDR (immediate) +@------------------------------------------------------------------------------ + ldr r1, [r5] + ldr r2, [r6, #32] + ldr r3, [r7, #124] + ldr r1, [sp] + ldr r2, [sp, #24] + ldr r3, [sp, #1020] + + +@ CHECK: ldr r1, [r5] @ encoding: [0x29,0x68] +@ CHECK: ldr r2, [r6, #32] @ encoding: [0x32,0x6a] +@ CHECK: ldr r3, [r7, #124] @ encoding: [0xfb,0x6f] +@ CHECK: ldr r1, [sp] @ encoding: [0x00,0x99] +@ CHECK: ldr r2, [sp, #24] @ encoding: [0x06,0x9a] +@ CHECK: ldr r3, [sp, #1020] @ encoding: [0xff,0x9b] + + +@------------------------------------------------------------------------------ +@ LDR (literal) +@------------------------------------------------------------------------------ + ldr r1, _foo + ldr r3, #604 + ldr r3, #368 + +@ CHECK: ldr r1, _foo @ encoding: [A,0x49] + @ fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_cp +@ CHECK: ldr r3, #604 @ encoding: [0x97,0x4b] +@ CHECK: ldr r3, #368 @ encoding: [0x5c,0x4b] + +@------------------------------------------------------------------------------ +@ LDR (register) +@------------------------------------------------------------------------------ + ldr r1, [r2, r3] + +@ CHECK: ldr r1, [r2, r3] @ encoding: [0xd1,0x58] + + +@------------------------------------------------------------------------------ +@ LDRB (immediate) +@------------------------------------------------------------------------------ + ldrb r4, [r3] + ldrb r5, [r6, #0] + ldrb r6, [r7, #31] + +@ CHECK: ldrb r4, [r3] @ encoding: [0x1c,0x78] +@ CHECK: ldrb r5, [r6] @ encoding: [0x35,0x78] +@ CHECK: ldrb r6, [r7, #31] @ encoding: [0xfe,0x7f] + + +@------------------------------------------------------------------------------ +@ LDRB (register) +@------------------------------------------------------------------------------ + ldrb r6, [r4, r5] + +@ CHECK: ldrb r6, [r4, r5] @ encoding: [0x66,0x5d] + + +@------------------------------------------------------------------------------ +@ LDRH (immediate) +@------------------------------------------------------------------------------ + ldrh r3, [r3] + ldrh r4, [r6, #2] + ldrh r5, [r7, #62] + +@ CHECK: ldrh r3, [r3] @ encoding: [0x1b,0x88] +@ CHECK: ldrh r4, [r6, #2] @ encoding: [0x74,0x88] +@ CHECK: ldrh r5, [r7, #62] @ encoding: [0xfd,0x8f] + + +@------------------------------------------------------------------------------ +@ LDRH (register) +@------------------------------------------------------------------------------ + ldrh r6, [r2, r6] + +@ CHECK: ldrh r6, [r2, r6] @ encoding: [0x96,0x5b] + + +@------------------------------------------------------------------------------ +@ LDRSB/LDRSH +@------------------------------------------------------------------------------ + ldrsb r6, [r2, r6] + ldrsh r3, [r7, r1] + +@ CHECK: ldrsb r6, [r2, r6] @ encoding: [0x96,0x57] +@ CHECK: ldrsh r3, [r7, r1] @ encoding: [0x7b,0x5e] + + +@------------------------------------------------------------------------------ +@ LSL (immediate) +@------------------------------------------------------------------------------ + lsls r4, r5, #0 + lsls r4, r5, #4 + +@ CHECK: lsls r4, r5, #0 @ encoding: [0x2c,0x00] +@ CHECK: lsls r4, r5, #4 @ encoding: [0x2c,0x01] + + +@------------------------------------------------------------------------------ +@ LSL (register) +@------------------------------------------------------------------------------ + lsls r2, r6 + +@ CHECK: lsls r2, r6 @ encoding: [0xb2,0x40] + + +@------------------------------------------------------------------------------ +@ LSR (immediate) +@------------------------------------------------------------------------------ + lsrs r1, r3, #1 + lsrs r1, r3, #32 + +@ CHECK: lsrs r1, r3, #1 @ encoding: [0x59,0x08] +@ CHECK: lsrs r1, r3, #32 @ encoding: [0x19,0x08] + + +@------------------------------------------------------------------------------ +@ LSR (register) +@------------------------------------------------------------------------------ + lsrs r2, r6 + +@ CHECK: lsrs r2, r6 @ encoding: [0xf2,0x40] + + +@------------------------------------------------------------------------------ +@ MOV (immediate) +@------------------------------------------------------------------------------ + movs r2, #0 + movs r2, #255 + movs r2, #23 + +@ CHECK: movs r2, #0 @ encoding: [0x00,0x22] +@ CHECK: movs r2, #255 @ encoding: [0xff,0x22] +@ CHECK: movs r2, #23 @ encoding: [0x17,0x22] + + +@------------------------------------------------------------------------------ +@ MOV (register) +@------------------------------------------------------------------------------ + mov r3, r4 + movs r1, r3 + +@ CHECK: mov r3, r4 @ encoding: [0x23,0x46] +@ CHECK: movs r1, r3 @ encoding: [0x19,0x00] + + +@------------------------------------------------------------------------------ +@ MUL +@------------------------------------------------------------------------------ + muls r1, r2, r1 + muls r3, r4 + +@ CHECK: muls r1, r2, r1 @ encoding: [0x51,0x43] +@ CHECK: muls r3, r4, r3 @ encoding: [0x63,0x43] + + +@------------------------------------------------------------------------------ +@ MVN +@------------------------------------------------------------------------------ + mvns r6, r3 + +@ CHECK: mvns r6, r3 @ encoding: [0xde,0x43] + + +@------------------------------------------------------------------------------ +@ NEG +@------------------------------------------------------------------------------ + negs r3, r4 + +@ CHECK: rsbs r3, r4, #0 @ encoding: [0x63,0x42] + +@------------------------------------------------------------------------------ +@ ORR +@------------------------------------------------------------------------------ + orrs r3, r4 + +@ CHECK-ERRORS: orrs r3, r4 @ encoding: [0x23,0x43] + + +@------------------------------------------------------------------------------ +@ POP +@------------------------------------------------------------------------------ + pop {r2, r3, r6} + +@ CHECK: pop {r2, r3, r6} @ encoding: [0x4c,0xbc] + + +@------------------------------------------------------------------------------ +@ PUSH +@------------------------------------------------------------------------------ + push {r1, r2, r7} + +@ CHECK: push {r1, r2, r7} @ encoding: [0x86,0xb4] + + +@------------------------------------------------------------------------------ +@ REV/REV16/REVSH +@------------------------------------------------------------------------------ + rev r6, r3 + rev16 r7, r2 + revsh r5, r1 + +@ CHECK: rev r6, r3 @ encoding: [0x1e,0xba] +@ CHECK: rev16 r7, r2 @ encoding: [0x57,0xba] +@ CHECK: revsh r5, r1 @ encoding: [0xcd,0xba] + + +@------------------------------------------------------------------------------ +@ ROR +@------------------------------------------------------------------------------ + rors r2, r7 + +@ CHECK: rors r2, r7 @ encoding: [0xfa,0x41] + + +@------------------------------------------------------------------------------ +@ RSB +@------------------------------------------------------------------------------ + rsbs r1, r3, #0 + +@ CHECK: rsbs r1, r3, #0 @ encoding: [0x59,0x42] + + +@------------------------------------------------------------------------------ +@ SBC +@------------------------------------------------------------------------------ + sbcs r4, r3 + +@ CHECK: sbcs r4, r3 @ encoding: [0x9c,0x41] + + +@------------------------------------------------------------------------------ +@ SETEND +@------------------------------------------------------------------------------ + setend be + setend le + +@ CHECK: setend be @ encoding: [0x58,0xb6] +@ CHECK: setend le @ encoding: [0x50,0xb6] + + +@------------------------------------------------------------------------------ +@ STM +@------------------------------------------------------------------------------ + stm r1!, {r2, r6} + stm r1!, {r1, r2, r3, r7} + +@ CHECK: stm r1!, {r2, r6} @ encoding: [0x44,0xc1] +@ CHECK: stm r1!, {r1, r2, r3, r7} @ encoding: [0x8e,0xc1] + + +@------------------------------------------------------------------------------ +@ STR (immediate) +@------------------------------------------------------------------------------ + str r2, [r7] + str r2, [r7, #0] + str r5, [r1, #4] + str r3, [r7, #124] + str r2, [sp] + str r3, [sp, #0] + str r4, [sp, #20] + str r5, [sp, #1020] + +@ CHECK: str r2, [r7] @ encoding: [0x3a,0x60] +@ CHECK: str r2, [r7] @ encoding: [0x3a,0x60] +@ CHECK: str r5, [r1, #4] @ encoding: [0x4d,0x60] +@ CHECK: str r3, [r7, #124] @ encoding: [0xfb,0x67] +@ CHECK: str r2, [sp] @ encoding: [0x00,0x92] +@ CHECK: str r3, [sp] @ encoding: [0x00,0x93] +@ CHECK: str r4, [sp, #20] @ encoding: [0x05,0x94] +@ CHECK: str r5, [sp, #1020] @ encoding: [0xff,0x95] + + +@------------------------------------------------------------------------------ +@ STR (register) +@------------------------------------------------------------------------------ + str r2, [r7, r3] + +@ CHECK: str r2, [r7, r3] @ encoding: [0xfa,0x50] + + +@------------------------------------------------------------------------------ +@ STRB (immediate) +@------------------------------------------------------------------------------ + strb r4, [r3] + strb r5, [r6, #0] + strb r6, [r7, #31] + +@ CHECK: strb r4, [r3] @ encoding: [0x1c,0x70] +@ CHECK: strb r5, [r6] @ encoding: [0x35,0x70] +@ CHECK: strb r6, [r7, #31] @ encoding: [0xfe,0x77] + + +@------------------------------------------------------------------------------ +@ STRB (register) +@------------------------------------------------------------------------------ + strb r6, [r4, r5] + +@ CHECK: strb r6, [r4, r5] @ encoding: [0x66,0x55] + + +@------------------------------------------------------------------------------ +@ STRH (immediate) +@------------------------------------------------------------------------------ + strh r3, [r3] + strh r4, [r6, #2] + strh r5, [r7, #62] + +@ CHECK: strh r3, [r3] @ encoding: [0x1b,0x80] +@ CHECK: strh r4, [r6, #2] @ encoding: [0x74,0x80] +@ CHECK: strh r5, [r7, #62] @ encoding: [0xfd,0x87] + + +@------------------------------------------------------------------------------ +@ STRH (register) +@------------------------------------------------------------------------------ + strh r6, [r2, r6] + +@ CHECK: strh r6, [r2, r6] @ encoding: [0x96,0x53] + + +@------------------------------------------------------------------------------ +@ SUB (immediate) +@------------------------------------------------------------------------------ + subs r1, r2, #3 + subs r2, #3 + subs r2, #8 + +@ CHECK: subs r1, r2, #3 @ encoding: [0xd1,0x1e] +@ CHECK: subs r2, #3 @ encoding: [0x03,0x3a] +@ CHECK: subs r2, #8 @ encoding: [0x08,0x3a] + + +@------------------------------------------------------------------------------ +@ SUB (SP minus immediate) +@------------------------------------------------------------------------------ + sub sp, #12 + sub sp, sp, #508 + +@ CHECK: sub sp, #12 @ encoding: [0x83,0xb0] +@ CHECK: sub sp, #508 @ encoding: [0xff,0xb0] + + +@------------------------------------------------------------------------------ +@ SUB (register) +@------------------------------------------------------------------------------ + subs r1, r2, r3 + +@ CHECK: subs r1, r2, r3 @ encoding: [0xd1,0x1a] + + +@------------------------------------------------------------------------------ +@ SVC +@------------------------------------------------------------------------------ + svc #0 + svc #255 + +@ CHECK: svc #0 @ encoding: [0x00,0xdf] +@ CHECK: svc #255 @ encoding: [0xff,0xdf] + + +@------------------------------------------------------------------------------ +@ SXTB/SXTH +@------------------------------------------------------------------------------ + sxtb r3, r5 + sxth r3, r5 + +@ CHECK: sxtb r3, r5 @ encoding: [0x6b,0xb2] +@ CHECK: sxth r3, r5 @ encoding: [0x2b,0xb2] + + +@------------------------------------------------------------------------------ +@ TST +@------------------------------------------------------------------------------ + tst r6, r1 + +@ CHECK: tst r6, r1 @ encoding: [0x0e,0x42] + + +@------------------------------------------------------------------------------ +@ UXTB/UXTH +@------------------------------------------------------------------------------ + uxtb r7, r2 + uxth r1, r4 + +@ CHECK: uxtb r7, r2 @ encoding: [0xd7,0xb2] +@ CHECK: uxth r1, r4 @ encoding: [0xa1,0xb2] + + +@------------------------------------------------------------------------------ +@ WFE/WFI/YIELD +@------------------------------------------------------------------------------ + wfe + wfi + yield + +@ CHECK: wfe @ encoding: [0x20,0xbf] +@ CHECK: wfi @ encoding: [0x30,0xbf] +@ CHECK: yield @ encoding: [0x10,0xbf] diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s new file mode 100644 index 0000000..68815da --- /dev/null +++ b/test/MC/ARM/basic-thumb2-instructions.s @@ -0,0 +1,3213 @@ +@ RUN: llvm-mc -triple=thumbv7-apple-darwin -show-encoding < %s | FileCheck %s + .syntax unified + .globl _func + +@ Check that the assembler can handle the documented syntax from the ARM ARM. +@ For complex constructs like shifter operands, check more thoroughly for them +@ once then spot check that following instructions accept the form generally. +@ This gives us good coverage while keeping the overall size of the test +@ more reasonable. + + +@ FIXME: Some 3-operand instructions have a 2-operand assembly syntax. + +_func: +@ CHECK: _func + +@------------------------------------------------------------------------------ +@ ADC (immediate) +@------------------------------------------------------------------------------ + adc r0, r1, #4 + adcs r0, r1, #0 + adc r1, r2, #255 + adc r3, r7, #0x00550055 + adc r8, r12, #0xaa00aa00 + adc r9, r7, #0xa5a5a5a5 + adc r5, r3, #0x87000000 + adc r4, r2, #0x7f800000 + adc r4, r2, #0x00000680 + +@ CHECK: adc r0, r1, #4 @ encoding: [0x41,0xf1,0x04,0x00] +@ CHECK: adcs r0, r1, #0 @ encoding: [0x51,0xf1,0x00,0x00] +@ CHECK: adc r1, r2, #255 @ encoding: [0x42,0xf1,0xff,0x01] +@ CHECK: adc r3, r7, #5570645 @ encoding: [0x47,0xf1,0x55,0x13] +@ CHECK: adc r8, r12, #2852170240 @ encoding: [0x4c,0xf1,0xaa,0x28] +@ CHECK: adc r9, r7, #2779096485 @ encoding: [0x47,0xf1,0xa5,0x39] +@ CHECK: adc r5, r3, #2264924160 @ encoding: [0x43,0xf1,0x07,0x45] +@ CHECK: adc r4, r2, #2139095040 @ encoding: [0x42,0xf1,0xff,0x44] +@ CHECK: adc r4, r2, #1664 @ encoding: [0x42,0xf5,0xd0,0x64] + +@------------------------------------------------------------------------------ +@ ADC (register) +@------------------------------------------------------------------------------ + adc r4, r5, r6 + adcs r4, r5, r6 + adc.w r9, r1, r3 + adcs.w r9, r1, r3 + adc r0, r1, r3, ror #4 + adcs r0, r1, r3, lsl #7 + adc.w r0, r1, r3, lsr #31 + adcs.w r0, r1, r3, asr #32 + +@ CHECK: adc.w r4, r5, r6 @ encoding: [0x45,0xeb,0x06,0x04] +@ CHECK: adcs.w r4, r5, r6 @ encoding: [0x55,0xeb,0x06,0x04] +@ CHECK: adc.w r9, r1, r3 @ encoding: [0x41,0xeb,0x03,0x09] +@ CHECK: adcs.w r9, r1, r3 @ encoding: [0x51,0xeb,0x03,0x09] +@ CHECK: adc.w r0, r1, r3, ror #4 @ encoding: [0x41,0xeb,0x33,0x10] +@ CHECK: adcs.w r0, r1, r3, lsl #7 @ encoding: [0x51,0xeb,0xc3,0x10] +@ CHECK: adc.w r0, r1, r3, lsr #31 @ encoding: [0x41,0xeb,0xd3,0x70] +@ CHECK: adcs.w r0, r1, r3, asr #32 @ encoding: [0x51,0xeb,0x23,0x00] + + +@------------------------------------------------------------------------------ +@ ADD (immediate) +@------------------------------------------------------------------------------ + itet eq + addeq r1, r2, #4 + addwne r5, r3, #1023 + addeq r4, r5, #293 + add r2, sp, #1024 + add r2, r8, #0xff00 + add r2, r3, #257 + addw r2, r3, #257 + add r12, r6, #0x100 + addw r12, r6, #0x100 + adds r1, r2, #0x1f0 + +@ CHECK: itet eq @ encoding: [0x0a,0xbf] +@ CHECK: addeq r1, r2, #4 @ encoding: [0x11,0x1d] +@ CHECK: addwne r5, r3, #1023 @ encoding: [0x03,0xf2,0xff,0x35] +@ CHECK: addweq r4, r5, #293 @ encoding: [0x05,0xf2,0x25,0x14] +@ CHECK: add.w r2, sp, #1024 @ encoding: [0x0d,0xf5,0x80,0x62] +@ CHECK: add.w r2, r8, #65280 @ encoding: [0x08,0xf5,0x7f,0x42] +@ CHECK: addw r2, r3, #257 @ encoding: [0x03,0xf2,0x01,0x12] +@ CHECK: addw r2, r3, #257 @ encoding: [0x03,0xf2,0x01,0x12] +@ CHECK: add.w r12, r6, #256 @ encoding: [0x06,0xf5,0x80,0x7c] +@ CHECK: addw r12, r6, #256 @ encoding: [0x06,0xf2,0x00,0x1c] +@ CHECK: adds.w r1, r2, #496 @ encoding: [0x12,0xf5,0xf8,0x71] + + +@------------------------------------------------------------------------------ +@ ADD (register) +@------------------------------------------------------------------------------ + add r1, r2, r8 + add r5, r9, r2, asr #32 + adds r7, r3, r1, lsl #31 + adds.w r0, r3, r6, lsr #25 + add.w r4, r8, r1, ror #12 + +@ CHECK: add.w r1, r2, r8 @ encoding: [0x02,0xeb,0x08,0x01] +@ CHECK: add.w r5, r9, r2, asr #32 @ encoding: [0x09,0xeb,0x22,0x05] +@ CHECK: adds.w r7, r3, r1, lsl #31 @ encoding: [0x13,0xeb,0xc1,0x77] +@ CHECK: adds.w r0, r3, r6, lsr #25 @ encoding: [0x13,0xeb,0x56,0x60] +@ CHECK: add.w r4, r8, r1, ror #12 @ encoding: [0x08,0xeb,0x31,0x34] + + +@------------------------------------------------------------------------------ +@ FIXME: ADR +@------------------------------------------------------------------------------ + + subw r11, pc, #3270 + adr.w r11, #-826 + +@ CHECK: subw r11, pc, #3270 @ encoding: [0xaf,0xf6,0xc6,0x4b] +@ CHECK: adr.w r11, #-826 @ encoding: [0xaf,0xf2,0x3a,0x3b] + +@------------------------------------------------------------------------------ +@ AND (immediate) +@------------------------------------------------------------------------------ + and r2, r5, #0xff000 + ands r3, r12, #0xf + and r1, #0xff + and r1, r1, #0xff + +@ CHECK: and r2, r5, #1044480 @ encoding: [0x05,0xf4,0x7f,0x22] +@ CHECK: ands r3, r12, #15 @ encoding: [0x1c,0xf0,0x0f,0x03] +@ CHECK: and r1, r1, #255 @ encoding: [0x01,0xf0,0xff,0x01] +@ CHECK: and r1, r1, #255 @ encoding: [0x01,0xf0,0xff,0x01] + + +@------------------------------------------------------------------------------ +@ AND (register) +@------------------------------------------------------------------------------ + and r4, r9, r8 + and r1, r4, r8, asr #3 + ands r2, r1, r7, lsl #1 + ands.w r4, r5, r2, lsr #20 + and.w r9, r12, r1, ror #17 + +@ CHECK: and.w r4, r9, r8 @ encoding: [0x09,0xea,0x08,0x04] +@ CHECK: and.w r1, r4, r8, asr #3 @ encoding: [0x04,0xea,0xe8,0x01] +@ CHECK: ands.w r2, r1, r7, lsl #1 @ encoding: [0x11,0xea,0x47,0x02] +@ CHECK: ands.w r4, r5, r2, lsr #20 @ encoding: [0x15,0xea,0x12,0x54] +@ CHECK: and.w r9, r12, r1, ror #17 @ encoding: [0x0c,0xea,0x71,0x49] + +@------------------------------------------------------------------------------ +@ ASR (immediate) +@------------------------------------------------------------------------------ + asr r2, r3, #12 + asrs r8, r3, #32 + asrs.w r2, r3, #1 + asr r2, r3, #4 + asrs r2, r12, #15 + + asr r3, #19 + asrs r8, #2 + asrs.w r7, #5 + asr.w r12, #21 + +@ CHECK: asr.w r2, r3, #12 @ encoding: [0x4f,0xea,0x23,0x32] +@ CHECK: asrs.w r8, r3, #32 @ encoding: [0x5f,0xea,0x23,0x08] +@ CHECK: asrs.w r2, r3, #1 @ encoding: [0x5f,0xea,0x63,0x02] +@ CHECK: asr.w r2, r3, #4 @ encoding: [0x4f,0xea,0x23,0x12] +@ CHECK: asrs.w r2, r12, #15 @ encoding: [0x5f,0xea,0xec,0x32] + +@ CHECK: asr.w r3, r3, #19 @ encoding: [0x4f,0xea,0xe3,0x43] +@ CHECK: asrs.w r8, r8, #2 @ encoding: [0x5f,0xea,0xa8,0x08] +@ CHECK: asrs.w r7, r7, #5 @ encoding: [0x5f,0xea,0x67,0x17] +@ CHECK: asr.w r12, r12, #21 @ encoding: [0x4f,0xea,0x6c,0x5c] + + +@------------------------------------------------------------------------------ +@ ASR (register) +@------------------------------------------------------------------------------ + asr r3, r4, r2 + asr.w r1, r2 + asrs r3, r4, r8 + +@ CHECK: asr.w r3, r4, r2 @ encoding: [0x44,0xfa,0x02,0xf3] +@ CHECK: asr.w r1, r1, r2 @ encoding: [0x41,0xfa,0x02,0xf1] +@ CHECK: asrs.w r3, r4, r8 @ encoding: [0x54,0xfa,0x08,0xf3] + + +@------------------------------------------------------------------------------ +@ B +@------------------------------------------------------------------------------ + b.w _bar + beq.w _bar + it eq + beq.w _bar + bmi.w #-183396 + +@ CHECK: b.w _bar @ encoding: [A,0xf0'A',A,0x90'A'] + @ fixup A - offset: 0, value: _bar, kind: fixup_t2_uncondbranch +@ CHECK: beq.w _bar @ encoding: [A,0xf0'A',A,0x80'A'] + @ fixup A - offset: 0, value: _bar, kind: fixup_t2_condbranch +@ CHECK: it eq @ encoding: [0x08,0xbf] +@ CHECK: beq.w _bar @ encoding: [A,0xf0'A',A,0x90'A'] + @ fixup A - offset: 0, value: _bar, kind: fixup_t2_uncondbranch +@ CHECK: bmi.w #-183396 @ encoding: [0x13,0xf5,0xce,0xa9] + + +@------------------------------------------------------------------------------ +@ BFC +@------------------------------------------------------------------------------ + bfc r5, #3, #17 + it lo + bfccc r5, #3, #17 + +@ CHECK: bfc r5, #3, #17 @ encoding: [0x6f,0xf3,0xd3,0x05] +@ CHECK: it lo @ encoding: [0x38,0xbf] +@ CHECK: bfclo r5, #3, #17 @ encoding: [0x6f,0xf3,0xd3,0x05] + + +@------------------------------------------------------------------------------ +@ BFI +@------------------------------------------------------------------------------ + bfi r5, r2, #3, #17 + it ne + bfine r5, r2, #3, #17 + +@ CHECK: bfi r5, r2, #3, #17 @ encoding: [0x62,0xf3,0xd3,0x05] +@ CHECK: it ne @ encoding: [0x18,0xbf] +@ CHECK: bfine r5, r2, #3, #17 @ encoding: [0x62,0xf3,0xd3,0x05] + + +@------------------------------------------------------------------------------ +@ BIC +@------------------------------------------------------------------------------ + bic r10, r1, #0xf + bic r12, r3, r6 + bic r11, r2, r6, lsl #12 + bic r8, r4, r1, lsr #11 + bic r7, r5, r7, lsr #15 + bic r6, r7, r9, asr #32 + bic r5, r6, r8, ror #1 + + @ destination register is optional + bic r1, #0xf + bic r1, r1 + bic r4, r2, lsl #31 + bic r6, r3, lsr #12 + bic r7, r4, lsr #7 + bic r8, r5, asr #15 + bic r12, r6, ror #29 + +@ CHECK: bic r10, r1, #15 @ encoding: [0x21,0xf0,0x0f,0x0a] +@ CHECK: bic.w r12, r3, r6 @ encoding: [0x23,0xea,0x06,0x0c] +@ CHECK: bic.w r11, r2, r6, lsl #12 @ encoding: [0x22,0xea,0x06,0x3b] +@ CHECK: bic.w r8, r4, r1, lsr #11 @ encoding: [0x24,0xea,0xd1,0x28] +@ CHECK: bic.w r7, r5, r7, lsr #15 @ encoding: [0x25,0xea,0xd7,0x37] +@ CHECK: bic.w r6, r7, r9, asr #32 @ encoding: [0x27,0xea,0x29,0x06] +@ CHECK: bic.w r5, r6, r8, ror #1 @ encoding: [0x26,0xea,0x78,0x05] + +@ CHECK: bic r1, r1, #15 @ encoding: [0x21,0xf0,0x0f,0x01] +@ CHECK: bic.w r1, r1, r1 @ encoding: [0x21,0xea,0x01,0x01] +@ CHECK: bic.w r4, r4, r2, lsl #31 @ encoding: [0x24,0xea,0xc2,0x74] +@ CHECK: bic.w r6, r6, r3, lsr #12 @ encoding: [0x26,0xea,0x13,0x36] +@ CHECK: bic.w r7, r7, r4, lsr #7 @ encoding: [0x27,0xea,0xd4,0x17] +@ CHECK: bic.w r8, r8, r5, asr #15 @ encoding: [0x28,0xea,0xe5,0x38] +@ CHECK: bic.w r12, r12, r6, ror #29 @ encoding: [0x2c,0xea,0x76,0x7c] + +@------------------------------------------------------------------------------ +@ BKPT +@------------------------------------------------------------------------------ + it pl + bkpt #234 + +@ CHECK: it pl @ encoding: [0x58,0xbf] +@ CHECK: bkpt #234 @ encoding: [0xea,0xbe] + +@------------------------------------------------------------------------------ +@ BXJ +@------------------------------------------------------------------------------ + bxj r5 + it ne + bxjne r7 + +@ CHECK: bxj r5 @ encoding: [0xc5,0xf3,0x00,0x8f] +@ CHECK: it ne @ encoding: [0x18,0xbf] +@ CHECK: bxjne r7 @ encoding: [0xc7,0xf3,0x00,0x8f] + + +@------------------------------------------------------------------------------ +@ CBZ/CBNZ +@------------------------------------------------------------------------------ + cbnz r7, #6 + cbnz r7, #12 + cbz r6, _bar + cbnz r6, _bar + +@ CHECK: cbnz r7, #6 @ encoding: [0x1f,0xb9] +@ CHECK: cbnz r7, #12 @ encoding: [0x37,0xb9] +@ CHECK: cbz r6, _bar @ encoding: [0x06'A',0xb1'A'] + @ fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_cb +@ CHECK: cbnz r6, _bar @ encoding: [0x06'A',0xb9'A'] + @ fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_cb + + +@------------------------------------------------------------------------------ +@ CDP/CDP2 +@------------------------------------------------------------------------------ + cdp p7, #1, c1, c1, c1, #4 + cdp2 p7, #1, c1, c1, c1, #4 + +@ CHECK: cdp p7, #1, c1, c1, c1, #4 @ encoding: [0x11,0xee,0x81,0x17] +@ CHECK: cdp2 p7, #1, c1, c1, c1, #4 @ encoding: [0x11,0xfe,0x81,0x17] + + +@------------------------------------------------------------------------------ +@ CLREX +@------------------------------------------------------------------------------ + clrex + it ne + clrexne + +@ CHECK: clrex @ encoding: [0xbf,0xf3,0x2f,0x8f] +@ CHECK: it ne @ encoding: [0x18,0xbf] +@ CHECK: clrexne @ encoding: [0xbf,0xf3,0x2f,0x8f] + + +@------------------------------------------------------------------------------ +@ CLZ +@------------------------------------------------------------------------------ + clz r1, r2 + it eq + clzeq r1, r2 + +@ CHECK: clz r1, r2 @ encoding: [0xb2,0xfa,0x82,0xf1] +@ CHECK: it eq @ encoding: [0x08,0xbf] +@ CHECK: clzeq r1, r2 @ encoding: [0xb2,0xfa,0x82,0xf1] + + +@------------------------------------------------------------------------------ +@ CMN +@------------------------------------------------------------------------------ + cmn r1, #0xf + cmn r8, r6 + cmn r1, r6, lsl #10 + cmn r1, r6, lsr #10 + cmn sp, r6, lsr #10 + cmn r1, r6, asr #10 + cmn r1, r6, ror #10 + +@ CHECK: cmn.w r1, #15 @ encoding: [0x11,0xf1,0x0f,0x0f] +@ CHECK: cmn.w r8, r6 @ encoding: [0x18,0xeb,0x06,0x0f] +@ CHECK: cmn.w r1, r6, lsl #10 @ encoding: [0x11,0xeb,0x86,0x2f] +@ CHECK: cmn.w r1, r6, lsr #10 @ encoding: [0x11,0xeb,0x96,0x2f] +@ CHECK: cmn.w sp, r6, lsr #10 @ encoding: [0x1d,0xeb,0x96,0x2f] +@ CHECK: cmn.w r1, r6, asr #10 @ encoding: [0x11,0xeb,0xa6,0x2f] +@ CHECK: cmn.w r1, r6, ror #10 @ encoding: [0x11,0xeb,0xb6,0x2f] + + +@------------------------------------------------------------------------------ +@ CMP +@------------------------------------------------------------------------------ + cmp r5, #0xff00 + cmp.w r4, r12 + cmp r9, r6, lsl #12 + cmp r3, r7, lsr #31 + cmp sp, r6, lsr #1 + cmp r2, r5, asr #24 + cmp r1, r4, ror #15 + +@ CHECK: cmp.w r5, #65280 @ encoding: [0xb5,0xf5,0x7f,0x4f] +@ CHECK: cmp.w r4, r12 @ encoding: [0xb4,0xeb,0x0c,0x0f] +@ CHECK: cmp.w r9, r6, lsl #12 @ encoding: [0xb9,0xeb,0x06,0x3f] +@ CHECK: cmp.w r3, r7, lsr #31 @ encoding: [0xb3,0xeb,0xd7,0x7f] +@ CHECK: cmp.w sp, r6, lsr #1 @ encoding: [0xbd,0xeb,0x56,0x0f] +@ CHECK: cmp.w r2, r5, asr #24 @ encoding: [0xb2,0xeb,0x25,0x6f] +@ CHECK: cmp.w r1, r4, ror #15 @ encoding: [0xb1,0xeb,0xf4,0x3f] + + +@------------------------------------------------------------------------------ +@ DBG +@------------------------------------------------------------------------------ + dbg #5 + dbg #0 + dbg #15 + +@ CHECK: dbg #5 @ encoding: [0xaf,0xf3,0xf5,0x80] +@ CHECK: dbg #0 @ encoding: [0xaf,0xf3,0xf0,0x80] +@ CHECK: dbg #15 @ encoding: [0xaf,0xf3,0xff,0x80] + + +@------------------------------------------------------------------------------ +@ DMB +@------------------------------------------------------------------------------ + dmb sy + dmb st + dmb sh + dmb ish + dmb shst + dmb ishst + dmb un + dmb nsh + dmb unst + dmb nshst + dmb osh + dmb oshst + dmb + +@ CHECK: dmb sy @ encoding: [0xbf,0xf3,0x5f,0x8f] +@ CHECK: dmb st @ encoding: [0xbf,0xf3,0x5e,0x8f] +@ CHECK: dmb ish @ encoding: [0xbf,0xf3,0x5b,0x8f] +@ CHECK: dmb ish @ encoding: [0xbf,0xf3,0x5b,0x8f] +@ CHECK: dmb ishst @ encoding: [0xbf,0xf3,0x5a,0x8f] +@ CHECK: dmb ishst @ encoding: [0xbf,0xf3,0x5a,0x8f] +@ CHECK: dmb nsh @ encoding: [0xbf,0xf3,0x57,0x8f] +@ CHECK: dmb nsh @ encoding: [0xbf,0xf3,0x57,0x8f] +@ CHECK: dmb nshst @ encoding: [0xbf,0xf3,0x56,0x8f] +@ CHECK: dmb nshst @ encoding: [0xbf,0xf3,0x56,0x8f] +@ CHECK: dmb osh @ encoding: [0xbf,0xf3,0x53,0x8f] +@ CHECK: dmb oshst @ encoding: [0xbf,0xf3,0x52,0x8f] +@ CHECK: dmb sy @ encoding: [0xbf,0xf3,0x5f,0x8f] + + +@------------------------------------------------------------------------------ +@ DSB +@------------------------------------------------------------------------------ + dsb sy + dsb st + dsb sh + dsb ish + dsb shst + dsb ishst + dsb un + dsb nsh + dsb unst + dsb nshst + dsb osh + dsb oshst + dsb + +@ CHECK: dsb sy @ encoding: [0xbf,0xf3,0x4f,0x8f] +@ CHECK: dsb st @ encoding: [0xbf,0xf3,0x4e,0x8f] +@ CHECK: dsb ish @ encoding: [0xbf,0xf3,0x4b,0x8f] +@ CHECK: dsb ish @ encoding: [0xbf,0xf3,0x4b,0x8f] +@ CHECK: dsb ishst @ encoding: [0xbf,0xf3,0x4a,0x8f] +@ CHECK: dsb ishst @ encoding: [0xbf,0xf3,0x4a,0x8f] +@ CHECK: dsb nsh @ encoding: [0xbf,0xf3,0x47,0x8f] +@ CHECK: dsb nsh @ encoding: [0xbf,0xf3,0x47,0x8f] +@ CHECK: dsb nshst @ encoding: [0xbf,0xf3,0x46,0x8f] +@ CHECK: dsb nshst @ encoding: [0xbf,0xf3,0x46,0x8f] +@ CHECK: dsb osh @ encoding: [0xbf,0xf3,0x43,0x8f] +@ CHECK: dsb oshst @ encoding: [0xbf,0xf3,0x42,0x8f] +@ CHECK: dsb sy @ encoding: [0xbf,0xf3,0x4f,0x8f] + + +@------------------------------------------------------------------------------ +@ EOR +@------------------------------------------------------------------------------ + eor r4, r5, #0xf000 + eor r4, r5, r6 + eor r4, r5, r6, lsl #5 + eor r4, r5, r6, lsr #5 + eor r4, r5, r6, lsr #5 + eor r4, r5, r6, asr #5 + eor r4, r5, r6, ror #5 + +@ CHECK: eor r4, r5, #61440 @ encoding: [0x85,0xf4,0x70,0x44] +@ CHECK: eor.w r4, r5, r6 @ encoding: [0x85,0xea,0x06,0x04] +@ CHECK: eor.w r4, r5, r6, lsl #5 @ encoding: [0x85,0xea,0x46,0x14] +@ CHECK: eor.w r4, r5, r6, lsr #5 @ encoding: [0x85,0xea,0x56,0x14] +@ CHECK: eor.w r4, r5, r6, lsr #5 @ encoding: [0x85,0xea,0x56,0x14] +@ CHECK: eor.w r4, r5, r6, asr #5 @ encoding: [0x85,0xea,0x66,0x14] +@ CHECK: eor.w r4, r5, r6, ror #5 @ encoding: [0x85,0xea,0x76,0x14] + + +@------------------------------------------------------------------------------ +@ ISB +@------------------------------------------------------------------------------ + isb sy + isb + +@ CHECK: isb sy @ encoding: [0xbf,0xf3,0x6f,0x8f] +@ CHECK: isb sy @ encoding: [0xbf,0xf3,0x6f,0x8f] + + +@------------------------------------------------------------------------------ +@ IT +@------------------------------------------------------------------------------ +@ Test encodings of a few full IT blocks, not just the IT instruction + + iteet eq + addeq r0, r1, r2 + nopne + subne r5, r6, r7 + addeq r1, r2, #4 + +@ CHECK: iteet eq @ encoding: [0x0d,0xbf] +@ CHECK: addeq r0, r1, r2 @ encoding: [0x88,0x18] +@ CHECK: nopne @ encoding: [0x00,0xbf] +@ CHECK: subne r5, r6, r7 @ encoding: [0xf5,0x1b] +@ CHECK: addeq r1, r2, #4 @ encoding: [0x11,0x1d] + + +@------------------------------------------------------------------------------ +@ LDC{L}/LDC2{L} +@------------------------------------------------------------------------------ + ldc2 p0, c8, [r1, #4] + ldc2 p1, c7, [r2] + ldc2 p2, c6, [r3, #-224] + ldc2 p3, c5, [r4, #-120]! + ldc2 p4, c4, [r5], #16 + ldc2 p5, c3, [r6], #-72 + ldc2l p6, c2, [r7, #4] + ldc2l p7, c1, [r8] + ldc2l p8, c0, [r9, #-224] + ldc2l p9, c1, [r10, #-120]! + ldc2l p10, c2, [r11], #16 + ldc2l p11, c3, [r12], #-72 + + ldc p12, c4, [r0, #4] + ldc p13, c5, [r1] + ldc p14, c6, [r2, #-224] + ldc p15, c7, [r3, #-120]! + ldc p5, c8, [r4], #16 + ldc p4, c9, [r5], #-72 + ldcl p3, c10, [r6, #4] + ldcl p2, c11, [r7] + ldcl p1, c12, [r8, #-224] + ldcl p0, c13, [r9, #-120]! + ldcl p6, c14, [r10], #16 + ldcl p7, c15, [r11], #-72 + + ldc2 p2, c8, [r1], { 25 } + +@ CHECK: ldc2 p0, c8, [r1, #4] @ encoding: [0x91,0xfd,0x01,0x80] +@ CHECK: ldc2 p1, c7, [r2] @ encoding: [0x92,0xfd,0x00,0x71] +@ CHECK: ldc2 p2, c6, [r3, #-224] @ encoding: [0x13,0xfd,0x38,0x62] +@ CHECK: ldc2 p3, c5, [r4, #-120]! @ encoding: [0x34,0xfd,0x1e,0x53] +@ CHECK: ldc2 p4, c4, [r5], #16 @ encoding: [0xb5,0xfc,0x04,0x44] +@ CHECK: ldc2 p5, c3, [r6], #-72 @ encoding: [0x36,0xfc,0x12,0x35] +@ CHECK: ldc2l p6, c2, [r7, #4] @ encoding: [0xd7,0xfd,0x01,0x26] +@ CHECK: ldc2l p7, c1, [r8] @ encoding: [0xd8,0xfd,0x00,0x17] +@ CHECK: ldc2l p8, c0, [r9, #-224] @ encoding: [0x59,0xfd,0x38,0x08] +@ CHECK: ldc2l p9, c1, [r10, #-120]! @ encoding: [0x7a,0xfd,0x1e,0x19] +@ CHECK: ldc2l p10, c2, [r11], #16 @ encoding: [0xfb,0xfc,0x04,0x2a] +@ CHECK: ldc2l p11, c3, [r12], #-72 @ encoding: [0x7c,0xfc,0x12,0x3b] + +@ CHECK: ldc p12, c4, [r0, #4] @ encoding: [0x90,0xed,0x01,0x4c] +@ CHECK: ldc p13, c5, [r1] @ encoding: [0x91,0xed,0x00,0x5d] +@ CHECK: ldc p14, c6, [r2, #-224] @ encoding: [0x12,0xed,0x38,0x6e] +@ CHECK: ldc p15, c7, [r3, #-120]! @ encoding: [0x33,0xed,0x1e,0x7f] +@ CHECK: ldc p5, c8, [r4], #16 @ encoding: [0xb4,0xec,0x04,0x85] +@ CHECK: ldc p4, c9, [r5], #-72 @ encoding: [0x35,0xec,0x12,0x94] +@ CHECK: ldcl p3, c10, [r6, #4] @ encoding: [0xd6,0xed,0x01,0xa3] +@ CHECK: ldcl p2, c11, [r7] @ encoding: [0xd7,0xed,0x00,0xb2] +@ CHECK: ldcl p1, c12, [r8, #-224] @ encoding: [0x58,0xed,0x38,0xc1] +@ CHECK: ldcl p0, c13, [r9, #-120]! @ encoding: [0x79,0xed,0x1e,0xd0] +@ CHECK: ldcl p6, c14, [r10], #16 @ encoding: [0xfa,0xec,0x04,0xe6] +@ CHECK: ldcl p7, c15, [r11], #-72 @ encoding: [0x7b,0xec,0x12,0xf7] + +@ CHECK: ldc2 p2, c8, [r1], {25} @ encoding: [0x91,0xfc,0x19,0x82] + + +@------------------------------------------------------------------------------ +@ LDMIA +@------------------------------------------------------------------------------ + ldmia.w r4, {r4, r5, r8, r9} + ldmia.w r4, {r5, r6} + ldmia.w r5!, {r3, r8} + ldm.w r4, {r4, r5, r8, r9} + ldm.w r4, {r5, r6} + ldm.w r5!, {r3, r8} + ldm.w r5!, {r1, r2} + ldm.w r2, {r1, r2} + + ldmia r4, {r4, r5, r8, r9} + ldmia r4, {r5, r6} + ldmia r5!, {r3, r8} + ldm r4, {r4, r5, r8, r9} + ldm r4, {r5, r6} + ldm r5!, {r3, r8} + ldmfd r5!, {r3, r8} + +@ CHECK: ldm.w r4, {r4, r5, r8, r9} @ encoding: [0x94,0xe8,0x30,0x03] +@ CHECK: ldm.w r4, {r5, r6} @ encoding: [0x94,0xe8,0x60,0x00] +@ CHECK: ldm.w r5!, {r3, r8} @ encoding: [0xb5,0xe8,0x08,0x01] +@ CHECK: ldm.w r4, {r4, r5, r8, r9} @ encoding: [0x94,0xe8,0x30,0x03] +@ CHECK: ldm.w r4, {r5, r6} @ encoding: [0x94,0xe8,0x60,0x00] +@ CHECK: ldm.w r5!, {r3, r8} @ encoding: [0xb5,0xe8,0x08,0x01] +@ CHECK: ldm.w r5!, {r1, r2} @ encoding: [0xb5,0xe8,0x06,0x00] +@ CHECK: ldm.w r2, {r1, r2} @ encoding: [0x92,0xe8,0x06,0x00] + +@ CHECK: ldm.w r4, {r4, r5, r8, r9} @ encoding: [0x94,0xe8,0x30,0x03] +@ CHECK: ldm.w r4, {r5, r6} @ encoding: [0x94,0xe8,0x60,0x00] +@ CHECK: ldm.w r5!, {r3, r8} @ encoding: [0xb5,0xe8,0x08,0x01] +@ CHECK: ldm.w r4, {r4, r5, r8, r9} @ encoding: [0x94,0xe8,0x30,0x03] +@ CHECK: ldm.w r4, {r5, r6} @ encoding: [0x94,0xe8,0x60,0x00] +@ CHECK: ldm.w r5!, {r3, r8} @ encoding: [0xb5,0xe8,0x08,0x01] +@ CHECK: ldm.w r5!, {r3, r8} @ encoding: [0xb5,0xe8,0x08,0x01] + + +@------------------------------------------------------------------------------ +@ LDMDB +@------------------------------------------------------------------------------ + ldmdb r4, {r4, r5, r8, r9} + ldmdb r4, {r5, r6} + ldmdb r5!, {r3, r8} + ldmea r5!, {r3, r8} + +@ CHECK: ldmdb r4, {r4, r5, r8, r9} @ encoding: [0x14,0xe9,0x30,0x03] +@ CHECK: ldmdb r4, {r5, r6} @ encoding: [0x14,0xe9,0x60,0x00] +@ CHECK: ldmdb r5!, {r3, r8} @ encoding: [0x35,0xe9,0x08,0x01] +@ CHECK: ldmdb r5!, {r3, r8} @ encoding: [0x35,0xe9,0x08,0x01] + + +@------------------------------------------------------------------------------ +@ LDR(immediate) +@------------------------------------------------------------------------------ + ldr r5, [r5, #-4] + ldr r5, [r6, #32] + ldr r5, [r6, #33] + ldr r5, [r6, #257] + ldr.w pc, [r7, #257] + ldr r2, [r4, #255]! + ldr r8, [sp, #4]! + ldr lr, [sp, #-4]! + ldr r2, [r4], #255 + ldr r8, [sp], #4 + ldr lr, [sp], #-4 + +@ CHECK: ldr r5, [r5, #-4] @ encoding: [0x55,0xf8,0x04,0x5c] +@ CHECK: ldr r5, [r6, #32] @ encoding: [0x35,0x6a] +@ CHECK: ldr.w r5, [r6, #33] @ encoding: [0xd6,0xf8,0x21,0x50] +@ CHECK: ldr.w r5, [r6, #257] @ encoding: [0xd6,0xf8,0x01,0x51] +@ CHECK: ldr.w pc, [r7, #257] @ encoding: [0xd7,0xf8,0x01,0xf1] +@ CHECK: ldr r2, [r4, #255]! @ encoding: [0x54,0xf8,0xff,0x2f] +@ CHECK: ldr r8, [sp, #4]! @ encoding: [0x5d,0xf8,0x04,0x8f] +@ CHECK: ldr lr, [sp, #-4]! @ encoding: [0x5d,0xf8,0x04,0xed] +@ CHECK: ldr r2, [r4], #255 @ encoding: [0x54,0xf8,0xff,0x2b] +@ CHECK: ldr r8, [sp], #4 @ encoding: [0x5d,0xf8,0x04,0x8b] +@ CHECK: ldr lr, [sp], #-4 @ encoding: [0x5d,0xf8,0x04,0xe9] + + +@------------------------------------------------------------------------------ +@ LDR(literal) +@------------------------------------------------------------------------------ + ldr.w r5, _foo + +@ CHECK: ldr.w r5, _foo @ encoding: [0x5f'A',0xf8'A',A,0x50'A'] + @ fixup A - offset: 0, value: _foo, kind: fixup_t2_ldst_pcrel_12 + + +@------------------------------------------------------------------------------ +@ LDR(register) +@------------------------------------------------------------------------------ + ldr r1, [r8, r1] + ldr.w r4, [r5, r2] + ldr r6, [r0, r2, lsl #3] + ldr r8, [r8, r2, lsl #2] + ldr r7, [sp, r2, lsl #1] + ldr r7, [sp, r2, lsl #0] + +@ CHECK: ldr.w r1, [r8, r1] @ encoding: [0x58,0xf8,0x01,0x10] +@ CHECK: ldr.w r4, [r5, r2] @ encoding: [0x55,0xf8,0x02,0x40] +@ CHECK: ldr.w r6, [r0, r2, lsl #3] @ encoding: [0x50,0xf8,0x32,0x60] +@ CHECK: ldr.w r8, [r8, r2, lsl #2] @ encoding: [0x58,0xf8,0x22,0x80] +@ CHECK: ldr.w r7, [sp, r2, lsl #1] @ encoding: [0x5d,0xf8,0x12,0x70] +@ CHECK: ldr.w r7, [sp, r2] @ encoding: [0x5d,0xf8,0x02,0x70] + + +@------------------------------------------------------------------------------ +@ LDRB(immediate) +@------------------------------------------------------------------------------ + ldrb r5, [r5, #-4] + ldrb r5, [r6, #32] + ldrb r5, [r6, #33] + ldrb r5, [r6, #257] + ldrb.w lr, [r7, #257] + ldrb r5, [r8, #255]! + ldrb r2, [r5, #4]! + ldrb r1, [r4, #-4]! + ldrb lr, [r3], #255 + ldrb r9, [r2], #4 + ldrb r3, [sp], #-4 + +@ CHECK: ldrb r5, [r5, #-4] @ encoding: [0x15,0xf8,0x04,0x5c] +@ CHECK: ldrb.w r5, [r6, #32] @ encoding: [0x96,0xf8,0x20,0x50] +@ CHECK: ldrb.w r5, [r6, #33] @ encoding: [0x96,0xf8,0x21,0x50] +@ CHECK: ldrb.w r5, [r6, #257] @ encoding: [0x96,0xf8,0x01,0x51] +@ CHECK: ldrb.w lr, [r7, #257] @ encoding: [0x97,0xf8,0x01,0xe1] +@ CHECK: ldrb r5, [r8, #255]! @ encoding: [0x18,0xf8,0xff,0x5f] +@ CHECK: ldrb r2, [r5, #4]! @ encoding: [0x15,0xf8,0x04,0x2f] +@ CHECK: ldrb r1, [r4, #-4]! @ encoding: [0x14,0xf8,0x04,0x1d] +@ CHECK: ldrb lr, [r3], #255 @ encoding: [0x13,0xf8,0xff,0xeb] +@ CHECK: ldrb r9, [r2], #4 @ encoding: [0x12,0xf8,0x04,0x9b] +@ CHECK: ldrb r3, [sp], #-4 @ encoding: [0x1d,0xf8,0x04,0x39] + + +@------------------------------------------------------------------------------ +@ LDRB(register) +@------------------------------------------------------------------------------ + ldrb r1, [r8, r1] + ldrb.w r4, [r5, r2] + ldrb r6, [r0, r2, lsl #3] + ldrb r8, [r8, r2, lsl #2] + ldrb r7, [sp, r2, lsl #1] + ldrb r7, [sp, r2, lsl #0] + +@ CHECK: ldrb.w r1, [r8, r1] @ encoding: [0x18,0xf8,0x01,0x10] +@ CHECK: ldrb.w r4, [r5, r2] @ encoding: [0x15,0xf8,0x02,0x40] +@ CHECK: ldrb.w r6, [r0, r2, lsl #3] @ encoding: [0x10,0xf8,0x32,0x60] +@ CHECK: ldrb.w r8, [r8, r2, lsl #2] @ encoding: [0x18,0xf8,0x22,0x80] +@ CHECK: ldrb.w r7, [sp, r2, lsl #1] @ encoding: [0x1d,0xf8,0x12,0x70] +@ CHECK: ldrb.w r7, [sp, r2] @ encoding: [0x1d,0xf8,0x02,0x70] + + +@------------------------------------------------------------------------------ +@ LDRBT +@------------------------------------------------------------------------------ + ldrbt r1, [r2] + ldrbt r1, [r8, #0] + ldrbt r1, [r8, #3] + ldrbt r1, [r8, #255] + +@ CHECK: ldrbt r1, [r2] @ encoding: [0x12,0xf8,0x00,0x1e] +@ CHECK: ldrbt r1, [r8] @ encoding: [0x18,0xf8,0x00,0x1e] +@ CHECK: ldrbt r1, [r8, #3] @ encoding: [0x18,0xf8,0x03,0x1e] +@ CHECK: ldrbt r1, [r8, #255] @ encoding: [0x18,0xf8,0xff,0x1e] + + +@------------------------------------------------------------------------------ +@ LDRD +@------------------------------------------------------------------------------ + ldrd r3, r5, [r6, #24] + ldrd r3, r5, [r6, #24]! + ldrd r3, r5, [r6], #4 + ldrd r3, r5, [r6], #-8 + ldrd r3, r5, [r6] + ldrd r8, r1, [r3, #0] + +@ CHECK: ldrd r3, r5, [r6, #24] @ encoding: [0xd6,0xe9,0x06,0x35] +@ CHECK: ldrd r3, r5, [r6, #24]! @ encoding: [0xf6,0xe9,0x06,0x35] +@ CHECK: ldrd r3, r5, [r6], #4 @ encoding: [0xf6,0xe8,0x01,0x35] +@ CHECK: ldrd r3, r5, [r6], #-8 @ encoding: [0x76,0xe8,0x02,0x35] +@ CHECK: ldrd r3, r5, [r6] @ encoding: [0xd6,0xe9,0x00,0x35] +@ CHECK: ldrd r8, r1, [r3] @ encoding: [0xd3,0xe9,0x00,0x81] + + +@------------------------------------------------------------------------------ +@ FIXME: LDRD(literal) +@------------------------------------------------------------------------------ + + +@------------------------------------------------------------------------------ +@ LDREX/LDREXB/LDREXH/LDREXD +@------------------------------------------------------------------------------ + ldrex r1, [r4] + ldrex r8, [r4, #0] + ldrex r2, [sp, #128] + ldrexb r5, [r7] + ldrexh r9, [r12] + ldrexd r9, r3, [r4] + +@ CHECK: ldrex r1, [r4] @ encoding: [0x54,0xe8,0x00,0x1f] +@ CHECK: ldrex r8, [r4] @ encoding: [0x54,0xe8,0x00,0x8f] +@ CHECK: ldrex r2, [sp, #128] @ encoding: [0x5d,0xe8,0x20,0x2f] +@ CHECK: ldrexb r5, [r7] @ encoding: [0xd7,0xe8,0x4f,0x5f] +@ CHECK: ldrexh r9, [r12] @ encoding: [0xdc,0xe8,0x5f,0x9f] +@ CHECK: ldrexd r9, r3, [r4] @ encoding: [0xd4,0xe8,0x7f,0x93] + + +@------------------------------------------------------------------------------ +@ LDRH(immediate) +@------------------------------------------------------------------------------ + ldrh r5, [r5, #-4] + ldrh r5, [r6, #32] + ldrh r5, [r6, #33] + ldrh r5, [r6, #257] + ldrh.w lr, [r7, #257] + ldrh r5, [r8, #255]! + ldrh r2, [r5, #4]! + ldrh r1, [r4, #-4]! + ldrh lr, [r3], #255 + ldrh r9, [r2], #4 + ldrh r3, [sp], #-4 + +@ CHECK: ldrh r5, [r5, #-4] @ encoding: [0x35,0xf8,0x04,0x5c] +@ CHECK: ldrh r5, [r6, #32] @ encoding: [0x35,0x8c] +@ CHECK: ldrh.w r5, [r6, #33] @ encoding: [0xb6,0xf8,0x21,0x50] +@ CHECK: ldrh.w r5, [r6, #257] @ encoding: [0xb6,0xf8,0x01,0x51] +@ CHECK: ldrh.w lr, [r7, #257] @ encoding: [0xb7,0xf8,0x01,0xe1] +@ CHECK: ldrh r5, [r8, #255]! @ encoding: [0x38,0xf8,0xff,0x5f] +@ CHECK: ldrh r2, [r5, #4]! @ encoding: [0x35,0xf8,0x04,0x2f] +@ CHECK: ldrh r1, [r4, #-4]! @ encoding: [0x34,0xf8,0x04,0x1d] +@ CHECK: ldrh lr, [r3], #255 @ encoding: [0x33,0xf8,0xff,0xeb] +@ CHECK: ldrh r9, [r2], #4 @ encoding: [0x32,0xf8,0x04,0x9b] +@ CHECK: ldrh r3, [sp], #-4 @ encoding: [0x3d,0xf8,0x04,0x39] + + +@------------------------------------------------------------------------------ +@ LDRH(register) +@------------------------------------------------------------------------------ + ldrh r1, [r8, r1] + ldrh.w r4, [r5, r2] + ldrh r6, [r0, r2, lsl #3] + ldrh r8, [r8, r2, lsl #2] + ldrh r7, [sp, r2, lsl #1] + ldrh r7, [sp, r2, lsl #0] + +@ CHECK: ldrh.w r1, [r8, r1] @ encoding: [0x38,0xf8,0x01,0x10] +@ CHECK: ldrh.w r4, [r5, r2] @ encoding: [0x35,0xf8,0x02,0x40] +@ CHECK: ldrh.w r6, [r0, r2, lsl #3] @ encoding: [0x30,0xf8,0x32,0x60] +@ CHECK: ldrh.w r8, [r8, r2, lsl #2] @ encoding: [0x38,0xf8,0x22,0x80] +@ CHECK: ldrh.w r7, [sp, r2, lsl #1] @ encoding: [0x3d,0xf8,0x12,0x70] +@ CHECK: ldrh.w r7, [sp, r2] @ encoding: [0x3d,0xf8,0x02,0x70] + + +@------------------------------------------------------------------------------ +@ LDRH(literal) +@------------------------------------------------------------------------------ + ldrh r5, _bar + +@ CHECK: ldrh.w r5, _bar @ encoding: [0xbf'A',0xf8'A',A,0x50'A'] +@ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_t2_ldst_pcrel_12 + + +@------------------------------------------------------------------------------ +@ LDRHT +@------------------------------------------------------------------------------ + ldrht r1, [r2] + ldrht r1, [r8, #0] + ldrht r1, [r8, #3] + ldrht r1, [r8, #255] + +@ CHECK: ldrht r1, [r2] @ encoding: [0x32,0xf8,0x00,0x1e] +@ CHECK: ldrht r1, [r8] @ encoding: [0x38,0xf8,0x00,0x1e] +@ CHECK: ldrht r1, [r8, #3] @ encoding: [0x38,0xf8,0x03,0x1e] +@ CHECK: ldrht r1, [r8, #255] @ encoding: [0x38,0xf8,0xff,0x1e] + + +@------------------------------------------------------------------------------ +@ LDRSB(immediate) +@------------------------------------------------------------------------------ + ldrsb r5, [r5, #-4] + ldrsb r5, [r6, #32] + ldrsb r5, [r6, #33] + ldrsb r5, [r6, #257] + ldrsb.w lr, [r7, #257] + +@ CHECK: ldrsb r5, [r5, #-4] @ encoding: [0x15,0xf9,0x04,0x5c] +@ CHECK: ldrsb.w r5, [r6, #32] @ encoding: [0x96,0xf9,0x20,0x50] +@ CHECK: ldrsb.w r5, [r6, #33] @ encoding: [0x96,0xf9,0x21,0x50] +@ CHECK: ldrsb.w r5, [r6, #257] @ encoding: [0x96,0xf9,0x01,0x51] +@ CHECK: ldrsb.w lr, [r7, #257] @ encoding: [0x97,0xf9,0x01,0xe1] + + +@------------------------------------------------------------------------------ +@ LDRSB(register) +@------------------------------------------------------------------------------ + ldrsb r1, [r8, r1] + ldrsb.w r4, [r5, r2] + ldrsb r6, [r0, r2, lsl #3] + ldrsb r8, [r8, r2, lsl #2] + ldrsb r7, [sp, r2, lsl #1] + ldrsb r7, [sp, r2, lsl #0] + ldrsb r5, [r8, #255]! + ldrsb r2, [r5, #4]! + ldrsb r1, [r4, #-4]! + ldrsb lr, [r3], #255 + ldrsb r9, [r2], #4 + ldrsb r3, [sp], #-4 + +@ CHECK: ldrsb.w r1, [r8, r1] @ encoding: [0x18,0xf9,0x01,0x10] +@ CHECK: ldrsb.w r4, [r5, r2] @ encoding: [0x15,0xf9,0x02,0x40] +@ CHECK: ldrsb.w r6, [r0, r2, lsl #3] @ encoding: [0x10,0xf9,0x32,0x60] +@ CHECK: ldrsb.w r8, [r8, r2, lsl #2] @ encoding: [0x18,0xf9,0x22,0x80] +@ CHECK: ldrsb.w r7, [sp, r2, lsl #1] @ encoding: [0x1d,0xf9,0x12,0x70] +@ CHECK: ldrsb.w r7, [sp, r2] @ encoding: [0x1d,0xf9,0x02,0x70] +@ CHECK: ldrsb r5, [r8, #255]! @ encoding: [0x18,0xf9,0xff,0x5f] +@ CHECK: ldrsb r2, [r5, #4]! @ encoding: [0x15,0xf9,0x04,0x2f] +@ CHECK: ldrsb r1, [r4, #-4]! @ encoding: [0x14,0xf9,0x04,0x1d] +@ CHECK: ldrsb lr, [r3], #255 @ encoding: [0x13,0xf9,0xff,0xeb] +@ CHECK: ldrsb r9, [r2], #4 @ encoding: [0x12,0xf9,0x04,0x9b] +@ CHECK: ldrsb r3, [sp], #-4 @ encoding: [0x1d,0xf9,0x04,0x39] + + +@------------------------------------------------------------------------------ +@ LDRSB(literal) +@------------------------------------------------------------------------------ + ldrsb r5, _bar + +@ CHECK: ldrsb.w r5, _bar @ encoding: [0x9f'A',0xf9'A',A,0x50'A'] +@ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_t2_ldst_pcrel_12 + + +@------------------------------------------------------------------------------ +@ LDRSBT +@------------------------------------------------------------------------------ + ldrsbt r1, [r2] + ldrsbt r1, [r8, #0] + ldrsbt r1, [r8, #3] + ldrsbt r1, [r8, #255] + +@ CHECK: ldrsbt r1, [r2] @ encoding: [0x12,0xf9,0x00,0x1e] +@ CHECK: ldrsbt r1, [r8] @ encoding: [0x18,0xf9,0x00,0x1e] +@ CHECK: ldrsbt r1, [r8, #3] @ encoding: [0x18,0xf9,0x03,0x1e] +@ CHECK: ldrsbt r1, [r8, #255] @ encoding: [0x18,0xf9,0xff,0x1e] + + +@------------------------------------------------------------------------------ +@ LDRSH(immediate) +@------------------------------------------------------------------------------ + ldrsh r5, [r5, #-4] + ldrsh r5, [r6, #32] + ldrsh r5, [r6, #33] + ldrsh r5, [r6, #257] + ldrsh.w lr, [r7, #257] + +@ CHECK: ldrsh r5, [r5, #-4] @ encoding: [0x35,0xf9,0x04,0x5c] +@ CHECK: ldrsh.w r5, [r6, #32] @ encoding: [0xb6,0xf9,0x20,0x50] +@ CHECK: ldrsh.w r5, [r6, #33] @ encoding: [0xb6,0xf9,0x21,0x50] +@ CHECK: ldrsh.w r5, [r6, #257] @ encoding: [0xb6,0xf9,0x01,0x51] +@ CHECK: ldrsh.w lr, [r7, #257] @ encoding: [0xb7,0xf9,0x01,0xe1] + + +@------------------------------------------------------------------------------ +@ LDRSH(register) +@------------------------------------------------------------------------------ + ldrsh r1, [r8, r1] + ldrsh.w r4, [r5, r2] + ldrsh r6, [r0, r2, lsl #3] + ldrsh r8, [r8, r2, lsl #2] + ldrsh r7, [sp, r2, lsl #1] + ldrsh r7, [sp, r2, lsl #0] + ldrsh r5, [r8, #255]! + ldrsh r2, [r5, #4]! + ldrsh r1, [r4, #-4]! + ldrsh lr, [r3], #255 + ldrsh r9, [r2], #4 + ldrsh r3, [sp], #-4 + +@ CHECK: ldrsh.w r1, [r8, r1] @ encoding: [0x38,0xf9,0x01,0x10] +@ CHECK: ldrsh.w r4, [r5, r2] @ encoding: [0x35,0xf9,0x02,0x40] +@ CHECK: ldrsh.w r6, [r0, r2, lsl #3] @ encoding: [0x30,0xf9,0x32,0x60] +@ CHECK: ldrsh.w r8, [r8, r2, lsl #2] @ encoding: [0x38,0xf9,0x22,0x80] +@ CHECK: ldrsh.w r7, [sp, r2, lsl #1] @ encoding: [0x3d,0xf9,0x12,0x70] +@ CHECK: ldrsh.w r7, [sp, r2] @ encoding: [0x3d,0xf9,0x02,0x70] +@ CHECK: ldrsh r5, [r8, #255]! @ encoding: [0x38,0xf9,0xff,0x5f] +@ CHECK: ldrsh r2, [r5, #4]! @ encoding: [0x35,0xf9,0x04,0x2f] +@ CHECK: ldrsh r1, [r4, #-4]! @ encoding: [0x34,0xf9,0x04,0x1d] +@ CHECK: ldrsh lr, [r3], #255 @ encoding: [0x33,0xf9,0xff,0xeb] +@ CHECK: ldrsh r9, [r2], #4 @ encoding: [0x32,0xf9,0x04,0x9b] +@ CHECK: ldrsh r3, [sp], #-4 @ encoding: [0x3d,0xf9,0x04,0x39] + + +@------------------------------------------------------------------------------ +@ LDRSH(literal) +@------------------------------------------------------------------------------ + ldrsh r5, _bar + +@ CHECK: ldrsh.w r5, _bar @ encoding: [0xbf'A',0xf9'A',A,0x50'A'] +@ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_t2_ldst_pcrel_12 + +@ TEMPORARILY DISABLED: +@ ldrsh.w r4, [pc, #1435] +@ : ldrsh.w r4, [pc, #1435] @ encoding: [0x3f,0xf9,0x9b,0x45] + +@------------------------------------------------------------------------------ +@ LDRSHT +@------------------------------------------------------------------------------ + ldrsht r1, [r2] + ldrsht r1, [r8, #0] + ldrsht r1, [r8, #3] + ldrsht r1, [r8, #255] + +@ CHECK: ldrsht r1, [r2] @ encoding: [0x32,0xf9,0x00,0x1e] +@ CHECK: ldrsht r1, [r8] @ encoding: [0x38,0xf9,0x00,0x1e] +@ CHECK: ldrsht r1, [r8, #3] @ encoding: [0x38,0xf9,0x03,0x1e] +@ CHECK: ldrsht r1, [r8, #255] @ encoding: [0x38,0xf9,0xff,0x1e] + + +@------------------------------------------------------------------------------ +@ LDRT +@------------------------------------------------------------------------------ + ldrt r1, [r2] + ldrt r2, [r6, #0] + ldrt r3, [r7, #3] + ldrt r4, [r9, #255] + +@ CHECK: ldrt r1, [r2] @ encoding: [0x52,0xf8,0x00,0x1e] +@ CHECK: ldrt r2, [r6] @ encoding: [0x56,0xf8,0x00,0x2e] +@ CHECK: ldrt r3, [r7, #3] @ encoding: [0x57,0xf8,0x03,0x3e] +@ CHECK: ldrt r4, [r9, #255] @ encoding: [0x59,0xf8,0xff,0x4e] + + +@------------------------------------------------------------------------------ +@ LSL (immediate) +@------------------------------------------------------------------------------ + lsl r2, r3, #12 + lsls r8, r3, #31 + lsls.w r2, r3, #1 + lsl r2, r3, #4 + lsls r2, r12, #15 + + lsl r3, #19 + lsls r8, #2 + lsls.w r7, #5 + lsl.w r12, #21 + +@ CHECK: lsl.w r2, r3, #12 @ encoding: [0x4f,0xea,0x03,0x32] +@ CHECK: lsls.w r8, r3, #31 @ encoding: [0x5f,0xea,0xc3,0x78] +@ CHECK: lsls.w r2, r3, #1 @ encoding: [0x5f,0xea,0x43,0x02] +@ CHECK: lsl.w r2, r3, #4 @ encoding: [0x4f,0xea,0x03,0x12] +@ CHECK: lsls.w r2, r12, #15 @ encoding: [0x5f,0xea,0xcc,0x32] + +@ CHECK: lsl.w r3, r3, #19 @ encoding: [0x4f,0xea,0xc3,0x43] +@ CHECK: lsls.w r8, r8, #2 @ encoding: [0x5f,0xea,0x88,0x08] +@ CHECK: lsls.w r7, r7, #5 @ encoding: [0x5f,0xea,0x47,0x17] +@ CHECK: lsl.w r12, r12, #21 @ encoding: [0x4f,0xea,0x4c,0x5c] + + +@------------------------------------------------------------------------------ +@ LSL (register) +@------------------------------------------------------------------------------ + lsl r3, r4, r2 + lsl.w r1, r2 + lsls r3, r4, r8 + +@ CHECK: lsl.w r3, r4, r2 @ encoding: [0x04,0xfa,0x02,0xf3] +@ CHECK: lsl.w r1, r1, r2 @ encoding: [0x01,0xfa,0x02,0xf1] +@ CHECK: lsls.w r3, r4, r8 @ encoding: [0x14,0xfa,0x08,0xf3] + + +@------------------------------------------------------------------------------ +@ LSR (immediate) +@------------------------------------------------------------------------------ + lsr r2, r3, #12 + lsrs r8, r3, #32 + lsrs.w r2, r3, #1 + lsr r2, r3, #4 + lsrs r2, r12, #15 + + lsr r3, #19 + lsrs r8, #2 + lsrs.w r7, #5 + lsr.w r12, #21 + +@ CHECK: lsr.w r2, r3, #12 @ encoding: [0x4f,0xea,0x13,0x32] +@ CHECK: lsrs.w r8, r3, #32 @ encoding: [0x5f,0xea,0x13,0x08] +@ CHECK: lsrs.w r2, r3, #1 @ encoding: [0x5f,0xea,0x53,0x02] +@ CHECK: lsr.w r2, r3, #4 @ encoding: [0x4f,0xea,0x13,0x12] +@ CHECK: lsrs.w r2, r12, #15 @ encoding: [0x5f,0xea,0xdc,0x32] + +@ CHECK: lsr.w r3, r3, #19 @ encoding: [0x4f,0xea,0xd3,0x43] +@ CHECK: lsrs.w r8, r8, #2 @ encoding: [0x5f,0xea,0x98,0x08] +@ CHECK: lsrs.w r7, r7, #5 @ encoding: [0x5f,0xea,0x57,0x17] +@ CHECK: lsr.w r12, r12, #21 @ encoding: [0x4f,0xea,0x5c,0x5c] + + +@------------------------------------------------------------------------------ +@ LSR (register) +@------------------------------------------------------------------------------ + lsr r3, r4, r2 + lsr.w r1, r2 + lsrs r3, r4, r8 + +@ CHECK: lsr.w r3, r4, r2 @ encoding: [0x24,0xfa,0x02,0xf3] +@ CHECK: lsr.w r1, r1, r2 @ encoding: [0x21,0xfa,0x02,0xf1] +@ CHECK: lsrs.w r3, r4, r8 @ encoding: [0x34,0xfa,0x08,0xf3] + +@------------------------------------------------------------------------------ +@ MCR/MCR2 +@------------------------------------------------------------------------------ + mcr p7, #1, r5, c1, c1, #4 + mcr2 p7, #1, r5, c1, c1, #4 + +@ CHECK: mcr p7, #1, r5, c1, c1, #4 @ encoding: [0x21,0xee,0x91,0x57] +@ CHECK: mcr2 p7, #1, r5, c1, c1, #4 @ encoding: [0x21,0xfe,0x91,0x57] + + +@------------------------------------------------------------------------------ +@ MCRR/MCRR2 +@------------------------------------------------------------------------------ + mcrr p7, #15, r5, r4, c1 + mcrr2 p7, #15, r5, r4, c1 + +@ CHECK: mcrr p7, #15, r5, r4, c1 @ encoding: [0x44,0xec,0xf1,0x57] +@ CHECK: mcrr2 p7, #15, r5, r4, c1 @ encoding: [0x44,0xfc,0xf1,0x57] + + +@------------------------------------------------------------------------------ +@ MLA/MLS +@------------------------------------------------------------------------------ + mla r1,r2,r3,r4 + mls r1,r2,r3,r4 + +@ CHECK: mla r1, r2, r3, r4 @ encoding: [0x02,0xfb,0x03,0x41] +@ CHECK: mls r1, r2, r3, r4 @ encoding: [0x02,0xfb,0x13,0x41] + + +@------------------------------------------------------------------------------ +@ MOV(immediate) +@------------------------------------------------------------------------------ + movs r1, #21 + movs.w r1, #21 + movs r8, #21 + movw r0, #65535 + movw r1, #43777 + movw r1, #43792 + mov.w r0, #0x3fc0000 + mov r0, #0x3fc0000 + movs.w r0, #0x3fc0000 + itte eq + movseq r1, #12 + moveq r1, #12 + movne.w r1, #12 + mov.w r6, #450 + +@ CHECK: movs r1, #21 @ encoding: [0x15,0x21] +@ CHECK: movs.w r1, #21 @ encoding: [0x5f,0xf0,0x15,0x01] +@ CHECK: movs.w r8, #21 @ encoding: [0x5f,0xf0,0x15,0x08] +@ CHECK: movw r0, #65535 @ encoding: [0x4f,0xf6,0xff,0x70] +@ CHECK: movw r1, #43777 @ encoding: [0x4a,0xf6,0x01,0x31] +@ CHECK: movw r1, #43792 @ encoding: [0x4a,0xf6,0x10,0x31] +@ CHECK: mov.w r0, #66846720 @ encoding: [0x4f,0xf0,0x7f,0x70] +@ CHECK: mov.w r0, #66846720 @ encoding: [0x4f,0xf0,0x7f,0x70] +@ CHECK: movs.w r0, #66846720 @ encoding: [0x5f,0xf0,0x7f,0x70] +@ CHECK: itte eq @ encoding: [0x06,0xbf] +@ CHECK: movseq.w r1, #12 @ encoding: [0x5f,0xf0,0x0c,0x01] +@ CHECK: moveq r1, #12 @ encoding: [0x0c,0x21] +@ CHECK: movne.w r1, #12 @ encoding: [0x4f,0xf0,0x0c,0x01] +@ CHECK: mov.w r6, #450 @ encoding: [0x4f,0xf4,0xe1,0x76] + + +@------------------------------------------------------------------------------ +@ MOVT +@------------------------------------------------------------------------------ + movt r3, #7 + movt r6, #0xffff + it eq + movteq r4, #0xff0 + +@ CHECK: movt r3, #7 @ encoding: [0xc0,0xf2,0x07,0x03] +@ CHECK: movt r6, #65535 @ encoding: [0xcf,0xf6,0xff,0x76] +@ CHECK: it eq @ encoding: [0x08,0xbf] +@ CHECK: movteq r4, #4080 @ encoding: [0xc0,0xf6,0xf0,0x74] + +@------------------------------------------------------------------------------ +@ MRC/MRC2 +@------------------------------------------------------------------------------ + mrc p14, #0, r1, c1, c2, #4 + mrc2 p14, #0, r1, c1, c2, #4 + +@ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xee,0x92,0x1e] +@ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xfe,0x92,0x1e] + + +@------------------------------------------------------------------------------ +@ MRRC/MRRC2 +@------------------------------------------------------------------------------ + mrrc p7, #1, r5, r4, c1 + mrrc2 p7, #1, r5, r4, c1 + +@ CHECK: mrrc p7, #1, r5, r4, c1 @ encoding: [0x54,0xec,0x11,0x57] +@ CHECK: mrrc2 p7, #1, r5, r4, c1 @ encoding: [0x54,0xfc,0x11,0x57] + + +@------------------------------------------------------------------------------ +@ MRS +@------------------------------------------------------------------------------ + mrs r8, apsr + mrs r8, cpsr + mrs r8, spsr + +@ CHECK: mrs r8, apsr @ encoding: [0xef,0xf3,0x00,0x88] +@ CHECK: mrs r8, apsr @ encoding: [0xef,0xf3,0x00,0x88] +@ CHECK: mrs r8, spsr @ encoding: [0xff,0xf3,0x00,0x88] + + +@------------------------------------------------------------------------------ +@ MSR +@------------------------------------------------------------------------------ + msr apsr, r1 + msr apsr_g, r2 + msr apsr_nzcvq, r3 + msr APSR_nzcvq, r4 + msr apsr_nzcvqg, r5 + msr cpsr_fc, r6 + msr cpsr_c, r7 + msr cpsr_x, r8 + msr cpsr_fc, r9 + msr cpsr_all, r11 + msr cpsr_fsx, r12 + msr spsr_fc, r0 + msr SPSR_fsxc, r5 + msr cpsr_fsxc, r8 + +@ CHECK: msr APSR_nzcvq, r1 @ encoding: [0x81,0xf3,0x00,0x88] +@ CHECK: msr APSR_g, r2 @ encoding: [0x82,0xf3,0x00,0x84] +@ CHECK: msr APSR_nzcvq, r3 @ encoding: [0x83,0xf3,0x00,0x88] +@ CHECK: msr APSR_nzcvq, r4 @ encoding: [0x84,0xf3,0x00,0x88] +@ CHECK: msr APSR_nzcvqg, r5 @ encoding: [0x85,0xf3,0x00,0x8c] +@ CHECK: msr CPSR_fc, r6 @ encoding: [0x86,0xf3,0x00,0x89] +@ CHECK: msr CPSR_c, r7 @ encoding: [0x87,0xf3,0x00,0x81] +@ CHECK: msr CPSR_x, r8 @ encoding: [0x88,0xf3,0x00,0x82] +@ CHECK: msr CPSR_fc, r9 @ encoding: [0x89,0xf3,0x00,0x89] +@ CHECK: msr CPSR_fc, r11 @ encoding: [0x8b,0xf3,0x00,0x89] +@ CHECK: msr CPSR_fsx, r12 @ encoding: [0x8c,0xf3,0x00,0x8e] +@ CHECK: msr SPSR_fc, r0 @ encoding: [0x90,0xf3,0x00,0x89] +@ CHECK: msr SPSR_fsxc, r5 @ encoding: [0x95,0xf3,0x00,0x8f] +@ CHECK: msr CPSR_fsxc, r8 @ encoding: [0x88,0xf3,0x00,0x8f] + + +@------------------------------------------------------------------------------ +@ MUL +@------------------------------------------------------------------------------ + muls r3, r4, r3 + mul r3, r4, r3 + mul r3, r4, r6 + it eq + muleq r3, r4, r5 + +@ CHECK: muls r3, r4, r3 @ encoding: [0x63,0x43] +@ CHECK: mul r3, r4, r3 @ encoding: [0x04,0xfb,0x03,0xf3] +@ CHECK: mul r3, r4, r6 @ encoding: [0x04,0xfb,0x06,0xf3] +@ CHECK: it eq @ encoding: [0x08,0xbf] +@ CHECK: muleq r3, r4, r5 @ encoding: [0x04,0xfb,0x05,0xf3] + + +@------------------------------------------------------------------------------ +@ MVN(immediate) +@------------------------------------------------------------------------------ + mvns r8, #21 + mvn r0, #0x3fc0000 + mvns r0, #0x3fc0000 + itte eq + mvnseq r1, #12 + mvneq r1, #12 + mvnne r1, #12 + +@ CHECK: mvns r8, #21 @ encoding: [0x7f,0xf0,0x15,0x08] +@ CHECK: mvn r0, #66846720 @ encoding: [0x6f,0xf0,0x7f,0x70] +@ CHECK: mvns r0, #66846720 @ encoding: [0x7f,0xf0,0x7f,0x70] +@ CHECK: itte eq @ encoding: [0x06,0xbf] +@ CHECK: mvnseq r1, #12 @ encoding: [0x7f,0xf0,0x0c,0x01] +@ CHECK: mvneq r1, #12 @ encoding: [0x6f,0xf0,0x0c,0x01] +@ CHECK: mvnne r1, #12 @ encoding: [0x6f,0xf0,0x0c,0x01] + + +@------------------------------------------------------------------------------ +@ MVN(register) +@------------------------------------------------------------------------------ + mvn r2, r3 + mvns r2, r3 + mvn r5, r6, lsl #19 + mvn r5, r6, lsr #9 + mvn r5, r6, asr #4 + mvn r5, r6, ror #6 + mvn r5, r6, rrx + it eq + mvneq r2, r3 + +@ CHECK: mvn.w r2, r3 @ encoding: [0x6f,0xea,0x03,0x02] +@ CHECK: mvns r2, r3 @ encoding: [0xda,0x43] +@ CHECK: mvn.w r5, r6, lsl #19 @ encoding: [0x6f,0xea,0xc6,0x45] +@ CHECK: mvn.w r5, r6, lsr #9 @ encoding: [0x6f,0xea,0x56,0x25] +@ CHECK: mvn.w r5, r6, asr #4 @ encoding: [0x6f,0xea,0x26,0x15] +@ CHECK: mvn.w r5, r6, ror #6 @ encoding: [0x6f,0xea,0xb6,0x15] +@ CHECK: mvn.w r5, r6, rrx @ encoding: [0x6f,0xea,0x36,0x05] +@ CHECK: it eq @ encoding: [0x08,0xbf] +@ CHECK: mvneq r2, r3 @ encoding: [0xda,0x43] + +@------------------------------------------------------------------------------ +@ NOP +@------------------------------------------------------------------------------ + nop.w + +@ CHECK: nop.w @ encoding: [0xaf,0xf3,0x00,0x80] + + +@------------------------------------------------------------------------------ +@ ORN +@------------------------------------------------------------------------------ + orn r4, r5, #0xf000 + orn r4, r5, r6 + orns r4, r5, r6 + orn r4, r5, r6, lsl #5 + orns r4, r5, r6, lsr #5 + orn r4, r5, r6, lsr #5 + orns r4, r5, r6, asr #5 + orn r4, r5, r6, ror #5 + +@ CHECK: orn r4, r5, #61440 @ encoding: [0x65,0xf4,0x70,0x44] +@ CHECK: orn r4, r5, r6 @ encoding: [0x65,0xea,0x06,0x04] +@ CHECK: orns r4, r5, r6 @ encoding: [0x75,0xea,0x06,0x04] +@ CHECK: orn r4, r5, r6, lsl #5 @ encoding: [0x65,0xea,0x46,0x14] +@ CHECK: orns r4, r5, r6, lsr #5 @ encoding: [0x75,0xea,0x56,0x14] +@ CHECK: orn r4, r5, r6, lsr #5 @ encoding: [0x65,0xea,0x56,0x14] +@ CHECK: orns r4, r5, r6, asr #5 @ encoding: [0x75,0xea,0x66,0x14] +@ CHECK: orn r4, r5, r6, ror #5 @ encoding: [0x65,0xea,0x76,0x14] + + +@------------------------------------------------------------------------------ +@ ORR +@------------------------------------------------------------------------------ + orr r4, r5, #0xf000 + orr r4, r5, r6 + orr r4, r5, r6, lsl #5 + orrs r4, r5, r6, lsr #5 + orr r4, r5, r6, lsr #5 + orrs r4, r5, r6, asr #5 + orr r4, r5, r6, ror #5 + +@ CHECK: orr r4, r5, #61440 @ encoding: [0x45,0xf4,0x70,0x44] +@ CHECK: orr.w r4, r5, r6 @ encoding: [0x45,0xea,0x06,0x04] +@ CHECK: orr.w r4, r5, r6, lsl #5 @ encoding: [0x45,0xea,0x46,0x14] +@ CHECK: orrs.w r4, r5, r6, lsr #5 @ encoding: [0x55,0xea,0x56,0x14] +@ CHECK: orr.w r4, r5, r6, lsr #5 @ encoding: [0x45,0xea,0x56,0x14] +@ CHECK: orrs.w r4, r5, r6, asr #5 @ encoding: [0x55,0xea,0x66,0x14] +@ CHECK: orr.w r4, r5, r6, ror #5 @ encoding: [0x45,0xea,0x76,0x14] + + +@------------------------------------------------------------------------------ +@ PKH +@------------------------------------------------------------------------------ + pkhbt r2, r2, r3 + pkhbt r2, r2, r3, lsl #31 + pkhbt r2, r2, r3, lsl #0 + pkhbt r2, r2, r3, lsl #15 + + pkhtb r2, r2, r3 + pkhtb r2, r2, r3, asr #31 + pkhtb r2, r2, r3, asr #15 + +@ CHECK: pkhbt r2, r2, r3 @ encoding: [0xc2,0xea,0x03,0x02] +@ CHECK: pkhbt r2, r2, r3, lsl #31 @ encoding: [0xc2,0xea,0xc3,0x72] +@ CHECK: pkhbt r2, r2, r3 @ encoding: [0xc2,0xea,0x03,0x02] +@ CHECK: pkhbt r2, r2, r3, lsl #15 @ encoding: [0xc2,0xea,0xc3,0x32] + +@ CHECK: pkhbt r2, r2, r3 @ encoding: [0xc2,0xea,0x03,0x02] +@ CHECK: pkhtb r2, r2, r3, asr #31 @ encoding: [0xc2,0xea,0xe3,0x72] +@ CHECK: pkhtb r2, r2, r3, asr #15 @ encoding: [0xc2,0xea,0xe3,0x32] + + +@------------------------------------------------------------------------------ +@ PLD(immediate) +@------------------------------------------------------------------------------ + pld [r5, #-4] + pld [r6, #32] + pld [r6, #33] + pld [r6, #257] + pld [r7, #257] + +@ CHECK: pld [r5, #-4] @ encoding: [0x15,0xf8,0x04,0xfc] +@ CHECK: pld [r6, #32] @ encoding: [0x96,0xf8,0x20,0xf0] +@ CHECK: pld [r6, #33] @ encoding: [0x96,0xf8,0x21,0xf0] +@ CHECK: pld [r6, #257] @ encoding: [0x96,0xf8,0x01,0xf1] +@ CHECK: pld [r7, #257] @ encoding: [0x97,0xf8,0x01,0xf1] + + +@------------------------------------------------------------------------------ +@ PLD(literal) +@------------------------------------------------------------------------------ + pld _foo + +@ CHECK: pld _foo @ encoding: [0x9f'A',0xf8'A',A,0xf0'A'] + @ fixup A - offset: 0, value: _foo, kind: fixup_t2_ldst_pcrel_12 + + +@------------------------------------------------------------------------------ +@ PLD(register) +@------------------------------------------------------------------------------ + pld [r8, r1] + pld [r5, r2] + pld [r0, r2, lsl #3] + pld [r8, r2, lsl #2] + pld [sp, r2, lsl #1] + pld [sp, r2, lsl #0] + +@ CHECK: pld [r8, r1] @ encoding: [0x18,0xf8,0x01,0xf0] +@ CHECK: pld [r5, r2] @ encoding: [0x15,0xf8,0x02,0xf0] +@ CHECK: pld [r0, r2, lsl #3] @ encoding: [0x10,0xf8,0x32,0xf0] +@ CHECK: pld [r8, r2, lsl #2] @ encoding: [0x18,0xf8,0x22,0xf0] +@ CHECK: pld [sp, r2, lsl #1] @ encoding: [0x1d,0xf8,0x12,0xf0] +@ CHECK: pld [sp, r2] @ encoding: [0x1d,0xf8,0x02,0xf0] + +@------------------------------------------------------------------------------ +@ PLI(immediate) +@------------------------------------------------------------------------------ + pli [r5, #-4] + pli [r6, #32] + pli [r6, #33] + pli [r6, #257] + pli [r7, #257] + +@ CHECK: pli [r5, #-4] @ encoding: [0x15,0xf9,0x04,0xfc] +@ CHECK: pli [r6, #32] @ encoding: [0x96,0xf9,0x20,0xf0] +@ CHECK: pli [r6, #33] @ encoding: [0x96,0xf9,0x21,0xf0] +@ CHECK: pli [r6, #257] @ encoding: [0x96,0xf9,0x01,0xf1] +@ CHECK: pli [r7, #257] @ encoding: [0x97,0xf9,0x01,0xf1] + + +@------------------------------------------------------------------------------ +@ PLI(literal) +@------------------------------------------------------------------------------ + pli _foo + + +@ CHECK: pli _foo @ encoding: [0x9f'A',0xf9'A',A,0xf0'A'] + @ fixup A - offset: 0, value: _foo, kind: fixup_t2_ldst_pcrel_12 + + +@------------------------------------------------------------------------------ +@ PLI(register) +@------------------------------------------------------------------------------ + pli [r8, r1] + pli [r5, r2] + pli [r0, r2, lsl #3] + pli [r8, r2, lsl #2] + pli [sp, r2, lsl #1] + pli [sp, r2, lsl #0] + +@ CHECK: pli [r8, r1] @ encoding: [0x18,0xf9,0x01,0xf0] +@ CHECK: pli [r5, r2] @ encoding: [0x15,0xf9,0x02,0xf0] +@ CHECK: pli [r0, r2, lsl #3] @ encoding: [0x10,0xf9,0x32,0xf0] +@ CHECK: pli [r8, r2, lsl #2] @ encoding: [0x18,0xf9,0x22,0xf0] +@ CHECK: pli [sp, r2, lsl #1] @ encoding: [0x1d,0xf9,0x12,0xf0] +@ CHECK: pli [sp, r2] @ encoding: [0x1d,0xf9,0x02,0xf0] + + +@------------------------------------------------------------------------------ +@ QADD/QADD16/QADD8 +@------------------------------------------------------------------------------ + qadd r1, r2, r3 + qadd16 r1, r2, r3 + qadd8 r1, r2, r3 + itte gt + qaddgt r1, r2, r3 + qadd16gt r1, r2, r3 + qadd8le r1, r2, r3 + +@ CHECK: qadd r1, r2, r3 @ encoding: [0x83,0xfa,0x82,0xf1] +@ CHECK: qadd16 r1, r2, r3 @ encoding: [0x92,0xfa,0x13,0xf1] +@ CHECK: qadd8 r1, r2, r3 @ encoding: [0x82,0xfa,0x13,0xf1] +@ CHECK: itte gt @ encoding: [0xc6,0xbf] +@ CHECK: qaddgt r1, r2, r3 @ encoding: [0x83,0xfa,0x82,0xf1] +@ CHECK: qadd16gt r1, r2, r3 @ encoding: [0x92,0xfa,0x13,0xf1] +@ CHECK: qadd8le r1, r2, r3 @ encoding: [0x82,0xfa,0x13,0xf1] + + +@------------------------------------------------------------------------------ +@ QDADD/QDSUB +@------------------------------------------------------------------------------ + qdadd r6, r7, r8 + qdsub r6, r7, r8 + itt hi + qdaddhi r6, r7, r8 + qdsubhi r6, r7, r8 + +@ CHECK: qdadd r6, r7, r8 @ encoding: [0x88,0xfa,0x97,0xf6] +@ CHECK: qdsub r6, r7, r8 @ encoding: [0x88,0xfa,0xb7,0xf6] +@ CHECK: itt hi @ encoding: [0x84,0xbf] +@ CHECK: qdaddhi r6, r7, r8 @ encoding: [0x88,0xfa,0x97,0xf6] +@ CHECK: qdsubhi r6, r7, r8 @ encoding: [0x88,0xfa,0xb7,0xf6] + + +@------------------------------------------------------------------------------ +@ QSAX +@------------------------------------------------------------------------------ + qsax r9, r12, r0 + it eq + qsaxeq r9, r12, r0 + +@ CHECK: qsax r9, r12, r0 @ encoding: [0xec,0xfa,0x10,0xf9] +@ CHECK: it eq @ encoding: [0x08,0xbf] +@ CHECK: qsaxeq r9, r12, r0 @ encoding: [0xec,0xfa,0x10,0xf9] + + +@------------------------------------------------------------------------------ +@ QSUB/QSUB16/QSUB8 +@------------------------------------------------------------------------------ + qsub r1, r2, r3 + qsub16 r1, r2, r3 + qsub8 r1, r2, r3 + itet le + qsuble r1, r2, r3 + qsub16gt r1, r2, r3 + qsub8le r1, r2, r3 + +@ CHECK: qsub r1, r2, r3 @ encoding: [0x83,0xfa,0xa2,0xf1] +@ CHECK: qsub16 r1, r2, r3 @ encoding: [0xd2,0xfa,0x13,0xf1] +@ CHECK: qsub8 r1, r2, r3 @ encoding: [0xc2,0xfa,0x13,0xf1] +@ CHECK: itet le @ encoding: [0xd6,0xbf] +@ CHECK: qsuble r1, r2, r3 @ encoding: [0x83,0xfa,0xa2,0xf1] +@ CHECK: qsub16gt r1, r2, r3 @ encoding: [0xd2,0xfa,0x13,0xf1] +@ CHECK: qsub8le r1, r2, r3 @ encoding: [0xc2,0xfa,0x13,0xf1] + + +@------------------------------------------------------------------------------ +@ RBIT +@------------------------------------------------------------------------------ + rbit r1, r2 + it ne + rbitne r1, r2 + +@ CHECK: rbit r1, r2 @ encoding: [0x92,0xfa,0xa2,0xf1] +@ CHECK: it ne @ encoding: [0x18,0xbf] +@ CHECK: rbitne r1, r2 @ encoding: [0x92,0xfa,0xa2,0xf1] + + +@------------------------------------------------------------------------------ +@ REV +@------------------------------------------------------------------------------ + rev.w r1, r2 + rev r2, r8 + itt ne + revne r1, r2 + revne r1, r8 + +@ CHECK: rev.w r1, r2 @ encoding: [0x92,0xfa,0x82,0xf1] +@ CHECK: rev.w r2, r8 @ encoding: [0x98,0xfa,0x88,0xf2] +@ CHECK: itt ne @ encoding: [0x1c,0xbf] +@ CHECK: revne r1, r2 @ encoding: [0x11,0xba] +@ CHECK: revne.w r1, r8 @ encoding: [0x98,0xfa,0x88,0xf1] + + +@------------------------------------------------------------------------------ +@ REV16 +@------------------------------------------------------------------------------ + rev16.w r1, r2 + rev16 r2, r8 + itt ne + rev16ne r1, r2 + rev16ne r1, r8 + +@ CHECK: rev16.w r1, r2 @ encoding: [0x92,0xfa,0x92,0xf1] +@ CHECK: rev16.w r2, r8 @ encoding: [0x98,0xfa,0x98,0xf2] +@ CHECK: itt ne @ encoding: [0x1c,0xbf] +@ CHECK: rev16ne r1, r2 @ encoding: [0x51,0xba] +@ CHECK: rev16ne.w r1, r8 @ encoding: [0x98,0xfa,0x98,0xf1] + + +@------------------------------------------------------------------------------ +@ REVSH +@------------------------------------------------------------------------------ + revsh.w r1, r2 + revsh r2, r8 + itt ne + revshne r1, r2 + revshne r1, r8 + +@ CHECK: revsh.w r1, r2 @ encoding: [0x92,0xfa,0xb2,0xf1] +@ CHECK: revsh.w r2, r8 @ encoding: [0x98,0xfa,0xb8,0xf2] +@ CHECK: itt ne @ encoding: [0x1c,0xbf] +@ CHECK: revshne r1, r2 @ encoding: [0xd1,0xba] +@ CHECK: revshne.w r1, r8 @ encoding: [0x98,0xfa,0xb8,0xf1] + + +@------------------------------------------------------------------------------ +@ ROR (immediate) +@------------------------------------------------------------------------------ + ror r2, r3, #12 + rors r8, r3, #31 + rors.w r2, r3, #1 + ror r2, r3, #4 + rors r2, r12, #15 + + ror r3, #19 + rors r8, #2 + rors.w r7, #5 + ror.w r12, #21 + +@ CHECK: ror.w r2, r3, #12 @ encoding: [0x4f,0xea,0x33,0x32] +@ CHECK: rors.w r8, r3, #31 @ encoding: [0x5f,0xea,0xf3,0x78] +@ CHECK: rors.w r2, r3, #1 @ encoding: [0x5f,0xea,0x73,0x02] +@ CHECK: ror.w r2, r3, #4 @ encoding: [0x4f,0xea,0x33,0x12] +@ CHECK: rors.w r2, r12, #15 @ encoding: [0x5f,0xea,0xfc,0x32] + +@ CHECK: ror.w r3, r3, #19 @ encoding: [0x4f,0xea,0xf3,0x43] +@ CHECK: rors.w r8, r8, #2 @ encoding: [0x5f,0xea,0xb8,0x08] +@ CHECK: rors.w r7, r7, #5 @ encoding: [0x5f,0xea,0x77,0x17] +@ CHECK: ror.w r12, r12, #21 @ encoding: [0x4f,0xea,0x7c,0x5c] + + +@------------------------------------------------------------------------------ +@ ROR (register) +@------------------------------------------------------------------------------ + ror r3, r4, r2 + ror.w r1, r2 + rors r3, r4, r8 + +@ CHECK: ror.w r3, r4, r2 @ encoding: [0x64,0xfa,0x02,0xf3] +@ CHECK: ror.w r1, r1, r2 @ encoding: [0x61,0xfa,0x02,0xf1] +@ CHECK: rors.w r3, r4, r8 @ encoding: [0x74,0xfa,0x08,0xf3] + + +@------------------------------------------------------------------------------ +@ RRX +@------------------------------------------------------------------------------ + rrx r1, r2 + rrxs r1, r2 + ite lt + rrxlt r9, r12 + rrxsge r8, r3 + +@ CHECK: rrx r1, r2 @ encoding: [0x4f,0xea,0x32,0x01] +@ CHECK: rrxs r1, r2 @ encoding: [0x5f,0xea,0x32,0x01] +@ CHECK: ite lt @ encoding: [0xb4,0xbf] +@ CHECK: rrxlt r9, r12 @ encoding: [0x4f,0xea,0x3c,0x09] +@ CHECK: rrxsge r8, r3 @ encoding: [0x5f,0xea,0x33,0x08] + +@------------------------------------------------------------------------------ +@ RSB (immediate) +@------------------------------------------------------------------------------ + rsb r2, r5, #0xff000 + rsbs r3, r12, #0xf + rsb r1, #0xff + rsb r1, r1, #0xff + +@ CHECK: rsb.w r2, r5, #1044480 @ encoding: [0xc5,0xf5,0x7f,0x22] +@ CHECK: rsbs.w r3, r12, #15 @ encoding: [0xdc,0xf1,0x0f,0x03] +@ CHECK: rsb.w r1, r1, #255 @ encoding: [0xc1,0xf1,0xff,0x01] +@ CHECK: rsb.w r1, r1, #255 @ encoding: [0xc1,0xf1,0xff,0x01] + + +@------------------------------------------------------------------------------ +@ RSB (register) +@------------------------------------------------------------------------------ + rsb r4, r8 + rsb r4, r9, r8 + rsb r1, r4, r8, asr #3 + rsbs r2, r1, r7, lsl #1 + +@ CHECK: rsb r4, r4, r8 @ encoding: [0xc4,0xeb,0x08,0x04] +@ CHECK: rsb r4, r9, r8 @ encoding: [0xc9,0xeb,0x08,0x04] +@ CHECK: rsb r1, r4, r8, asr #3 @ encoding: [0xc4,0xeb,0xe8,0x01] +@ CHECK: rsbs r2, r1, r7, lsl #1 @ encoding: [0xd1,0xeb,0x47,0x02] + + +@------------------------------------------------------------------------------ +@ SADD16 +@------------------------------------------------------------------------------ + sadd16 r3, r4, r8 + it ne + sadd16ne r3, r4, r8 + +@ CHECK: sadd16 r3, r4, r8 @ encoding: [0x94,0xfa,0x08,0xf3] +@ CHECK: it ne @ encoding: [0x18,0xbf] +@ CHECK: sadd16ne r3, r4, r8 @ encoding: [0x94,0xfa,0x08,0xf3] + + +@------------------------------------------------------------------------------ +@ SADD8 +@------------------------------------------------------------------------------ + sadd8 r3, r4, r8 + it ne + sadd8ne r3, r4, r8 + +@ CHECK: sadd8 r3, r4, r8 @ encoding: [0x84,0xfa,0x08,0xf3] +@ CHECK: it ne @ encoding: [0x18,0xbf] +@ CHECK: sadd8ne r3, r4, r8 @ encoding: [0x84,0xfa,0x08,0xf3] + + +@------------------------------------------------------------------------------ +@ SASX +@------------------------------------------------------------------------------ + saddsubx r9, r2, r7 + it ne + saddsubxne r2, r5, r6 + sasx r9, r2, r7 + it ne + sasxne r2, r5, r6 + +@ CHECK: sasx r9, r2, r7 @ encoding: [0xa2,0xfa,0x07,0xf9] +@ CHECK: it ne @ encoding: [0x18,0xbf] +@ CHECK: sasxne r2, r5, r6 @ encoding: [0xa5,0xfa,0x06,0xf2] +@ CHECK: sasx r9, r2, r7 @ encoding: [0xa2,0xfa,0x07,0xf9] +@ CHECK: it ne @ encoding: [0x18,0xbf] +@ CHECK: sasxne r2, r5, r6 @ encoding: [0xa5,0xfa,0x06,0xf2] + + +@------------------------------------------------------------------------------ +@ SBC (immediate) +@------------------------------------------------------------------------------ + sbc r0, r1, #4 + sbcs r0, r1, #0 + sbc r1, r2, #255 + sbc r3, r7, #0x00550055 + sbc r8, r12, #0xaa00aa00 + sbc r9, r7, #0xa5a5a5a5 + sbc r5, r3, #0x87000000 + sbc r4, r2, #0x7f800000 + sbc r4, r2, #0x00000680 + +@ CHECK: sbc r0, r1, #4 @ encoding: [0x61,0xf1,0x04,0x00] +@ CHECK: sbcs r0, r1, #0 @ encoding: [0x71,0xf1,0x00,0x00] +@ CHECK: sbc r1, r2, #255 @ encoding: [0x62,0xf1,0xff,0x01] +@ CHECK: sbc r3, r7, #5570645 @ encoding: [0x67,0xf1,0x55,0x13] +@ CHECK: sbc r8, r12, #2852170240 @ encoding: [0x6c,0xf1,0xaa,0x28] +@ CHECK: sbc r9, r7, #2779096485 @ encoding: [0x67,0xf1,0xa5,0x39] +@ CHECK: sbc r5, r3, #2264924160 @ encoding: [0x63,0xf1,0x07,0x45] +@ CHECK: sbc r4, r2, #2139095040 @ encoding: [0x62,0xf1,0xff,0x44] +@ CHECK: sbc r4, r2, #1664 @ encoding: [0x62,0xf5,0xd0,0x64] + + +@------------------------------------------------------------------------------ +@ SBC (register) +@------------------------------------------------------------------------------ + sbc r4, r5, r6 + sbcs r4, r5, r6 + sbc.w r9, r1, r3 + sbcs.w r9, r1, r3 + sbc r0, r1, r3, ror #4 + sbcs r0, r1, r3, lsl #7 + sbc.w r0, r1, r3, lsr #31 + sbcs.w r0, r1, r3, asr #32 + +@ CHECK: sbc.w r4, r5, r6 @ encoding: [0x65,0xeb,0x06,0x04] +@ CHECK: sbcs.w r4, r5, r6 @ encoding: [0x75,0xeb,0x06,0x04] +@ CHECK: sbc.w r9, r1, r3 @ encoding: [0x61,0xeb,0x03,0x09] +@ CHECK: sbcs.w r9, r1, r3 @ encoding: [0x71,0xeb,0x03,0x09] +@ CHECK: sbc.w r0, r1, r3, ror #4 @ encoding: [0x61,0xeb,0x33,0x10] +@ CHECK: sbcs.w r0, r1, r3, lsl #7 @ encoding: [0x71,0xeb,0xc3,0x10] +@ CHECK: sbc.w r0, r1, r3, lsr #31 @ encoding: [0x61,0xeb,0xd3,0x70] +@ CHECK: sbcs.w r0, r1, r3, asr #32 @ encoding: [0x71,0xeb,0x23,0x00] + + +@------------------------------------------------------------------------------ +@ SBFX +@------------------------------------------------------------------------------ + sbfx r4, r5, #16, #1 + it gt + sbfxgt r4, r5, #16, #16 + +@ CHECK: sbfx r4, r5, #16, #1 @ encoding: [0x45,0xf3,0x00,0x44] +@ CHECK: it gt @ encoding: [0xc8,0xbf] +@ CHECK: sbfxgt r4, r5, #16, #16 @ encoding: [0x45,0xf3,0x0f,0x44] + + +@------------------------------------------------------------------------------ +@ SEL +@------------------------------------------------------------------------------ + sel r5, r9, r2 + it le + selle r5, r9, r2 + +@ CHECK: sel r5, r9, r2 @ encoding: [0xa9,0xfa,0x82,0xf5] +@ CHECK: it le @ encoding: [0xd8,0xbf] +@ CHECK: selle r5, r9, r2 @ encoding: [0xa9,0xfa,0x82,0xf5] + + +@------------------------------------------------------------------------------ +@ SEV +@------------------------------------------------------------------------------ + sev.w + it eq + seveq.w + +@ CHECK: sev.w @ encoding: [0xaf,0xf3,0x04,0x80] +@ CHECK: it eq @ encoding: [0x08,0xbf] +@ CHECK: seveq.w @ encoding: [0xaf,0xf3,0x04,0x80] + + +@------------------------------------------------------------------------------ +@ SADD16/SADD8 +@------------------------------------------------------------------------------ + sadd16 r1, r2, r3 + sadd8 r1, r2, r3 + ite gt + sadd16gt r1, r2, r3 + sadd8le r1, r2, r3 + +@ CHECK: sadd16 r1, r2, r3 @ encoding: [0x92,0xfa,0x03,0xf1] +@ CHECK: sadd8 r1, r2, r3 @ encoding: [0x82,0xfa,0x03,0xf1] +@ CHECK: ite gt @ encoding: [0xcc,0xbf] +@ CHECK: sadd16gt r1, r2, r3 @ encoding: [0x92,0xfa,0x03,0xf1] +@ CHECK: sadd8le r1, r2, r3 @ encoding: [0x82,0xfa,0x03,0xf1] + + +@------------------------------------------------------------------------------ +@ SHASX +@------------------------------------------------------------------------------ + shasx r4, r8, r2 + it gt + shasxgt r4, r8, r2 + shaddsubx r4, r8, r2 + it gt + shaddsubxgt r4, r8, r2 + +@ CHECK: shasx r4, r8, r2 @ encoding: [0xa8,0xfa,0x22,0xf4] +@ CHECK: it gt @ encoding: [0xc8,0xbf] +@ CHECK: shasxgt r4, r8, r2 @ encoding: [0xa8,0xfa,0x22,0xf4] +@ CHECK: shasx r4, r8, r2 @ encoding: [0xa8,0xfa,0x22,0xf4] +@ CHECK: it gt @ encoding: [0xc8,0xbf] +@ CHECK: shasxgt r4, r8, r2 @ encoding: [0xa8,0xfa,0x22,0xf4] + + +@------------------------------------------------------------------------------ +@ SHASX +@------------------------------------------------------------------------------ + shsax r4, r8, r2 + it gt + shsaxgt r4, r8, r2 + shsubaddx r4, r8, r2 + it gt + shsubaddxgt r4, r8, r2 + +@ CHECK: shsax r4, r8, r2 @ encoding: [0xe8,0xfa,0x22,0xf4] +@ CHECK: it gt @ encoding: [0xc8,0xbf] +@ CHECK: shsaxgt r4, r8, r2 @ encoding: [0xe8,0xfa,0x22,0xf4] +@ CHECK: shsax r4, r8, r2 @ encoding: [0xe8,0xfa,0x22,0xf4] +@ CHECK: it gt @ encoding: [0xc8,0xbf] +@ CHECK: shsaxgt r4, r8, r2 @ encoding: [0xe8,0xfa,0x22,0xf4] + + +@------------------------------------------------------------------------------ +@ SHSUB16/SHSUB8 +@------------------------------------------------------------------------------ + shsub16 r4, r8, r2 + shsub8 r4, r8, r2 + itt gt + shsub16gt r4, r8, r2 + shsub8gt r4, r8, r2 + +@ CHECK: shsub16 r4, r8, r2 @ encoding: [0xd8,0xfa,0x22,0xf4] +@ CHECK: shsub8 r4, r8, r2 @ encoding: [0xc8,0xfa,0x22,0xf4] +@ CHECK: itt gt @ encoding: [0xc4,0xbf] +@ CHECK: shsub16gt r4, r8, r2 @ encoding: [0xd8,0xfa,0x22,0xf4] +@ CHECK: shsub8gt r4, r8, r2 @ encoding: [0xc8,0xfa,0x22,0xf4] + + +@------------------------------------------------------------------------------ +@ SMLABB/SMLABT/SMLATB/SMLATT +@------------------------------------------------------------------------------ + smlabb r3, r1, r9, r0 + smlabt r5, r6, r4, r1 + smlatb r4, r2, r3, r2 + smlatt r8, r3, r8, r4 + itete gt + smlabbgt r3, r1, r9, r0 + smlabtle r5, r6, r4, r1 + smlatbgt r4, r2, r3, r2 + smlattle r8, r3, r8, r4 + +@ CHECK: smlabb r3, r1, r9, r0 @ encoding: [0x11,0xfb,0x09,0x03] +@ CHECK: smlabt r5, r6, r4, r1 @ encoding: [0x16,0xfb,0x14,0x15] +@ CHECK: smlatb r4, r2, r3, r2 @ encoding: [0x12,0xfb,0x23,0x24] +@ CHECK: smlatt r8, r3, r8, r4 @ encoding: [0x13,0xfb,0x38,0x48] +@ CHECK: itete gt @ encoding: [0xcb,0xbf] +@ CHECK: smlabbgt r3, r1, r9, r0 @ encoding: [0x11,0xfb,0x09,0x03] +@ CHECK: smlabtle r5, r6, r4, r1 @ encoding: [0x16,0xfb,0x14,0x15] +@ CHECK: smlatbgt r4, r2, r3, r2 @ encoding: [0x12,0xfb,0x23,0x24] +@ CHECK: smlattle r8, r3, r8, r4 @ encoding: [0x13,0xfb,0x38,0x48] + + +@------------------------------------------------------------------------------ +@ SMLAD/SMLADX +@------------------------------------------------------------------------------ + smlad r2, r3, r5, r8 + smladx r2, r3, r5, r8 + itt hi + smladhi r2, r3, r5, r8 + smladxhi r2, r3, r5, r8 + +@ CHECK: smlad r2, r3, r5, r8 @ encoding: [0x23,0xfb,0x05,0x82] +@ CHECK: smladx r2, r3, r5, r8 @ encoding: [0x23,0xfb,0x15,0x82] +@ CHECK: itt hi @ encoding: [0x84,0xbf] +@ CHECK: smladhi r2, r3, r5, r8 @ encoding: [0x23,0xfb,0x05,0x82] +@ CHECK: smladxhi r2, r3, r5, r8 @ encoding: [0x23,0xfb,0x15,0x82] + + +@------------------------------------------------------------------------------ +@ SMLAL +@------------------------------------------------------------------------------ + smlal r2, r3, r5, r8 + it eq + smlaleq r2, r3, r5, r8 + +@ CHECK: smlal r2, r3, r5, r8 @ encoding: [0xc5,0xfb,0x08,0x23] +@ CHECK: it eq @ encoding: [0x08,0xbf] +@ CHECK: smlaleq r2, r3, r5, r8 @ encoding: [0xc5,0xfb,0x08,0x23] + + +@------------------------------------------------------------------------------ +@ SMLALBB/SMLALBT/SMLALTB/SMLALTT +@------------------------------------------------------------------------------ + smlalbb r3, r1, r9, r0 + smlalbt r5, r6, r4, r1 + smlaltb r4, r2, r3, r2 + smlaltt r8, r3, r8, r4 + iteet ge + smlalbbge r3, r1, r9, r0 + smlalbtlt r5, r6, r4, r1 + smlaltblt r4, r2, r3, r2 + smlalttge r8, r3, r8, r4 + +@ CHECK: smlalbb r3, r1, r9, r0 @ encoding: [0xc9,0xfb,0x80,0x31] +@ CHECK: smlalbt r5, r6, r4, r1 @ encoding: [0xc4,0xfb,0x91,0x56] +@ CHECK: smlaltb r4, r2, r3, r2 @ encoding: [0xc3,0xfb,0xa2,0x42] +@ CHECK: smlaltt r8, r3, r8, r4 @ encoding: [0xc8,0xfb,0xb4,0x83] +@ CHECK: iteet ge @ encoding: [0xad,0xbf] +@ CHECK: smlalbbge r3, r1, r9, r0 @ encoding: [0xc9,0xfb,0x80,0x31] +@ CHECK: smlalbtlt r5, r6, r4, r1 @ encoding: [0xc4,0xfb,0x91,0x56] +@ CHECK: smlaltblt r4, r2, r3, r2 @ encoding: [0xc3,0xfb,0xa2,0x42] +@ CHECK: smlalttge r8, r3, r8, r4 @ encoding: [0xc8,0xfb,0xb4,0x83] + + +@------------------------------------------------------------------------------ +@ SMLALD/SMLALDX +@------------------------------------------------------------------------------ + smlald r2, r3, r5, r8 + smlaldx r2, r3, r5, r8 + ite eq + smlaldeq r2, r3, r5, r8 + smlaldxne r2, r3, r5, r8 + +@ CHECK: smlald r2, r3, r5, r8 @ encoding: [0xc5,0xfb,0xc8,0x23] +@ CHECK: smlaldx r2, r3, r5, r8 @ encoding: [0xc5,0xfb,0xd8,0x23] +@ CHECK: ite eq @ encoding: [0x0c,0xbf] +@ CHECK: smlaldeq r2, r3, r5, r8 @ encoding: [0xc5,0xfb,0xc8,0x23] +@ CHECK: smlaldxne r2, r3, r5, r8 @ encoding: [0xc5,0xfb,0xd8,0x23] + + +@------------------------------------------------------------------------------ +@ SMLAWB/SMLAWT +@------------------------------------------------------------------------------ + smlawb r2, r3, r10, r8 + smlawt r8, r3, r5, r9 + ite eq + smlawbeq r2, r7, r5, r8 + smlawtne r1, r3, r0, r8 + +@ CHECK: smlawb r2, r3, r10, r8 @ encoding: [0x33,0xfb,0x0a,0x82] +@ CHECK: smlawt r8, r3, r5, r9 @ encoding: [0x33,0xfb,0x15,0x98] +@ CHECK: ite eq @ encoding: [0x0c,0xbf] +@ CHECK: smlawbeq r2, r7, r5, r8 @ encoding: [0x37,0xfb,0x05,0x82] +@ CHECK: smlawtne r1, r3, r0, r8 @ encoding: [0x33,0xfb,0x10,0x81] + + +@------------------------------------------------------------------------------ +@ SMLSD/SMLSDX +@------------------------------------------------------------------------------ + smlsd r2, r3, r5, r8 + smlsdx r2, r3, r5, r8 + ite le + smlsdle r2, r3, r5, r8 + smlsdxgt r2, r3, r5, r8 + +@ CHECK: smlsd r2, r3, r5, r8 @ encoding: [0x43,0xfb,0x05,0x82] +@ CHECK: smlsdx r2, r3, r5, r8 @ encoding: [0x43,0xfb,0x15,0x82] +@ CHECK: ite le @ encoding: [0xd4,0xbf] +@ CHECK: smlsdle r2, r3, r5, r8 @ encoding: [0x43,0xfb,0x05,0x82] +@ CHECK: smlsdxgt r2, r3, r5, r8 @ encoding: [0x43,0xfb,0x15,0x82] + + +@------------------------------------------------------------------------------ +@ SMLSLD/SMLSLDX +@------------------------------------------------------------------------------ + smlsld r2, r9, r5, r1 + smlsldx r4, r11, r2, r8 + ite ge + smlsldge r8, r2, r5, r6 + smlsldxlt r1, r0, r3, r8 + +@ CHECK: smlsld r2, r9, r5, r1 @ encoding: [0xd5,0xfb,0xc1,0x29] +@ CHECK: smlsldx r4, r11, r2, r8 @ encoding: [0xd2,0xfb,0xd8,0x4b] +@ CHECK: ite ge @ encoding: [0xac,0xbf] +@ CHECK: smlsldge r8, r2, r5, r6 @ encoding: [0xd5,0xfb,0xc6,0x82] +@ CHECK: smlsldxlt r1, r0, r3, r8 @ encoding: [0xd3,0xfb,0xd8,0x10] + + +@------------------------------------------------------------------------------ +@ SMMLA/SMMLAR +@------------------------------------------------------------------------------ + smmla r1, r2, r3, r4 + smmlar r4, r3, r2, r1 + ite lo + smmlalo r1, r2, r3, r4 + smmlarcs r4, r3, r2, r1 + +@ CHECK: smmla r1, r2, r3, r4 @ encoding: [0x52,0xfb,0x03,0x41] +@ CHECK: smmlar r4, r3, r2, r1 @ encoding: [0x53,0xfb,0x12,0x14] +@ CHECK: ite lo @ encoding: [0x34,0xbf] +@ CHECK: smmlalo r1, r2, r3, r4 @ encoding: [0x52,0xfb,0x03,0x41] +@ CHECK: smmlarhs r4, r3, r2, r1 @ encoding: [0x53,0xfb,0x12,0x14] + + +@------------------------------------------------------------------------------ +@ SMMLS/SMMLSR +@------------------------------------------------------------------------------ + smmls r1, r2, r3, r4 + smmlsr r4, r3, r2, r1 + ite lo + smmlslo r1, r2, r3, r4 + smmlsrcs r4, r3, r2, r1 + +@ CHECK: smmls r1, r2, r3, r4 @ encoding: [0x62,0xfb,0x03,0x41] +@ CHECK: smmlsr r4, r3, r2, r1 @ encoding: [0x63,0xfb,0x12,0x14] +@ CHECK: ite lo @ encoding: [0x34,0xbf] +@ CHECK: smmlslo r1, r2, r3, r4 @ encoding: [0x62,0xfb,0x03,0x41] +@ CHECK: smmlsrhs r4, r3, r2, r1 @ encoding: [0x63,0xfb,0x12,0x14] + + +@------------------------------------------------------------------------------ +@ SMMUL/SMMULR +@------------------------------------------------------------------------------ + smmul r2, r3, r4 + smmulr r3, r2, r1 + ite cc + smmulcc r2, r3, r4 + smmulrhs r3, r2, r1 + +@ CHECK: smmul r2, r3, r4 @ encoding: [0x53,0xfb,0x04,0xf2] +@ CHECK: smmulr r3, r2, r1 @ encoding: [0x52,0xfb,0x11,0xf3] +@ CHECK: ite lo @ encoding: [0x34,0xbf] +@ CHECK: smmullo r2, r3, r4 @ encoding: [0x53,0xfb,0x04,0xf2] +@ CHECK: smmulrhs r3, r2, r1 @ encoding: [0x52,0xfb,0x11,0xf3] + + +@------------------------------------------------------------------------------ +@ SMUAD/SMUADX +@------------------------------------------------------------------------------ + smuad r2, r3, r4 + smuadx r3, r2, r1 + ite lt + smuadlt r2, r3, r4 + smuadxge r3, r2, r1 + +@ CHECK: smuad r2, r3, r4 @ encoding: [0x23,0xfb,0x04,0xf2] +@ CHECK: smuadx r3, r2, r1 @ encoding: [0x22,0xfb,0x11,0xf3] +@ CHECK: ite lt @ encoding: [0xb4,0xbf] +@ CHECK: smuadlt r2, r3, r4 @ encoding: [0x23,0xfb,0x04,0xf2] +@ CHECK: smuadxge r3, r2, r1 @ encoding: [0x22,0xfb,0x11,0xf3] + + +@------------------------------------------------------------------------------ +@ SMULBB/SMULBT/SMULTB/SMULTT +@------------------------------------------------------------------------------ + smulbb r3, r9, r0 + smulbt r5, r4, r1 + smultb r4, r2, r2 + smultt r8, r3, r4 + itete ge + smulbbge r1, r9, r0 + smulbtlt r5, r6, r4 + smultbge r2, r3, r2 + smulttlt r8, r3, r4 + +@ CHECK: smulbb r3, r9, r0 @ encoding: [0x19,0xfb,0x00,0xf3] +@ CHECK: smulbt r5, r4, r1 @ encoding: [0x14,0xfb,0x11,0xf5] +@ CHECK: smultb r4, r2, r2 @ encoding: [0x12,0xfb,0x22,0xf4] +@ CHECK: smultt r8, r3, r4 @ encoding: [0x13,0xfb,0x34,0xf8] +@ CHECK: itete ge @ encoding: [0xab,0xbf] +@ CHECK: smulbbge r1, r9, r0 @ encoding: [0x19,0xfb,0x00,0xf1] +@ CHECK: smulbtlt r5, r6, r4 @ encoding: [0x16,0xfb,0x14,0xf5] +@ CHECK: smultbge r2, r3, r2 @ encoding: [0x13,0xfb,0x22,0xf2] +@ CHECK: smulttlt r8, r3, r4 @ encoding: [0x13,0xfb,0x34,0xf8] + + +@------------------------------------------------------------------------------ +@ SMULL +@------------------------------------------------------------------------------ + smull r3, r9, r0, r1 + it eq + smulleq r8, r3, r4, r5 + +@ CHECK: smull r3, r9, r0, r1 @ encoding: [0x80,0xfb,0x01,0x39] +@ CHECK: it eq @ encoding: [0x08,0xbf] +@ CHECK: smulleq r8, r3, r4, r5 @ encoding: [0x84,0xfb,0x05,0x83] + + +@------------------------------------------------------------------------------ +@ SMULWB/SMULWT +@------------------------------------------------------------------------------ + smulwb r3, r9, r0 + smulwt r3, r9, r2 + ite gt + smulwbgt r3, r9, r0 + smulwtle r3, r9, r2 + +@ CHECK: smulwb r3, r9, r0 @ encoding: [0x39,0xfb,0x00,0xf3] +@ CHECK: smulwt r3, r9, r2 @ encoding: [0x39,0xfb,0x12,0xf3] +@ CHECK: ite gt @ encoding: [0xcc,0xbf] +@ CHECK: smulwbgt r3, r9, r0 @ encoding: [0x39,0xfb,0x00,0xf3] +@ CHECK: smulwtle r3, r9, r2 @ encoding: [0x39,0xfb,0x12,0xf3] + + +@------------------------------------------------------------------------------ +@ SMUSD/SMUSDX +@------------------------------------------------------------------------------ + smusd r3, r0, r1 + smusdx r3, r9, r2 + ite eq + smusdeq r8, r3, r2 + smusdxne r7, r4, r3 + +@ CHECK: smusd r3, r0, r1 @ encoding: [0x40,0xfb,0x01,0xf3] +@ CHECK: smusdx r3, r9, r2 @ encoding: [0x49,0xfb,0x12,0xf3] +@ CHECK: ite eq @ encoding: [0x0c,0xbf] +@ CHECK: smusdeq r8, r3, r2 @ encoding: [0x43,0xfb,0x02,0xf8] +@ CHECK: smusdxne r7, r4, r3 @ encoding: [0x44,0xfb,0x13,0xf7] + + +@------------------------------------------------------------------------------ +@ SRS +@------------------------------------------------------------------------------ + srsdb sp, #1 + srsia sp, #0 + + srsdb sp!, #19 + srsia sp!, #2 + + srsea sp, #10 + srsfd sp, #9 + + srsea sp!, #5 + srsfd sp!, #5 + + srs sp, #5 + srs sp!, #5 + +@ CHECK: srsdb sp, #1 @ encoding: [0x0d,0xe8,0x01,0xc0] +@ CHECK: srsia sp, #0 @ encoding: [0x8d,0xe9,0x00,0xc0] +@ CHECK: srsdb sp!, #19 @ encoding: [0x2d,0xe8,0x13,0xc0] +@ CHECK: srsia sp!, #2 @ encoding: [0xad,0xe9,0x02,0xc0] +@ CHECK: srsdb sp, #10 @ encoding: [0x0d,0xe8,0x0a,0xc0] +@ CHECK: srsia sp, #9 @ encoding: [0x8d,0xe9,0x09,0xc0] +@ CHECK: srsdb sp!, #5 @ encoding: [0x2d,0xe8,0x05,0xc0] +@ CHECK: srsia sp!, #5 @ encoding: [0xad,0xe9,0x05,0xc0] +@ CHECK: srsia sp, #5 @ encoding: [0x8d,0xe9,0x05,0xc0] +@ CHECK: srsia sp!, #5 @ encoding: [0xad,0xe9,0x05,0xc0] + + +@------------------------------------------------------------------------------ +@ SSAT +@------------------------------------------------------------------------------ + ssat r8, #1, r10 + ssat r8, #1, r10, lsl #0 + ssat r8, #1, r10, lsl #31 + ssat r8, #1, r10, asr #1 + +@ CHECK: ssat r8, #1, r10 @ encoding: [0x0a,0xf3,0x00,0x08] +@ CHECK: ssat r8, #1, r10 @ encoding: [0x0a,0xf3,0x00,0x08] +@ CHECK: ssat r8, #1, r10, lsl #31 @ encoding: [0x0a,0xf3,0xc0,0x78] +@ CHECK: ssat r8, #1, r10, asr #1 @ encoding: [0x2a,0xf3,0x40,0x08] + + +@------------------------------------------------------------------------------ +@ SSAT16 +@------------------------------------------------------------------------------ + ssat16 r2, #1, r7 + ssat16 r3, #16, r5 + +@ CHECK: ssat16 r2, #1, r7 @ encoding: [0x27,0xf3,0x00,0x02] +@ CHECK: ssat16 r3, #16, r5 @ encoding: [0x25,0xf3,0x0f,0x03] + + +@------------------------------------------------------------------------------ +@ SSAX +@------------------------------------------------------------------------------ + ssubaddx r2, r3, r4 + it lt + ssubaddxlt r2, r3, r4 + ssax r2, r3, r4 + it lt + ssaxlt r2, r3, r4 + +@ CHECK: ssax r2, r3, r4 @ encoding: [0xe3,0xfa,0x04,0xf2] +@ CHECK: it lt @ encoding: [0xb8,0xbf] +@ CHECK: ssaxlt r2, r3, r4 @ encoding: [0xe3,0xfa,0x04,0xf2] +@ CHECK: ssax r2, r3, r4 @ encoding: [0xe3,0xfa,0x04,0xf2] +@ CHECK: it lt @ encoding: [0xb8,0xbf] +@ CHECK: ssaxlt r2, r3, r4 @ encoding: [0xe3,0xfa,0x04,0xf2] + + +@------------------------------------------------------------------------------ +@ SSUB16/SSUB8 +@------------------------------------------------------------------------------ + ssub16 r1, r0, r6 + ssub8 r9, r2, r4 + ite ne + ssub16ne r5, r3, r2 + ssub8eq r5, r1, r2 + +@ CHECK: ssub16 r1, r0, r6 @ encoding: [0xd0,0xfa,0x06,0xf1] +@ CHECK: ssub8 r9, r2, r4 @ encoding: [0xc2,0xfa,0x04,0xf9] +@ CHECK: ite ne @ encoding: [0x14,0xbf] +@ CHECK: ssub16ne r5, r3, r2 @ encoding: [0xd3,0xfa,0x02,0xf5] +@ CHECK: ssub8eq r5, r1, r2 @ encoding: [0xc1,0xfa,0x02,0xf5] + + +@------------------------------------------------------------------------------ +@ STC{L}/STC2{L} +@------------------------------------------------------------------------------ + stc2 p0, c8, [r1, #4] + stc2 p1, c7, [r2] + stc2 p2, c6, [r3, #-224] + stc2 p3, c5, [r4, #-120]! + stc2 p4, c4, [r5], #16 + stc2 p5, c3, [r6], #-72 + stc2l p6, c2, [r7, #4] + stc2l p7, c1, [r8] + stc2l p8, c0, [r9, #-224] + stc2l p9, c1, [r10, #-120]! + stc2l p10, c2, [r11], #16 + stc2l p11, c3, [r12], #-72 + + stc p12, c4, [r0, #4] + stc p13, c5, [r1] + stc p14, c6, [r2, #-224] + stc p15, c7, [r3, #-120]! + stc p5, c8, [r4], #16 + stc p4, c9, [r5], #-72 + stcl p3, c10, [r6, #4] + stcl p2, c11, [r7] + stcl p1, c12, [r8, #-224] + stcl p0, c13, [r9, #-120]! + stcl p6, c14, [r10], #16 + stcl p7, c15, [r11], #-72 + + stc2 p2, c8, [r1], { 25 } + +@ CHECK: stc2 p0, c8, [r1, #4] @ encoding: [0x81,0xfd,0x01,0x80] +@ CHECK: stc2 p1, c7, [r2] @ encoding: [0x82,0xfd,0x00,0x71] +@ CHECK: stc2 p2, c6, [r3, #-224] @ encoding: [0x03,0xfd,0x38,0x62] +@ CHECK: stc2 p3, c5, [r4, #-120]! @ encoding: [0x24,0xfd,0x1e,0x53] +@ CHECK: stc2 p4, c4, [r5], #16 @ encoding: [0xa5,0xfc,0x04,0x44] +@ CHECK: stc2 p5, c3, [r6], #-72 @ encoding: [0x26,0xfc,0x12,0x35] +@ CHECK: stc2l p6, c2, [r7, #4] @ encoding: [0xc7,0xfd,0x01,0x26] +@ CHECK: stc2l p7, c1, [r8] @ encoding: [0xc8,0xfd,0x00,0x17] +@ CHECK: stc2l p8, c0, [r9, #-224] @ encoding: [0x49,0xfd,0x38,0x08] +@ CHECK: stc2l p9, c1, [r10, #-120]! @ encoding: [0x6a,0xfd,0x1e,0x19] +@ CHECK: stc2l p10, c2, [r11], #16 @ encoding: [0xeb,0xfc,0x04,0x2a] +@ CHECK: stc2l p11, c3, [r12], #-72 @ encoding: [0x6c,0xfc,0x12,0x3b] + +@ CHECK: stc p12, c4, [r0, #4] @ encoding: [0x80,0xed,0x01,0x4c] +@ CHECK: stc p13, c5, [r1] @ encoding: [0x81,0xed,0x00,0x5d] +@ CHECK: stc p14, c6, [r2, #-224] @ encoding: [0x02,0xed,0x38,0x6e] +@ CHECK: stc p15, c7, [r3, #-120]! @ encoding: [0x23,0xed,0x1e,0x7f] +@ CHECK: stc p5, c8, [r4], #16 @ encoding: [0xa4,0xec,0x04,0x85] +@ CHECK: stc p4, c9, [r5], #-72 @ encoding: [0x25,0xec,0x12,0x94] +@ CHECK: stcl p3, c10, [r6, #4] @ encoding: [0xc6,0xed,0x01,0xa3] +@ CHECK: stcl p2, c11, [r7] @ encoding: [0xc7,0xed,0x00,0xb2] +@ CHECK: stcl p1, c12, [r8, #-224] @ encoding: [0x48,0xed,0x38,0xc1] +@ CHECK: stcl p0, c13, [r9, #-120]! @ encoding: [0x69,0xed,0x1e,0xd0] +@ CHECK: stcl p6, c14, [r10], #16 @ encoding: [0xea,0xec,0x04,0xe6] +@ CHECK: stcl p7, c15, [r11], #-72 @ encoding: [0x6b,0xec,0x12,0xf7] + +@ CHECK: stc2 p2, c8, [r1], {25} @ encoding: [0x81,0xfc,0x19,0x82] + + +@------------------------------------------------------------------------------ +@ STMIA +@------------------------------------------------------------------------------ + stmia.w r4, {r4, r5, r8, r9} + stmia.w r4, {r5, r6} + stmia.w r5!, {r3, r8} + stm.w r4, {r4, r5, r8, r9} + stm.w r4, {r5, r6} + stm.w r5!, {r3, r8} + stm.w r5!, {r1, r2} + stm.w r2, {r1, r2} + + stmia r4, {r4, r5, r8, r9} + stmia r4, {r5, r6} + stmia r5!, {r3, r8} + stm r4, {r4, r5, r8, r9} + stm r4, {r5, r6} + stm r5!, {r3, r8} + stmea r5!, {r3, r8} + +@ CHECK: stm.w r4, {r4, r5, r8, r9} @ encoding: [0x84,0xe8,0x30,0x03] +@ CHECK: stm.w r4, {r5, r6} @ encoding: [0x84,0xe8,0x60,0x00] +@ CHECK: stm.w r5!, {r3, r8} @ encoding: [0xa5,0xe8,0x08,0x01] +@ CHECK: stm.w r4, {r4, r5, r8, r9} @ encoding: [0x84,0xe8,0x30,0x03] +@ CHECK: stm.w r4, {r5, r6} @ encoding: [0x84,0xe8,0x60,0x00] +@ CHECK: stm.w r5!, {r3, r8} @ encoding: [0xa5,0xe8,0x08,0x01] +@ CHECK: stm.w r5!, {r1, r2} @ encoding: [0xa5,0xe8,0x06,0x00] +@ CHECK: stm.w r2, {r1, r2} @ encoding: [0x82,0xe8,0x06,0x00] + +@ CHECK: stm.w r4, {r4, r5, r8, r9} @ encoding: [0x84,0xe8,0x30,0x03] +@ CHECK: stm.w r4, {r5, r6} @ encoding: [0x84,0xe8,0x60,0x00] +@ CHECK: stm.w r5!, {r3, r8} @ encoding: [0xa5,0xe8,0x08,0x01] +@ CHECK: stm.w r4, {r4, r5, r8, r9} @ encoding: [0x84,0xe8,0x30,0x03] +@ CHECK: stm.w r4, {r5, r6} @ encoding: [0x84,0xe8,0x60,0x00] +@ CHECK: stm.w r5!, {r3, r8} @ encoding: [0xa5,0xe8,0x08,0x01] +@ CHECK: stm.w r5!, {r3, r8} @ encoding: [0xa5,0xe8,0x08,0x01] + + +@------------------------------------------------------------------------------ +@ STMDB +@------------------------------------------------------------------------------ + stmdb r4, {r4, r5, r8, r9} + stmdb r4, {r5, r6} + stmdb r5!, {r3, r8} + stmea r5!, {r3, r8} + +@ CHECK: stmdb r4, {r4, r5, r8, r9} @ encoding: [0x04,0xe9,0x30,0x03] +@ CHECK: stmdb r4, {r5, r6} @ encoding: [0x04,0xe9,0x60,0x00] +@ CHECK: stmdb r5!, {r3, r8} @ encoding: [0x25,0xe9,0x08,0x01] +@ CHECK: stm.w r5!, {r3, r8} @ encoding: [0xa5,0xe8,0x08,0x01] + + +@------------------------------------------------------------------------------ +@ STR(immediate) +@------------------------------------------------------------------------------ + str r5, [r5, #-4] + str r5, [r6, #32] + str r5, [r6, #33] + str r5, [r6, #257] + str.w pc, [r7, #257] + str r2, [r4, #255]! + str r8, [sp, #4]! + str lr, [sp, #-4]! + str r2, [r4], #255 + str r8, [sp], #4 + str lr, [sp], #-4 + +@ CHECK: str r5, [r5, #-4] @ encoding: [0x45,0xf8,0x04,0x5c] +@ CHECK: str r5, [r6, #32] @ encoding: [0x35,0x62] +@ CHECK: str.w r5, [r6, #33] @ encoding: [0xc6,0xf8,0x21,0x50] +@ CHECK: str.w r5, [r6, #257] @ encoding: [0xc6,0xf8,0x01,0x51] +@ CHECK: str.w pc, [r7, #257] @ encoding: [0xc7,0xf8,0x01,0xf1] +@ CHECK: str r2, [r4, #255]! @ encoding: [0x44,0xf8,0xff,0x2f] +@ CHECK: str r8, [sp, #4]! @ encoding: [0x4d,0xf8,0x04,0x8f] +@ CHECK: str lr, [sp, #-4]! @ encoding: [0x4d,0xf8,0x04,0xed] +@ CHECK: str r2, [r4], #255 @ encoding: [0x44,0xf8,0xff,0x2b] +@ CHECK: str r8, [sp], #4 @ encoding: [0x4d,0xf8,0x04,0x8b] +@ CHECK: str lr, [sp], #-4 @ encoding: [0x4d,0xf8,0x04,0xe9] + + +@------------------------------------------------------------------------------ +@ STR(register) +@------------------------------------------------------------------------------ + str r1, [r8, r1] + str.w r4, [r5, r2] + str r6, [r0, r2, lsl #3] + str r8, [r8, r2, lsl #2] + str r7, [sp, r2, lsl #1] + str r7, [sp, r2, lsl #0] + +@ CHECK: str.w r1, [r8, r1] @ encoding: [0x48,0xf8,0x01,0x10] +@ CHECK: str.w r4, [r5, r2] @ encoding: [0x45,0xf8,0x02,0x40] +@ CHECK: str.w r6, [r0, r2, lsl #3] @ encoding: [0x40,0xf8,0x32,0x60] +@ CHECK: str.w r8, [r8, r2, lsl #2] @ encoding: [0x48,0xf8,0x22,0x80] +@ CHECK: str.w r7, [sp, r2, lsl #1] @ encoding: [0x4d,0xf8,0x12,0x70] +@ CHECK: str.w r7, [sp, r2] @ encoding: [0x4d,0xf8,0x02,0x70] + + +@------------------------------------------------------------------------------ +@ STRB(immediate) +@------------------------------------------------------------------------------ + strb r5, [r5, #-4] + strb r5, [r6, #32] + strb r5, [r6, #33] + strb r5, [r6, #257] + strb.w lr, [r7, #257] + strb r5, [r8, #255]! + strb r2, [r5, #4]! + strb r1, [r4, #-4]! + strb lr, [r3], #255 + strb r9, [r2], #4 + strb r3, [sp], #-4 + strb r4, [r8, #-0]! + +@ CHECK: strb r5, [r5, #-4] @ encoding: [0x05,0xf8,0x04,0x5c] +@ CHECK: strb.w r5, [r6, #32] @ encoding: [0x86,0xf8,0x20,0x50] +@ CHECK: strb.w r5, [r6, #33] @ encoding: [0x86,0xf8,0x21,0x50] +@ CHECK: strb.w r5, [r6, #257] @ encoding: [0x86,0xf8,0x01,0x51] +@ CHECK: strb.w lr, [r7, #257] @ encoding: [0x87,0xf8,0x01,0xe1] +@ CHECK: strb r5, [r8, #255]! @ encoding: [0x08,0xf8,0xff,0x5f] +@ CHECK: strb r2, [r5, #4]! @ encoding: [0x05,0xf8,0x04,0x2f] +@ CHECK: strb r1, [r4, #-4]! @ encoding: [0x04,0xf8,0x04,0x1d] +@ CHECK: strb lr, [r3], #255 @ encoding: [0x03,0xf8,0xff,0xeb] +@ CHECK: strb r9, [r2], #4 @ encoding: [0x02,0xf8,0x04,0x9b] +@ CHECK: strb r3, [sp], #-4 @ encoding: [0x0d,0xf8,0x04,0x39] +@ CHECK: strb r4, [r8, #-0]! @ encoding: [0x08,0xf8,0x00,0x4d] + + +@------------------------------------------------------------------------------ +@ STRB(register) +@------------------------------------------------------------------------------ + strb r1, [r8, r1] + strb.w r4, [r5, r2] + strb r6, [r0, r2, lsl #3] + strb r8, [r8, r2, lsl #2] + strb r7, [sp, r2, lsl #1] + strb r7, [sp, r2, lsl #0] + +@ CHECK: strb.w r1, [r8, r1] @ encoding: [0x08,0xf8,0x01,0x10] +@ CHECK: strb.w r4, [r5, r2] @ encoding: [0x05,0xf8,0x02,0x40] +@ CHECK: strb.w r6, [r0, r2, lsl #3] @ encoding: [0x00,0xf8,0x32,0x60] +@ CHECK: strb.w r8, [r8, r2, lsl #2] @ encoding: [0x08,0xf8,0x22,0x80] +@ CHECK: strb.w r7, [sp, r2, lsl #1] @ encoding: [0x0d,0xf8,0x12,0x70] +@ CHECK: strb.w r7, [sp, r2] @ encoding: [0x0d,0xf8,0x02,0x70] + + +@------------------------------------------------------------------------------ +@ STRBT +@------------------------------------------------------------------------------ + strbt r1, [r2] + strbt r1, [r8, #0] + strbt r1, [r8, #3] + strbt r1, [r8, #255] + +@ CHECK: strbt r1, [r2] @ encoding: [0x02,0xf8,0x00,0x1e] +@ CHECK: strbt r1, [r8] @ encoding: [0x08,0xf8,0x00,0x1e] +@ CHECK: strbt r1, [r8, #3] @ encoding: [0x08,0xf8,0x03,0x1e] +@ CHECK: strbt r1, [r8, #255] @ encoding: [0x08,0xf8,0xff,0x1e] + + +@------------------------------------------------------------------------------ +@ STRD +@------------------------------------------------------------------------------ + strd r3, r5, [r6, #24] + strd r3, r5, [r6, #24]! + strd r3, r5, [r6], #4 + strd r3, r5, [r6], #-8 + strd r3, r5, [r6] + strd r8, r1, [r3, #0] + +@ CHECK: strd r3, r5, [r6, #24] @ encoding: [0xc6,0xe9,0x06,0x35] +@ CHECK: strd r3, r5, [r6, #24]! @ encoding: [0xe6,0xe9,0x06,0x35] +@ CHECK: strd r3, r5, [r6], #4 @ encoding: [0xe6,0xe8,0x01,0x35] +@ CHECK: strd r3, r5, [r6], #-8 @ encoding: [0x66,0xe8,0x02,0x35] +@ CHECK: strd r3, r5, [r6] @ encoding: [0xc6,0xe9,0x00,0x35] +@ CHECK: strd r8, r1, [r3] @ encoding: [0xc3,0xe9,0x00,0x81] + + +@------------------------------------------------------------------------------ +@ STREX/STREXB/STREXH/STREXD +@------------------------------------------------------------------------------ + strex r1, r8, [r4] + strex r8, r2, [r4, #0] + strex r2, r12, [sp, #128] + strexb r5, r1, [r7] + strexh r9, r7, [r12] + strexd r9, r3, r6, [r4] + +@ CHECK: strex r1, r8, [r4] @ encoding: [0x44,0xe8,0x00,0x81] +@ CHECK: strex r8, r2, [r4] @ encoding: [0x44,0xe8,0x00,0x28] +@ CHECK: strex r2, r12, [sp, #128] @ encoding: [0x4d,0xe8,0x20,0xc2] +@ CHECK: strexb r5, r1, [r7] @ encoding: [0xc7,0xe8,0x45,0x1f] +@ CHECK: strexh r9, r7, [r12] @ encoding: [0xcc,0xe8,0x59,0x7f] +@ CHECK: strexd r9, r3, r6, [r4] @ encoding: [0xc4,0xe8,0x79,0x36] + + +@------------------------------------------------------------------------------ +@ STRH(immediate) +@------------------------------------------------------------------------------ + strh r5, [r5, #-4] + strh r5, [r6, #32] + strh r5, [r6, #33] + strh r5, [r6, #257] + strh.w lr, [r7, #257] + strh r5, [r8, #255]! + strh r2, [r5, #4]! + strh r1, [r4, #-4]! + strh lr, [r3], #255 + strh r9, [r2], #4 + strh r3, [sp], #-4 + +@ CHECK: strh r5, [r5, #-4] @ encoding: [0x25,0xf8,0x04,0x5c] +@ CHECK: strh r5, [r6, #32] @ encoding: [0x35,0x84] +@ CHECK: strh.w r5, [r6, #33] @ encoding: [0xa6,0xf8,0x21,0x50] +@ CHECK: strh.w r5, [r6, #257] @ encoding: [0xa6,0xf8,0x01,0x51] +@ CHECK: strh.w lr, [r7, #257] @ encoding: [0xa7,0xf8,0x01,0xe1] +@ CHECK: strh r5, [r8, #255]! @ encoding: [0x28,0xf8,0xff,0x5f] +@ CHECK: strh r2, [r5, #4]! @ encoding: [0x25,0xf8,0x04,0x2f] +@ CHECK: strh r1, [r4, #-4]! @ encoding: [0x24,0xf8,0x04,0x1d] +@ CHECK: strh lr, [r3], #255 @ encoding: [0x23,0xf8,0xff,0xeb] +@ CHECK: strh r9, [r2], #4 @ encoding: [0x22,0xf8,0x04,0x9b] +@ CHECK: strh r3, [sp], #-4 @ encoding: [0x2d,0xf8,0x04,0x39] + + +@------------------------------------------------------------------------------ +@ STRH(register) +@------------------------------------------------------------------------------ + strh r1, [r8, r1] + strh.w r4, [r5, r2] + strh r6, [r0, r2, lsl #3] + strh r8, [r8, r2, lsl #2] + strh r7, [sp, r2, lsl #1] + strh r7, [sp, r2, lsl #0] + +@ CHECK: strh.w r1, [r8, r1] @ encoding: [0x28,0xf8,0x01,0x10] +@ CHECK: strh.w r4, [r5, r2] @ encoding: [0x25,0xf8,0x02,0x40] +@ CHECK: strh.w r6, [r0, r2, lsl #3] @ encoding: [0x20,0xf8,0x32,0x60] +@ CHECK: strh.w r8, [r8, r2, lsl #2] @ encoding: [0x28,0xf8,0x22,0x80] +@ CHECK: strh.w r7, [sp, r2, lsl #1] @ encoding: [0x2d,0xf8,0x12,0x70] +@ CHECK: strh.w r7, [sp, r2] @ encoding: [0x2d,0xf8,0x02,0x70] + + +@------------------------------------------------------------------------------ +@ STRHT +@------------------------------------------------------------------------------ + strht r1, [r2] + strht r1, [r8, #0] + strht r1, [r8, #3] + strht r1, [r8, #255] + +@ CHECK: strht r1, [r2] @ encoding: [0x22,0xf8,0x00,0x1e] +@ CHECK: strht r1, [r8] @ encoding: [0x28,0xf8,0x00,0x1e] +@ CHECK: strht r1, [r8, #3] @ encoding: [0x28,0xf8,0x03,0x1e] +@ CHECK: strht r1, [r8, #255] @ encoding: [0x28,0xf8,0xff,0x1e] + + +@------------------------------------------------------------------------------ +@ STRT +@------------------------------------------------------------------------------ + strt r1, [r2] + strt r1, [r8, #0] + strt r1, [r8, #3] + strt r1, [r8, #255] + +@ CHECK: strt r1, [r2] @ encoding: [0x42,0xf8,0x00,0x1e] +@ CHECK: strt r1, [r8] @ encoding: [0x48,0xf8,0x00,0x1e] +@ CHECK: strt r1, [r8, #3] @ encoding: [0x48,0xf8,0x03,0x1e] +@ CHECK: strt r1, [r8, #255] @ encoding: [0x48,0xf8,0xff,0x1e] + + +@------------------------------------------------------------------------------ +@ SUB (immediate) +@------------------------------------------------------------------------------ + itet eq + subeq r1, r2, #4 + subwne r5, r3, #1023 + subeq r4, r5, #293 + sub r2, sp, #1024 + sub r2, r8, #0xff00 + sub r2, r3, #257 + subw r2, r3, #257 + sub r12, r6, #0x100 + subw r12, r6, #0x100 + subs r1, r2, #0x1f0 + +@ CHECK: itet eq @ encoding: [0x0a,0xbf] +@ CHECK: subeq r1, r2, #4 @ encoding: [0x11,0x1f] +@ CHECK: subwne r5, r3, #1023 @ encoding: [0xa3,0xf2,0xff,0x35] +@ CHECK: subweq r4, r5, #293 @ encoding: [0xa5,0xf2,0x25,0x14] +@ CHECK: sub.w r2, sp, #1024 @ encoding: [0xad,0xf5,0x80,0x62] +@ CHECK: sub.w r2, r8, #65280 @ encoding: [0xa8,0xf5,0x7f,0x42] +@ CHECK: subw r2, r3, #257 @ encoding: [0xa3,0xf2,0x01,0x12] +@ CHECK: subw r2, r3, #257 @ encoding: [0xa3,0xf2,0x01,0x12] +@ CHECK: sub.w r12, r6, #256 @ encoding: [0xa6,0xf5,0x80,0x7c] +@ CHECK: subw r12, r6, #256 @ encoding: [0xa6,0xf2,0x00,0x1c] +@ CHECK: subs.w r1, r2, #496 @ encoding: [0xb2,0xf5,0xf8,0x71] + + +@------------------------------------------------------------------------------ +@ SUB (register) +@------------------------------------------------------------------------------ + sub r4, r5, r6 + sub r4, r5, r6, lsl #5 + sub r4, r5, r6, lsr #5 + sub.w r4, r5, r6, lsr #5 + sub r4, r5, r6, asr #5 + sub r4, r5, r6, ror #5 + sub.w r5, r2, r12, rrx + +@ CHECK: sub.w r4, r5, r6 @ encoding: [0xa5,0xeb,0x06,0x04] +@ CHECK: sub.w r4, r5, r6, lsl #5 @ encoding: [0xa5,0xeb,0x46,0x14] +@ CHECK: sub.w r4, r5, r6, lsr #5 @ encoding: [0xa5,0xeb,0x56,0x14] +@ CHECK: sub.w r4, r5, r6, lsr #5 @ encoding: [0xa5,0xeb,0x56,0x14] +@ CHECK: sub.w r4, r5, r6, asr #5 @ encoding: [0xa5,0xeb,0x66,0x14] +@ CHECK: sub.w r4, r5, r6, ror #5 @ encoding: [0xa5,0xeb,0x76,0x14] +@ CHECK: sub.w r5, r2, r12, rrx @ encoding: [0xa2,0xeb,0x3c,0x05] + + +@------------------------------------------------------------------------------ +@ SVC +@------------------------------------------------------------------------------ + svc #0 + ite eq + svceq #255 + swine #33 + +@ CHECK: svc #0 @ encoding: [0x00,0xdf] +@ CHECK: ite eq @ encoding: [0x0c,0xbf] +@ CHECK: svceq #255 @ encoding: [0xff,0xdf] +@ CHECK: svcne #33 @ encoding: [0x21,0xdf] + + +@------------------------------------------------------------------------------ +@ SXTAB +@------------------------------------------------------------------------------ + sxtab r2, r3, r4 + sxtab r4, r5, r6, ror #0 + it lt + sxtablt r6, r2, r9, ror #8 + sxtab r5, r1, r4, ror #16 + sxtab r7, r8, r3, ror #24 + +@ CHECK: sxtab r2, r3, r4 @ encoding: [0x43,0xfa,0x84,0xf2] +@ CHECK: sxtab r4, r5, r6 @ encoding: [0x45,0xfa,0x86,0xf4] +@ CHECK: it lt @ encoding: [0xb8,0xbf] +@ CHECK: sxtablt r6, r2, r9, ror #8 @ encoding: [0x42,0xfa,0x99,0xf6] +@ CHECK: sxtab r5, r1, r4, ror #16 @ encoding: [0x41,0xfa,0xa4,0xf5] +@ CHECK: sxtab r7, r8, r3, ror #24 @ encoding: [0x48,0xfa,0xb3,0xf7] + + +@------------------------------------------------------------------------------ +@ SXTAB16 +@------------------------------------------------------------------------------ + sxtab16 r6, r2, r7, ror #0 + sxtab16 r3, r5, r8, ror #8 + sxtab16 r3, r2, r1, ror #16 + ite ne + sxtab16ne r0, r1, r4 + sxtab16eq r1, r2, r3, ror #24 + +@ CHECK: sxtab16 r6, r2, r7 @ encoding: [0x22,0xfa,0x87,0xf6] +@ CHECK: sxtab16 r3, r5, r8, ror #8 @ encoding: [0x25,0xfa,0x98,0xf3] +@ CHECK: sxtab16 r3, r2, r1, ror #16 @ encoding: [0x22,0xfa,0xa1,0xf3] +@ CHECK: ite ne @ encoding: [0x14,0xbf] +@ CHECK: sxtab16ne r0, r1, r4 @ encoding: [0x21,0xfa,0x84,0xf0] +@ CHECK: sxtab16eq r1, r2, r3, ror #24 @ encoding: [0x22,0xfa,0xb3,0xf1] + + +@------------------------------------------------------------------------------ +@ SXTAH +@------------------------------------------------------------------------------ + sxtah r1, r3, r9 + sxtah r3, r8, r3, ror #8 + sxtah r9, r3, r3, ror #24 + ite hi + sxtahhi r6, r1, r6, ror #0 + sxtahls r2, r2, r4, ror #16 + +@ CHECK: sxtah r1, r3, r9 @ encoding: [0x03,0xfa,0x89,0xf1] +@ CHECK: sxtah r3, r8, r3, ror #8 @ encoding: [0x08,0xfa,0x93,0xf3] +@ CHECK: sxtah r9, r3, r3, ror #24 @ encoding: [0x03,0xfa,0xb3,0xf9] +@ CHECK: ite hi @ encoding: [0x8c,0xbf] +@ CHECK: sxtahhi r6, r1, r6 @ encoding: [0x01,0xfa,0x86,0xf6] +@ CHECK: sxtahls r2, r2, r4, ror #16 @ encoding: [0x02,0xfa,0xa4,0xf2] + + +@------------------------------------------------------------------------------ +@ SXTB +@------------------------------------------------------------------------------ + sxtb r5, r6, ror #0 + sxtb r6, r9, ror #8 + sxtb r8, r3, ror #24 + ite ge + sxtbge r2, r4 + sxtblt r5, r1, ror #16 + sxtb.w r7, r8 + +@ CHECK: sxtb r5, r6 @ encoding: [0x75,0xb2] +@ CHECK: sxtb.w r6, r9, ror #8 @ encoding: [0x4f,0xfa,0x99,0xf6] +@ CHECK: sxtb.w r8, r3, ror #24 @ encoding: [0x4f,0xfa,0xb3,0xf8] +@ CHECK: ite ge @ encoding: [0xac,0xbf] +@ CHECK: sxtbge r2, r4 @ encoding: [0x62,0xb2] +@ CHECK: sxtblt.w r5, r1, ror #16 @ encoding: [0x4f,0xfa,0xa1,0xf5] +@ CHECK: sxtb.w r7, r8 @ encoding: [0x4f,0xfa,0x88,0xf7] + + +@------------------------------------------------------------------------------ +@ SXTB16 +@------------------------------------------------------------------------------ + sxtb16 r1, r4 + sxtb16 r6, r7, ror #0 + sxtb16 r3, r1, ror #16 + ite cs + sxtb16cs r3, r5, ror #8 + sxtb16lo r2, r3, ror #24 + +@ CHECK: sxtb16 r1, r4 @ encoding: [0x2f,0xfa,0x84,0xf1] +@ CHECK: sxtb16 r6, r7 @ encoding: [0x2f,0xfa,0x87,0xf6] +@ CHECK: sxtb16 r3, r1, ror #16 @ encoding: [0x2f,0xfa,0xa1,0xf3] +@ CHECK: ite hs @ encoding: [0x2c,0xbf] +@ CHECK: sxtb16hs r3, r5, ror #8 @ encoding: [0x2f,0xfa,0x95,0xf3] +@ CHECK: sxtb16lo r2, r3, ror #24 @ encoding: [0x2f,0xfa,0xb3,0xf2] + + +@------------------------------------------------------------------------------ +@ SXTH +@------------------------------------------------------------------------------ + sxth r1, r6, ror #0 + sxth r3, r8, ror #8 + sxth r9, r3, ror #24 + itt ne + sxthne r3, r9 + sxthne r2, r2, ror #16 + sxth.w r7, r8 + +@ CHECK: sxth r1, r6 @ encoding: [0x31,0xb2] +@ CHECK: sxth.w r3, r8, ror #8 @ encoding: [0x0f,0xfa,0x98,0xf3] +@ CHECK: sxth.w r9, r3, ror #24 @ encoding: [0x0f,0xfa,0xb3,0xf9] +@ CHECK: itt ne @ encoding: [0x1c,0xbf] +@ CHECK: sxthne.w r3, r9 @ encoding: [0x0f,0xfa,0x89,0xf3] +@ CHECK: sxthne.w r2, r2, ror #16 @ encoding: [0x0f,0xfa,0xa2,0xf2] +@ CHECK: sxth.w r7, r8 @ encoding: [0x0f,0xfa,0x88,0xf7] + + +@------------------------------------------------------------------------------ +@ SXTB +@------------------------------------------------------------------------------ + sxtb r5, r6, ror #0 + sxtb.w r6, r9, ror #8 + sxtb r8, r3, ror #24 + ite ge + sxtbge r2, r4 + sxtblt r5, r1, ror #16 + +@ CHECK: sxtb r5, r6 @ encoding: [0x75,0xb2] +@ CHECK: sxtb.w r6, r9, ror #8 @ encoding: [0x4f,0xfa,0x99,0xf6] +@ CHECK: sxtb.w r8, r3, ror #24 @ encoding: [0x4f,0xfa,0xb3,0xf8] +@ CHECK: ite ge @ encoding: [0xac,0xbf] +@ CHECK: sxtbge r2, r4 @ encoding: [0x62,0xb2] +@ CHECK: sxtblt.w r5, r1, ror #16 @ encoding: [0x4f,0xfa,0xa1,0xf5] + + +@------------------------------------------------------------------------------ +@ SXTB16 +@------------------------------------------------------------------------------ + sxtb16 r1, r4 + sxtb16 r6, r7, ror #0 + sxtb16 r3, r1, ror #16 + ite cs + sxtb16cs r3, r5, ror #8 + sxtb16lo r2, r3, ror #24 + +@ CHECK: sxtb16 r1, r4 @ encoding: [0x2f,0xfa,0x84,0xf1] +@ CHECK: sxtb16 r6, r7 @ encoding: [0x2f,0xfa,0x87,0xf6] +@ CHECK: sxtb16 r3, r1, ror #16 @ encoding: [0x2f,0xfa,0xa1,0xf3] +@ CHECK: ite hs @ encoding: [0x2c,0xbf] +@ CHECK: sxtb16hs r3, r5, ror #8 @ encoding: [0x2f,0xfa,0x95,0xf3] +@ CHECK: sxtb16lo r2, r3, ror #24 @ encoding: [0x2f,0xfa,0xb3,0xf2] + + +@------------------------------------------------------------------------------ +@ SXTH +@------------------------------------------------------------------------------ + sxth r1, r6, ror #0 + sxth.w r3, r8, ror #8 + sxth r9, r3, ror #24 + itt ne + sxthne r3, r9 + sxthne r2, r2, ror #16 + +@ CHECK: sxth r1, r6 @ encoding: [0x31,0xb2] +@ CHECK: sxth.w r3, r8, ror #8 @ encoding: [0x0f,0xfa,0x98,0xf3] +@ CHECK: sxth.w r9, r3, ror #24 @ encoding: [0x0f,0xfa,0xb3,0xf9] +@ CHECK: itt ne @ encoding: [0x1c,0xbf] +@ CHECK: sxthne.w r3, r9 @ encoding: [0x0f,0xfa,0x89,0xf3] +@ CHECK: sxthne.w r2, r2, ror #16 @ encoding: [0x0f,0xfa,0xa2,0xf2] + + +@------------------------------------------------------------------------------ +@ TBB/TBH +@------------------------------------------------------------------------------ + tbb [r3, r8] + tbh [r3, r8, lsl #1] + it eq + tbbeq [r3, r8] + it cs + tbhcs [r3, r8, lsl #1] + +@ CHECK: tbb [r3, r8] @ encoding: [0xd3,0xe8,0x08,0xf0] +@ CHECK: tbh [r3, r8, lsl #1] @ encoding: [0xd3,0xe8,0x18,0xf0] +@ CHECK: it eq @ encoding: [0x08,0xbf] +@ CHECK: tbbeq [r3, r8] @ encoding: [0xd3,0xe8,0x08,0xf0] +@ CHECK: it hs @ encoding: [0x28,0xbf] +@ CHECK: tbhhs [r3, r8, lsl #1] @ encoding: [0xd3,0xe8,0x18,0xf0] + + +@------------------------------------------------------------------------------ +@ TEQ +@------------------------------------------------------------------------------ + teq r5, #0xf000 + teq r4, r5 + teq r4, r5, lsl #5 + teq r4, r5, lsr #5 + teq r4, r5, lsr #5 + teq r4, r5, asr #5 + teq r4, r5, ror #5 + +@ CHECK: teq.w r5, #61440 @ encoding: [0x95,0xf4,0x70,0x4f] +@ CHECK: teq.w r4, r5 @ encoding: [0x94,0xea,0x05,0x0f] +@ CHECK: teq.w r4, r5, lsl #5 @ encoding: [0x94,0xea,0x45,0x1f] +@ CHECK: teq.w r4, r5, lsr #5 @ encoding: [0x94,0xea,0x55,0x1f] +@ CHECK: teq.w r4, r5, lsr #5 @ encoding: [0x94,0xea,0x55,0x1f] +@ CHECK: teq.w r4, r5, asr #5 @ encoding: [0x94,0xea,0x65,0x1f] +@ CHECK: teq.w r4, r5, ror #5 @ encoding: [0x94,0xea,0x75,0x1f] + + +@------------------------------------------------------------------------------ +@ TST +@------------------------------------------------------------------------------ + tst r5, #0xf000 + tst r2, r5 + tst r3, r12, lsl #5 + tst r4, r11, lsr #4 + tst r5, r10, lsr #12 + tst r6, r9, asr #30 + tst r7, r8, ror #2 + +@ CHECK: tst.w r5, #61440 @ encoding: [0x15,0xf4,0x70,0x4f] +@ CHECK: tst r2, r5 @ encoding: [0x2a,0x42] +@ CHECK: tst.w r3, r12, lsl #5 @ encoding: [0x13,0xea,0x4c,0x1f] +@ CHECK: tst.w r4, r11, lsr #4 @ encoding: [0x14,0xea,0x1b,0x1f] +@ CHECK: tst.w r5, r10, lsr #12 @ encoding: [0x15,0xea,0x1a,0x3f] +@ CHECK: tst.w r6, r9, asr #30 @ encoding: [0x16,0xea,0xa9,0x7f] +@ CHECK: tst.w r7, r8, ror #2 @ encoding: [0x17,0xea,0xb8,0x0f] + + +@------------------------------------------------------------------------------ +@ UADD16/UADD8 +@------------------------------------------------------------------------------ + uadd16 r1, r2, r3 + uadd8 r1, r2, r3 + ite gt + uadd16gt r1, r2, r3 + uadd8le r1, r2, r3 + +@ CHECK: uadd16 r1, r2, r3 @ encoding: [0x92,0xfa,0x43,0xf1] +@ CHECK: uadd8 r1, r2, r3 @ encoding: [0x82,0xfa,0x43,0xf1] +@ CHECK: ite gt @ encoding: [0xcc,0xbf] +@ CHECK: uadd16gt r1, r2, r3 @ encoding: [0x92,0xfa,0x43,0xf1] +@ CHECK: uadd8le r1, r2, r3 @ encoding: [0x82,0xfa,0x43,0xf1] + + +@------------------------------------------------------------------------------ +@ UASX +@------------------------------------------------------------------------------ + uasx r9, r12, r0 + it eq + uasxeq r9, r12, r0 + uaddsubx r9, r12, r0 + it eq + uaddsubxeq r9, r12, r0 + +@ CHECK: uasx r9, r12, r0 @ encoding: [0xac,0xfa,0x40,0xf9] +@ CHECK: it eq @ encoding: [0x08,0xbf] +@ CHECK: uasxeq r9, r12, r0 @ encoding: [0xac,0xfa,0x40,0xf9] +@ CHECK: uasx r9, r12, r0 @ encoding: [0xac,0xfa,0x40,0xf9] +@ CHECK: it eq @ encoding: [0x08,0xbf] +@ CHECK: uasxeq r9, r12, r0 @ encoding: [0xac,0xfa,0x40,0xf9] + + +@------------------------------------------------------------------------------ +@ UBFX +@------------------------------------------------------------------------------ + ubfx r4, r5, #16, #1 + it gt + ubfxgt r4, r5, #16, #16 + +@ CHECK: ubfx r4, r5, #16, #1 @ encoding: [0xc5,0xf3,0x00,0x44] +@ CHECK: it gt @ encoding: [0xc8,0xbf] +@ CHECK: ubfxgt r4, r5, #16, #16 @ encoding: [0xc5,0xf3,0x0f,0x44] + + +@------------------------------------------------------------------------------ +@ UHADD16/UHADD8 +@------------------------------------------------------------------------------ + uhadd16 r4, r8, r2 + uhadd8 r4, r8, r2 + itt gt + uhadd16gt r4, r8, r2 + uhadd8gt r4, r8, r2 + +@ CHECK: uhadd16 r4, r8, r2 @ encoding: [0x98,0xfa,0x62,0xf4] +@ CHECK: uhadd8 r4, r8, r2 @ encoding: [0x88,0xfa,0x62,0xf4] +@ CHECK: itt gt @ encoding: [0xc4,0xbf] +@ CHECK: uhadd16gt r4, r8, r2 @ encoding: [0x98,0xfa,0x62,0xf4] +@ CHECK: uhadd8gt r4, r8, r2 @ encoding: [0x88,0xfa,0x62,0xf4] + + +@------------------------------------------------------------------------------ +@ UHASX/UHSAX +@------------------------------------------------------------------------------ + uhasx r4, r1, r5 + uhsax r5, r6, r6 + itt gt + uhasxgt r6, r9, r8 + uhsaxgt r7, r8, r12 + uhaddsubx r4, r1, r5 + uhsubaddx r5, r6, r6 + itt gt + uhaddsubxgt r6, r9, r8 + uhsubaddxgt r7, r8, r12 + +@ CHECK: uhasx r4, r1, r5 @ encoding: [0xa1,0xfa,0x65,0xf4] +@ CHECK: uhsax r5, r6, r6 @ encoding: [0xe6,0xfa,0x66,0xf5] +@ CHECK: itt gt @ encoding: [0xc4,0xbf] +@ CHECK: uhasxgt r6, r9, r8 @ encoding: [0xa9,0xfa,0x68,0xf6] +@ CHECK: uhsaxgt r7, r8, r12 @ encoding: [0xe8,0xfa,0x6c,0xf7] +@ CHECK: uhasx r4, r1, r5 @ encoding: [0xa1,0xfa,0x65,0xf4] +@ CHECK: uhsax r5, r6, r6 @ encoding: [0xe6,0xfa,0x66,0xf5] +@ CHECK: itt gt @ encoding: [0xc4,0xbf] +@ CHECK: uhasxgt r6, r9, r8 @ encoding: [0xa9,0xfa,0x68,0xf6] +@ CHECK: uhsaxgt r7, r8, r12 @ encoding: [0xe8,0xfa,0x6c,0xf7] + + +@------------------------------------------------------------------------------ +@ UHSUB16/UHSUB8 +@------------------------------------------------------------------------------ + uhsub16 r5, r8, r3 + uhsub8 r1, r7, r6 + itt lt + uhsub16lt r4, r9, r12 + uhsub8lt r3, r1, r5 + +@ CHECK: uhsub16 r5, r8, r3 @ encoding: [0xd8,0xfa,0x63,0xf5] +@ CHECK: uhsub8 r1, r7, r6 @ encoding: [0xc7,0xfa,0x66,0xf1] +@ CHECK: itt lt @ encoding: [0xbc,0xbf] +@ CHECK: uhsub16lt r4, r9, r12 @ encoding: [0xd9,0xfa,0x6c,0xf4] +@ CHECK: uhsub8lt r3, r1, r5 @ encoding: [0xc1,0xfa,0x65,0xf3] + + +@------------------------------------------------------------------------------ +@ UMAAL +@------------------------------------------------------------------------------ + umaal r3, r4, r5, r6 + it lt + umaallt r3, r4, r5, r6 + +@ CHECK: umaal r3, r4, r5, r6 @ encoding: [0xe5,0xfb,0x66,0x34] +@ CHECK: it lt @ encoding: [0xb8,0xbf] +@ CHECK: umaallt r3, r4, r5, r6 @ encoding: [0xe5,0xfb,0x66,0x34] + + +@------------------------------------------------------------------------------ +@ UMLAL +@------------------------------------------------------------------------------ + umlal r2, r4, r6, r8 + it gt + umlalgt r6, r1, r2, r6 + +@ CHECK: umlal r2, r4, r6, r8 @ encoding: [0xe6,0xfb,0x08,0x24] +@ CHECK: it gt @ encoding: [0xc8,0xbf] +@ CHECK: umlalgt r6, r1, r2, r6 @ encoding: [0xe2,0xfb,0x06,0x61] + + +@------------------------------------------------------------------------------ +@ UMULL +@------------------------------------------------------------------------------ + umull r2, r4, r6, r8 + it gt + umullgt r6, r1, r2, r6 + +@ CHECK: umull r2, r4, r6, r8 @ encoding: [0xa6,0xfb,0x08,0x24] +@ CHECK: it gt @ encoding: [0xc8,0xbf] +@ CHECK: umullgt r6, r1, r2, r6 @ encoding: [0xa2,0xfb,0x06,0x61] + + +@------------------------------------------------------------------------------ +@ UQADD16/UQADD8 +@------------------------------------------------------------------------------ + uqadd16 r1, r2, r3 + uqadd8 r3, r4, r8 + ite gt + uqadd16gt r4, r7, r9 + uqadd8le r8, r1, r2 + +@ CHECK: uqadd16 r1, r2, r3 @ encoding: [0x92,0xfa,0x53,0xf1] +@ CHECK: uqadd8 r3, r4, r8 @ encoding: [0x84,0xfa,0x58,0xf3] +@ CHECK: ite gt @ encoding: [0xcc,0xbf] +@ CHECK: uqadd16gt r4, r7, r9 @ encoding: [0x97,0xfa,0x59,0xf4] +@ CHECK: uqadd8le r8, r1, r2 @ encoding: [0x81,0xfa,0x52,0xf8] + + +@------------------------------------------------------------------------------ +@ UQASX/UQSAX +@------------------------------------------------------------------------------ + uqasx r1, r2, r3 + uqsax r3, r4, r8 + ite gt + uqasxgt r4, r7, r9 + uqsaxle r8, r1, r2 + + uqaddsubx r1, r2, r3 + uqsubaddx r3, r4, r8 + ite gt + uqaddsubxgt r4, r7, r9 + uqsubaddxle r8, r1, r2 + +@ CHECK: uqasx r1, r2, r3 @ encoding: [0xa2,0xfa,0x53,0xf1] +@ CHECK: uqsax r3, r4, r8 @ encoding: [0xe4,0xfa,0x58,0xf3] +@ CHECK: ite gt @ encoding: [0xcc,0xbf] +@ CHECK: uqasxgt r4, r7, r9 @ encoding: [0xa7,0xfa,0x59,0xf4] +@ CHECK: uqsaxle r8, r1, r2 @ encoding: [0xe1,0xfa,0x52,0xf8] + +@ CHECK: uqasx r1, r2, r3 @ encoding: [0xa2,0xfa,0x53,0xf1] +@ CHECK: uqsax r3, r4, r8 @ encoding: [0xe4,0xfa,0x58,0xf3] +@ CHECK: ite gt @ encoding: [0xcc,0xbf] +@ CHECK: uqasxgt r4, r7, r9 @ encoding: [0xa7,0xfa,0x59,0xf4] +@ CHECK: uqsaxle r8, r1, r2 @ encoding: [0xe1,0xfa,0x52,0xf8] + + +@------------------------------------------------------------------------------ +@ UQSUB16/UQSUB8 +@------------------------------------------------------------------------------ + uqsub8 r8, r2, r9 + uqsub16 r1, r9, r7 + ite gt + uqsub8gt r3, r1, r6 + uqsub16le r4, r6, r4 + +@ CHECK: uqsub8 r8, r2, r9 @ encoding: [0xc2,0xfa,0x59,0xf8] +@ CHECK: uqsub16 r1, r9, r7 @ encoding: [0xd9,0xfa,0x57,0xf1] +@ CHECK: ite gt @ encoding: [0xcc,0xbf] +@ CHECK: uqsub8gt r3, r1, r6 @ encoding: [0xc1,0xfa,0x56,0xf3] +@ CHECK: uqsub16le r4, r6, r4 @ encoding: [0xd6,0xfa,0x54,0xf4] + + +@------------------------------------------------------------------------------ +@ UQSUB16/UQSUB8 +@------------------------------------------------------------------------------ + usad8 r1, r9, r7 + usada8 r8, r2, r9, r12 + ite gt + usada8gt r3, r1, r6, r9 + usad8le r4, r6, r4 + +@ CHECK: usad8 r1, r9, r7 @ encoding: [0x79,0xfb,0x07,0xf1] +@ CHECK: usada8 r8, r2, r9, r12 @ encoding: [0x72,0xfb,0x09,0xc8] +@ CHECK: ite gt @ encoding: [0xcc,0xbf] +@ CHECK: usada8gt r3, r1, r6, r9 @ encoding: [0x71,0xfb,0x06,0x93] +@ CHECK: usad8le r4, r6, r4 @ encoding: [0x76,0xfb,0x04,0xf4] + + +@------------------------------------------------------------------------------ +@ USAT +@------------------------------------------------------------------------------ + usat r8, #1, r10 + usat r8, #4, r10, lsl #0 + usat r8, #5, r10, lsl #31 + usat r8, #16, r10, asr #1 + +@ CHECK: usat r8, #1, r10 @ encoding: [0x8a,0xf3,0x01,0x08] +@ CHECK: usat r8, #4, r10 @ encoding: [0x8a,0xf3,0x04,0x08] +@ CHECK: usat r8, #5, r10, lsl #31 @ encoding: [0x8a,0xf3,0xc5,0x78] +@ CHECK: usat r8, #16, r10, asr #1 @ encoding: [0xaa,0xf3,0x50,0x08] + + +@------------------------------------------------------------------------------ +@ USAT16 +@------------------------------------------------------------------------------ + usat16 r2, #2, r7 + usat16 r3, #15, r5 + +@ CHECK: usat16 r2, #2, r7 @ encoding: [0xa7,0xf3,0x02,0x02] +@ CHECK: usat16 r3, #15, r5 @ encoding: [0xa5,0xf3,0x0f,0x03] + + +@------------------------------------------------------------------------------ +@ USAX +@------------------------------------------------------------------------------ + usax r2, r3, r4 + it ne + usaxne r6, r1, r9 + usubaddx r2, r3, r4 + it ne + usubaddxne r6, r1, r9 + +@ CHECK: usax r2, r3, r4 @ encoding: [0xe3,0xfa,0x44,0xf2] +@ CHECK: it ne @ encoding: [0x18,0xbf] +@ CHECK: usaxne r6, r1, r9 @ encoding: [0xe1,0xfa,0x49,0xf6] +@ CHECK: usax r2, r3, r4 @ encoding: [0xe3,0xfa,0x44,0xf2] +@ CHECK: it ne @ encoding: [0x18,0xbf] +@ CHECK: usaxne r6, r1, r9 @ encoding: [0xe1,0xfa,0x49,0xf6] + + +@------------------------------------------------------------------------------ +@ USUB16/USUB8 +@------------------------------------------------------------------------------ + usub16 r4, r2, r7 + usub8 r1, r8, r5 + ite hi + usub16hi r1, r1, r3 + usub8ls r9, r2, r3 + +@ CHECK: usub16 r4, r2, r7 @ encoding: [0xd2,0xfa,0x47,0xf4] +@ CHECK: usub8 r1, r8, r5 @ encoding: [0xc8,0xfa,0x45,0xf1] +@ CHECK: ite hi @ encoding: [0x8c,0xbf] +@ CHECK: usub16hi r1, r1, r3 @ encoding: [0xd1,0xfa,0x43,0xf1] +@ CHECK: usub8ls r9, r2, r3 @ encoding: [0xc2,0xfa,0x43,0xf9] + + +@------------------------------------------------------------------------------ +@ UXTAB +@------------------------------------------------------------------------------ + uxtab r2, r3, r4 + uxtab r4, r5, r6, ror #0 + it lt + uxtablt r6, r2, r9, ror #8 + uxtab r5, r1, r4, ror #16 + uxtab r7, r8, r3, ror #24 + +@ CHECK: uxtab r2, r3, r4 @ encoding: [0x53,0xfa,0x84,0xf2] +@ CHECK: uxtab r4, r5, r6 @ encoding: [0x55,0xfa,0x86,0xf4] +@ CHECK: it lt @ encoding: [0xb8,0xbf] +@ CHECK: uxtablt r6, r2, r9, ror #8 @ encoding: [0x52,0xfa,0x99,0xf6] +@ CHECK: uxtab r5, r1, r4, ror #16 @ encoding: [0x51,0xfa,0xa4,0xf5] +@ CHECK: uxtab r7, r8, r3, ror #24 @ encoding: [0x58,0xfa,0xb3,0xf7] + + +@------------------------------------------------------------------------------ +@ UXTAB16 +@------------------------------------------------------------------------------ + it ge + uxtab16ge r0, r1, r4 + uxtab16 r6, r2, r7, ror #0 + uxtab16 r3, r5, r8, ror #8 + uxtab16 r3, r2, r1, ror #16 + it eq + uxtab16eq r1, r2, r3, ror #24 + +@ CHECK: it ge @ encoding: [0xa8,0xbf] +@ CHECK: uxtab16ge r0, r1, r4 @ encoding: [0x31,0xfa,0x84,0xf0] +@ CHECK: uxtab16 r6, r2, r7 @ encoding: [0x32,0xfa,0x87,0xf6] +@ CHECK: uxtab16 r3, r5, r8, ror #8 @ encoding: [0x35,0xfa,0x98,0xf3] +@ CHECK: uxtab16 r3, r2, r1, ror #16 @ encoding: [0x32,0xfa,0xa1,0xf3] +@ CHECK: it eq @ encoding: [0x08,0xbf] +@ CHECK: uxtab16eq r1, r2, r3, ror #24 @ encoding: [0x32,0xfa,0xb3,0xf1] + + +@------------------------------------------------------------------------------ +@ UXTAH +@------------------------------------------------------------------------------ + uxtah r1, r3, r9 + it hi + uxtahhi r6, r1, r6, ror #0 + uxtah r3, r8, r3, ror #8 + it lo + uxtahlo r2, r2, r4, ror #16 + uxtah r9, r3, r3, ror #24 + +@ CHECK: uxtah r1, r3, r9 @ encoding: [0x13,0xfa,0x89,0xf1] +@ CHECK: it hi @ encoding: [0x88,0xbf] +@ CHECK: uxtahhi r6, r1, r6 @ encoding: [0x11,0xfa,0x86,0xf6] +@ CHECK: uxtah r3, r8, r3, ror #8 @ encoding: [0x18,0xfa,0x93,0xf3] +@ CHECK: it lo @ encoding: [0x38,0xbf] +@ CHECK: uxtahlo r2, r2, r4, ror #16 @ encoding: [0x12,0xfa,0xa4,0xf2] +@ CHECK: uxtah r9, r3, r3, ror #24 @ encoding: [0x13,0xfa,0xb3,0xf9] + + +@------------------------------------------------------------------------------ +@ UXTB +@------------------------------------------------------------------------------ + it ge + uxtbge r2, r4 + uxtb r5, r6, ror #0 + uxtb r6, r9, ror #8 + it cc + uxtbcc r5, r1, ror #16 + uxtb r8, r3, ror #24 + uxtb.w r7, r8 + +@ CHECK: it ge @ encoding: [0xa8,0xbf] +@ CHECK: uxtbge r2, r4 @ encoding: [0xe2,0xb2] +@ CHECK: uxtb r5, r6 @ encoding: [0xf5,0xb2] +@ CHECK: uxtb.w r6, r9, ror #8 @ encoding: [0x5f,0xfa,0x99,0xf6] +@ CHECK: it lo @ encoding: [0x38,0xbf] +@ CHECK: uxtblo.w r5, r1, ror #16 @ encoding: [0x5f,0xfa,0xa1,0xf5] +@ CHECK: uxtb.w r8, r3, ror #24 @ encoding: [0x5f,0xfa,0xb3,0xf8] +@ CHECK: uxtb.w r7, r8 @ encoding: [0x5f,0xfa,0x88,0xf7] + + +@------------------------------------------------------------------------------ +@ UXTB16 +@------------------------------------------------------------------------------ + uxtb16 r1, r4 + uxtb16 r6, r7, ror #0 + it cs + uxtb16cs r3, r5, ror #8 + uxtb16 r3, r1, ror #16 + it ge + uxtb16ge r2, r3, ror #24 + +@ CHECK: uxtb16 r1, r4 @ encoding: [0x3f,0xfa,0x84,0xf1] +@ CHECK: uxtb16 r6, r7 @ encoding: [0x3f,0xfa,0x87,0xf6] +@ CHECK: it hs @ encoding: [0x28,0xbf] +@ CHECK: uxtb16hs r3, r5, ror #8 @ encoding: [0x3f,0xfa,0x95,0xf3] +@ CHECK: uxtb16 r3, r1, ror #16 @ encoding: [0x3f,0xfa,0xa1,0xf3] +@ CHECK: it ge @ encoding: [0xa8,0xbf] +@ CHECK: uxtb16ge r2, r3, ror #24 @ encoding: [0x3f,0xfa,0xb3,0xf2] + + +@------------------------------------------------------------------------------ +@ UXTH +@------------------------------------------------------------------------------ + it ne + uxthne r3, r9 + uxth r1, r6, ror #0 + uxth r3, r8, ror #8 + it le + uxthle r2, r2, ror #16 + uxth r9, r3, ror #24 + uxth.w r7, r8 + +@ CHECK: it ne @ encoding: [0x18,0xbf] +@ CHECK: uxthne.w r3, r9 @ encoding: [0x1f,0xfa,0x89,0xf3] +@ CHECK: uxth r1, r6 @ encoding: [0xb1,0xb2] +@ CHECK: uxth.w r3, r8, ror #8 @ encoding: [0x1f,0xfa,0x98,0xf3] +@ CHECK: it le @ encoding: [0xd8,0xbf] +@ CHECK: uxthle.w r2, r2, ror #16 @ encoding: [0x1f,0xfa,0xa2,0xf2] +@ CHECK: uxth.w r9, r3, ror #24 @ encoding: [0x1f,0xfa,0xb3,0xf9] +@ CHECK: uxth.w r7, r8 @ encoding: [0x1f,0xfa,0x88,0xf7] + +@------------------------------------------------------------------------------ +@ WFE/WFI/YIELD +@------------------------------------------------------------------------------ + wfe + wfi + yield + itet lt + wfelt + wfige + yieldlt + +@ CHECK: wfe @ encoding: [0x20,0xbf] +@ CHECK: wfi @ encoding: [0x30,0xbf] +@ CHECK: yield @ encoding: [0x10,0xbf] +@ CHECK: itet lt @ encoding: [0xb6,0xbf] +@ CHECK: wfelt @ encoding: [0x20,0xbf] +@ CHECK: wfige @ encoding: [0x30,0xbf] +@ CHECK: yieldlt @ encoding: [0x10,0xbf] diff --git a/test/MC/ARM/diagnostics.s b/test/MC/ARM/diagnostics.s index 4537a0f..f722dd7 100644 --- a/test/MC/ARM/diagnostics.s +++ b/test/MC/ARM/diagnostics.s @@ -88,3 +88,230 @@ @ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-ERRORS: error: invalid operand for instruction + + + @ Out of range immediate for MOV + movw r9, 0x10000 +@ CHECK-ERRORS: error: invalid operand for instruction + + @ Invalid 's' bit usage for MOVW + movs r6, #0xffff + movwseq r9, #0xffff +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: instruction 'movw' can not set flags, but 's' suffix specified + + @ Out of range immediate for MOVT + movt r9, 0x10000 +@ CHECK-ERRORS: error: invalid operand for instruction + + @ Out of range immediates for MRC/MRC2/MRRC/MRRC2 + mrc p14, #8, r1, c1, c2, #4 + mrc p14, #1, r1, c1, c2, #8 + mrc2 p14, #8, r1, c1, c2, #4 + mrc2 p14, #0, r1, c1, c2, #9 + mrrc p7, #16, r5, r4, c1 + mrrc2 p7, #17, r5, r4, c1 +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction + + @ Shifter operand validation for PKH instructions. + pkhbt r2, r2, r3, lsl #-1 + pkhbt r2, r2, r3, lsl #32 + pkhtb r2, r2, r3, asr #0 + pkhtb r2, r2, r3, asr #33 + pkhbt r2, r2, r3, asr #3 + pkhtb r2, r2, r3, lsl #3 + +@ CHECK-ERRORS: error: immediate value out of range +@ CHECK-ERRORS: pkhbt r2, r2, r3, lsl #-1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: immediate value out of range +@ CHECK-ERRORS: pkhbt r2, r2, r3, lsl #32 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: immediate value out of range +@ CHECK-ERRORS: pkhtb r2, r2, r3, asr #0 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: immediate value out of range +@ CHECK-ERRORS: pkhtb r2, r2, r3, asr #33 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: lsl operand expected. +@ CHECK-ERRORS: pkhbt r2, r2, r3, asr #3 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: asr operand expected. +@ CHECK-ERRORS: pkhtb r2, r2, r3, lsl #3 +@ CHECK-ERRORS: ^ + + + @ bad values for SETEND + setendne be + setend me + setend 1 + +@ CHECK-ERRORS: error: instruction 'setend' is not predicable, but condition code specified +@ CHECK-ERRORS: setendne be +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: 'be' or 'le' operand expected +@ CHECK-ERRORS: setend me +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: 'be' or 'le' operand expected +@ CHECK-ERRORS: setend 1 +@ CHECK-ERRORS: ^ + + + @ Out of range immediates and bad shift types for SSAT + ssat r8, #0, r10, lsl #8 + ssat r8, #33, r10, lsl #8 + ssat r8, #1, r10, lsl #-1 + ssat r8, #1, r10, lsl #32 + ssat r8, #1, r10, asr #0 + ssat r8, #1, r10, asr #33 + ssat r8, #1, r10, lsr #5 + ssat r8, #1, r10, lsl fred + ssat r8, #1, r10, lsl #fred + +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: ssat r8, #0, r10, lsl #8 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: ssat r8, #33, r10, lsl #8 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: 'lsr' shift amount must be in range [0,31] +@ CHECK-ERRORS: ssat r8, #1, r10, lsl #-1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: 'lsr' shift amount must be in range [0,31] +@ CHECK-ERRORS: ssat r8, #1, r10, lsl #32 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: 'asr' shift amount must be in range [1,32] +@ CHECK-ERRORS: ssat r8, #1, r10, asr #0 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: 'asr' shift amount must be in range [1,32] +@ CHECK-ERRORS: ssat r8, #1, r10, asr #33 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: shift operator 'asr' or 'lsl' expected +@ CHECK-ERRORS: ssat r8, #1, r10, lsr #5 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: '#' expected +@ CHECK-ERRORS: ssat r8, #1, r10, lsl fred +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: shift amount must be an immediate +@ CHECK-ERRORS: ssat r8, #1, r10, lsl #fred +@ CHECK-ERRORS: ^ + + @ Out of range immediates for SSAT16 + ssat16 r2, #0, r7 + ssat16 r3, #17, r5 + +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: ssat16 r2, #0, r7 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: ssat16 r3, #17, r5 +@ CHECK-ERRORS: ^ + + + @ Out of order STM registers + stmda sp!, {r5, r2} + +@ CHECK-ERRORS: error: register list not in ascending order +@ CHECK-ERRORS: stmda sp!, {r5, r2} +@ CHECK-ERRORS: ^ + + + @ Out of range immediate on SVC + svc #0x1000000 +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: svc #0x1000000 +@ CHECK-ERRORS: ^ + + + @ Out of order Rt/Rt2 operands for ldrexd/strexd + ldrexd r4, r3, [r8] + strexd r6, r5, r3, [r8] + +@ CHECK-ERRORS: error: destination operands must be sequential +@ CHECK-ERRORS: ldrexd r4, r3, [r8] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: source operands must be sequential +@ CHECK-ERRORS: strexd r6, r5, r3, [r8] +@ CHECK-ERRORS: ^ + + @ Illegal rotate operators for extend instructions + sxtb r8, r3, #8 + sxtb r8, r3, ror 24 + sxtb r8, r3, ror #8 - + sxtab r3, r8, r3, ror #(fred - wilma) + sxtab r7, r8, r3, ror #25 + sxtah r9, r3, r3, ror #-8 + sxtb16ge r2, r3, lsr #24 + +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: sxtb r8, r3, #8 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: '#' expected +@ CHECK-ERRORS: sxtb r8, r3, ror 24 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: unknown token in expression +@ CHECK-ERRORS: sxtb r8, r3, ror #8 - +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: malformed rotate expression +@ CHECK-ERRORS: sxtb r8, r3, ror #8 - +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: rotate amount must be an immediate +@ CHECK-ERRORS: sxtab r3, r8, r3, ror #(fred - wilma) +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: 'ror' rotate amount must be 8, 16, or 24 +@ CHECK-ERRORS: sxtab r7, r8, r3, ror #25 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: 'ror' rotate amount must be 8, 16, or 24 +@ CHECK-ERRORS: sxtah r9, r3, r3, ror #-8 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: sxtb16ge r2, r3, lsr #24 +@ CHECK-ERRORS: ^ + + @ Out of range width for SBFX/UBFX + sbfx r4, r5, #31, #2 + ubfxgt r4, r5, #16, #17 + +@ CHECK-ERRORS: error: bitfield width must be in range [1,32-lsb] +@ CHECK-ERRORS: sbfx r4, r5, #31, #2 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: bitfield width must be in range [1,32-lsb] +@ CHECK-ERRORS: ubfxgt r4, r5, #16, #17 +@ CHECK-ERRORS: ^ + + @ Out of order Rt/Rt2 operands for ldrd + ldrd r4, r3, [r8] + ldrd r4, r3, [r8, #8]! + ldrd r4, r3, [r8], #8 +@ CHECK-ERRORS: error: destination operands must be sequential +@ CHECK-ERRORS: ldrd r4, r3, [r8] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination operands must be sequential +@ CHECK-ERRORS: ldrd r4, r3, [r8, #8]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination operands must be sequential +@ CHECK-ERRORS: ldrd r4, r3, [r8], #8 +@ CHECK-ERRORS: ^ + + + @ Bad register lists for VFP. + vpush {s0, s3} +@ CHECK-ERRORS: error: non-contiguous register range +@ CHECK-ERRORS: vpush {s0, s3} +@ CHECK-ERRORS: ^ + + @ Out of range coprocessor option immediate. + ldc2 p2, c8, [r1], { 256 } + ldc2 p2, c8, [r1], { -1 } + +@ CHECK-ERRORS: error: coprocessor option must be an immediate in range [0, 255] +@ CHECK-ERRORS: ldc2 p2, c8, [r1], { 256 } +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: coprocessor option must be an immediate in range [0, 255] +@ CHECK-ERRORS: ldc2 p2, c8, [r1], { -1 } +@ CHECK-ERRORS: ^ diff --git a/test/MC/ARM/elf-movt.s b/test/MC/ARM/elf-movt.s index 18061f5..02bb5a6 100644 --- a/test/MC/ARM/elf-movt.s +++ b/test/MC/ARM/elf-movt.s @@ -27,13 +27,13 @@ barf: @ @barf @ OBJ-NEXT: 'sh_entsize', 0x00000000 @ OBJ-NEXT: '_section_data', 'f00f0fe3 f40f4fe3' -@ OBJ: Relocation 0x00000000 +@ OBJ: Relocation 0 @ OBJ-NEXT: 'r_offset', 0x00000000 @ OBJ-NEXT: 'r_sym' -@ OBJ-NEXT: 'r_type', 0x0000002d +@ OBJ-NEXT: 'r_type', 0x2d -@ OBJ: Relocation 0x00000001 +@ OBJ: Relocation 1 @ OBJ-NEXT: 'r_offset', 0x00000004 @ OBJ-NEXT: 'r_sym' -@ OBJ-NEXT: 'r_type', 0x0000002e +@ OBJ-NEXT: 'r_type', 0x2e diff --git a/test/MC/ARM/elf-reloc-01.ll b/test/MC/ARM/elf-reloc-01.ll index eb6e243..e6efe7e 100644 --- a/test/MC/ARM/elf-reloc-01.ll +++ b/test/MC/ARM/elf-reloc-01.ll @@ -60,11 +60,11 @@ bb3: ; preds = %bb, %entry declare void @exit(i32) noreturn nounwind -;; OBJ: Relocation 0x00000001 +;; OBJ: Relocation 1 ;; OBJ-NEXT: 'r_offset', -;; OBJ-NEXT: 'r_sym', 0x00000002 -;; OBJ-NEXT: 'r_type', 0x0000002b +;; OBJ-NEXT: 'r_sym', 0x000002 +;; OBJ-NEXT: 'r_type', 0x2b -;; OBJ: Symbol 0x00000002 +;; OBJ: Symbol 2 ;; OBJ-NEXT: '_MergedGlobals' ;; OBJ-NEXT: 'st_value', 0x00000010 diff --git a/test/MC/ARM/elf-reloc-02.ll b/test/MC/ARM/elf-reloc-02.ll index 091e89f..e51bac3 100644 --- a/test/MC/ARM/elf-reloc-02.ll +++ b/test/MC/ARM/elf-reloc-02.ll @@ -41,10 +41,10 @@ declare i32 @write(...) declare void @exit(i32) noreturn nounwind -;; OBJ: Relocation 0x00000000 +;; OBJ: Relocation 0 ;; OBJ-NEXT: 'r_offset', -;; OBJ-NEXT: 'r_sym', 0x00000002 -;; OBJ-NEXT: 'r_type', 0x0000002b +;; OBJ-NEXT: 'r_sym', 0x000002 +;; OBJ-NEXT: 'r_type', 0x2b -;; OBJ: Symbol 0x00000002 +;; OBJ: Symbol 2 ;; OBJ-NEXT: '.L.str' diff --git a/test/MC/ARM/elf-reloc-03.ll b/test/MC/ARM/elf-reloc-03.ll index 91dba55..922242f 100644 --- a/test/MC/ARM/elf-reloc-03.ll +++ b/test/MC/ARM/elf-reloc-03.ll @@ -88,10 +88,10 @@ entry: declare void @exit(i32) noreturn nounwind -;; OBJ: Relocation 0x00000001 +;; OBJ: Relocation 1 ;; OBJ-NEXT: 'r_offset', -;; OBJ-NEXT: 'r_sym', 0x0000000c -;; OBJ-NEXT: 'r_type', 0x0000002b +;; OBJ-NEXT: 'r_sym', 0x00000c +;; OBJ-NEXT: 'r_type', 0x2b -;; OBJ: Symbol 0x0000000c +;; OBJ: Symbol 12 ;; OBJ-NEXT: 'vtable' diff --git a/test/MC/ARM/elf-thumbfunc-reloc.ll b/test/MC/ARM/elf-thumbfunc-reloc.ll index 6fce4038..e7cb01e 100644 --- a/test/MC/ARM/elf-thumbfunc-reloc.ll +++ b/test/MC/ARM/elf-thumbfunc-reloc.ll @@ -22,16 +22,16 @@ entry: ; make sure that bl 0 <foo> (fff7feff) is correctly encoded -; CHECK: '_section_data', '70470000 2de90048 fff7feff bde80088' +; CHECK: '_section_data', '704700bf 2de90048 fff7feff bde80008' ; Offset Info Type Sym.Value Sym. Name ; 00000008 0000070a R_ARM_THM_CALL 00000001 foo -; CHECK: Relocation 0x00000000 +; CHECK: Relocation 0 ; CHECK-NEXT: 'r_offset', 0x00000008 -; CHECK-NEXT: 'r_sym', 0x00000007 -; CHECK-NEXT: 'r_type', 0x0000000a +; CHECK-NEXT: 'r_sym', 0x000007 +; CHECK-NEXT: 'r_type', 0x0a ; make sure foo is thumb function: bit 0 = 1 -; CHECK: Symbol 0x00000007 +; CHECK: Symbol 7 ; CHECK-NEXT: 'foo' ; CHECK-NEXT: 'st_value', 0x00000001 diff --git a/test/MC/ARM/elf-thumbfunc.s b/test/MC/ARM/elf-thumbfunc.s index a1b3c31..0aa7f41 100644 --- a/test/MC/ARM/elf-thumbfunc.s +++ b/test/MC/ARM/elf-thumbfunc.s @@ -12,9 +12,9 @@ foo: bx lr @@ make sure foo is thumb function: bit 0 = 1 (st_value) -@CHECK: Symbol 0x00000004 +@CHECK: Symbol 4 @CHECK-NEXT: 'st_name', 0x00000001 @CHECK-NEXT: 'st_value', 0x00000001 @CHECK-NEXT: 'st_size', 0x00000000 -@CHECK-NEXT: 'st_bind', 0x00000001 -@CHECK-NEXT: 'st_type', 0x00000002 +@CHECK-NEXT: 'st_bind', 0x1 +@CHECK-NEXT: 'st_type', 0x2 diff --git a/test/MC/ARM/mode-switch.s b/test/MC/ARM/mode-switch.s index 4cc986a..9d49954 100644 --- a/test/MC/ARM/mode-switch.s +++ b/test/MC/ARM/mode-switch.s @@ -1,17 +1,15 @@ @ Test ARM / Thumb mode switching with .code -@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s -@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -triple armv7-unknown-unknown -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -triple thumbv7-unknown-unknown -show-encoding <%s | FileCheck %s .code 16 - -@ CHECK: add.w r0, r0, r1 @ encoding: [0x00,0xeb,0x01,0x00] add.w r0, r0, r1 +@ CHECK: add.w r0, r0, r1 @ encoding: [0x00,0xeb,0x01,0x00] .code 32 -@ CHECK: add r0, r0, r1 @ encoding: [0x01,0x00,0x80,0xe0] add r0, r0, r1 +@ CHECK: add r0, r0, r1 @ encoding: [0x01,0x00,0x80,0xe0] .code 16 -@ CHECK: add r0, r0, r1 @ encoding: [0x40,0x18] - - add r0, r0, r1 + adds r0, r0, r1 +@ CHECK: adds r0, r0, r1 @ encoding: [0x40,0x18] diff --git a/test/MC/ARM/neon-bitwise-encoding.s b/test/MC/ARM/neon-bitwise-encoding.s index 8710923..81e2c4d 100644 --- a/test/MC/ARM/neon-bitwise-encoding.s +++ b/test/MC/ARM/neon-bitwise-encoding.s @@ -1,47 +1,55 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s -@ XFAIL: * -@ CHECK: vand d16, d17, d16 @ encoding: [0xb0,0x01,0x41,0xf2] vand d16, d17, d16 -@ CHECK: vand q8, q8, q9 @ encoding: [0xf2,0x01,0x40,0xf2] vand q8, q8, q9 -@ CHECK: veor d16, d17, d16 @ encoding: [0xb0,0x01,0x41,0xf3] +@ CHECK: vand d16, d17, d16 @ encoding: [0xb0,0x01,0x41,0xf2] +@ CHECK: vand q8, q8, q9 @ encoding: [0xf2,0x01,0x40,0xf2] + veor d16, d17, d16 -@ CHECK: veor q8, q8, q9 @ encoding: [0xf2,0x01,0x40,0xf3] veor q8, q8, q9 -@ CHECK: vorr d16, d17, d16 @ encoding: [0xb0,0x01,0x61,0xf2] +@ CHECK: veor d16, d17, d16 @ encoding: [0xb0,0x01,0x41,0xf3] +@ CHECK: veor q8, q8, q9 @ encoding: [0xf2,0x01,0x40,0xf3] + vorr d16, d17, d16 -@ CHECK: vorr q8, q8, q9 @ encoding: [0xf2,0x01,0x60,0xf2] vorr q8, q8, q9 -@ CHECK: vorr.i32 d16, #0x1000000 @ encoding: [0x11,0x07,0xc0,0xf2] - vorr.i32 d16, #0x1000000 -@ CHECK: vorr.i32 q8, #0x1000000 @ encoding: [0x51,0x07,0xc0,0xf2] - vorr.i32 q8, #0x1000000 -@ CHECK: vorr.i32 q8, #0x0 @ encoding: [0x50,0x01,0xc0,0xf2] - vorr.i32 q8, #0x0 -@ CHECK: vbic d16, d17, d16 @ encoding: [0xb0,0x01,0x51,0xf2] +@ CHECK: vorr d16, d17, d16 @ encoding: [0xb0,0x01,0x61,0xf2] +@ CHECK: vorr q8, q8, q9 @ encoding: [0xf2,0x01,0x60,0xf2] + + vorr.i32 d16, #0x1000000 + vorr.i32 q8, #0x1000000 + vorr.i32 q8, #0x0 + +@ FIXME: vorr.i32 d16, #0x1000000 @ encoding: [0x11,0x07,0xc0,0xf2] +@ FIXME: vorr.i32 q8, #0x1000000 @ encoding: [0x51,0x07,0xc0,0xf2] +@ FIXME: vorr.i32 q8, #0x0 @ encoding: [0x50,0x01,0xc0,0xf2] + vbic d16, d17, d16 -@ CHECK: vbic q8, q8, q9 @ encoding: [0xf2,0x01,0x50,0xf2] vbic q8, q8, q9 -@ CHECK: vbic.i32 d16, #0xFF000000 @ encoding: [0x3f,0x07,0xc7,0xf3] - vbic.i32 d16, #0xFF000000 -@ CHECK: vbic.i32 q8, #0xFF000000 @ encoding: [0x7f,0x07,0xc7,0xf3] - vbic.i32 q8, #0xFF000000 + vbic.i32 d16, #0xFF000000 + vbic.i32 q8, #0xFF000000 + +@ CHECK: vbic d16, d17, d16 @ encoding: [0xb0,0x01,0x51,0xf2] +@ CHECK: vbic q8, q8, q9 @ encoding: [0xf2,0x01,0x50,0xf2] +@ FIXME: vbic.i32 d16, #0xFF000000 @ encoding: [0x3f,0x07,0xc7,0xf3] +@ FIXME: vbic.i32 q8, #0xFF000000 @ encoding: [0x7f,0x07,0xc7,0xf3] -@ CHECK: vorn d16, d17, d16 @ encoding: [0xb0,0x01,0x71,0xf2] vorn d16, d17, d16 -@ CHECK: vorn q8, q8, q9 @ encoding: [0xf2,0x01,0x70,0xf2] vorn q8, q8, q9 -@ CHECK: vmvn d16, d16 @ encoding: [0xa0,0x05,0xf0,0xf3] +@ CHECK: vorn d16, d17, d16 @ encoding: [0xb0,0x01,0x71,0xf2] +@ CHECK: vorn q8, q8, q9 @ encoding: [0xf2,0x01,0x70,0xf2] + vmvn d16, d16 -@ CHECK: vmvn q8, q8 @ encoding: [0xe0,0x05,0xf0,0xf3] vmvn q8, q8 -@ CHECK: vbsl d18, d17, d16 @ encoding: [0xb0,0x21,0x51,0xf3] +@ CHECK: vmvn d16, d16 @ encoding: [0xa0,0x05,0xf0,0xf3] +@ CHECK: vmvn q8, q8 @ encoding: [0xe0,0x05,0xf0,0xf3] + vbsl d18, d17, d16 -@ CHECK: vbsl q8, q10, q9 @ encoding: [0xf2,0x01,0x54,0xf3] vbsl q8, q10, q9 + +@ CHECK: vbsl d18, d17, d16 @ encoding: [0xb0,0x21,0x51,0xf3] +@ CHECK: vbsl q8, q10, q9 @ encoding: [0xf2,0x01,0x54,0xf3] diff --git a/test/MC/ARM/neon-cmp-encoding.s b/test/MC/ARM/neon-cmp-encoding.s index 6bfc549..d94e2f7 100644 --- a/test/MC/ARM/neon-cmp-encoding.s +++ b/test/MC/ARM/neon-cmp-encoding.s @@ -1,115 +1,113 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s -@ XFAIL: * -@ FIXME: We cannot currently test the following instructions, which are -@ currently marked as for-disassembly only in the .td files: -@ - VCEQz -@ - VCGEz, VCLEz -@ - VCGTz, VCLTz - -@ CHECK: vceq.i8 d16, d16, d17 @ encoding: [0xb1,0x08,0x40,0xf3] vceq.i8 d16, d16, d17 -@ CHECK: vceq.i16 d16, d16, d17 @ encoding: [0xb1,0x08,0x50,0xf3] vceq.i16 d16, d16, d17 -@ CHECK: vceq.i32 d16, d16, d17 @ encoding: [0xb1,0x08,0x60,0xf3] vceq.i32 d16, d16, d17 -@ CHECK: vceq.f32 d16, d16, d17 @ encoding: [0xa1,0x0e,0x40,0xf2] vceq.f32 d16, d16, d17 -@ CHECK: vceq.i8 q8, q8, q9 @ encoding: [0xf2,0x08,0x40,0xf3] vceq.i8 q8, q8, q9 -@ CHECK: vceq.i16 q8, q8, q9 @ encoding: [0xf2,0x08,0x50,0xf3] vceq.i16 q8, q8, q9 -@ CHECK: vceq.i32 q8, q8, q9 @ encoding: [0xf2,0x08,0x60,0xf3] vceq.i32 q8, q8, q9 -@ CHECK: vceq.f32 q8, q8, q9 @ encoding: [0xe2,0x0e,0x40,0xf2] vceq.f32 q8, q8, q9 -@ CHECK: vcge.s8 d16, d16, d17 @ encoding: [0xb1,0x03,0x40,0xf2] +@ CHECK: vceq.i8 d16, d16, d17 @ encoding: [0xb1,0x08,0x40,0xf3] +@ CHECK: vceq.i16 d16, d16, d17 @ encoding: [0xb1,0x08,0x50,0xf3] +@ CHECK: vceq.i32 d16, d16, d17 @ encoding: [0xb1,0x08,0x60,0xf3] +@ CHECK: vceq.f32 d16, d16, d17 @ encoding: [0xa1,0x0e,0x40,0xf2] +@ CHECK: vceq.i8 q8, q8, q9 @ encoding: [0xf2,0x08,0x40,0xf3] +@ CHECK: vceq.i16 q8, q8, q9 @ encoding: [0xf2,0x08,0x50,0xf3] +@ CHECK: vceq.i32 q8, q8, q9 @ encoding: [0xf2,0x08,0x60,0xf3] +@ CHECK: vceq.f32 q8, q8, q9 @ encoding: [0xe2,0x0e,0x40,0xf2] + vcge.s8 d16, d16, d17 -@ CHECK: vcge.s16 d16, d16, d17 @ encoding: [0xb1,0x03,0x50,0xf2] vcge.s16 d16, d16, d17 -@ CHECK: vcge.s32 d16, d16, d17 @ encoding: [0xb1,0x03,0x60,0xf2] vcge.s32 d16, d16, d17 -@ CHECK: vcge.u8 d16, d16, d17 @ encoding: [0xb1,0x03,0x40,0xf3] vcge.u8 d16, d16, d17 -@ CHECK: vcge.u16 d16, d16, d17 @ encoding: [0xb1,0x03,0x50,0xf3] vcge.u16 d16, d16, d17 -@ CHECK: vcge.u32 d16, d16, d17 @ encoding: [0xb1,0x03,0x60,0xf3] vcge.u32 d16, d16, d17 -@ CHECK: vcge.f32 d16, d16, d17 @ encoding: [0xa1,0x0e,0x40,0xf3] vcge.f32 d16, d16, d17 -@ CHECK: vcge.s8 q8, q8, q9 @ encoding: [0xf2,0x03,0x40,0xf2] vcge.s8 q8, q8, q9 -@ CHECK: vcge.s16 q8, q8, q9 @ encoding: [0xf2,0x03,0x50,0xf2] vcge.s16 q8, q8, q9 -@ CHECK: vcge.s32 q8, q8, q9 @ encoding: [0xf2,0x03,0x60,0xf2] vcge.s32 q8, q8, q9 -@ CHECK: vcge.u8 q8, q8, q9 @ encoding: [0xf2,0x03,0x40,0xf3] vcge.u8 q8, q8, q9 -@ CHECK: vcge.u16 q8, q8, q9 @ encoding: [0xf2,0x03,0x50,0xf3] vcge.u16 q8, q8, q9 -@ CHECK: vcge.u32 q8, q8, q9 @ encoding: [0xf2,0x03,0x60,0xf3] vcge.u32 q8, q8, q9 -@ CHECK: vcge.f32 q8, q8, q9 @ encoding: [0xe2,0x0e,0x40,0xf3] vcge.f32 q8, q8, q9 -@ CHECK: vacge.f32 d16, d16, d17 @ encoding: [0xb1,0x0e,0x40,0xf3] vacge.f32 d16, d16, d17 -@ CHECK: vacge.f32 q8, q8, q9 @ encoding: [0xf2,0x0e,0x40,0xf3] vacge.f32 q8, q8, q9 -@ CHECK: vcgt.s8 d16, d16, d17 @ encoding: [0xa1,0x03,0x40,0xf2] +@ CHECK: vcge.s8 d16, d16, d17 @ encoding: [0xb1,0x03,0x40,0xf2] +@ CHECK: vcge.s16 d16, d16, d17 @ encoding: [0xb1,0x03,0x50,0xf2] +@ CHECK: vcge.s32 d16, d16, d17 @ encoding: [0xb1,0x03,0x60,0xf2] +@ CHECK: vcge.u8 d16, d16, d17 @ encoding: [0xb1,0x03,0x40,0xf3] +@ CHECK: vcge.u16 d16, d16, d17 @ encoding: [0xb1,0x03,0x50,0xf3] +@ CHECK: vcge.u32 d16, d16, d17 @ encoding: [0xb1,0x03,0x60,0xf3] +@ CHECK: vcge.f32 d16, d16, d17 @ encoding: [0xa1,0x0e,0x40,0xf3] +@ CHECK: vcge.s8 q8, q8, q9 @ encoding: [0xf2,0x03,0x40,0xf2] +@ CHECK: vcge.s16 q8, q8, q9 @ encoding: [0xf2,0x03,0x50,0xf2] +@ CHECK: vcge.s32 q8, q8, q9 @ encoding: [0xf2,0x03,0x60,0xf2] +@ CHECK: vcge.u8 q8, q8, q9 @ encoding: [0xf2,0x03,0x40,0xf3] +@ CHECK: vcge.u16 q8, q8, q9 @ encoding: [0xf2,0x03,0x50,0xf3] +@ CHECK: vcge.u32 q8, q8, q9 @ encoding: [0xf2,0x03,0x60,0xf3] +@ CHECK: vcge.f32 q8, q8, q9 @ encoding: [0xe2,0x0e,0x40,0xf3] +@ CHECK: vacge.f32 d16, d16, d17 @ encoding: [0xb1,0x0e,0x40,0xf3] +@ CHECK: vacge.f32 q8, q8, q9 @ encoding: [0xf2,0x0e,0x40,0xf3] + vcgt.s8 d16, d16, d17 -@ CHECK: vcgt.s16 d16, d16, d17 @ encoding: [0xa1,0x03,0x50,0xf2] vcgt.s16 d16, d16, d17 -@ CHECK: vcgt.s32 d16, d16, d17 @ encoding: [0xa1,0x03,0x60,0xf2] vcgt.s32 d16, d16, d17 -@ CHECK: vcgt.u8 d16, d16, d17 @ encoding: [0xa1,0x03,0x40,0xf3] vcgt.u8 d16, d16, d17 -@ CHECK: vcgt.u16 d16, d16, d17 @ encoding: [0xa1,0x03,0x50,0xf3] vcgt.u16 d16, d16, d17 -@ CHECK: vcgt.u32 d16, d16, d17 @ encoding: [0xa1,0x03,0x60,0xf3] vcgt.u32 d16, d16, d17 -@ CHECK: vcgt.f32 d16, d16, d17 @ encoding: [0xa1,0x0e,0x60,0xf3] vcgt.f32 d16, d16, d17 -@ CHECK: vcgt.s8 q8, q8, q9 @ encoding: [0xe2,0x03,0x40,0xf2] vcgt.s8 q8, q8, q9 -@ CHECK: vcgt.s16 q8, q8, q9 @ encoding: [0xe2,0x03,0x50,0xf2] vcgt.s16 q8, q8, q9 -@ CHECK: vcgt.s32 q8, q8, q9 @ encoding: [0xe2,0x03,0x60,0xf2] vcgt.s32 q8, q8, q9 -@ CHECK: vcgt.u8 q8, q8, q9 @ encoding: [0xe2,0x03,0x40,0xf3] vcgt.u8 q8, q8, q9 -@ CHECK: vcgt.u16 q8, q8, q9 @ encoding: [0xe2,0x03,0x50,0xf3] vcgt.u16 q8, q8, q9 -@ CHECK: vcgt.u32 q8, q8, q9 @ encoding: [0xe2,0x03,0x60,0xf3] vcgt.u32 q8, q8, q9 -@ CHECK: vcgt.f32 q8, q8, q9 @ encoding: [0xe2,0x0e,0x60,0xf3] vcgt.f32 q8, q8, q9 -@ CHECK: vacgt.f32 d16, d16, d17 @ encoding: [0xb1,0x0e,0x60,0xf3] vacgt.f32 d16, d16, d17 -@ CHECK: vacgt.f32 q8, q8, q9 @ encoding: [0xf2,0x0e,0x60,0xf3] vacgt.f32 q8, q8, q9 -@ CHECK: vtst.8 d16, d16, d17 @ encoding: [0xb1,0x08,0x40,0xf2] +@ CHECK: vcgt.s8 d16, d16, d17 @ encoding: [0xa1,0x03,0x40,0xf2] +@ CHECK: vcgt.s16 d16, d16, d17 @ encoding: [0xa1,0x03,0x50,0xf2] +@ CHECK: vcgt.s32 d16, d16, d17 @ encoding: [0xa1,0x03,0x60,0xf2] +@ CHECK: vcgt.u8 d16, d16, d17 @ encoding: [0xa1,0x03,0x40,0xf3] +@ CHECK: vcgt.u16 d16, d16, d17 @ encoding: [0xa1,0x03,0x50,0xf3] +@ CHECK: vcgt.u32 d16, d16, d17 @ encoding: [0xa1,0x03,0x60,0xf3] +@ CHECK: vcgt.f32 d16, d16, d17 @ encoding: [0xa1,0x0e,0x60,0xf3] +@ CHECK: vcgt.s8 q8, q8, q9 @ encoding: [0xe2,0x03,0x40,0xf2] +@ CHECK: vcgt.s16 q8, q8, q9 @ encoding: [0xe2,0x03,0x50,0xf2] +@ CHECK: vcgt.s32 q8, q8, q9 @ encoding: [0xe2,0x03,0x60,0xf2] +@ CHECK: vcgt.u8 q8, q8, q9 @ encoding: [0xe2,0x03,0x40,0xf3] +@ CHECK: vcgt.u16 q8, q8, q9 @ encoding: [0xe2,0x03,0x50,0xf3] +@ CHECK: vcgt.u32 q8, q8, q9 @ encoding: [0xe2,0x03,0x60,0xf3] +@ CHECK: vcgt.f32 q8, q8, q9 @ encoding: [0xe2,0x0e,0x60,0xf3] +@ CHECK: vacgt.f32 d16, d16, d17 @ encoding: [0xb1,0x0e,0x60,0xf3] +@ CHECK: vacgt.f32 q8, q8, q9 @ encoding: [0xf2,0x0e,0x60,0xf3] + vtst.8 d16, d16, d17 -@ CHECK: vtst.16 d16, d16, d17 @ encoding: [0xb1,0x08,0x50,0xf2] vtst.16 d16, d16, d17 -@ CHECK: vtst.32 d16, d16, d17 @ encoding: [0xb1,0x08,0x60,0xf2] vtst.32 d16, d16, d17 -@ CHECK: vtst.8 q8, q8, q9 @ encoding: [0xf2,0x08,0x40,0xf2] vtst.8 q8, q8, q9 -@ CHECK: vtst.16 q8, q8, q9 @ encoding: [0xf2,0x08,0x50,0xf2] vtst.16 q8, q8, q9 -@ CHECK: vtst.32 q8, q8, q9 @ encoding: [0xf2,0x08,0x60,0xf2] vtst.32 q8, q8, q9 -@ CHECK: vceq.i8 d16, d16, #0 @ encoding: [0x20,0x01,0xf1,0xf3] - vceq.i8 d16, d16, #0 -@ CHECK: vcge.s8 d16, d16, #0 @ encoding: [0xa0,0x00,0xf1,0xf3] - vcge.s8 d16, d16, #0 -@ CHECK: vcle.s8 d16, d16, #0 @ encoding: [0xa0,0x01,0xf1,0xf3] - vcle.s8 d16, d16, #0 -@ CHECK: vcgt.s8 d16, d16, #0 @ encoding: [0x20,0x00,0xf1,0xf3] - vcgt.s8 d16, d16, #0 -@ CHECK: vclt.s8 d16, d16, #0 @ encoding: [0x20,0x02,0xf1,0xf3] - vclt.s8 d16, d16, #0 +@ CHECK: vtst.8 d16, d16, d17 @ encoding: [0xb1,0x08,0x40,0xf2] +@ CHECK: vtst.16 d16, d16, d17 @ encoding: [0xb1,0x08,0x50,0xf2] +@ CHECK: vtst.32 d16, d16, d17 @ encoding: [0xb1,0x08,0x60,0xf2] +@ CHECK: vtst.8 q8, q8, q9 @ encoding: [0xf2,0x08,0x40,0xf2] +@ CHECK: vtst.16 q8, q8, q9 @ encoding: [0xf2,0x08,0x50,0xf2] +@ CHECK: vtst.32 q8, q8, q9 @ encoding: [0xf2,0x08,0x60,0xf2] + + vceq.i8 d16, d16, #0 + vcge.s8 d16, d16, #0 + vcle.s8 d16, d16, #0 + vcgt.s8 d16, d16, #0 + vclt.s8 d16, d16, #0 + +@ CHECK: vceq.i8 d16, d16, #0 @ encoding: [0x20,0x01,0xf1,0xf3] +@ CHECK: vcge.s8 d16, d16, #0 @ encoding: [0xa0,0x00,0xf1,0xf3] +@ CHECK: vcle.s8 d16, d16, #0 @ encoding: [0xa0,0x01,0xf1,0xf3] +@ CHECK: vcgt.s8 d16, d16, #0 @ encoding: [0x20,0x00,0xf1,0xf3] +@ CHECK: vclt.s8 d16, d16, #0 @ encoding: [0x20,0x02,0xf1,0xf3] diff --git a/test/MC/ARM/neon-dup-encoding.s b/test/MC/ARM/neon-dup-encoding.s index 0aebdce..31dcf0b 100644 --- a/test/MC/ARM/neon-dup-encoding.s +++ b/test/MC/ARM/neon-dup-encoding.s @@ -1,27 +1,33 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s -@ XFAIL: * -@ CHECK: vdup.8 d16, r0 @ encoding: [0x90,0x0b,0xc0,0xee] vdup.8 d16, r0 -@ CHECK: vdup.16 d16, r0 @ encoding: [0xb0,0x0b,0x80,0xee] vdup.16 d16, r0 -@ CHECK: vdup.32 d16, r0 @ encoding: [0x90,0x0b,0x80,0xee] vdup.32 d16, r0 -@ CHECK: vdup.8 q8, r0 @ encoding: [0x90,0x0b,0xe0,0xee] + +@ CHECK: vdup.8 d16, r0 @ encoding: [0x90,0x0b,0xc0,0xee] +@ CHECK: vdup.16 d16, r0 @ encoding: [0xb0,0x0b,0x80,0xee] +@ CHECK: vdup.32 d16, r0 @ encoding: [0x90,0x0b,0x80,0xee] + vdup.8 q8, r0 -@ CHECK: vdup.16 q8, r0 @ encoding: [0xb0,0x0b,0xa0,0xee] vdup.16 q8, r0 -@ CHECK: vdup.32 q8, r0 @ encoding: [0x90,0x0b,0xa0,0xee] vdup.32 q8, r0 -@ CHECK: vdup.8 d16, d16[1] @ encoding: [0x20,0x0c,0xf3,0xf3] + +@ CHECK: vdup.8 q8, r0 @ encoding: [0x90,0x0b,0xe0,0xee] +@ CHECK: vdup.16 q8, r0 @ encoding: [0xb0,0x0b,0xa0,0xee] +@ CHECK: vdup.32 q8, r0 @ encoding: [0x90,0x0b,0xa0,0xee] + vdup.8 d16, d16[1] -@ CHECK: vdup.16 d16, d16[1] @ encoding: [0x20,0x0c,0xf6,0xf3] vdup.16 d16, d16[1] -@ CHECK: vdup.32 d16, d16[1] @ encoding: [0x20,0x0c,0xfc,0xf3] vdup.32 d16, d16[1] -@ CHECK: vdup.8 q8, d16[1] @ encoding: [0x60,0x0c,0xf3,0xf3] + +@ CHECK: vdup.8 d16, d16[1] @ encoding: [0x20,0x0c,0xf3,0xf3] +@ CHECK: vdup.16 d16, d16[1] @ encoding: [0x20,0x0c,0xf6,0xf3] +@ CHECK: vdup.32 d16, d16[1] @ encoding: [0x20,0x0c,0xfc,0xf3] + vdup.8 q8, d16[1] -@ CHECK: vdup.16 q8, d16[1] @ encoding: [0x60,0x0c,0xf6,0xf3] vdup.16 q8, d16[1] -@ CHECK: vdup.32 q8, d16[1] @ encoding: [0x60,0x0c,0xfc,0xf3] vdup.32 q8, d16[1] + +@ CHECK: vdup.8 q8, d16[1] @ encoding: [0x60,0x0c,0xf3,0xf3] +@ CHECK: vdup.16 q8, d16[1] @ encoding: [0x60,0x0c,0xf6,0xf3] +@ CHECK: vdup.32 q8, d16[1] @ encoding: [0x60,0x0c,0xfc,0xf3] diff --git a/test/MC/ARM/neon-mov-encoding.s b/test/MC/ARM/neon-mov-encoding.s index ca678d0..02eec12 100644 --- a/test/MC/ARM/neon-mov-encoding.s +++ b/test/MC/ARM/neon-mov-encoding.s @@ -1,117 +1,131 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s @ XFAIL: * -@ CHECK: vmov.i8 d16, #0x8 @ encoding: [0x18,0x0e,0xc0,0xf2] - vmov.i8 d16, #0x8 -@ CHECK: vmov.i16 d16, #0x10 @ encoding: [0x10,0x08,0xc1,0xf2] + vmov.i8 d16, #0x8 vmov.i16 d16, #0x10 -@ CHECK: vmov.i16 d16, #0x1000 @ encoding: [0x10,0x0a,0xc1,0xf2] vmov.i16 d16, #0x1000 -@ CHECK: vmov.i32 d16, #0x20 @ encoding: [0x10,0x00,0xc2,0xf2] vmov.i32 d16, #0x20 -@ CHECK: vmov.i32 d16, #0x2000 @ encoding: [0x10,0x02,0xc2,0xf2] vmov.i32 d16, #0x2000 -@ CHECK: vmov.i32 d16, #0x200000 @ encoding: [0x10,0x04,0xc2,0xf2] vmov.i32 d16, #0x200000 -@ CHECK: vmov.i32 d16, #0x20000000 @ encoding: [0x10,0x06,0xc2,0xf2] vmov.i32 d16, #0x20000000 -@ CHECK: vmov.i32 d16, #0x20FF @ encoding: [0x10,0x0c,0xc2,0xf2] vmov.i32 d16, #0x20FF -@ CHECK: vmov.i32 d16, #0x20FFFF @ encoding: [0x10,0x0d,0xc2,0xf2] vmov.i32 d16, #0x20FFFF -@ CHECK: vmov.i64 d16, #0xFF0000FF0000FFFF @ encoding: [0x33,0x0e,0xc1,0xf3] vmov.i64 d16, #0xFF0000FF0000FFFF -@ CHECK: vmov.i8 q8, #0x8 @ encoding: [0x58,0x0e,0xc0,0xf2] - vmov.i8 q8, #0x8 -@ CHECK: vmov.i16 q8, #0x10 @ encoding: [0x50,0x08,0xc1,0xf2] + +@ CHECK: vmov.i8 d16, #0x8 @ encoding: [0x18,0x0e,0xc0,0xf2] +@ CHECK: vmov.i16 d16, #0x10 @ encoding: [0x10,0x08,0xc1,0xf2] +@ CHECK: vmov.i16 d16, #0x1000 @ encoding: [0x10,0x0a,0xc1,0xf2] +@ CHECK: vmov.i32 d16, #0x20 @ encoding: [0x10,0x00,0xc2,0xf2] +@ CHECK: vmov.i32 d16, #0x2000 @ encoding: [0x10,0x02,0xc2,0xf2] +@ CHECK: vmov.i32 d16, #0x200000 @ encoding: [0x10,0x04,0xc2,0xf2] +@ CHECK: vmov.i32 d16, #0x20000000 @ encoding: [0x10,0x06,0xc2,0xf2] +@ CHECK: vmov.i32 d16, #0x20FF @ encoding: [0x10,0x0c,0xc2,0xf2] +@ CHECK: vmov.i32 d16, #0x20FFFF @ encoding: [0x10,0x0d,0xc2,0xf2] +@ CHECK: vmov.i64 d16, #0xFF0000FF0000FFFF @ encoding: [0x33,0x0e,0xc1,0xf3] + + + + vmov.i8 q8, #0x8 vmov.i16 q8, #0x10 -@ CHECK: vmov.i16 q8, #0x1000 @ encoding: [0x50,0x0a,0xc1,0xf2] vmov.i16 q8, #0x1000 -@ CHECK: vmov.i32 q8, #0x20 @ encoding: [0x50,0x00,0xc2,0xf2] vmov.i32 q8, #0x20 -@ CHECK: vmov.i32 q8, #0x2000 @ encoding: [0x50,0x02,0xc2,0xf2] vmov.i32 q8, #0x2000 -@ CHECK: vmov.i32 q8, #0x200000 @ encoding: [0x50,0x04,0xc2,0xf2] vmov.i32 q8, #0x200000 -@ CHECK: vmov.i32 q8, #0x20000000 @ encoding: [0x50,0x06,0xc2,0xf2] vmov.i32 q8, #0x20000000 -@ CHECK: vmov.i32 q8, #0x20FF @ encoding: [0x50,0x0c,0xc2,0xf2] vmov.i32 q8, #0x20FF -@ CHECK: vmov.i32 q8, #0x20FFFF @ encoding: [0x50,0x0d,0xc2,0xf2] vmov.i32 q8, #0x20FFFF -@ CHECK: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0x73,0x0e,0xc1,0xf3] vmov.i64 q8, #0xFF0000FF0000FFFF -@ CHECK: vmvn.i16 d16, #0x10 @ encoding: [0x30,0x08,0xc1,0xf2] + +@ CHECK: vmov.i8 q8, #0x8 @ encoding: [0x58,0x0e,0xc0,0xf2] +@ CHECK: vmov.i16 q8, #0x10 @ encoding: [0x50,0x08,0xc1,0xf2] +@ CHECK: vmov.i16 q8, #0x1000 @ encoding: [0x50,0x0a,0xc1,0xf2] +@ CHECK: vmov.i32 q8, #0x20 @ encoding: [0x50,0x00,0xc2,0xf2] +@ CHECK: vmov.i32 q8, #0x2000 @ encoding: [0x50,0x02,0xc2,0xf2] +@ CHECK: vmov.i32 q8, #0x200000 @ encoding: [0x50,0x04,0xc2,0xf2] +@ CHECK: vmov.i32 q8, #0x20000000 @ encoding: [0x50,0x06,0xc2,0xf2] +@ CHECK: vmov.i32 q8, #0x20FF @ encoding: [0x50,0x0c,0xc2,0xf2] +@ CHECK: vmov.i32 q8, #0x20FFFF @ encoding: [0x50,0x0d,0xc2,0xf2] +@ CHECK: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0x73,0x0e,0xc1,0xf3] + vmvn.i16 d16, #0x10 -@ CHECK: vmvn.i16 d16, #0x1000 @ encoding: [0x30,0x0a,0xc1,0xf2] vmvn.i16 d16, #0x1000 -@ CHECK: vmvn.i32 d16, #0x20 @ encoding: [0x30,0x00,0xc2,0xf2] vmvn.i32 d16, #0x20 -@ CHECK: vmvn.i32 d16, #0x2000 @ encoding: [0x30,0x02,0xc2,0xf2] vmvn.i32 d16, #0x2000 -@ CHECK: vmvn.i32 d16, #0x200000 @ encoding: [0x30,0x04,0xc2,0xf2] vmvn.i32 d16, #0x200000 -@ CHECK: vmvn.i32 d16, #0x20000000 @ encoding: [0x30,0x06,0xc2,0xf2] vmvn.i32 d16, #0x20000000 -@ CHECK: vmvn.i32 d16, #0x20FF @ encoding: [0x30,0x0c,0xc2,0xf2] vmvn.i32 d16, #0x20FF -@ CHECK: vmvn.i32 d16, #0x20FFFF @ encoding: [0x30,0x0d,0xc2,0xf2] vmvn.i32 d16, #0x20FFFF -@ CHECK: vmovl.s8 q8, d16 @ encoding: [0x30,0x0a,0xc8,0xf2] + +@ CHECK: vmvn.i16 d16, #0x10 @ encoding: [0x30,0x08,0xc1,0xf2] +@ CHECK: vmvn.i16 d16, #0x1000 @ encoding: [0x30,0x0a,0xc1,0xf2] +@ CHECK: vmvn.i32 d16, #0x20 @ encoding: [0x30,0x00,0xc2,0xf2] +@ CHECK: vmvn.i32 d16, #0x2000 @ encoding: [0x30,0x02,0xc2,0xf2] +@ CHECK: vmvn.i32 d16, #0x200000 @ encoding: [0x30,0x04,0xc2,0xf2] +@ CHECK: vmvn.i32 d16, #0x20000000 @ encoding: [0x30,0x06,0xc2,0xf2] +@ CHECK: vmvn.i32 d16, #0x20FF @ encoding: [0x30,0x0c,0xc2,0xf2] +@ CHECK: vmvn.i32 d16, #0x20FFFF @ encoding: [0x30,0x0d,0xc2,0xf2] + vmovl.s8 q8, d16 -@ CHECK: vmovl.s16 q8, d16 @ encoding: [0x30,0x0a,0xd0,0xf2] vmovl.s16 q8, d16 -@ CHECK: vmovl.s32 q8, d16 @ encoding: [0x30,0x0a,0xe0,0xf2] vmovl.s32 q8, d16 -@ CHECK: vmovl.u8 q8, d16 @ encoding: [0x30,0x0a,0xc8,0xf3] vmovl.u8 q8, d16 -@ CHECK: vmovl.u16 q8, d16 @ encoding: [0x30,0x0a,0xd0,0xf3] vmovl.u16 q8, d16 -@ CHECK: vmovl.u32 q8, d16 @ encoding: [0x30,0x0a,0xe0,0xf3] vmovl.u32 q8, d16 -@ CHECK: vmovn.i16 d16, q8 @ encoding: [0x20,0x02,0xf2,0xf3] + +@ CHECK: vmovl.s8 q8, d16 @ encoding: [0x30,0x0a,0xc8,0xf2] +@ CHECK: vmovl.s16 q8, d16 @ encoding: [0x30,0x0a,0xd0,0xf2] +@ CHECK: vmovl.s32 q8, d16 @ encoding: [0x30,0x0a,0xe0,0xf2] +@ CHECK: vmovl.u8 q8, d16 @ encoding: [0x30,0x0a,0xc8,0xf3] +@ CHECK: vmovl.u16 q8, d16 @ encoding: [0x30,0x0a,0xd0,0xf3] +@ CHECK: vmovl.u32 q8, d16 @ encoding: [0x30,0x0a,0xe0,0xf3] + + vmovn.i16 d16, q8 -@ CHECK: vmovn.i32 d16, q8 @ encoding: [0x20,0x02,0xf6,0xf3] vmovn.i32 d16, q8 -@ CHECK: vmovn.i64 d16, q8 @ encoding: [0x20,0x02,0xfa,0xf3] vmovn.i64 d16, q8 -@ CHECK: vqmovn.s16 d16, q8 @ encoding: [0xa0,0x02,0xf2,0xf3] vqmovn.s16 d16, q8 -@ CHECK: vqmovn.s32 d16, q8 @ encoding: [0xa0,0x02,0xf6,0xf3] vqmovn.s32 d16, q8 -@ CHECK: vqmovn.s64 d16, q8 @ encoding: [0xa0,0x02,0xfa,0xf3] vqmovn.s64 d16, q8 -@ CHECK: vqmovn.u16 d16, q8 @ encoding: [0xe0,0x02,0xf2,0xf3] vqmovn.u16 d16, q8 -@ CHECK: vqmovn.u32 d16, q8 @ encoding: [0xe0,0x02,0xf6,0xf3] vqmovn.u32 d16, q8 -@ CHECK: vqmovn.u64 d16, q8 @ encoding: [0xe0,0x02,0xfa,0xf3] vqmovn.u64 d16, q8 -@ CHECK: vqmovun.s16 d16, q8 @ encoding: [0x60,0x02,0xf2,0xf3] vqmovun.s16 d16, q8 -@ CHECK: vqmovun.s32 d16, q8 @ encoding: [0x60,0x02,0xf6,0xf3] vqmovun.s32 d16, q8 -@ CHECK: vqmovun.s64 d16, q8 @ encoding: [0x60,0x02,0xfa,0xf3] vqmovun.s64 d16, q8 -@ CHECK: vmov.s8 r0, d16[1] @ encoding: [0xb0,0x0b,0x50,0xee] - vmov.s8 r0, d16[1] -@ CHECK: vmov.s16 r0, d16[1] @ encoding: [0xf0,0x0b,0x10,0xee] + +@ CHECK: vmovn.i16 d16, q8 @ encoding: [0x20,0x02,0xf2,0xf3] +@ CHECK: vmovn.i32 d16, q8 @ encoding: [0x20,0x02,0xf6,0xf3] +@ CHECK: vmovn.i64 d16, q8 @ encoding: [0x20,0x02,0xfa,0xf3] +@ CHECK: vqmovn.s16 d16, q8 @ encoding: [0xa0,0x02,0xf2,0xf3] +@ CHECK: vqmovn.s32 d16, q8 @ encoding: [0xa0,0x02,0xf6,0xf3] +@ CHECK: vqmovn.s64 d16, q8 @ encoding: [0xa0,0x02,0xfa,0xf3] +@ CHECK: vqmovn.u16 d16, q8 @ encoding: [0xe0,0x02,0xf2,0xf3] +@ CHECK: vqmovn.u32 d16, q8 @ encoding: [0xe0,0x02,0xf6,0xf3] +@ CHECK: vqmovn.u64 d16, q8 @ encoding: [0xe0,0x02,0xfa,0xf3] +@ CHECK: vqmovun.s16 d16, q8 @ encoding: [0x60,0x02,0xf2,0xf3] +@ CHECK: vqmovun.s32 d16, q8 @ encoding: [0x60,0x02,0xf6,0xf3] +@ CHECK: vqmovun.s64 d16, q8 @ encoding: [0x60,0x02,0xfa,0xf3] + + vmov.s8 r0, d16[1] vmov.s16 r0, d16[1] -@ CHECK: vmov.u8 r0, d16[1] @ encoding: [0xb0,0x0b,0xd0,0xee] - vmov.u8 r0, d16[1] -@ CHECK: vmov.u16 r0, d16[1] @ encoding: [0xf0,0x0b,0x90,0xee] + vmov.u8 r0, d16[1] vmov.u16 r0, d16[1] -@ CHECK: vmov.32 r0, d16[1] @ encoding: [0x90,0x0b,0x30,0xee] - vmov.32 r0, d16[1] -@ CHECK: vmov.8 d16[1], r1 @ encoding: [0xb0,0x1b,0x40,0xee] + vmov.32 r0, d16[1] vmov.8 d16[1], r1 -@ CHECK: vmov.16 d16[1], r1 @ encoding: [0xf0,0x1b,0x00,0xee] vmov.16 d16[1], r1 -@ CHECK: vmov.32 d16[1], r1 @ encoding: [0x90,0x1b,0x20,0xee] vmov.32 d16[1], r1 -@ CHECK: vmov.8 d18[1], r1 @ encoding: [0xb0,0x1b,0x42,0xee] vmov.8 d18[1], r1 -@ CHECK: vmov.16 d18[1], r1 @ encoding: [0xf0,0x1b,0x02,0xee] vmov.16 d18[1], r1 -@ CHECK: vmov.32 d18[1], r1 @ encoding: [0x90,0x1b,0x22,0xee] vmov.32 d18[1], r1 + +@ CHECK: vmov.s8 r0, d16[1] @ encoding: [0xb0,0x0b,0x50,0xee] +@ CHECK: vmov.s16 r0, d16[1] @ encoding: [0xf0,0x0b,0x10,0xee] +@ CHECK: vmov.u8 r0, d16[1] @ encoding: [0xb0,0x0b,0xd0,0xee] +@ CHECK: vmov.u16 r0, d16[1] @ encoding: [0xf0,0x0b,0x90,0xee] +@ CHECK: vmov.32 r0, d16[1] @ encoding: [0x90,0x0b,0x30,0xee] +@ CHECK: vmov.8 d16[1], r1 @ encoding: [0xb0,0x1b,0x40,0xee] +@ CHECK: vmov.16 d16[1], r1 @ encoding: [0xf0,0x1b,0x00,0xee] +@ CHECK: vmov.32 d16[1], r1 @ encoding: [0x90,0x1b,0x20,0xee] +@ CHECK: vmov.8 d18[1], r1 @ encoding: [0xb0,0x1b,0x42,0xee] +@ CHECK: vmov.16 d18[1], r1 @ encoding: [0xf0,0x1b,0x02,0xee] +@ CHECK: vmov.32 d18[1], r1 @ encoding: [0x90,0x1b,0x22,0xee] diff --git a/test/MC/ARM/neon-mul-accum-encoding.s b/test/MC/ARM/neon-mul-accum-encoding.s index e269dea..ed9ceb3 100644 --- a/test/MC/ARM/neon-mul-accum-encoding.s +++ b/test/MC/ARM/neon-mul-accum-encoding.s @@ -1,11 +1,10 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s -@ XFAIL: * @ CHECK: vmla.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xf2] vmla.i8 d16, d18, d17 @ CHECK: vmla.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xf2] vmla.i16 d16, d18, d17 -@ CHECK: vmla.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xf2] +@ CHECK: vmla.i32 d16, d18, d17 @ encoding: [0xa1,0x09,0x62,0xf2] vmla.i32 d16, d18, d17 @ CHECK: vmla.f32 d16, d18, d17 @ encoding: [0xb1,0x0d,0x42,0xf2] vmla.f32 d16, d18, d17 diff --git a/test/MC/ARM/neon-mul-encoding.s b/test/MC/ARM/neon-mul-encoding.s index 4ff192f..4dc7803 100644 --- a/test/MC/ARM/neon-mul-encoding.s +++ b/test/MC/ARM/neon-mul-encoding.s @@ -1,56 +1,82 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s -@ CHECK: vmul.i8 d16, d16, d17 @ encoding: [0xb1,0x09,0x40,0xf2] - vmul.i8 d16, d16, d17 -@ CHECK: vmul.i16 d16, d16, d17 @ encoding: [0xb1,0x09,0x50,0xf2] - vmul.i16 d16, d16, d17 -@ CHECK: vmul.i32 d16, d16, d17 @ encoding: [0xb1,0x09,0x60,0xf2] - vmul.i32 d16, d16, d17 -@ CHECK: vmul.f32 d16, d16, d17 @ encoding: [0xb1,0x0d,0x40,0xf3] - vmul.f32 d16, d16, d17 -@ CHECK: vmul.i8 q8, q8, q9 @ encoding: [0xf2,0x09,0x40,0xf2] - vmul.i8 q8, q8, q9 -@ CHECK: vmul.i16 q8, q8, q9 @ encoding: [0xf2,0x09,0x50,0xf2] - vmul.i16 q8, q8, q9 -@ CHECK: vmul.i32 q8, q8, q9 @ encoding: [0xf2,0x09,0x60,0xf2] - vmul.i32 q8, q8, q9 -@ CHECK: vmul.f32 q8, q8, q9 @ encoding: [0xf2,0x0d,0x40,0xf3] - vmul.f32 q8, q8, q9 -@ CHECK: vmul.p8 d16, d16, d17 @ encoding: [0xb1,0x09,0x40,0xf3] - vmul.p8 d16, d16, d17 -@ CHECK: vmul.p8 q8, q8, q9 @ encoding: [0xf2,0x09,0x40,0xf3] - vmul.p8 q8, q8, q9 -@ CHECK: vqdmulh.s16 d16, d16, d17 @ encoding: [0xa1,0x0b,0x50,0xf2] - vqdmulh.s16 d16, d16, d17 -@ CHECK: vqdmulh.s32 d16, d16, d17 @ encoding: [0xa1,0x0b,0x60,0xf2] - vqdmulh.s32 d16, d16, d17 -@ CHECK: vqdmulh.s16 q8, q8, q9 @ encoding: [0xe2,0x0b,0x50,0xf2] - vqdmulh.s16 q8, q8, q9 -@ CHECK: vqdmulh.s32 q8, q8, q9 @ encoding: [0xe2,0x0b,0x60,0xf2] - vqdmulh.s32 q8, q8, q9 -@ CHECK: vqrdmulh.s16 d16, d16, d17 @ encoding: [0xa1,0x0b,0x50,0xf3] - vqrdmulh.s16 d16, d16, d17 -@ CHECK: vqrdmulh.s32 d16, d16, d17 @ encoding: [0xa1,0x0b,0x60,0xf3] - vqrdmulh.s32 d16, d16, d17 -@ CHECK: vqrdmulh.s16 q8, q8, q9 @ encoding: [0xe2,0x0b,0x50,0xf3] - vqrdmulh.s16 q8, q8, q9 -@ CHECK: vqrdmulh.s32 q8, q8, q9 @ encoding: [0xe2,0x0b,0x60,0xf3] - vqrdmulh.s32 q8, q8, q9 -@ CHECK: vmull.s8 q8, d16, d17 @ encoding: [0xa1,0x0c,0xc0,0xf2] - vmull.s8 q8, d16, d17 -@ CHECK: vmull.s16 q8, d16, d17 @ encoding: [0xa1,0x0c,0xd0,0xf2] - vmull.s16 q8, d16, d17 -@ CHECK: vmull.s32 q8, d16, d17 @ encoding: [0xa1,0x0c,0xe0,0xf2] - vmull.s32 q8, d16, d17 -@ CHECK: vmull.u8 q8, d16, d17 @ encoding: [0xa1,0x0c,0xc0,0xf3] - vmull.u8 q8, d16, d17 -@ CHECK: vmull.u16 q8, d16, d17 @ encoding: [0xa1,0x0c,0xd0,0xf3] - vmull.u16 q8, d16, d17 -@ CHECK: vmull.u32 q8, d16, d17 @ encoding: [0xa1,0x0c,0xe0,0xf3] - vmull.u32 q8, d16, d17 -@ CHECK: vmull.p8 q8, d16, d17 @ encoding: [0xa1,0x0e,0xc0,0xf2] - vmull.p8 q8, d16, d17 -@ CHECK: vqdmull.s16 q8, d16, d17 @ encoding: [0xa1,0x0d,0xd0,0xf2] - vqdmull.s16 q8, d16, d17 -@ CHECK: vqdmull.s32 q8, d16, d17 @ encoding: [0xa1,0x0d,0xe0,0xf2] - vqdmull.s32 q8, d16, d17 + vmla.i8 d16, d18, d17 + vmla.i16 d16, d18, d17 + vmla.i32 d16, d18, d17 + vmla.f32 d16, d18, d17 + vmla.i8 q9, q8, q10 + vmla.i16 q9, q8, q10 + vmla.i32 q9, q8, q10 + vmla.f32 q9, q8, q10 + +@ CHECK: vmla.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xf2] +@ CHECK: vmla.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xf2] +@ CHECK: vmla.i32 d16, d18, d17 @ encoding: [0xa1,0x09,0x62,0xf2] +@ CHECK: vmla.f32 d16, d18, d17 @ encoding: [0xb1,0x0d,0x42,0xf2] +@ CHECK: vmla.i8 q9, q8, q10 @ encoding: [0xe4,0x29,0x40,0xf2] +@ CHECK: vmla.i16 q9, q8, q10 @ encoding: [0xe4,0x29,0x50,0xf2] +@ CHECK: vmla.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xf2] +@ CHECK: vmla.f32 q9, q8, q10 @ encoding: [0xf4,0x2d,0x40,0xf2] + + + vmlal.s8 q8, d19, d18 + vmlal.s16 q8, d19, d18 + vmlal.s32 q8, d19, d18 + vmlal.u8 q8, d19, d18 + vmlal.u16 q8, d19, d18 + vmlal.u32 q8, d19, d18 + +@ CHECK: vmlal.s8 q8, d19, d18 @ encoding: [0xa2,0x08,0xc3,0xf2] +@ CHECK: vmlal.s16 q8, d19, d18 @ encoding: [0xa2,0x08,0xd3,0xf2] +@ CHECK: vmlal.s32 q8, d19, d18 @ encoding: [0xa2,0x08,0xe3,0xf2] +@ CHECK: vmlal.u8 q8, d19, d18 @ encoding: [0xa2,0x08,0xc3,0xf3] +@ CHECK: vmlal.u16 q8, d19, d18 @ encoding: [0xa2,0x08,0xd3,0xf3] +@ CHECK: vmlal.u32 q8, d19, d18 @ encoding: [0xa2,0x08,0xe3,0xf3] + + + vqdmlal.s16 q8, d19, d18 + vqdmlal.s32 q8, d19, d18 + +@ CHECK: vqdmlal.s16 q8, d19, d18 @ encoding: [0xa2,0x09,0xd3,0xf2] +@ CHECK: vqdmlal.s32 q8, d19, d18 @ encoding: [0xa2,0x09,0xe3,0xf2] + + + vmls.i8 d16, d18, d17 + vmls.i16 d16, d18, d17 + vmls.i32 d16, d18, d17 + vmls.f32 d16, d18, d17 + vmls.i8 q9, q8, q10 + vmls.i16 q9, q8, q10 + vmls.i32 q9, q8, q10 + vmls.f32 q9, q8, q10 + +@ CHECK: vmls.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xf3] +@ CHECK: vmls.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xf3] +@ CHECK: vmls.i32 d16, d18, d17 @ encoding: [0xa1,0x09,0x62,0xf3] +@ CHECK: vmls.f32 d16, d18, d17 @ encoding: [0xb1,0x0d,0x62,0xf2] +@ CHECK: vmls.i8 q9, q8, q10 @ encoding: [0xe4,0x29,0x40,0xf3] +@ CHECK: vmls.i16 q9, q8, q10 @ encoding: [0xe4,0x29,0x50,0xf3] +@ CHECK: vmls.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xf3] +@ CHECK: vmls.f32 q9, q8, q10 @ encoding: [0xf4,0x2d,0x60,0xf2] + + + vmlsl.s8 q8, d19, d18 + vmlsl.s16 q8, d19, d18 + vmlsl.s32 q8, d19, d18 + vmlsl.u8 q8, d19, d18 + vmlsl.u16 q8, d19, d18 + vmlsl.u32 q8, d19, d18 + +@ CHECK: vmlsl.s8 q8, d19, d18 @ encoding: [0xa2,0x0a,0xc3,0xf2] +@ CHECK: vmlsl.s16 q8, d19, d18 @ encoding: [0xa2,0x0a,0xd3,0xf2] +@ CHECK: vmlsl.s32 q8, d19, d18 @ encoding: [0xa2,0x0a,0xe3,0xf2] +@ CHECK: vmlsl.u8 q8, d19, d18 @ encoding: [0xa2,0x0a,0xc3,0xf3] +@ CHECK: vmlsl.u16 q8, d19, d18 @ encoding: [0xa2,0x0a,0xd3,0xf3] +@ CHECK: vmlsl.u32 q8, d19, d18 @ encoding: [0xa2,0x0a,0xe3,0xf3] + + + vqdmlsl.s16 q8, d19, d18 + vqdmlsl.s32 q8, d19, d18 + +@ CHECK: vqdmlsl.s16 q8, d19, d18 @ encoding: [0xa2,0x0b,0xd3,0xf2] +@ CHECK: vqdmlsl.s32 q8, d19, d18 @ encoding: [0xa2,0x0b,0xe3,0xf2] diff --git a/test/MC/ARM/neon-vld-encoding.s b/test/MC/ARM/neon-vld-encoding.s index be55f47..55c8868 100644 --- a/test/MC/ARM/neon-vld-encoding.s +++ b/test/MC/ARM/neon-vld-encoding.s @@ -1,110 +1,125 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s @ XFAIL: * -@ CHECK: vld1.8 {d16}, [r0, :64] @ encoding: [0x1f,0x07,0x60,0xf4] vld1.8 {d16}, [r0, :64] -@ CHECK: vld1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x60,0xf4] - vld1.16 {d16}, [r0] -@ CHECK: vld1.32 {d16}, [r0] @ encoding: [0x8f,0x07,0x60,0xf4] - vld1.32 {d16}, [r0] -@ CHECK: vld1.64 {d16}, [r0] @ encoding: [0xcf,0x07,0x60,0xf4] - vld1.64 {d16}, [r0] + vld1.16 {d16}, [r0] + vld1.32 {d16}, [r0] + vld1.64 {d16}, [r0] + vld1.8 {d16, d17}, [r0, :64] + vld1.16 {d16, d17}, [r0, :128] + vld1.32 {d16, d17}, [r0] + vld1.64 {d16, d17}, [r0] + +@ CHECK: vld1.8 {d16}, [r0, :64] @ encoding: [0x1f,0x07,0x60,0xf4] +@ CHECK: vld1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x60,0xf4] +@ CHECK: vld1.32 {d16}, [r0] @ encoding: [0x8f,0x07,0x60,0xf4] +@ CHECK: vld1.64 {d16}, [r0] @ encoding: [0xcf,0x07,0x60,0xf4] @ CHECK: vld1.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x0a,0x60,0xf4] - vld1.8 {d16, d17}, [r0, :64] -@ CHECK: vld1.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x0a,0x60,0xf4] - vld1.16 {d16, d17}, [r0, :128] -@ CHECK: vld1.32 {d16, d17}, [r0] @ encoding: [0x8f,0x0a,0x60,0xf4] - vld1.32 {d16, d17}, [r0] -@ CHECK: vld1.64 {d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x60,0xf4] - vld1.64 {d16, d17}, [r0] +@ CHECK: vld1.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x0a,0x60,0xf4] +@ CHECK: vld1.32 {d16, d17}, [r0]@ encoding: [0x8f,0x0a,0x60,0xf4] +@ CHECK: vld1.64 {d16, d17}, [r0]@ encoding: [0xcf,0x0a,0x60,0xf4] + + + vld2.8 {d16, d17}, [r0, :64] + vld2.16 {d16, d17}, [r0, :128] + vld2.32 {d16, d17}, [r0] + vld2.8 {d16, d17, d18, d19}, [r0, :64] + vld2.16 {d16, d17, d18, d19}, [r0, :128] + vld2.32 {d16, d17, d18, d19}, [r0, :256] @ CHECK: vld2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x60,0xf4] - vld2.8 {d16, d17}, [r0, :64] -@ CHECK: vld2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x60,0xf4] - vld2.16 {d16, d17}, [r0, :128] -@ CHECK: vld2.32 {d16, d17}, [r0] @ encoding: [0x8f,0x08,0x60,0xf4] - vld2.32 {d16, d17}, [r0] -@ CHECK: vld2.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x03,0x60,0xf4] - vld2.8 {d16, d17, d18, d19}, [r0, :64] -@ CHECK: vld2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x60,0xf4] - vld2.16 {d16, d17, d18, d19}, [r0, :128] -@ CHECK: vld2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x60,0xf4] - vld2.32 {d16, d17, d18, d19}, [r0, :256] +@ CHECK: vld2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x60,0xf4] +@ CHECK: vld2.32 {d16, d17}, [r0]@ encoding: [0x8f,0x08,0x60,0xf4] +@ CHECK: vld2.8 {d16, d17, d18, d19}, [r0, :64]@ encoding: [0x1f,0x03,0x60,0xf4] +@ CHECK: vld2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x60,0xf4] +@ CHECK: vld2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x60,0xf4] + + + vld3.8 {d16, d17, d18}, [r0, :64] + vld3.16 {d16, d17, d18}, [r0] + vld3.32 {d16, d17, d18}, [r0] + vld3.8 {d16, d18, d20}, [r0, :64]! + vld3.8 {d17, d19, d21}, [r0, :64]! + vld3.16 {d16, d18, d20}, [r0]! + vld3.16 {d17, d19, d21}, [r0]! + vld3.32 {d16, d18, d20}, [r0]! + vld3.32 {d17, d19, d21}, [r0]! @ CHECK: vld3.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x04,0x60,0xf4] - vld3.8 {d16, d17, d18}, [r0, :64] -@ CHECK: vld3.16 {d16, d17, d18}, [r0] @ encoding: [0x4f,0x04,0x60,0xf4] - vld3.16 {d16, d17, d18}, [r0] -@ CHECK: vld3.32 {d16, d17, d18}, [r0] @ encoding: [0x8f,0x04,0x60,0xf4] - vld3.32 {d16, d17, d18}, [r0] +@ CHECK: vld3.16 {d16, d17, d18}, [r0] @ encoding: [0x4f,0x04,0x60,0xf4] +@ CHECK: vld3.32 {d16, d17, d18}, [r0] @ encoding: [0x8f,0x04,0x60,0xf4] @ CHECK: vld3.8 {d16, d18, d20}, [r0, :64]! @ encoding: [0x1d,0x05,0x60,0xf4] - vld3.8 {d16, d18, d20}, [r0, :64]! @ CHECK: vld3.8 {d17, d19, d21}, [r0, :64]! @ encoding: [0x1d,0x15,0x60,0xf4] - vld3.8 {d17, d19, d21}, [r0, :64]! -@ CHECK: vld3.16 {d16, d18, d20}, [r0]! @ encoding: [0x4d,0x05,0x60,0xf4] - vld3.16 {d16, d18, d20}, [r0]! -@ CHECK: vld3.16 {d17, d19, d21}, [r0]! @ encoding: [0x4d,0x15,0x60,0xf4] - vld3.16 {d17, d19, d21}, [r0]! -@ CHECK: vld3.32 {d16, d18, d20}, [r0]! @ encoding: [0x8d,0x05,0x60,0xf4] - vld3.32 {d16, d18, d20}, [r0]! -@ CHECK: vld3.32 {d17, d19, d21}, [r0]! @ encoding: [0x8d,0x15,0x60,0xf4] - vld3.32 {d17, d19, d21}, [r0]! - -@ CHECK: vld4.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x00,0x60,0xf4] - vld4.8 {d16, d17, d18, d19}, [r0, :64] -@ CHECK: vld4.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x00,0x60,0xf4] - vld4.16 {d16, d17, d18, d19}, [r0, :128] -@ CHECK: vld4.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x00,0x60,0xf4] - vld4.32 {d16, d17, d18, d19}, [r0, :256] -@ CHECK: vld4.8 {d16, d18, d20, d22}, [r0, :256]! @ encoding: [0x3d,0x01,0x60,0xf4] - vld4.8 {d16, d18, d20, d22}, [r0, :256]! -@ CHECK: vld4.8 {d17, d19, d21, d23}, [r0, :256]! @ encoding: [0x3d,0x11,0x60,0xf4] - vld4.8 {d17, d19, d21, d23}, [r0, :256]! -@ CHECK: vld4.16 {d16, d18, d20, d22}, [r0]! @ encoding: [0x4d,0x01,0x60,0xf4] - vld4.16 {d16, d18, d20, d22}, [r0]! -@ CHECK: vld4.16 {d17, d19, d21, d23}, [r0]! @ encoding: [0x4d,0x11,0x60,0xf4] - vld4.16 {d17, d19, d21, d23}, [r0]! -@ CHECK: vld4.32 {d16, d18, d20, d22}, [r0]! @ encoding: [0x8d,0x01,0x60,0xf4] - vld4.32 {d16, d18, d20, d22}, [r0]! -@ CHECK: vld4.32 {d17, d19, d21, d23}, [r0]! @ encoding: [0x8d,0x11,0x60,0xf4] - vld4.32 {d17, d19, d21, d23}, [r0]! +@ CHECK: vld3.16 {d16, d18, d20}, [r0]! @ encoding: [0x4d,0x05,0x60,0xf4] +@ CHECK: vld3.16 {d17, d19, d21}, [r0]! @ encoding: [0x4d,0x15,0x60,0xf4] +@ CHECK: vld3.32 {d16, d18, d20}, [r0]! @ encoding: [0x8d,0x05,0x60,0xf4] +@ CHECK: vld3.32 {d17, d19, d21}, [r0]! @ encoding: [0x8d,0x15,0x60,0xf4] + + + vld4.8 {d16, d17, d18, d19}, [r0, :64] + vld4.16 {d16, d17, d18, d19}, [r0, :128] + vld4.32 {d16, d17, d18, d19}, [r0, :256] + vld4.8 {d16, d18, d20, d22}, [r0, :256]! + vld4.8 {d17, d19, d21, d23}, [r0, :256]! + vld4.16 {d16, d18, d20, d22}, [r0]! + vld4.16 {d17, d19, d21, d23}, [r0]! + vld4.32 {d16, d18, d20, d22}, [r0]! + vld4.32 {d17, d19, d21, d23}, [r0]! + +@ CHECK: vld4.8 {d16, d17, d18, d19}, [r0, :64]@ encoding: [0x1f,0x00,0x60,0xf4] +@ CHECK: vld4.16 {d16, d17, d18, d19}, [r0,:128]@ encoding:[0x6f,0x00,0x60,0xf4] +@ CHECK: vld4.32 {d16, d17, d18, d19}, [r0,:256]@ encoding:[0xbf,0x00,0x60,0xf4] +@ CHECK: vld4.8 {d16, d18, d20, d22}, [r0,:256]!@ encoding:[0x3d,0x01,0x60,0xf4] +@ CHECK: vld4.8 {d17, d19, d21, d23}, [r0,:256]!@ encoding:[0x3d,0x11,0x60,0xf4] +@ CHECK: vld4.16 {d16, d18, d20, d22}, [r0]! @ encoding: [0x4d,0x01,0x60,0xf4] +@ CHECK: vld4.16 {d17, d19, d21, d23}, [r0]! @ encoding: [0x4d,0x11,0x60,0xf4] +@ CHECK: vld4.32 {d16, d18, d20, d22}, [r0]! @ encoding: [0x8d,0x01,0x60,0xf4] +@ CHECK: vld4.32 {d17, d19, d21, d23}, [r0]! @ encoding: [0x8d,0x11,0x60,0xf4] + + + vld1.8 {d16[3]}, [r0] + vld1.16 {d16[2]}, [r0, :16] + vld1.32 {d16[1]}, [r0, :32] @ CHECK: vld1.8 {d16[3]}, [r0] @ encoding: [0x6f,0x00,0xe0,0xf4] - vld1.8 {d16[3]}, [r0] -@ CHECK: vld1.16 {d16[2]}, [r0, :16] @ encoding: [0x9f,0x04,0xe0,0xf4] - vld1.16 {d16[2]}, [r0, :16] -@ CHECK: vld1.32 {d16[1]}, [r0, :32] @ encoding: [0xbf,0x08,0xe0,0xf4] - vld1.32 {d16[1]}, [r0, :32] +@ CHECK: vld1.16 {d16[2]}, [r0, :16] @ encoding: [0x9f,0x04,0xe0,0xf4] +@ CHECK: vld1.32 {d16[1]}, [r0, :32] @ encoding: [0xbf,0x08,0xe0,0xf4] + + + vld2.8 {d16[1], d17[1]}, [r0, :16] + vld2.16 {d16[1], d17[1]}, [r0, :32] + vld2.32 {d16[1], d17[1]}, [r0] + vld2.16 {d17[1], d19[1]}, [r0] + vld2.32 {d17[0], d19[0]}, [r0, :64] @ CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xe0,0xf4] - vld2.8 {d16[1], d17[1]}, [r0, :16] -@ CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xe0,0xf4] - vld2.16 {d16[1], d17[1]}, [r0, :32] -@ CHECK: vld2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xe0,0xf4] - vld2.32 {d16[1], d17[1]}, [r0] -@ CHECK: vld2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xe0,0xf4] - vld2.16 {d17[1], d19[1]}, [r0] -@ CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xe0,0xf4] - vld2.32 {d17[0], d19[0]}, [r0, :64] +@ CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xe0,0xf4] +@ CHECK: vld2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xe0,0xf4] +@ CHECK: vld2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xe0,0xf4] +@ CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xe0,0xf4] + + + vld3.8 {d16[1], d17[1], d18[1]}, [r0] + vld3.16 {d16[1], d17[1], d18[1]}, [r0] + vld3.32 {d16[1], d17[1], d18[1]}, [r0] + vld3.16 {d16[1], d18[1], d20[1]}, [r0] + vld3.32 {d17[1], d19[1], d21[1]}, [r0] @ CHECK: vld3.8 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x2f,0x02,0xe0,0xf4] - vld3.8 {d16[1], d17[1], d18[1]}, [r0] -@ CHECK: vld3.16 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x4f,0x06,0xe0,0xf4] - vld3.16 {d16[1], d17[1], d18[1]}, [r0] -@ CHECK: vld3.32 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x8f,0x0a,0xe0,0xf4] - vld3.32 {d16[1], d17[1], d18[1]}, [r0] -@ CHECK: vld3.16 {d16[1], d18[1], d20[1]}, [r0] @ encoding: [0x6f,0x06,0xe0,0xf4] - vld3.16 {d16[1], d18[1], d20[1]}, [r0] -@ CHECK: vld3.32 {d17[1], d19[1], d21[1]}, [r0] @ encoding: [0xcf,0x1a,0xe0,0xf4] - vld3.32 {d17[1], d19[1], d21[1]}, [r0] +@ CHECK: vld3.16 {d16[1], d17[1], d18[1]}, [r0]@ encoding: [0x4f,0x06,0xe0,0xf4] +@ CHECK: vld3.32 {d16[1], d17[1], d18[1]}, [r0]@ encoding: [0x8f,0x0a,0xe0,0xf4] +@ CHECK: vld3.16 {d16[1], d18[1], d20[1]}, [r0]@ encoding: [0x6f,0x06,0xe0,0xf4] +@ CHECK: vld3.32 {d17[1], d19[1], d21[1]}, [r0]@ encoding: [0xcf,0x1a,0xe0,0xf4] + + + vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] + vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] + vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] + vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64] + vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @ CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] @ encoding: [0x3f,0x03,0xe0,0xf4] - vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] -@ CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] @ encoding: [0x4f,0x07,0xe0,0xf4] - vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] -@ CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] @ encoding: [0xaf,0x0b,0xe0,0xf4] - vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] -@ CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64] @ encoding: [0x7f,0x07,0xe0,0xf4] - vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64] -@ CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @ encoding: [0x4f,0x1b,0xe0,0xf4] - vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] +@ CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] @ encoding: [0x4f,0x07,0xe0,0xf4] +@ CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] @ encoding: [0xaf,0x0b,0xe0,0xf4] +@ CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64] @ encoding: [0x7f,0x07,0xe0,0xf4] +@ CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @ encoding: [0x4f,0x1b,0xe0,0xf4] diff --git a/test/MC/ARM/neont2-absdiff-encoding.s b/test/MC/ARM/neont2-absdiff-encoding.s index 2096357..4313483 100644 --- a/test/MC/ARM/neont2-absdiff-encoding.s +++ b/test/MC/ARM/neont2-absdiff-encoding.s @@ -1,86 +1,91 @@ -@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s -@ XFAIL: * -@ NOTE: This currently fails because the ASM parser doesn't parse vabal. +@RUN: llvm-mc -triple thumbv7-unknown-unknown -show-encoding < %s | FileCheck %s .code 16 -@ CHECK: vabd.s8 d16, d16, d17 @ encoding: [0xa1,0x07,0x40,0xef] vabd.s8 d16, d16, d17 -@ CHECK: vabd.s16 d16, d16, d17 @ encoding: [0xa1,0x07,0x50,0xef] vabd.s16 d16, d16, d17 -@ CHECK: vabd.s32 d16, d16, d17 @ encoding: [0xa1,0x07,0x60,0xef] vabd.s32 d16, d16, d17 -@ CHECK: vabd.u8 d16, d16, d17 @ encoding: [0xa1,0x07,0x40,0xff] vabd.u8 d16, d16, d17 -@ CHECK: vabd.u16 d16, d16, d17 @ encoding: [0xa1,0x07,0x50,0xff] vabd.u16 d16, d16, d17 - @ CHECK: vabd.u32 d16, d16, d17 @ encoding: [0xa1,0x07,0x60,0xff] vabd.u32 d16, d16, d17 -@ CHECK: vabd.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x60,0xff] vabd.f32 d16, d16, d17 -@ CHECK: vabd.s8 q8, q8, q9 @ encoding: [0xe2,0x07,0x40,0xef] vabd.s8 q8, q8, q9 -@ CHECK: vabd.s16 q8, q8, q9 @ encoding: [0xe2,0x07,0x50,0xef] vabd.s16 q8, q8, q9 -@ CHECK: vabd.s32 q8, q8, q9 @ encoding: [0xe2,0x07,0x60,0xef] vabd.s32 q8, q8, q9 -@ CHECK: vabd.u8 q8, q8, q9 @ encoding: [0xe2,0x07,0x40,0xff] vabd.u8 q8, q8, q9 -@ CHECK: vabd.u16 q8, q8, q9 @ encoding: [0xe2,0x07,0x50,0xff] vabd.u16 q8, q8, q9 -@ CHECK: vabd.u32 q8, q8, q9 @ encoding: [0xe2,0x07,0x60,0xff] vabd.u32 q8, q8, q9 -@ CHECK: vabd.f32 q8, q8, q9 @ encoding: [0xe2,0x0d,0x60,0xff] vabd.f32 q8, q8, q9 -@ CHECK: vabdl.s8 q8, d16, d17 @ encoding: [0xa1,0x07,0xc0,0xef] +@ CHECK: vabd.s8 d16, d16, d17 @ encoding: [0x40,0xef,0xa1,0x07] +@ CHECK: vabd.s16 d16, d16, d17 @ encoding: [0x50,0xef,0xa1,0x07] +@ CHECK: vabd.s32 d16, d16, d17 @ encoding: [0x60,0xef,0xa1,0x07] +@ CHECK: vabd.u8 d16, d16, d17 @ encoding: [0x40,0xff,0xa1,0x07] +@ CHECK: vabd.u16 d16, d16, d17 @ encoding: [0x50,0xff,0xa1,0x07] +@ CHECK: vabd.u32 d16, d16, d17 @ encoding: [0x60,0xff,0xa1,0x07] +@ CHECK: vabd.f32 d16, d16, d17 @ encoding: [0x60,0xff,0xa1,0x0d] +@ CHECK: vabd.s8 q8, q8, q9 @ encoding: [0x40,0xef,0xe2,0x07] +@ CHECK: vabd.s16 q8, q8, q9 @ encoding: [0x50,0xef,0xe2,0x07] +@ CHECK: vabd.s32 q8, q8, q9 @ encoding: [0x60,0xef,0xe2,0x07] +@ CHECK: vabd.u8 q8, q8, q9 @ encoding: [0x40,0xff,0xe2,0x07] +@ CHECK: vabd.u16 q8, q8, q9 @ encoding: [0x50,0xff,0xe2,0x07] +@ CHECK: vabd.u32 q8, q8, q9 @ encoding: [0x60,0xff,0xe2,0x07] +@ CHECK: vabd.f32 q8, q8, q9 @ encoding: [0x60,0xff,0xe2,0x0d] + + vabdl.s8 q8, d16, d17 -@ CHECK: vabdl.s16 q8, d16, d17 @ encoding: [0xa1,0x07,0xd0,0xef] vabdl.s16 q8, d16, d17 -@ CHECK: vabdl.s32 q8, d16, d17 @ encoding: [0xa1,0x07,0xe0,0xef] vabdl.s32 q8, d16, d17 -@ CHECK: vabdl.u8 q8, d16, d17 @ encoding: [0xa1,0x07,0xc0,0xff] vabdl.u8 q8, d16, d17 -@ CHECK: vabdl.u16 q8, d16, d17 @ encoding: [0xa1,0x07,0xd0,0xff] vabdl.u16 q8, d16, d17 -@ CHECK: vabdl.u32 q8, d16, d17 @ encoding: [0xa1,0x07,0xe0,0xff] vabdl.u32 q8, d16, d17 -@ CHECK: vaba.s8 d16, d18, d17 @ encoding: [0xb1,0x07,0x42,0xef] +@ CHECK: vabdl.s8 q8, d16, d17 @ encoding: [0xc0,0xef,0xa1,0x07] +@ CHECK: vabdl.s16 q8, d16, d17 @ encoding: [0xd0,0xef,0xa1,0x07] +@ CHECK: vabdl.s32 q8, d16, d17 @ encoding: [0xe0,0xef,0xa1,0x07] +@ CHECK: vabdl.u8 q8, d16, d17 @ encoding: [0xc0,0xff,0xa1,0x07] +@ CHECK: vabdl.u16 q8, d16, d17 @ encoding: [0xd0,0xff,0xa1,0x07] +@ CHECK: vabdl.u32 q8, d16, d17 @ encoding: [0xe0,0xff,0xa1,0x07] + + vaba.s8 d16, d18, d17 -@ CHECK: vaba.s16 d16, d18, d17 @ encoding: [0xb1,0x07,0x52,0xef] vaba.s16 d16, d18, d17 -@ CHECK: vaba.s32 d16, d18, d17 @ encoding: [0xb1,0x07,0x62,0xef] vaba.s32 d16, d18, d17 -@ CHECK: vaba.u8 d16, d18, d17 @ encoding: [0xb1,0x07,0x42,0xff] vaba.u8 d16, d18, d17 -@ CHECK: vaba.u16 d16, d18, d17 @ encoding: [0xb1,0x07,0x52,0xff] vaba.u16 d16, d18, d17 -@ CHECK: vaba.u32 d16, d18, d17 @ encoding: [0xb1,0x07,0x62,0xff] vaba.u32 d16, d18, d17 -@ CHECK: vaba.s8 q9, q8, q10 @ encoding: [0xf4,0x27,0x40,0xef] vaba.s8 q9, q8, q10 -@ CHECK: vaba.s16 q9, q8, q10 @ encoding: [0xf4,0x27,0x50,0xef] vaba.s16 q9, q8, q10 -@ CHECK: vaba.s32 q9, q8, q10 @ encoding: [0xf4,0x27,0x60,0xef] vaba.s32 q9, q8, q10 -@ CHECK: vaba.u8 q9, q8, q10 @ encoding: [0xf4,0x27,0x40,0xff] vaba.u8 q9, q8, q10 -@ CHECK: vaba.u16 q9, q8, q10 @ encoding: [0xf4,0x27,0x50,0xff] vaba.u16 q9, q8, q10 -@ CHECK: vaba.u32 q9, q8, q10 @ encoding: [0xf4,0x27,0x60,0xff] vaba.u32 q9, q8, q10 -@ CHECK: vabal.s8 q8, d19, d18 @ encoding: [0xa2,0x05,0xc3,0xef] +@ CHECK: vaba.s8 d16, d18, d17 @ encoding: [0x42,0xef,0xb1,0x07] +@ CHECK: vaba.s16 d16, d18, d17 @ encoding: [0x52,0xef,0xb1,0x07] +@ CHECK: vaba.s32 d16, d18, d17 @ encoding: [0x62,0xef,0xb1,0x07] +@ CHECK: vaba.u8 d16, d18, d17 @ encoding: [0x42,0xff,0xb1,0x07] +@ CHECK: vaba.u16 d16, d18, d17 @ encoding: [0x52,0xff,0xb1,0x07] +@ CHECK: vaba.u32 d16, d18, d17 @ encoding: [0x62,0xff,0xb1,0x07] +@ CHECK: vaba.s8 q9, q8, q10 @ encoding: [0x40,0xef,0xf4,0x27] +@ CHECK: vaba.s16 q9, q8, q10 @ encoding: [0x50,0xef,0xf4,0x27] +@ CHECK: vaba.s32 q9, q8, q10 @ encoding: [0x60,0xef,0xf4,0x27] +@ CHECK: vaba.u8 q9, q8, q10 @ encoding: [0x40,0xff,0xf4,0x27] +@ CHECK: vaba.u16 q9, q8, q10 @ encoding: [0x50,0xff,0xf4,0x27] +@ CHECK: vaba.u32 q9, q8, q10 @ encoding: [0x60,0xff,0xf4,0x27] + + vabal.s8 q8, d19, d18 -@ CHECK: vabal.s16 q8, d19, d18 @ encoding: [0xa2,0x05,0xd3,0xef] vabal.s16 q8, d19, d18 -@ CHECK: vabal.s32 q8, d19, d18 @ encoding: [0xa2,0x05,0xe3,0xef] vabal.s32 q8, d19, d18 -@ CHECK: vabal.u8 q8, d19, d18 @ encoding: [0xa2,0x05,0xc3,0xff] vabal.u8 q8, d19, d18 -@ CHECK: vabal.u16 q8, d19, d18 @ encoding: [0xa2,0x05,0xd3,0xff] vabal.u16 q8, d19, d18 -@ CHECK: vabal.u32 q8, d19, d18 @ encoding: [0xa2,0x05,0xe3,0xff] vabal.u32 q8, d19, d18 +@ CHECK: vabal.s8 q8, d19, d18 @ encoding: [0xc3,0xef,0xa2,0x05] +@ CHECK: vabal.s16 q8, d19, d18 @ encoding: [0xd3,0xef,0xa2,0x05] +@ CHECK: vabal.s32 q8, d19, d18 @ encoding: [0xe3,0xef,0xa2,0x05] +@ CHECK: vabal.u8 q8, d19, d18 @ encoding: [0xc3,0xff,0xa2,0x05] +@ CHECK: vabal.u16 q8, d19, d18 @ encoding: [0xd3,0xff,0xa2,0x05] +@ CHECK: vabal.u32 q8, d19, d18 @ encoding: [0xe3,0xff,0xa2,0x05] + diff --git a/test/MC/ARM/neont2-bitcount-encoding.s b/test/MC/ARM/neont2-bitcount-encoding.s index 4280cbd..bd525f1 100644 --- a/test/MC/ARM/neont2-bitcount-encoding.s +++ b/test/MC/ARM/neont2-bitcount-encoding.s @@ -1,34 +1,38 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s -@ XFAIL: * .code 16 -@ CHECK: vcnt.8 d16, d16 @ encoding: [0x20,0x05,0xf0,0xff] vcnt.8 d16, d16 -@ CHECK: vcnt.8 q8, q8 @ encoding: [0x60,0x05,0xf0,0xff] vcnt.8 q8, q8 -@ CHECK: vclz.i8 d16, d16 @ encoding: [0xa0,0x04,0xf0,0xff] + +@ CHECK: vcnt.8 d16, d16 @ encoding: [0xf0,0xff,0x20,0x05] +@ CHECK: vcnt.8 q8, q8 @ encoding: [0xf0,0xff,0x60,0x05] + vclz.i8 d16, d16 -@ CHECK: vclz.i16 d16, d16 @ encoding: [0xa0,0x04,0xf4,0xff] vclz.i16 d16, d16 -@ CHECK: vclz.i32 d16, d16 @ encoding: [0xa0,0x04,0xf8,0xff] vclz.i32 d16, d16 -@ CHECK: vclz.i8 q8, q8 @ encoding: [0xe0,0x04,0xf0,0xff] vclz.i8 q8, q8 -@ CHECK: vclz.i16 q8, q8 @ encoding: [0xe0,0x04,0xf4,0xff] vclz.i16 q8, q8 -@ CHECK: vclz.i32 q8, q8 @ encoding: [0xe0,0x04,0xf8,0xff] vclz.i32 q8, q8 -@ CHECK: vcls.s8 d16, d16 @ encoding: [0x20,0x04,0xf0,0xff] + +@ CHECK: vclz.i8 d16, d16 @ encoding: [0xf0,0xff,0xa0,0x04] +@ CHECK: vclz.i16 d16, d16 @ encoding: [0xf4,0xff,0xa0,0x04] +@ CHECK: vclz.i32 d16, d16 @ encoding: [0xf8,0xff,0xa0,0x04] +@ CHECK: vclz.i8 q8, q8 @ encoding: [0xf0,0xff,0xe0,0x04] +@ CHECK: vclz.i16 q8, q8 @ encoding: [0xf4,0xff,0xe0,0x04] +@ CHECK: vclz.i32 q8, q8 @ encoding: [0xf8,0xff,0xe0,0x04] + vcls.s8 d16, d16 -@ CHECK: vcls.s16 d16, d16 @ encoding: [0x20,0x04,0xf4,0xff] vcls.s16 d16, d16 -@ CHECK: vcls.s32 d16, d16 @ encoding: [0x20,0x04,0xf8,0xff] vcls.s32 d16, d16 -@ CHECK: vcls.s8 q8, q8 @ encoding: [0x60,0x04,0xf0,0xff] vcls.s8 q8, q8 -@ CHECK: vcls.s16 q8, q8 @ encoding: [0x60,0x04,0xf4,0xff] vcls.s16 q8, q8 -@ CHECK: vcls.s32 q8, q8 @ encoding: [0x60,0x04,0xf8,0xff] vcls.s32 q8, q8 +@ CHECK: vcls.s8 d16, d16 @ encoding: [0xf0,0xff,0x20,0x04] +@ CHECK: vcls.s16 d16, d16 @ encoding: [0xf4,0xff,0x20,0x04] +@ CHECK: vcls.s32 d16, d16 @ encoding: [0xf8,0xff,0x20,0x04] +@ CHECK: vcls.s8 q8, q8 @ encoding: [0xf0,0xff,0x60,0x04] +@ CHECK: vcls.s16 q8, q8 @ encoding: [0xf4,0xff,0x60,0x04] +@ CHECK: vcls.s32 q8, q8 @ encoding: [0xf8,0xff,0x60,0x04] + diff --git a/test/MC/ARM/neont2-bitwise-encoding.s b/test/MC/ARM/neont2-bitwise-encoding.s index 3acd7a8..175873b 100644 --- a/test/MC/ARM/neont2-bitwise-encoding.s +++ b/test/MC/ARM/neont2-bitwise-encoding.s @@ -1,49 +1,55 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s -@ XFAIL: * .code 16 -@ CHECK: vand d16, d17, d16 @ encoding: [0xb0,0x01,0x41,0xef] vand d16, d17, d16 -@ CHECK: vand q8, q8, q9 @ encoding: [0xf2,0x01,0x40,0xef] vand q8, q8, q9 -@ CHECK: veor d16, d17, d16 @ encoding: [0xb0,0x01,0x41,0xff] +@ CHECK: vand d16, d17, d16 @ encoding: [0x41,0xef,0xb0,0x01] +@ CHECK: vand q8, q8, q9 @ encoding: [0x40,0xef,0xf2,0x01] + veor d16, d17, d16 -@ CHECK: veor q8, q8, q9 @ encoding: [0xf2,0x01,0x40,0xff] veor q8, q8, q9 -@ CHECK: vorr d16, d17, d16 @ encoding: [0xb0,0x01,0x61,0xef] +@ CHECK: veor d16, d17, d16 @ encoding: [0x41,0xff,0xb0,0x01] +@ CHECK: veor q8, q8, q9 @ encoding: [0x40,0xff,0xf2,0x01] + + vorr d16, d17, d16 -@ CHECK: vorr q8, q8, q9 @ encoding: [0xf2,0x01,0x60,0xef] vorr q8, q8, q9 -@ CHECK: vorr.i32 d16, #0x1000000 @ encoding: [0x11,0x07,0xc0,0xef] - vorr.i32 d16, #0x1000000 -@ CHECK: vorr.i32 q8, #0x1000000 @ encoding: [0x51,0x07,0xc0,0xef] - vorr.i32 q8, #0x1000000 -@ CHECK: vorr.i32 q8, #0x0 @ encoding: [0x50,0x01,0xc0,0xef] - vorr.i32 q8, #0x0 - -@ CHECK: vbic d16, d17, d16 @ encoding: [0xb0,0x01,0x51,0xef] +@ vorr.i32 d16, #0x1000000 +@ vorr.i32 q8, #0x1000000 +@ vorr.i32 q8, #0x0 + +@ CHECK: vorr d16, d17, d16 @ encoding: [0x61,0xef,0xb0,0x01] +@ CHECK: vorr q8, q8, q9 @ encoding: [0x60,0xef,0xf2,0x01] + + vbic d16, d17, d16 -@ CHECK: vbic q8, q8, q9 @ encoding: [0xf2,0x01,0x50,0xef] vbic q8, q8, q9 -@ CHECK: vbic.i32 d16, #0xFF000000 @ encoding: [0x3f,0x07,0xc7,0xff] - vbic.i32 d16, #0xFF000000 -@ CHECK: vbic.i32 q8, #0xFF000000 @ encoding: [0x7f,0x07,0xc7,0xff] - vbic.i32 q8, #0xFF000000 +@ vbic.i32 d16, #0xFF000000 +@ vbic.i32 q8, #0xFF000000 + +@ CHECK: vbic d16, d17, d16 @ encoding: [0x51,0xef,0xb0,0x01] +@ CHECK: vbic q8, q8, q9 @ encoding: [0x50,0xef,0xf2,0x01] + -@ CHECK: vorn d16, d17, d16 @ encoding: [0xb0,0x01,0x71,0xef] vorn d16, d17, d16 -@ CHECK: vorn q8, q8, q9 @ encoding: [0xf2,0x01,0x70,0xef] vorn q8, q8, q9 -@ CHECK: vmvn d16, d16 @ encoding: [0xa0,0x05,0xf0,0xff] +@ CHECK: vorn d16, d17, d16 @ encoding: [0x71,0xef,0xb0,0x01] +@ CHECK: vorn q8, q8, q9 @ encoding: [0x70,0xef,0xf2,0x01] + + vmvn d16, d16 -@ CHECK: vmvn q8, q8 @ encoding: [0xe0,0x05,0xf0,0xff] vmvn q8, q8 -@ CHECK: vbsl d18, d17, d16 @ encoding: [0xb0,0x21,0x51,0xff] +@ CHECK: vmvn d16, d16 @ encoding: [0xf0,0xff,0xa0,0x05] +@ CHECK: vmvn q8, q8 @ encoding: [0xf0,0xff,0xe0,0x05] + + vbsl d18, d17, d16 -@ CHECK: vbsl q8, q10, q9 @ encoding: [0xf2,0x01,0x54,0xff] vbsl q8, q10, q9 + +@ CHECK: vbsl d18, d17, d16 @ encoding: [0x51,0xff,0xb0,0x21] +@ CHECK: vbsl q8, q10, q9 @ encoding: [0x54,0xff,0xf2,0x01] diff --git a/test/MC/ARM/neont2-dup-encoding.s b/test/MC/ARM/neont2-dup-encoding.s index da6e78f..bf25d70 100644 --- a/test/MC/ARM/neont2-dup-encoding.s +++ b/test/MC/ARM/neont2-dup-encoding.s @@ -1,29 +1,43 @@ -@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s -@ XFAIL: * +@RUN: llvm-mc -triple thumbv7-unknown-unknown -show-encoding < %s | FileCheck %s .code 16 -@ CHECK: vdup.8 d16, r0 @ encoding: [0x90,0x0b,0xc0,0xee] - vdup.8 d16, r0 -@ CHECK: vdup.16 d16, r0 @ encoding: [0xb0,0x0b,0x80,0xee] - vdup.16 d16, r0 -@ CHECK: vdup.32 d16, r0 @ encoding: [0x90,0x0b,0x80,0xee] - vdup.32 d16, r0 -@ CHECK: vdup.8 q8, r0 @ encoding: [0x90,0x0b,0xe0,0xee] - vdup.8 q8, r0 -@ CHECK: vdup.16 q8, r0 @ encoding: [0xb0,0x0b,0xa0,0xee] - vdup.16 q8, r0 -@ CHECK: vdup.32 q8, r0 @ encoding: [0x90,0x0b,0xa0,0xee] - vdup.32 q8, r0 -@ CHECK: vdup.8 d16, d16[1] @ encoding: [0x20,0x0c,0xf3,0xff] - vdup.8 d16, d16[1] -@ CHECK: vdup.16 d16, d16[1] @ encoding: [0x20,0x0c,0xf6,0xff] - vdup.16 d16, d16[1] -@ CHECK: vdup.32 d16, d16[1] @ encoding: [0x20,0x0c,0xfc,0xff] - vdup.32 d16, d16[1] -@ CHECK: vdup.8 q8, d16[1] @ encoding: [0x60,0x0c,0xf3,0xff] - vdup.8 q8, d16[1] -@ CHECK: vdup.16 q8, d16[1] @ encoding: [0x60,0x0c,0xf6,0xff] - vdup.16 q8, d16[1] -@ CHECK: vdup.32 q8, d16[1] @ encoding: [0x60,0x0c,0xfc,0xff] - vdup.32 q8, d16[1] + vdup.8 d16, r1 + vdup.16 d15, r2 + vdup.32 d14, r3 + vdup.8 q9, r4 + vdup.16 q8, r5 + vdup.32 q7, r6 + +@ CHECK: vdup.8 d16, r1 @ encoding: [0xc0,0xee,0x90,0x1b] +@ CHECK: vdup.16 d15, r2 @ encoding: [0x8f,0xee,0x30,0x2b] +@ CHECK: vdup.32 d14, r3 @ encoding: [0x8e,0xee,0x10,0x3b] +@ CHECK: vdup.8 q9, r4 @ encoding: [0xe2,0xee,0x90,0x4b] +@ CHECK: vdup.16 q8, r5 @ encoding: [0xa0,0xee,0xb0,0x5b] +@ CHECK: vdup.32 q7, r6 @ encoding: [0xae,0xee,0x10,0x6b] + + vdup.8 d16, d11[0] + vdup.16 d17, d12[0] + vdup.32 d18, d13[0] + vdup.8 q3, d10[0] + vdup.16 q9, d9[0] + vdup.32 q8, d8[0] + vdup.8 d16, d11[1] + vdup.16 d17, d12[1] + vdup.32 d18, d13[1] + vdup.8 q3, d10[1] + vdup.16 q9, d9[1] + vdup.32 q8, d8[1] + +@ CHECK: vdup.8 d16, d11[0] @ encoding: [0xf1,0xff,0x0b,0x0c] +@ CHECK: vdup.16 d17, d12[0] @ encoding: [0xf2,0xff,0x0c,0x1c] +@ CHECK: vdup.32 d18, d13[0] @ encoding: [0xf4,0xff,0x0d,0x2c] +@ CHECK: vdup.8 q3, d10[0] @ encoding: [0xb1,0xff,0x4a,0x6c] +@ CHECK: vdup.16 q9, d9[0] @ encoding: [0xf2,0xff,0x49,0x2c] +@ CHECK: vdup.32 q8, d8[0] @ encoding: [0xf4,0xff,0x48,0x0c] +@ CHECK: vdup.8 d16, d11[1] @ encoding: [0xf3,0xff,0x0b,0x0c] +@ CHECK: vdup.16 d17, d12[1] @ encoding: [0xf6,0xff,0x0c,0x1c] +@ CHECK: vdup.32 d18, d13[1] @ encoding: [0xfc,0xff,0x0d,0x2c] +@ CHECK: vdup.8 q3, d10[1] @ encoding: [0xb3,0xff,0x4a,0x6c] +@ CHECK: vdup.16 q9, d9[1] @ encoding: [0xf6,0xff,0x49,0x2c] +@ CHECK: vdup.32 q8, d8[1] @ encoding: [0xfc,0xff,0x48,0x0c] diff --git a/test/MC/ARM/neont2-mul-accum-encoding.s b/test/MC/ARM/neont2-mul-accum-encoding.s index e21c67d..be4bf79 100644 --- a/test/MC/ARM/neont2-mul-accum-encoding.s +++ b/test/MC/ARM/neont2-mul-accum-encoding.s @@ -1,69 +1,84 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s -@ XFAIL: * .code 16 -@ CHECK: vmla.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xef] vmla.i8 d16, d18, d17 -@ CHECK: vmla.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xef] vmla.i16 d16, d18, d17 -@ CHECK: vmla.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xef] vmla.i32 d16, d18, d17 -@ CHECK: vmla.f32 d16, d18, d17 @ encoding: [0xb1,0x0d,0x42,0xef] vmla.f32 d16, d18, d17 -@ CHECK: vmla.i8 q9, q8, q10 @ encoding: [0xe4,0x29,0x40,0xef] vmla.i8 q9, q8, q10 -@ CHECK: vmla.i16 q9, q8, q10 @ encoding: [0xe4,0x29,0x50,0xef] vmla.i16 q9, q8, q10 -@ CHECK: vmla.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xef] vmla.i32 q9, q8, q10 -@ CHECK: vmla.f32 q9, q8, q10 @ encoding: [0xf4,0x2d,0x40,0xef] vmla.f32 q9, q8, q10 -@ CHECK: vmlal.s8 q8, d19, d18 @ encoding: [0xa2,0x08,0xc3,0xef] + +@ CHECK: vmla.i8 d16, d18, d17 @ encoding: [0x42,0xef,0xa1,0x09] +@ CHECK: vmla.i16 d16, d18, d17 @ encoding: [0x52,0xef,0xa1,0x09] +@ CHECK: vmla.i32 d16, d18, d17 @ encoding: [0x62,0xef,0xa1,0x09] +@ CHECK: vmla.f32 d16, d18, d17 @ encoding: [0x42,0xef,0xb1,0x0d] +@ CHECK: vmla.i8 q9, q8, q10 @ encoding: [0x40,0xef,0xe4,0x29] +@ CHECK: vmla.i16 q9, q8, q10 @ encoding: [0x50,0xef,0xe4,0x29] +@ CHECK: vmla.i32 q9, q8, q10 @ encoding: [0x60,0xef,0xe4,0x29] +@ CHECK: vmla.f32 q9, q8, q10 @ encoding: [0x40,0xef,0xf4,0x2d] + + vmlal.s8 q8, d19, d18 -@ CHECK: vmlal.s16 q8, d19, d18 @ encoding: [0xa2,0x08,0xd3,0xef] vmlal.s16 q8, d19, d18 -@ CHECK: vmlal.s32 q8, d19, d18 @ encoding: [0xa2,0x08,0xe3,0xef] vmlal.s32 q8, d19, d18 -@ CHECK: vmlal.u8 q8, d19, d18 @ encoding: [0xa2,0x08,0xc3,0xff] vmlal.u8 q8, d19, d18 -@ CHECK: vmlal.u16 q8, d19, d18 @ encoding: [0xa2,0x08,0xd3,0xff] vmlal.u16 q8, d19, d18 -@ CHECK: vmlal.u32 q8, d19, d18 @ encoding: [0xa2,0x08,0xe3,0xff] vmlal.u32 q8, d19, d18 -@ CHECK: vqdmlal.s16 q8, d19, d18 @ encoding: [0xa2,0x09,0xd3,0xef] + +@ CHECK: vmlal.s8 q8, d19, d18 @ encoding: [0xc3,0xef,0xa2,0x08] +@ CHECK: vmlal.s16 q8, d19, d18 @ encoding: [0xd3,0xef,0xa2,0x08] +@ CHECK: vmlal.s32 q8, d19, d18 @ encoding: [0xe3,0xef,0xa2,0x08] +@ CHECK: vmlal.u8 q8, d19, d18 @ encoding: [0xc3,0xff,0xa2,0x08] +@ CHECK: vmlal.u16 q8, d19, d18 @ encoding: [0xd3,0xff,0xa2,0x08] +@ CHECK: vmlal.u32 q8, d19, d18 @ encoding: [0xe3,0xff,0xa2,0x08] + + vqdmlal.s16 q8, d19, d18 -@ CHECK: vqdmlal.s32 q8, d19, d18 @ encoding: [0xa2,0x09,0xe3,0xef] vqdmlal.s32 q8, d19, d18 -@ CHECK: vmls.i8 d16, d18, d17 @ encoding: [0xa1,0x09,0x42,0xff] + +@ CHECK: vqdmlal.s16 q8, d19, d18 @ encoding: [0xd3,0xef,0xa2,0x09] +@ CHECK: vqdmlal.s32 q8, d19, d18 @ encoding: [0xe3,0xef,0xa2,0x09] + + vmls.i8 d16, d18, d17 -@ CHECK: vmls.i16 d16, d18, d17 @ encoding: [0xa1,0x09,0x52,0xff] vmls.i16 d16, d18, d17 -@ CHECK: vmls.i32 d16, d18, d17 @ encoding: [0xa1,0x09,0x62,0xff] vmls.i32 d16, d18, d17 -@ CHECK: vmls.f32 d16, d18, d17 @ encoding: [0xb1,0x0d,0x62,0xef] vmls.f32 d16, d18, d17 -@ CHECK: vmls.i8 q9, q8, q10 @ encoding: [0xe4,0x29,0x40,0xff] vmls.i8 q9, q8, q10 -@ CHECK: vmls.i16 q9, q8, q10 @ encoding: [0xe4,0x29,0x50,0xff] vmls.i16 q9, q8, q10 -@ CHECK: vmls.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xff] vmls.i32 q9, q8, q10 -@ CHECK: vmls.f32 q9, q8, q10 @ encoding: [0xf4,0x2d,0x60,0xef] vmls.f32 q9, q8, q10 -@ CHECK: vmlsl.s8 q8, d19, d18 @ encoding: [0xa2,0x0a,0xc3,0xef] + +@ CHECK: vmls.i8 d16, d18, d17 @ encoding: [0x42,0xff,0xa1,0x09] +@ CHECK: vmls.i16 d16, d18, d17 @ encoding: [0x52,0xff,0xa1,0x09] +@ CHECK: vmls.i32 d16, d18, d17 @ encoding: [0x62,0xff,0xa1,0x09] +@ CHECK: vmls.f32 d16, d18, d17 @ encoding: [0x62,0xef,0xb1,0x0d] +@ CHECK: vmls.i8 q9, q8, q10 @ encoding: [0x40,0xff,0xe4,0x29] +@ CHECK: vmls.i16 q9, q8, q10 @ encoding: [0x50,0xff,0xe4,0x29] +@ CHECK: vmls.i32 q9, q8, q10 @ encoding: [0x60,0xff,0xe4,0x29] +@ CHECK: vmls.f32 q9, q8, q10 @ encoding: [0x60,0xef,0xf4,0x2d] + + vmlsl.s8 q8, d19, d18 -@ CHECK: vmlsl.s16 q8, d19, d18 @ encoding: [0xa2,0x0a,0xd3,0xef] vmlsl.s16 q8, d19, d18 -@ CHECK: vmlsl.s32 q8, d19, d18 @ encoding: [0xa2,0x0a,0xe3,0xef] vmlsl.s32 q8, d19, d18 -@ CHECK: vmlsl.u8 q8, d19, d18 @ encoding: [0xa2,0x0a,0xc3,0xff] vmlsl.u8 q8, d19, d18 -@ CHECK: vmlsl.u16 q8, d19, d18 @ encoding: [0xa2,0x0a,0xd3,0xff] vmlsl.u16 q8, d19, d18 -@ CHECK: vmlsl.u32 q8, d19, d18 @ encoding: [0xa2,0x0a,0xe3,0xff] vmlsl.u32 q8, d19, d18 -@ CHECK: vqdmlsl.s16 q8, d19, d18 @ encoding: [0xa2,0x0b,0xd3,0xef] + +@ CHECK: vmlsl.s8 q8, d19, d18 @ encoding: [0xc3,0xef,0xa2,0x0a] +@ CHECK: vmlsl.s16 q8, d19, d18 @ encoding: [0xd3,0xef,0xa2,0x0a] +@ CHECK: vmlsl.s32 q8, d19, d18 @ encoding: [0xe3,0xef,0xa2,0x0a] +@ CHECK: vmlsl.u8 q8, d19, d18 @ encoding: [0xc3,0xff,0xa2,0x0a] +@ CHECK: vmlsl.u16 q8, d19, d18 @ encoding: [0xd3,0xff,0xa2,0x0a] +@ CHECK: vmlsl.u32 q8, d19, d18 @ encoding: [0xe3,0xff,0xa2,0x0a] + + vqdmlsl.s16 q8, d19, d18 -@ CHECK: vqdmlsl.s32 q8, d19, d18 @ encoding: [0xa2,0x0b,0xe3,0xef] vqdmlsl.s32 q8, d19, d18 + +@ CHECK: vqdmlsl.s16 q8, d19, d18 @ encoding: [0xd3,0xef,0xa2,0x0b] +@ CHECK: vqdmlsl.s32 q8, d19, d18 @ encoding: [0xe3,0xef,0xa2,0x0b] diff --git a/test/MC/ARM/neont2-pairwise-encoding.s b/test/MC/ARM/neont2-pairwise-encoding.s index ef90922..29aac36 100644 --- a/test/MC/ARM/neont2-pairwise-encoding.s +++ b/test/MC/ARM/neont2-pairwise-encoding.s @@ -1,89 +1,100 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s -@ XFAIL: * .code 16 + vpadd.i8 d1, d5, d11 + vpadd.i16 d13, d2, d12 + vpadd.i32 d14, d1, d13 + vpadd.f32 d19, d16, d14 -@ CHECK: vpadd.i8 d16, d17, d16 @ encoding: [0xb0,0x0b,0x41,0xef] - vpadd.i8 d16, d17, d16 -@ CHECK: vpadd.i16 d16, d17, d16 @ encoding: [0xb0,0x0b,0x51,0xef] - vpadd.i16 d16, d17, d16 -@ CHECK: vpadd.i32 d16, d17, d16 @ encoding: [0xb0,0x0b,0x61,0xef] - vpadd.i32 d16, d17, d16 -@ CHECK: vpadd.f32 d16, d16, d17 @ encoding: [0xa1,0x0d,0x40,0xff] - vpadd.f32 d16, d16, d17 -@ CHECK: vpaddl.s8 d16, d16 @ encoding: [0x20,0x02,0xf0,0xff] - vpaddl.s8 d16, d16 -@ CHECK: vpaddl.s16 d16, d16 @ encoding: [0x20,0x02,0xf4,0xff] - vpaddl.s16 d16, d16 -@ CHECK: vpaddl.s32 d16, d16 @ encoding: [0x20,0x02,0xf8,0xff] - vpaddl.s32 d16, d16 -@ CHECK: vpaddl.u8 d16, d16 @ encoding: [0xa0,0x02,0xf0,0xff] - vpaddl.u8 d16, d16 -@ CHECK: vpaddl.u16 d16, d16 @ encoding: [0xa0,0x02,0xf4,0xff] - vpaddl.u16 d16, d16 -@ CHECK: vpaddl.u32 d16, d16 @ encoding: [0xa0,0x02,0xf8,0xff] - vpaddl.u32 d16, d16 -@ CHECK: vpaddl.s8 q8, q8 @ encoding: [0x60,0x02,0xf0,0xff] - vpaddl.s8 q8, q8 -@ CHECK: vpaddl.s16 q8, q8 @ encoding: [0x60,0x02,0xf4,0xff] - vpaddl.s16 q8, q8 -@ CHECK: vpaddl.s32 q8, q8 @ encoding: [0x60,0x02,0xf8,0xff] - vpaddl.s32 q8, q8 -@ CHECK: vpaddl.u8 q8, q8 @ encoding: [0xe0,0x02,0xf0,0xff] - vpaddl.u8 q8, q8 -@ CHECK: vpaddl.u16 q8, q8 @ encoding: [0xe0,0x02,0xf4,0xff] - vpaddl.u16 q8, q8 -@ CHECK: vpaddl.u32 q8, q8 @ encoding: [0xe0,0x02,0xf8,0xff] - vpaddl.u32 q8, q8 -@ CHECK: vpadal.s8 d16, d17 @ encoding: [0x21,0x06,0xf0,0xff] - vpadal.s8 d16, d17 -@ CHECK: vpadal.s16 d16, d17 @ encoding: [0x21,0x06,0xf4,0xff] - vpadal.s16 d16, d17 -@ CHECK: vpadal.s32 d16, d17 @ encoding: [0x21,0x06,0xf8,0xff] - vpadal.s32 d16, d17 -@ CHECK: vpadal.u8 d16, d17 @ encoding: [0xa1,0x06,0xf0,0xff] - vpadal.u8 d16, d17 -@ CHECK: vpadal.u16 d16, d17 @ encoding: [0xa1,0x06,0xf4,0xff] - vpadal.u16 d16, d17 -@ CHECK: vpadal.u32 d16, d17 @ encoding: [0xa1,0x06,0xf8,0xff] - vpadal.u32 d16, d17 -@ CHECK: vpadal.s8 q9, q8 @ encoding: [0x60,0x26,0xf0,0xff] - vpadal.s8 q9, q8 -@ CHECK: vpadal.s16 q9, q8 @ encoding: [0x60,0x26,0xf4,0xff] - vpadal.s16 q9, q8 -@ CHECK: vpadal.s32 q9, q8 @ encoding: [0x60,0x26,0xf8,0xff] - vpadal.s32 q9, q8 -@ CHECK: vpadal.u8 q9, q8 @ encoding: [0xe0,0x26,0xf0,0xff] - vpadal.u8 q9, q8 -@ CHECK: vpadal.u16 q9, q8 @ encoding: [0xe0,0x26,0xf4,0xff] - vpadal.u16 q9, q8 -@ CHECK: vpadal.u32 q9, q8 @ encoding: [0xe0,0x26,0xf8,0xff] - vpadal.u32 q9, q8 -@ CHECK: vpmin.s8 d16, d16, d17 @ encoding: [0xb1,0x0a,0x40,0xef] - vpmin.s8 d16, d16, d17 -@ CHECK: vpmin.s16 d16, d16, d17 @ encoding: [0xb1,0x0a,0x50,0xef] - vpmin.s16 d16, d16, d17 -@ CHECK: vpmin.s32 d16, d16, d17 @ encoding: [0xb1,0x0a,0x60,0xef] - vpmin.s32 d16, d16, d17 -@ CHECK: vpmin.u8 d16, d16, d17 @ encoding: [0xb1,0x0a,0x40,0xff] - vpmin.u8 d16, d16, d17 -@ CHECK: vpmin.u16 d16, d16, d17 @ encoding: [0xb1,0x0a,0x50,0xff] - vpmin.u16 d16, d16, d17 -@ CHECK: vpmin.u32 d16, d16, d17 @ encoding: [0xb1,0x0a,0x60,0xff] - vpmin.u32 d16, d16, d17 -@ CHECK: vpmin.f32 d16, d16, d17 @ encoding: [0xa1,0x0f,0x60,0xff] - vpmin.f32 d16, d16, d17 -@ CHECK: vpmax.s8 d16, d16, d17 @ encoding: [0xa1,0x0a,0x40,0xef] - vpmax.s8 d16, d16, d17 -@ CHECK: vpmax.s16 d16, d16, d17 @ encoding: [0xa1,0x0a,0x50,0xef] - vpmax.s16 d16, d16, d17 -@ CHECK: vpmax.s32 d16, d16, d17 @ encoding: [0xa1,0x0a,0x60,0xef] - vpmax.s32 d16, d16, d17 -@ CHECK: vpmax.u8 d16, d16, d17 @ encoding: [0xa1,0x0a,0x40,0xff] - vpmax.u8 d16, d16, d17 -@ CHECK: vpmax.u16 d16, d16, d17 @ encoding: [0xa1,0x0a,0x50,0xff] - vpmax.u16 d16, d16, d17 -@ CHECK: vpmax.u32 d16, d16, d17 @ encoding: [0xa1,0x0a,0x60,0xff] - vpmax.u32 d16, d16, d17 -@ CHECK: vpmax.f32 d16, d16, d17 @ encoding: [0xa1,0x0f,0x40,0xff] - vpmax.f32 d16, d16, d17 +@ CHECK: vpadd.i8 d1, d5, d11 @ encoding: [0x05,0xef,0x1b,0x1b] +@ CHECK: vpadd.i16 d13, d2, d12 @ encoding: [0x12,0xef,0x1c,0xdb] +@ CHECK: vpadd.i32 d14, d1, d13 @ encoding: [0x21,0xef,0x1d,0xeb] +@ CHECK: vpadd.f32 d19, d16, d14 @ encoding: [0x40,0xff,0x8e,0x3d] + + + vpaddl.s8 d7, d10 + vpaddl.s16 d8, d11 + vpaddl.s32 d9, d12 + vpaddl.u8 d0, d13 + vpaddl.u16 d5, d14 + vpaddl.u32 d6, d15 + vpaddl.s8 q4, q7 + vpaddl.s16 q5, q6 + vpaddl.s32 q6, q5 + vpaddl.u8 q7, q4 + vpaddl.u16 q8, q3 + vpaddl.u32 q9, q2 + +@ CHECK: vpaddl.s8 d7, d10 @ encoding: [0xb0,0xff,0x0a,0x72] +@ CHECK: vpaddl.s16 d8, d11 @ encoding: [0xb4,0xff,0x0b,0x82] +@ CHECK: vpaddl.s32 d9, d12 @ encoding: [0xb8,0xff,0x0c,0x92] +@ CHECK: vpaddl.u8 d0, d13 @ encoding: [0xb0,0xff,0x8d,0x02] +@ CHECK: vpaddl.u16 d5, d14 @ encoding: [0xb4,0xff,0x8e,0x52] +@ CHECK: vpaddl.u32 d6, d15 @ encoding: [0xb8,0xff,0x8f,0x62] +@ CHECK: vpaddl.s8 q4, q7 @ encoding: [0xb0,0xff,0x4e,0x82] +@ CHECK: vpaddl.s16 q5, q6 @ encoding: [0xb4,0xff,0x4c,0xa2] +@ CHECK: vpaddl.s32 q6, q5 @ encoding: [0xb8,0xff,0x4a,0xc2] +@ CHECK: vpaddl.u8 q7, q4 @ encoding: [0xb0,0xff,0xc8,0xe2] +@ CHECK: vpaddl.u16 q8, q3 @ encoding: [0xf4,0xff,0xc6,0x02] +@ CHECK: vpaddl.u32 q9, q2 @ encoding: [0xf8,0xff,0xc4,0x22] + + + vpadal.s8 d16, d4 + vpadal.s16 d20, d9 + vpadal.s32 d18, d1 + vpadal.u8 d14, d25 + vpadal.u16 d12, d6 + vpadal.u32 d11, d7 + vpadal.s8 q4, q10 + vpadal.s16 q5, q11 + vpadal.s32 q6, q12 + vpadal.u8 q7, q13 + vpadal.u16 q8, q14 + vpadal.u32 q9, q15 + +@ CHECK: vpadal.s8 d16, d4 @ encoding: [0xf0,0xff,0x04,0x06] +@ CHECK: vpadal.s16 d20, d9 @ encoding: [0xf4,0xff,0x09,0x46] +@ CHECK: vpadal.s32 d18, d1 @ encoding: [0xf8,0xff,0x01,0x26] +@ CHECK: vpadal.u8 d14, d25 @ encoding: [0xb0,0xff,0xa9,0xe6] +@ CHECK: vpadal.u16 d12, d6 @ encoding: [0xb4,0xff,0x86,0xc6] +@ CHECK: vpadal.u32 d11, d7 @ encoding: [0xb8,0xff,0x87,0xb6] +@ CHECK: vpadal.s8 q4, q10 @ encoding: [0xb0,0xff,0x64,0x86] +@ CHECK: vpadal.s16 q5, q11 @ encoding: [0xb4,0xff,0x66,0xa6] +@ CHECK: vpadal.s32 q6, q12 @ encoding: [0xb8,0xff,0x68,0xc6] +@ CHECK: vpadal.u8 q7, q13 @ encoding: [0xb0,0xff,0xea,0xe6] +@ CHECK: vpadal.u16 q8, q14 @ encoding: [0xf4,0xff,0xec,0x06] +@ CHECK: vpadal.u32 q9, q15 @ encoding: [0xf8,0xff,0xee,0x26] + + + vpmin.s8 d16, d29, d10 + vpmin.s16 d17, d28, d11 + vpmin.s32 d18, d27, d12 + vpmin.u8 d19, d26, d13 + vpmin.u16 d20, d25, d14 + vpmin.u32 d21, d24, d15 + vpmin.f32 d22, d23, d16 + +@ CHECK: vpmin.s8 d16, d29, d10 @ encoding: [0x4d,0xef,0x9a,0x0a] +@ CHECK: vpmin.s16 d17, d28, d11 @ encoding: [0x5c,0xef,0x9b,0x1a] +@ CHECK: vpmin.s32 d18, d27, d12 @ encoding: [0x6b,0xef,0x9c,0x2a] +@ CHECK: vpmin.u8 d19, d26, d13 @ encoding: [0x4a,0xff,0x9d,0x3a] +@ CHECK: vpmin.u16 d20, d25, d14 @ encoding: [0x59,0xff,0x9e,0x4a] +@ CHECK: vpmin.u32 d21, d24, d15 @ encoding: [0x68,0xff,0x9f,0x5a] +@ CHECK: vpmin.f32 d22, d23, d16 @ encoding: [0x67,0xff,0xa0,0x6f] + + + vpmax.s8 d3, d20, d17 + vpmax.s16 d4, d21, d16 + vpmax.s32 d5, d22, d15 + vpmax.u8 d6, d23, d14 + vpmax.u16 d7, d24, d13 + vpmax.u32 d8, d25, d12 + vpmax.f32 d9, d26, d11 + +@ CHECK: vpmax.s8 d3, d20, d17 @ encoding: [0x04,0xef,0xa1,0x3a] +@ CHECK: vpmax.s16 d4, d21, d16 @ encoding: [0x15,0xef,0xa0,0x4a] +@ CHECK: vpmax.s32 d5, d22, d15 @ encoding: [0x26,0xef,0x8f,0x5a] +@ CHECK: vpmax.u8 d6, d23, d14 @ encoding: [0x07,0xff,0x8e,0x6a] +@ CHECK: vpmax.u16 d7, d24, d13 @ encoding: [0x18,0xff,0x8d,0x7a] +@ CHECK: vpmax.u32 d8, d25, d12 @ encoding: [0x29,0xff,0x8c,0x8a] +@ CHECK: vpmax.f32 d9, d26, d11 @ encoding: [0x0a,0xff,0x8b,0x9f] diff --git a/test/MC/ARM/nop-armv4-padding.s b/test/MC/ARM/nop-armv4-padding.s new file mode 100644 index 0000000..8f646db --- /dev/null +++ b/test/MC/ARM/nop-armv4-padding.s @@ -0,0 +1,10 @@ +@ RUN: llvm-mc -triple armv4-apple-darwin %s -filetype=obj -o %t.obj +@ RUN: macho-dump --dump-section-data < %t.obj > %t.dump +@ RUN: FileCheck %s < %t.dump + +x: + add r0, r1, r2 + .align 4 + add r0, r1, r2 + +@ CHECK: ('_section_data', '020081e0 00001a0e 00001a0e 00001a0e 020081e0') diff --git a/test/MC/ARM/nop-armv6t2-padding.s b/test/MC/ARM/nop-armv6t2-padding.s new file mode 100644 index 0000000..0e25718 --- /dev/null +++ b/test/MC/ARM/nop-armv6t2-padding.s @@ -0,0 +1,10 @@ +@ RUN: llvm-mc -triple armv6t2-apple-darwin %s -filetype=obj -o %t.obj +@ RUN: macho-dump --dump-section-data < %t.obj > %t.dump +@ RUN: FileCheck %s < %t.dump + +x: + add r0, r1, r2 + .align 4 + add r0, r1, r2 + +@ CHECK: ('_section_data', '020081e0 007820e3 007820e3 007820e3 020081e0') diff --git a/test/MC/ARM/nop-thumb-padding.s b/test/MC/ARM/nop-thumb-padding.s new file mode 100644 index 0000000..1e173f1 --- /dev/null +++ b/test/MC/ARM/nop-thumb-padding.s @@ -0,0 +1,12 @@ +@ RUN: llvm-mc -triple armv6-apple-darwin %s -filetype=obj -o %t.obj +@ RUN: macho-dump --dump-section-data < %t.obj > %t.dump +@ RUN: FileCheck %s < %t.dump + +.thumb_func x +.code 16 +x: + adds r0, r1, r2 + .align 4 + adds r0, r1, r2 + +@ CHECK: ('_section_data', '8818c046 c046c046 c046c046 c046c046 8818') diff --git a/test/MC/ARM/nop-thumb2-padding.s b/test/MC/ARM/nop-thumb2-padding.s new file mode 100644 index 0000000..a8aa3a1 --- /dev/null +++ b/test/MC/ARM/nop-thumb2-padding.s @@ -0,0 +1,12 @@ +@ RUN: llvm-mc -triple armv7-apple-darwin %s -filetype=obj -o %t.obj +@ RUN: macho-dump --dump-section-data < %t.obj > %t.dump +@ RUN: FileCheck %s < %t.dump + +.thumb_func x +.code 16 +x: + adds r0, r1, r2 + .align 4 + adds r0, r1, r2 + +@ CHECK: ('_section_data', '881800bf 00bf00bf 00bf00bf 00bf00bf 8818') diff --git a/test/MC/ARM/reg-list.s b/test/MC/ARM/reg-list.s deleted file mode 100644 index 4dd392e..0000000 --- a/test/MC/ARM/reg-list.s +++ /dev/null @@ -1,8 +0,0 @@ -@ RUN: llvm-mc -triple thumb-apple-darwin10 -show-encoding < %s 2> %t | FileCheck %s -@ RUN: FileCheck --check-prefix=CHECK-WARNINGS < %t %s - - push {r7, lr} -@ CHECK-WARNINGS: register not in ascending order in register list - - push {lr, r7} -@ CHECK: push {lr, r7} diff --git a/test/MC/ARM/simple-encoding.ll b/test/MC/ARM/simple-encoding.ll deleted file mode 100644 index 14ed945..0000000 --- a/test/MC/ARM/simple-encoding.ll +++ /dev/null @@ -1,236 +0,0 @@ -;RUN: llc -mtriple=armv7-apple-darwin -show-mc-encoding -disable-cgp-branch-opts -join-physregs < %s | FileCheck %s - - -;FIXME: Once the ARM integrated assembler is up and going, these sorts of tests -; should run on .s source files rather than using llc to generate the -; assembly. There's also a large number of instruction encodings the -; compiler never generates, so we need the integrated assembler to be -; able to test those at all. - -declare void @llvm.trap() nounwind -declare i32 @llvm.ctlz.i32(i32) - -define i32 @foo(i32 %a, i32 %b) { -; CHECK: foo -; CHECK: trap @ encoding: [0xfe,0xde,0xff,0xe7] -; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1] - - tail call void @llvm.trap() - ret i32 undef -} - -define i32 @f2(i32 %a, i32 %b) { -; CHECK: f2 -; CHECK: add r0, r1, r0 @ encoding: [0x00,0x00,0x81,0xe0] -; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1] - %add = add nsw i32 %b, %a - ret i32 %add -} - - -define i32 @f3(i32 %a, i32 %b) { -; CHECK: f3 -; CHECK: add r0, r0, r1, lsl #3 @ encoding: [0x81,0x01,0x80,0xe0] -; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1] - %mul = shl i32 %b, 3 - %add = add nsw i32 %mul, %a - ret i32 %add -} - -define i32 @f4(i32 %a, i32 %b) { -; CHECK: f4 -; CHECK: add r0, r0, #4064 @ encoding: [0xfe,0x0e,0x80,0xe2] -; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1] - %add = add nsw i32 %a, 4064 - ret i32 %add -} - -define i32 @f5(i32 %a, i32 %b, i32 %c) { -; CHECK: f5 -; CHECK: cmp r0, r1 @ encoding: [0x01,0x00,0x50,0xe1] -; CHECK: mov r0, r2 @ encoding: [0x02,0x00,0xa0,0xe1] -; CHECK: movgt r0, r1 @ encoding: [0x01,0x00,0xa0,0xc1] - %cmp = icmp sgt i32 %a, %b - %retval.0 = select i1 %cmp, i32 %b, i32 %c - ret i32 %retval.0 -} - -define i64 @f6(i64 %a, i64 %b, i64 %c) { -; CHECK: f6 -; CHECK: adds r0, r2, r0 @ encoding: [0x00,0x00,0x92,0xe0] -; CHECK: adc r1, r3, r1 @ encoding: [0x01,0x10,0xa3,0xe0] - %add = add nsw i64 %b, %a - ret i64 %add -} - -define i32 @f7(i32 %a, i32 %b) { -; CHECK: f7 -; CHECK: uxtab r0, r0, r1 @ encoding: [0x71,0x00,0xe0,0xe6] - %and = and i32 %b, 255 - %add = add i32 %and, %a - ret i32 %add -} - -define i32 @f8(i32 %a) { -; CHECK: f8 -; CHECK: movt r0, #42405 @ encoding: [0xa5,0x05,0x4a,0xe3] - %and = and i32 %a, 65535 - %or = or i32 %and, -1515913216 - ret i32 %or -} - -define i32 @f9() { -; CHECK: f9 -; CHECK: movw r0, #42405 @ encoding: [0xa5,0x05,0x0a,0xe3] - ret i32 42405 -} - -define i64 @f10(i64 %a) { -; CHECK: f10 -; CHECK: asrs r1, r1, #1 @ encoding: [0xc1,0x10,0xb0,0xe1] -; CHECK: rrx r0, r0 @ encoding: [0x60,0x00,0xa0,0xe1] - %shr = ashr i64 %a, 1 - ret i64 %shr -} - -define i32 @f11([1 x i32] %A.coerce0, [1 x i32] %B.coerce0) { -; CHECK: f11 -; CHECK: ubfx r1, r1, #8, #5 @ encoding: [0x51,0x14,0xe4,0xe7] -; CHECK: sbfx r0, r0, #13, #7 @ encoding: [0xd0,0x06,0xa6,0xe7] - %tmp1 = extractvalue [1 x i32] %A.coerce0, 0 - %tmp2 = extractvalue [1 x i32] %B.coerce0, 0 - %tmp3 = shl i32 %tmp1, 12 - %bf.val.sext = ashr i32 %tmp3, 25 - %tmp4 = lshr i32 %tmp2, 8 - %bf.clear2 = and i32 %tmp4, 31 - %mul = mul nsw i32 %bf.val.sext, %bf.clear2 - ret i32 %mul -} - -define i32 @f12(i32 %a) { -; CHECK: f12: -; CHECK: bfc r0, #4, #20 @ encoding: [0x1f,0x02,0xd7,0xe7] - %tmp = and i32 %a, 4278190095 - ret i32 %tmp -} - -define i64 @f13() { -; CHECK: f13: -; CHECK: mvn r0, #0 @ encoding: [0x00,0x00,0xe0,0xe3] -; CHECK: mvn r1, #-2147483648 @ encoding: [0x02,0x11,0xe0,0xe3] - ret i64 9223372036854775807 -} - -define i32 @f14(i32 %x, i32 %y) { -; CHECK: f14: -; CHECK: smmul r0, r1, r0 @ encoding: [0x11,0xf0,0x50,0xe7] - %tmp = sext i32 %x to i64 - %tmp1 = sext i32 %y to i64 - %tmp2 = mul i64 %tmp1, %tmp - %tmp3 = lshr i64 %tmp2, 32 - %tmp3.upgrd.1 = trunc i64 %tmp3 to i32 - ret i32 %tmp3.upgrd.1 -} - -define i32 @f15(i32 %x, i32 %y) { -; CHECK: f15: -; CHECK: umull r1, r0, r1, r0 @ encoding: [0x91,0x10,0x80,0xe0] - %tmp = zext i32 %x to i64 - %tmp1 = zext i32 %y to i64 - %tmp2 = mul i64 %tmp1, %tmp - %tmp3 = lshr i64 %tmp2, 32 - %tmp3.upgrd.2 = trunc i64 %tmp3 to i32 - ret i32 %tmp3.upgrd.2 -} - -define i32 @f16(i16 %x, i32 %y) { -; CHECK: f16: -; CHECK: smulbt r0, r0, r1 @ encoding: [0xc0,0x01,0x60,0xe1] - %tmp1 = add i16 %x, 2 - %tmp2 = sext i16 %tmp1 to i32 - %tmp3 = ashr i32 %y, 16 - %tmp4 = mul i32 %tmp2, %tmp3 - ret i32 %tmp4 -} - -define i32 @f17(i32 %x, i32 %y) { -; CHECK: f17: -; CHECK: smultt r0, r1, r0 @ encoding: [0xe1,0x00,0x60,0xe1] - %tmp1 = ashr i32 %x, 16 - %tmp3 = ashr i32 %y, 16 - %tmp4 = mul i32 %tmp3, %tmp1 - ret i32 %tmp4 -} - -define i32 @f18(i32 %a, i16 %x, i32 %y) { -; CHECK: f18: -; CHECK: smlabt r0, r1, r2, r0 @ encoding: [0xc1,0x02,0x00,0xe1] - %tmp = sext i16 %x to i32 - %tmp2 = ashr i32 %y, 16 - %tmp3 = mul i32 %tmp2, %tmp - %tmp5 = add i32 %tmp3, %a - ret i32 %tmp5 -} - -define i32 @f19(i32 %x) { -; CHECK: f19 -; CHECK: clz r0, r0 @ encoding: [0x10,0x0f,0x6f,0xe1] - %tmp.1 = call i32 @llvm.ctlz.i32( i32 %x ) - ret i32 %tmp.1 -} - -define i32 @f20(i32 %X) { -; CHECK: f20 -; CHECK: rev16 r0, r0 @ encoding: [0xb0,0x0f,0xbf,0xe6] - %tmp1 = lshr i32 %X, 8 - %X15 = bitcast i32 %X to i32 - %tmp4 = shl i32 %X15, 8 - %tmp2 = and i32 %tmp1, 16711680 - %tmp5 = and i32 %tmp4, -16777216 - %tmp9 = and i32 %tmp1, 255 - %tmp13 = and i32 %tmp4, 65280 - %tmp6 = or i32 %tmp5, %tmp2 - %tmp10 = or i32 %tmp6, %tmp13 - %tmp14 = or i32 %tmp10, %tmp9 - ret i32 %tmp14 -} - -define i32 @f21(i32 %X) { -; CHECK: f21 -; CHECK: revsh r0, r0 @ encoding: [0xb0,0x0f,0xff,0xe6] - %tmp1 = lshr i32 %X, 8 - %tmp1.upgrd.1 = trunc i32 %tmp1 to i16 - %tmp3 = trunc i32 %X to i16 - %tmp2 = and i16 %tmp1.upgrd.1, 255 - %tmp4 = shl i16 %tmp3, 8 - %tmp5 = or i16 %tmp2, %tmp4 - %tmp5.upgrd.2 = sext i16 %tmp5 to i32 - ret i32 %tmp5.upgrd.2 -} - -define i32 @f22(i32 %X, i32 %Y) { -; CHECK: f22 -; CHECK: pkhtb r0, r0, r1, asr #22 @ encoding: [0x51,0x0b,0x80,0xe6] - %tmp1 = and i32 %X, -65536 - %tmp2 = lshr i32 %Y, 22 - %tmp3 = or i32 %tmp2, %tmp1 - ret i32 %tmp3 -} - -define i32 @f23(i32 %X, i32 %Y) { -; CHECK: f23 -; CHECK: pkhbt r0, r0, r1, lsl #18 @ encoding: [0x11,0x09,0x80,0xe6] - %tmp1 = and i32 %X, 65535 - %tmp2 = shl i32 %Y, 18 - %tmp3 = or i32 %tmp1, %tmp2 - ret i32 %tmp3 -} - -define void @f24(i32 %a) { -; CHECK: f24 -; CHECK: cmp r0, #65536 @ encoding: [0x01,0x08,0x50,0xe3] - %b = icmp ugt i32 %a, 65536 - br i1 %b, label %r, label %r -r: - ret void -} diff --git a/test/MC/ARM/simple-fp-encoding.s b/test/MC/ARM/simple-fp-encoding.s index 8917380..e7d452a 100644 --- a/test/MC/ARM/simple-fp-encoding.s +++ b/test/MC/ARM/simple-fp-encoding.s @@ -2,7 +2,7 @@ @ CHECK: vadd.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x71,0xee] vadd.f64 d16, d17, d16 - + @ CHECK: vadd.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x30,0xee] vadd.f32 s0, s1, s0 @@ -36,18 +36,18 @@ @ CHECK: vcmpe.f32 s1, s0 @ encoding: [0xc0,0x0a,0xf4,0xee] vcmpe.f32 s1, s0 -@ FIXME: vcmpe.f64 d16, #0 @ encoding: [0xc0,0x0b,0xf5,0xee] -@ vcmpe.f64 d16, #0 +@ CHECK: vcmpe.f64 d16, #0 @ encoding: [0xc0,0x0b,0xf5,0xee] + vcmpe.f64 d16, #0 -@ FIXME: vcmpe.f32 s0, #0 @ encoding: [0xc0,0x0a,0xb5,0xee] -@ vcmpe.f32 s0, #0 +@ CHECK: vcmpe.f32 s0, #0 @ encoding: [0xc0,0x0a,0xb5,0xee] + vcmpe.f32 s0, #0 @ CHECK: vabs.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf0,0xee] vabs.f64 d16, d16 @ CHECK: vabs.f32 s0, s0 @ encoding: [0xc0,0x0a,0xb0,0xee] vabs.f32 s0, s0 - + @ CHECK: vcvt.f32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xb7,0xee] vcvt.f32.f64 s0, d16 @@ -114,9 +114,11 @@ @ CHECK: vnmls.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x51,0xee] vnmls.f32 s1, s2, s0 -@ FIXME: vmrs apsr_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee] -@ vmrs apsr_nzcv, fpscr - +@ CHECK: vmrs apsr_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee] +@ CHECK: vmrs apsr_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee] + vmrs apsr_nzcv, fpscr + fmstat + @ CHECK: vnegne.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0x1e] vnegne.f64 d16, d16 @@ -139,11 +141,15 @@ @ CHECK: vmsr fpsid, r0 @ encoding: [0x10,0x0a,0xe0,0xee] vmsr fpsid, r0 -@ FIXME: vmov.f64 d16, #3.000000e+00 @ encoding: [0x08,0x0b,0xf0,0xee] -@ vmov.f64 d16, #3.000000e+00 + vmov.f64 d16, #3.000000e+00 + vmov.f32 s0, #3.000000e+00 + vmov.f64 d16, #-3.000000e+00 + vmov.f32 s0, #-3.000000e+00 -@ FIXME: vmov.f32 s0, #3.000000e+00 @ encoding: [0x08,0x0a,0xb0,0xee] -@ vmov.f32 s0, #3.000000e+00 +@ CHECK: vmov.f64 d16, #3.000000e+00 @ encoding: [0x08,0x0b,0xf0,0xee] +@ CHECK: vmov.f32 s0, #3.000000e+00 @ encoding: [0x08,0x0a,0xb0,0xee] +@ CHECK: vmov.f64 d16, #-3.000000e+00 @ encoding: [0x08,0x0b,0xf8,0xee] +@ CHECK: vmov.f32 s0, #-3.000000e+00 @ encoding: [0x08,0x0a,0xb8,0xee] @ CHECK: vmov s0, r0 @ encoding: [0x10,0x0a,0x00,0xee] @ CHECK: vmov s1, r1 @ encoding: [0x90,0x1a,0x00,0xee] @@ -173,13 +179,13 @@ @ CHECK: vldr.64 d1, [r2, #-32] @ encoding: [0x08,0x1b,0x12,0xed] vldr.64 d1, [r2, #32] vldr.64 d1, [r2, #-32] - + @ CHECK: vldr.64 d2, [r3] @ encoding: [0x00,0x2b,0x93,0xed] vldr.64 d2, [r3] @ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] @ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] -@ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed] +@ CHECK: vldr.64 d3, [pc, #-0] @ encoding: [0x00,0x3b,0x1f,0xed] vldr.64 d3, [pc] vldr.64 d3, [pc,#0] vldr.64 d3, [pc,#-0] @@ -191,13 +197,13 @@ @ CHECK: vldr.32 s1, [r2, #-32] @ encoding: [0x08,0x0a,0x52,0xed] vldr.32 s1, [r2, #32] vldr.32 s1, [r2, #-32] - + @ CHECK: vldr.32 s2, [r3] @ encoding: [0x00,0x1a,0x93,0xed] vldr.32 s2, [r3] @ CHECK: vldr.32 s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed] @ CHECK: vldr.32 s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed] -@ CHECK: vldr.32 s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed] +@ CHECK: vldr.32 s5, [pc, #-0] @ encoding: [0x00,0x2a,0x5f,0xed] vldr.32 s5, [pc] vldr.32 s5, [pc,#0] vldr.32 s5, [pc,#-0] @@ -234,3 +240,6 @@ vcvtr.s32.f32 s0, s1 vcvtr.u32.f64 s0, d0 vcvtr.u32.f32 s0, s1 + +@ CHECK: vmovne s25, s26, r2, r5 + vmovne s25, s26, r2, r5 @ encoding: [0x39,0x2a,0x45,0x1c] diff --git a/test/MC/ARM/thumb-diagnostics.s b/test/MC/ARM/thumb-diagnostics.s new file mode 100644 index 0000000..d02c27e --- /dev/null +++ b/test/MC/ARM/thumb-diagnostics.s @@ -0,0 +1,139 @@ +@ RUN: not llvm-mc -triple=thumbv6-apple-darwin < %s 2> %t +@ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s +@ RUN: not llvm-mc -triple=thumbv5-apple-darwin < %s 2> %t +@ RUN: FileCheck --check-prefix=CHECK-ERRORS-V5 < %t %s + +@ Check for various assembly diagnostic messages on invalid input. + +@ ADD instruction w/o 'S' suffix. + add r1, r2, r3 +@ CHECK-ERRORS: error: invalid instruction +@ CHECK-ERRORS: add r1, r2, r3 +@ CHECK-ERRORS: ^ + +@ Instructions which require v6+ for both registers to be low regs. + add r2, r3 + mov r2, r3 +@ CHECK-ERRORS: error: instruction variant requires Thumb2 +@ CHECK-ERRORS: add r2, r3 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS-V5: error: instruction variant requires ARMv6 or later +@ CHECK-ERRORS-V5: mov r2, r3 +@ CHECK-ERRORS-V5: ^ + + +@ Out of range immediates for ASR instruction. + asrs r2, r3, #33 + asrs r2, r3, #0 +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: asrs r2, r3, #33 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: asrs r2, r3, #0 +@ CHECK-ERRORS: ^ + +@ Out of range immediates for BKPT instruction. + bkpt #256 + bkpt #-1 +error: invalid operand for instruction + bkpt #256 + ^ +error: invalid operand for instruction + bkpt #-1 + ^ + +@ Invalid writeback and register lists for LDM + ldm r2!, {r5, r8} + ldm r2, {r5, r7} + ldm r2!, {r2, r3, r4} +@ CHECK-ERRORS: error: registers must be in range r0-r7 +@ CHECK-ERRORS: ldm r2!, {r5, r8} +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: writeback operator '!' expected +@ CHECK-ERRORS: ldm r2, {r5, r7} +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: writeback operator '!' not allowed when base register in register list +@ CHECK-ERRORS: ldm r2!, {r2, r3, r4} +@ CHECK-ERRORS: ^ + + +@ Invalid writeback and register lists for PUSH/POP + pop {r1, r2, r10} + push {r8, r9} +@ CHECK-ERRORS: error: registers must be in range r0-r7 or pc +@ CHECK-ERRORS: pop {r1, r2, r10} +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: registers must be in range r0-r7 or lr +@ CHECK-ERRORS: push {r8, r9} +@ CHECK-ERRORS: ^ + + +@ Invalid writeback and register lists for STM + stm r1, {r2, r6} + stm r1!, {r2, r9} +@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled +@ CHECK-ERRORS: stm r1, {r2, r6} +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: registers must be in range r0-r7 +@ CHECK-ERRORS: stm r1!, {r2, r9} +@ CHECK-ERRORS: ^ + +@ Out of range immediates for LSL instruction. + lsls r4, r5, #-1 + lsls r4, r5, #32 +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: lsls r4, r5, #-1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: lsls r4, r5, #32 +@ CHECK-ERRORS: ^ + +@ Mismatched source/destination operands for MUL instruction. + muls r1, r2, r3 +@ CHECK-ERRORS: error: destination register must match source register +@ CHECK-ERRORS: muls r1, r2, r3 +@ CHECK-ERRORS: ^ + + +@ Out of range immediates for STR instruction. + str r2, [r7, #-1] + str r5, [r1, #3] + str r3, [r7, #128] +@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled +@ CHECK-ERRORS: str r2, [r7, #-1] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled +@ CHECK-ERRORS: str r5, [r1, #3] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled +@ CHECK-ERRORS: str r3, [r7, #128] +@ CHECK-ERRORS: ^ + +@ Out of range immediate for SVC instruction. + svc #-1 + svc #256 +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: svc #-1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled +@ CHECK-ERRORS: svc #256 +@ CHECK-ERRORS: ^ + + +@ Out of range immediate for ADD SP instructions + add sp, #-1 + add sp, #3 + add sp, sp, #512 + add r2, sp, #1024 +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: add sp, #-1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: add sp, #3 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled +@ CHECK-ERRORS: add sp, sp, #512 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled +@ CHECK-ERRORS: add r2, sp, #1024 +@ CHECK-ERRORS: ^ diff --git a/test/MC/ARM/thumb-nop.s b/test/MC/ARM/thumb-nop.s new file mode 100644 index 0000000..0b580ea --- /dev/null +++ b/test/MC/ARM/thumb-nop.s @@ -0,0 +1,9 @@ +@ RUN: llvm-mc -triple=thumbv6-apple-darwin -show-encoding < %s | FileCheck %s -check-prefix=CHECK-V6 +@ RUN: llvm-mc -triple=thumbv7-apple-darwin -show-encoding < %s | FileCheck %s -check-prefix=CHECK-V7 + + .syntax unified + + nop + +@ CHECK-V6: nop @ encoding: [0xc0,0x46] +@ CHECK-V7: nop @ encoding: [0x00,0xbf] diff --git a/test/MC/ARM/thumb.s b/test/MC/ARM/thumb.s index 79ea2e4..625882c 100644 --- a/test/MC/ARM/thumb.s +++ b/test/MC/ARM/thumb.s @@ -1,60 +1,58 @@ @ RUN: llvm-mc -triple thumbv6-apple-darwin -show-encoding < %s | FileCheck %s .code 16 -@ CHECK: cmp r1, r2 @ encoding: [0x91,0x42] cmp r1, r2 +@ CHECK: cmp r1, r2 @ encoding: [0x91,0x42] -@ CHECK: pop {r1, r2, r4} @ encoding: [0x16,0xbc] pop {r1, r2, r4} +@ CHECK: pop {r1, r2, r4} @ encoding: [0x16,0xbc] -@ CHECK: trap @ encoding: [0xfe,0xde] trap +@ CHECK: trap @ encoding: [0xfe,0xde] -@ CHECK: blx r9 @ encoding: [0xc8,0x47] blx r9 + blx r10 +@ CHECK: blx r9 @ encoding: [0xc8,0x47] @ CHECK: blx r10 @ encoding: [0xd0,0x47] - blx r10 -@ CHECK: rev r2, r3 @ encoding: [0x1a,0xba] -@ CHECK: rev16 r3, r4 @ encoding: [0x63,0xba] -@ CHECK: revsh r5, r6 @ encoding: [0xf5,0xba] rev r2, r3 rev16 r3, r4 revsh r5, r6 +@ CHECK: rev r2, r3 @ encoding: [0x1a,0xba] +@ CHECK: rev16 r3, r4 @ encoding: [0x63,0xba] +@ CHECK: revsh r5, r6 @ encoding: [0xf5,0xba] -@ CHECK: sxtb r2, r3 @ encoding: [0x5a,0xb2] -@ CHECK: sxth r2, r3 @ encoding: [0x1a,0xb2] sxtb r2, r3 sxth r2, r3 +@ CHECK: sxtb r2, r3 @ encoding: [0x5a,0xb2] +@ CHECK: sxth r2, r3 @ encoding: [0x1a,0xb2] -@ CHECK: tst r4, r5 @ encoding: [0x2c,0x42] tst r4, r5 +@ CHECK: tst r4, r5 @ encoding: [0x2c,0x42] -@ CHECK: uxtb r3, r6 @ encoding: [0xf3,0xb2] -@ CHECK: uxth r3, r6 @ encoding: [0xb3,0xb2] uxtb r3, r6 uxth r3, r6 +@ CHECK: uxtb r3, r6 @ encoding: [0xf3,0xb2] +@ CHECK: uxth r3, r6 @ encoding: [0xb3,0xb2] -@ CHECK: ldr r3, [r1, r2] @ encoding: [0x8b,0x58] ldr r3, [r1, r2] +@ CHECK: ldr r3, [r1, r2] @ encoding: [0x8b,0x58] -@ CHECK: bkpt #2 @ encoding: [0x02,0xbe] - bkpt #2 + bkpt #2 +@ CHECK: bkpt #2 @ encoding: [0x02,0xbe] -@ CHECK: nop @ encoding: [0x00,0xbf] nop +@ CHECK: nop @ encoding: [0xc0,0x46] -@ CHECK: yield @ encoding: [0x10,0xbf] - yield - -@ CHECK: wfe @ encoding: [0x20,0xbf] wfe - -@ CHECK: wfi @ encoding: [0x30,0xbf] wfi + yield +@ CHECK: wfe @ encoding: [0x20,0xbf] +@ CHECK: wfi @ encoding: [0x30,0xbf] +@ CHECK: yield @ encoding: [0x10,0xbf] -@ CHECK: cpsie aif @ encoding: [0x67,0xb6] cpsie aif +@ CHECK: cpsie aif @ encoding: [0x67,0xb6] -@ CHECK: mov r0, pc @ encoding: [0x78,0x46] mov r0, pc +@ CHECK: mov r0, pc @ encoding: [0x78,0x46] diff --git a/test/MC/ARM/thumb2-diagnostics.s b/test/MC/ARM/thumb2-diagnostics.s new file mode 100644 index 0000000..e38f53c --- /dev/null +++ b/test/MC/ARM/thumb2-diagnostics.s @@ -0,0 +1,44 @@ +@ RUN: not llvm-mc -triple=thumbv7-apple-darwin < %s 2> %t +@ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s + +@ Ill-formed IT block instructions. + itet eq + addle r0, r1, r2 + nop + it le + iteeee gt + ittfe le + nopeq + +@ CHECK-ERRORS: error: incorrect condition in IT block; got 'le', but expected 'eq' +@ CHECK-ERRORS: addle r0, r1, r2 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: incorrect condition in IT block; got 'al', but expected 'ne' +@ CHECK-ERRORS: nop +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: instructions in IT block must be predicable +@ CHECK-ERRORS: it le +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: too many conditions on IT instruction +@ CHECK-ERRORS: iteeee gt +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: illegal IT block condition mask 'tfe' +@ CHECK-ERRORS: ittfe le +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: predicated instructions must be in IT block +@ CHECK-ERRORS: nopeq +@ CHECK-ERRORS: ^ + + @ Out of range immediates for MRC/MRC2/MRRC/MRRC2 + mrc p14, #8, r1, c1, c2, #4 + mrc p14, #1, r1, c1, c2, #8 + mrc2 p14, #8, r1, c1, c2, #4 + mrc2 p14, #0, r1, c1, c2, #9 + mrrc p7, #16, r5, r4, c1 + mrrc2 p7, #17, r5, r4, c1 +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction diff --git a/test/MC/ARM/thumb2-mclass.s b/test/MC/ARM/thumb2-mclass.s new file mode 100644 index 0000000..10460f9 --- /dev/null +++ b/test/MC/ARM/thumb2-mclass.s @@ -0,0 +1,74 @@ +@ RUN: llvm-mc -triple=thumbv7m-apple-darwin -show-encoding < %s | FileCheck %s + .syntax unified + .globl _func + +@ Check that the assembler can handle the documented syntax from the ARM ARM. +@ These tests test instruction encodings specific to v7m & v7m (FeatureMClass). + +@------------------------------------------------------------------------------ +@ MRS +@------------------------------------------------------------------------------ + + mrs r0, apsr + mrs r0, iapsr + mrs r0, eapsr + mrs r0, xpsr + mrs r0, ipsr + mrs r0, epsr + mrs r0, iepsr + mrs r0, msp + mrs r0, psp + mrs r0, primask + mrs r0, basepri + mrs r0, basepri_max + mrs r0, faultmask + mrs r0, control + +@ CHECK: mrs r0, apsr @ encoding: [0xef,0xf3,0x00,0x80] +@ CHECK: mrs r0, iapsr @ encoding: [0xef,0xf3,0x01,0x80] +@ CHECK: mrs r0, eapsr @ encoding: [0xef,0xf3,0x02,0x80] +@ CHECK: mrs r0, xpsr @ encoding: [0xef,0xf3,0x03,0x80] +@ CHECK: mrs r0, ipsr @ encoding: [0xef,0xf3,0x05,0x80] +@ CHECK: mrs r0, epsr @ encoding: [0xef,0xf3,0x06,0x80] +@ CHECK: mrs r0, iepsr @ encoding: [0xef,0xf3,0x07,0x80] +@ CHECK: mrs r0, msp @ encoding: [0xef,0xf3,0x08,0x80] +@ CHECK: mrs r0, psp @ encoding: [0xef,0xf3,0x09,0x80] +@ CHECK: mrs r0, primask @ encoding: [0xef,0xf3,0x10,0x80] +@ CHECK: mrs r0, basepri @ encoding: [0xef,0xf3,0x11,0x80] +@ CHECK: mrs r0, basepri_max @ encoding: [0xef,0xf3,0x12,0x80] +@ CHECK: mrs r0, faultmask @ encoding: [0xef,0xf3,0x13,0x80] +@ CHECK: mrs r0, control @ encoding: [0xef,0xf3,0x14,0x80] + +@------------------------------------------------------------------------------ +@ MSR +@------------------------------------------------------------------------------ + + msr apsr, r0 + msr iapsr, r0 + msr eapsr, r0 + msr xpsr, r0 + msr ipsr, r0 + msr epsr, r0 + msr iepsr, r0 + msr msp, r0 + msr psp, r0 + msr primask, r0 + msr basepri, r0 + msr basepri_max, r0 + msr faultmask, r0 + msr control, r0 + +@ CHECK: msr apsr, r0 @ encoding: [0x80,0xf3,0x00,0x80] +@ CHECK: msr iapsr, r0 @ encoding: [0x80,0xf3,0x01,0x80] +@ CHECK: msr eapsr, r0 @ encoding: [0x80,0xf3,0x02,0x80] +@ CHECK: msr xpsr, r0 @ encoding: [0x80,0xf3,0x03,0x80] +@ CHECK: msr ipsr, r0 @ encoding: [0x80,0xf3,0x05,0x80] +@ CHECK: msr epsr, r0 @ encoding: [0x80,0xf3,0x06,0x80] +@ CHECK: msr iepsr, r0 @ encoding: [0x80,0xf3,0x07,0x80] +@ CHECK: msr msp, r0 @ encoding: [0x80,0xf3,0x08,0x80] +@ CHECK: msr psp, r0 @ encoding: [0x80,0xf3,0x09,0x80] +@ CHECK: msr primask, r0 @ encoding: [0x80,0xf3,0x10,0x80] +@ CHECK: msr basepri, r0 @ encoding: [0x80,0xf3,0x11,0x80] +@ CHECK: msr basepri_max, r0 @ encoding: [0x80,0xf3,0x12,0x80] +@ CHECK: msr faultmask, r0 @ encoding: [0x80,0xf3,0x13,0x80] +@ CHECK: msr control, r0 @ encoding: [0x80,0xf3,0x14,0x80] diff --git a/test/MC/ARM/thumb2.s b/test/MC/ARM/thumb2.s deleted file mode 100644 index 7d632db..0000000 --- a/test/MC/ARM/thumb2.s +++ /dev/null @@ -1,355 +0,0 @@ -@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s -@ XFAIL: * -.code 16 - -@ CHECK: adc r1, r1, #171 @ encoding: [0xab,0x01,0x41,0xf1] - adc r1, r1, #171 -@ CHECK: adc r1, r1, #1179666 @ encoding: [0x12,0x11,0x41,0xf1] - adc r1, r1, #1179666 -@ CHECK: adc r1, r1, #872428544 @ encoding: [0x34,0x21,0x41,0xf1] - adc r1, r1, #872428544 -@ CHECK: adc r1, r1, #1448498774 @ encoding: [0x56,0x31,0x41,0xf1] - adc r1, r1, #1448498774 -@ CHECK: adc r1, r1, #66846720 @ encoding: [0x7f,0x71,0x41,0xf1] - adc r1, r1, #66846720 - -@ CHECK: mvn r0, #187 @ encoding: [0xbb,0x00,0x6f,0xf0] - mvn r0, #187 -@ CHECK: mvn r0, #11141290 @ encoding: [0xaa,0x10,0x6f,0xf0] - mvn r0, #11141290 -@ CHECK: mvn r0, #-872363008 @ encoding: [0xcc,0x20,0x6f,0xf0] - mvn r0, #-872363008 -@ CHECK: mvn r0, #1114112 @ encoding: [0x88,0x10,0x6f,0xf4] - mvn r0, #1114112 - -@ CHECK: cmp.w r0, #11141290 @ encoding: [0xaa,0x1f,0xb0,0xf1] - cmp.w r0, #11141290 -@ CHECK: cmp.w r0, #-872363008 @ encoding: [0xcc,0x2f,0xb0,0xf1] - cmp.w r0, #-872363008 -@ CHECK: cmp.w r0, #-572662307 @ encoding: [0xdd,0x3f,0xb0,0xf1] - cmp.w r0, #-572662307 -@ CHECK: cmp.w r0, #1114112 @ encoding: [0x88,0x1f,0xb0,0xf5] - cmp.w r0, #1114112 -@ CHECK: cmp.w r0, r1, lsl #5 @ encoding: [0x41,0x1f,0xb0,0xeb] - cmp.w r0, r1, lsl #5 - -@ CHECK: sxtab r0, r1, r0 @ encoding: [0x80,0xf0,0x41,0xfa] - sxtab r0, r1, r0 @ encoding: [0x80,0xf0,0x41,0xfa] - -@ CHECK: movw r0, #65535 @ encoding: [0xff,0x70,0x4f,0xf6] - movw r0, #65535 -@ CHECK: movw r1, #43777 @ encoding: [0x01,0x31,0x4a,0xf6] - movw r1, #43777 -@ CHECK: movt r1, #427 @ encoding: [0xab,0x11,0xc0,0xf2] - movt r1, #427 -@ CHECK: movw r1, #43792 @ encoding: [0x10,0x31,0x4a,0xf6] - movw r1, #43792 -@ CHECK: movt r1, #4267 @ encoding: [0xab,0x01,0xc0,0xf2] - movt r1, #4267 -@ CHECK: mov.w r0, #66846720 @ encoding: [0x7f,0x70,0x4f,0xf0] - mov.w r0, #66846720 - -@ Aliases w/ the vanilla 'mov' mnemonic, and explicit alternative selection. - mov r2, #0xbf000000 - mov r1, #0x100 - mov r3, #32 - mov.w r3, #32 - movw r3, #32 - -@ CHECK: mov.w r2, #3204448256 @ encoding: [0x4f,0xf0,0x3f,0x42] -@ CHECK: mov.w r1, #256 @ encoding: [0x4f,0xf4,0x80,0x71] -@ CHECK: mov r3, #32 @ encoding: [0x20,0x23] -@ CHECK: mov.w r3, #32 @ encoding: [0x4f,0xf0,0x20,0x03] -@ CHECK: movw r3, #32 @ encoding: [0x40,0xf2,0x20,0x03] - - - - -@ CHECK: rrx r0, r0 @ encoding: [0x30,0x00,0x4f,0xea] - rrx r0, r0 - -@ CHECK: bfc r0, #4, #20 @ encoding: [0x17,0x10,0x6f,0xf3] - bfc r0, #4, #20 -@ CHECK: bfc r0, #0, #23 @ encoding: [0x16,0x00,0x6f,0xf3] - bfc r0, #0, #23 -@ CHECK: bfc r0, #12, #20 @ encoding: [0x1f,0x30,0x6f,0xf3] - bfc r0, #12, #20 - -@ CHECK: sbfx r0, r0, #7, #11 @ encoding: [0xca,0x10,0x40,0xf3] - sbfx r0, r0, #7, #11 -@ CHECK: ubfx r0, r0, #7, #11 @ encoding: [0xca,0x10,0xc0,0xf3] - ubfx r0, r0, #7, #11 - -@ CHECK: mla r0, r0, r1, r2 @ encoding: [0x01,0x20,0x00,0xfb] - mla r0, r0, r1, r2 -@ CHECK: mls r0, r0, r1, r2 @ encoding: [0x11,0x20,0x00,0xfb] - mls r0, r0, r1, r2 - -@ CHECK: smlabt r0, r1, r2, r0 @ encoding: [0x12,0x00,0x11,0xfb] - smlabt r0, r1, r2, r0 - -@ CHECK: clz r0, r0 @ encoding: [0x80,0xf0,0xb0,0xfa] - clz r0, r0 - -@ CHECK: pkhbt r0, r0, r1, lsl #16 @ encoding: [0x01,0x40,0xc0,0xea] - pkhbt r0, r0, r1, lsl #16 -@ CHECK: pkhbt r0, r0, r1, lsl #12 @ encoding: [0x01,0x30,0xc0,0xea] - pkhbt r0, r0, r1, lsl #16 -@ CHECK: pkhbt r0, r0, r1, lsl #18 @ encoding: [0x81,0x40,0xc0,0xea] - pkhbt r0, r0, r1, lsl #18 -@ CHECK: pkhbt r0, r0, r1 @ encoding: [0x01,0x00,0xc0,0xea] - pkhbt r0, r0, r1 -@ CHECK: pkhtb r0, r0, r1, asr #16 @ encoding: [0x21,0x40,0xc0,0xea] - pkhtb r0, r0, r1, asr #16 -@ CHECK: pkhtb r0, r0, r1, asr #12 @ encoding: [0x21,0x30,0xc0,0xea] - pkhtb r0, r0, r1, asr #12 -@ CHECK: pkhtb r0, r0, r1, asr #18 @ encoding: [0xa1,0x40,0xc0,0xea] - pkhtb r0, r0, r1, asr #18 -@ CHECK: pkhtb r0, r0, r1, asr #22 @ encoding: [0xa1,0x50,0xc0,0xea] - pkhtb r0, r0, r1, asr #22 - -@ CHECK: str.w r0, [r1, #4092] @ encoding: [0xfc,0x0f,0xc1,0xf8] - str.w r0, [r1, #4092] -@ CHECK: str r0, [r1, #-128] @ encoding: [0x80,0x0c,0x41,0xf8] - str r0, [r1, #-128] -@ CHECK: str.w r0, [r1, r2, lsl #2] @ encoding: [0x22,0x00,0x41,0xf8 - str.w r0, [r1, r2, lsl #2] - -@ CHECK: ldr.w r0, [r0, #4092] @ encoding: [0xfc,0x0f,0xd0,0xf8] - ldr.w r0, [r0, #4092] -@ CHECK: ldr r0, [r0, #-128] @ encoding: [0x80,0x0c,0x50,0xf8] - ldr r0, [r0, #-128] -@ CHECK: ldr.w r0, [r0, r1, lsl #2] @ encoding: [0x21,0x00,0x50,0xf8] - ldr.w r0, [r0, r1, lsl #2] - -@ CHECK: str r1, [r0, #16]! @ encoding: [0x10,0x1f,0x40,0xf8] - str r1, [r0, #16]! -@ CHECK: strh r1, [r0, #8]! @ encoding: [0x08,0x1f,0x20,0xf8] - strh r1, [r0, #8]! -@ CHECK: strh r2, [r0], #-4 @ encoding: [0x04,0x29,0x20,0xf8] - strh r2, [r0], #-4 -@ CHECK: str r2, [r0], #-4 @ encoding: [0x04,0x29,0x40,0xf8] - str r2, [r0], #-4 - -@ CHECK: ldr r2, [r0, #16]! @ encoding: [0x10,0x2f,0x50,0xf8] - ldr r2, [r0, #16]! -@ CHECK: ldr r2, [r0, #-64]! @ encoding: [0x40,0x2d,0x50,0xf8] - ldr r2, [r0, #-64]! -@ CHECK: ldrsb r2, [r0, #4]! @ encoding: [0x04,0x2f,0x10,0xf9] - ldrsb r2, [r0, #4]! - -@ CHECK: strb.w r0, [r1, #4092] @ encoding: [0xfc,0x0f,0x81,0xf8] - strb.w r0, [r1, #4092] -@ CHECK: strb r0, [r1, #-128] @ encoding: [0x80,0x0c,0x01,0xf8] - strb r0, [r1, #-128] -@ CHECK: strb.w r0, [r1, r2, lsl #2] @ encoding: [0x22,0x00,0x01,0xf8] - strb.w r0, [r1, r2, lsl #2] -@ CHECK: strh.w r0, [r1, #4092] @ encoding: [0xfc,0x0f,0xa1,0xf8] - strh.w r0, [r1, #4092] -@ CHECK: strh r0, [r1, #-128] @ encoding: [0x80,0x0c,0x21,0xf8] - strh r0, [r1, #-128] -@ CHECK: strh r0, [r1, #-128] @ encoding: [0x80,0x0c,0x21,0xf8] - strh r0, [r1, #-128] -@ CHECK: strh.w r0, [r1, r2, lsl #2] @ encoding: [0x22,0x00,0x21,0xf8] - strh.w r0, [r1, r2, lsl #2] - -@ CHECK: ldrb r0, [r0, #-1] @ encoding: [0x01,0x0c,0x10,0xf8] - ldrb r0, [r0, #-1] -@ CHECK: ldrb r0, [r0, #-128] @ encoding: [0x80,0x0c,0x10,0xf8] - ldrb r0, [r0, #-128] -@ CHECK: ldrb.w r0, [r0, r1, lsl #2] @ encoding: [0x21,0x00,0x10,0xf8] - ldrb.w r0, [r0, r1, lsl #2] -@ CHECK: ldrh.w r0, [r0, #2046] @ encoding: [0xfe,0x07,0xb0,0xf8] - ldrh.w r0, [r0, #2046] -@ CHECK: ldrh r0, [r0, #-128] @ encoding: [0x80,0x0c,0x30,0xf8] - ldrh r0, [r0, #-128] -@ CHECK: ldrh.w r0, [r0, r1, lsl #2] @ encoding: [0x21,0x00,0x30,0xf8] - ldrh.w r0, [r0, r1, lsl #2] -@ CHECK: ldrsb.w r0, [r0] @ encoding: [0x00,0x00,0x90,0xf9] - ldrsb.w r0, [r0] -@ CHECK: ldrsh.w r0, [r0] @ encoding: [0x00,0x00,0xb0,0xf9] - ldrsh.w r0, [r0] -@ CHECK: bfi r0, r0, #5, #7 @ encoding: [0x60,0xf3,0x4b,0x10] - bfi r0, r0, #5, #7 -@ CHECK: isb @ encoding: [0xbf,0xf3,0x6f,0x8f] - isb -@ CHECK: mrs r0, cpsr @ encoding: [0xef,0xf3,0x00,0x80] - mrs r0, cpsr -@ CHECK: vmrs r0, fpscr @ encoding: [0xf1,0xee,0x10,0x0a] - vmrs r0, fpscr -@ CHECK: vmrs r0, fpexc @ encoding: [0xf8,0xee,0x10,0x0a] - vmrs r0, fpexc -@ CHECK: vmrs r0, fpsid @ encoding: [0xf0,0xee,0x10,0x0a] - vmrs r0, fpsid - -@ CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a] - vmsr fpscr, r0 -@ CHECK: vmsr fpexc, r0 @ encoding: [0xe8,0xee,0x10,0x0a] - vmsr fpexc, r0 -@ CHECK: vmsr fpsid, r0 @ encoding: [0xe0,0xee,0x10,0x0a] - vmsr fpsid, r0 - -@ CHECK: mcr p7, #1, r5, c1, c1, #4 @ encoding: [0x21,0xee,0x91,0x57] - mcr p7, #1, r5, c1, c1, #4 - -@ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xee,0x92,0x1e] - mrc p14, #0, r1, c1, c2, #4 - -@ CHECK: mcrr p7, #1, r5, r4, c1 @ encoding: [0x44,0xec,0x11,0x57] - mcrr p7, #1, r5, r4, c1 - -@ CHECK: mrrc p7, #1, r5, r4, c1 @ encoding: [0x54,0xec,0x11,0x57] - mrrc p7, #1, r5, r4, c1 - -@ CHECK: mcr2 p7, #1, r5, c1, c1, #4 @ encoding: [0x21,0xfe,0x91,0x57] - mcr2 p7, #1, r5, c1, c1, #4 - -@ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xfe,0x92,0x1e] - mrc2 p14, #0, r1, c1, c2, #4 - -@ CHECK: mcrr2 p7, #1, r5, r4, c1 @ encoding: [0x44,0xfc,0x11,0x57] - mcrr2 p7, #1, r5, r4, c1 - -@ CHECK: mrrc2 p7, #1, r5, r4, c1 @ encoding: [0x54,0xfc,0x11,0x57] - mrrc2 p7, #1, r5, r4, c1 - -@ CHECK: cdp p7, #1, c1, c1, c1, #4 @ encoding: [0x11,0xee,0x81,0x17] - cdp p7, #1, c1, c1, c1, #4 - -@ CHECK: cdp2 p7, #1, c1, c1, c1, #4 @ encoding: [0x11,0xfe,0x81,0x17] - cdp2 p7, #1, c1, c1, c1, #4 - -@ CHECK: clrex @ encoding: [0xbf,0xf3,0x2f,0x8f] - clrex - -@ CHECK: clz r9, r0 @ encoding: [0xb0,0xfa,0x80,0xf9] - clz r9, r0 - -@ CHECK: qadd r1, r2, r3 @ encoding: [0x83,0xfa,0x82,0xf1] - qadd r1, r2, r3 - -@ CHECK: qsub r1, r2, r3 @ encoding: [0x83,0xfa,0xa2,0xf1] - qsub r1, r2, r3 - -@ CHECK: qdadd r1, r2, r3 @ encoding: [0x83,0xfa,0x92,0xf1] - qdadd r1, r2, r3 - -@ CHECK: qdsub r1, r2, r3 @ encoding: [0x83,0xfa,0xb2,0xf1] - qdsub r1, r2, r3 - -@ CHECK: nop.w @ encoding: [0xaf,0xf3,0x00,0x80] - nop.w - -@ CHECK: yield.w @ encoding: [0xaf,0xf3,0x01,0x80] - yield.w - -@ CHECK: wfe.w @ encoding: [0xaf,0xf3,0x02,0x80] - wfe.w - -@ CHECK: wfi.w @ encoding: [0xaf,0xf3,0x03,0x80] - wfi.w - -@ CHECK: dmb sy @ encoding: [0xbf,0xf3,0x5f,0x8f] - dmb sy -@ CHECK: dmb st @ encoding: [0xbf,0xf3,0x5e,0x8f] - dmb st -@ CHECK: dmb ish @ encoding: [0xbf,0xf3,0x5b,0x8f] - dmb ish -@ CHECK: dmb ishst @ encoding: [0xbf,0xf3,0x5a,0x8f] - dmb ishst -@ CHECK: dmb nsh @ encoding: [0xbf,0xf3,0x57,0x8f] - dmb nsh -@ CHECK: dmb nshst @ encoding: [0xbf,0xf3,0x56,0x8f] - dmb nshst -@ CHECK: dmb osh @ encoding: [0xbf,0xf3,0x53,0x8f] - dmb osh -@ CHECK: dmb oshst @ encoding: [0xbf,0xf3,0x52,0x8f] - dmb oshst - -@ CHECK: dsb sy @ encoding: [0xbf,0xf3,0x4f,0x8f] - dsb sy -@ CHECK: dsb st @ encoding: [0xbf,0xf3,0x4e,0x8f] - dsb st -@ CHECK: dsb ish @ encoding: [0xbf,0xf3,0x4b,0x8f] - dsb ish -@ CHECK: dsb ishst @ encoding: [0xbf,0xf3,0x4a,0x8f] - dsb ishst -@ CHECK: dsb nsh @ encoding: [0xbf,0xf3,0x47,0x8f] - dsb nsh -@ CHECK: dsb nshst @ encoding: [0xbf,0xf3,0x46,0x8f] - dsb nshst -@ CHECK: dsb osh @ encoding: [0xbf,0xf3,0x43,0x8f] - dsb osh -@ CHECK: dsb oshst @ encoding: [0xbf,0xf3,0x42,0x8f] - dsb oshst - -@ CHECK: cpsie.w aif @ encoding: [0xaf,0xf3,0xe0,0x84] - cpsie.w aif -@ CHECK: cps #15 @ encoding: [0xaf,0xf3,0x0f,0x81] - cps #15 -@ CHECK: cpsie.w if, #10 @ encoding: [0xaf,0xf3,0x6a,0x85] - cpsie.w if, #10 - -@ CHECK: msr cpsr_fc, r0 @ encoding: [0x80,0xf3,0x00,0x89] - msr apsr, r0 -@ CHECK: msr cpsr_s, r0 @ encoding: [0x80,0xf3,0x00,0x84] - msr apsr_g, r0 -@ CHECK: msr cpsr_f, r0 @ encoding: [0x80,0xf3,0x00,0x88] - msr apsr_nzcvq, r0 -@ CHECK: msr cpsr_fs, r0 @ encoding: [0x80,0xf3,0x00,0x8c] - msr apsr_nzcvqg, r0 -@ CHECK: msr cpsr_fc, r0 @ encoding: [0x80,0xf3,0x00,0x89] - msr cpsr_fc, r0 -@ CHECK: msr cpsr_c, r0 @ encoding: [0x80,0xf3,0x00,0x81] - msr cpsr_c, r0 -@ CHECK: msr cpsr_x, r0 @ encoding: [0x80,0xf3,0x00,0x82] - msr cpsr_x, r0 -@ CHECK: msr cpsr_fc, r0 @ encoding: [0x80,0xf3,0x00,0x89] - msr cpsr_fc, r0 -@ CHECK: msr cpsr_fsx, r0 @ encoding: [0x80,0xf3,0x00,0x8e] - msr cpsr_fsx, r0 -@ CHECK: msr spsr_fc, r0 @ encoding: [0x90,0xf3,0x00,0x89] - msr spsr_fc, r0 -@ CHECK: msr spsr_fsxc, r0 @ encoding: [0x90,0xf3,0x00,0x8f] - msr spsr_fsxc, r0 -@ CHECK: msr cpsr_fsxc, r0 @ encoding: [0x80,0xf3,0x00,0x8f] - msr cpsr_fsxc, r0 - -@ CHECK: strexb r0, r1, [r2] @ encoding: [0xc2,0xe8,0x40,0x1f] - strexb r0, r1, [r2] -@ CHECK: strexh r0, r1, [r2] @ encoding: [0xc2,0xe8,0x50,0x1f] - strexh r0, r1, [r2] -@ CHECK: strex r0, r1, [r2] @ encoding: [0x42,0xe8,0x00,0x10] - strex r0, r1, [r2] -@ CHECK: strexd r0, r2, r3, [r1] @ encoding: [0xc1,0xe8,0x70,0x23] - strexd r0, r2, r3, [r1] -@ CHECK: ldrexb r0, [r0] @ encoding: [0xd0,0xe8,0x4f,0x0f] - ldrexb r0, [r0] -@ CHECK: ldrexh r0, [r0] @ encoding: [0xd0,0xe8,0x5f,0x0f] - ldrexh r0, [r0] -@ CHECK: ldrex r0, [r0] @ encoding: [0x50,0xe8,0x00,0x0f] - ldrex r0, [r0] -@ CHECK: ldrexd r0, r1, [r0] @ encoding: [0xd0,0xe8,0x7f,0x01] - ldrexd r0, r1, [r0] -@ CHECK: ssat16 r0, #7, r0 @ encoding: [0x20,0xf3,0x06,0x00] - ssat16 r0, #7, r0 - - and r1, #0xff - and r1, r1, #0xff - orr r1, 0x100 - orr r1, r1, 0x100 - eor r1, 0x100 - eor r1, r1, 0x100 - bic r1, 0x100 - bic r1, r1, 0x100 - -@ CHECK: and r1, r1, #255 @ encoding: [0x01,0xf0,0xff,0x01] -@ CHECK: and r1, r1, #255 @ encoding: [0x01,0xf0,0xff,0x01] -@ CHECK: orr r1, r1, #256 @ encoding: [0x41,0xf4,0x80,0x71] -@ CHECK: orr r1, r1, #256 @ encoding: [0x41,0xf4,0x80,0x71] -@ CHECK: eor r1, r1, #256 @ encoding: [0x81,0xf4,0x80,0x71] -@ CHECK: eor r1, r1, #256 @ encoding: [0x81,0xf4,0x80,0x71] -@ CHECK: bic r1, r1, #256 @ encoding: [0x21,0xf4,0x80,0x71] -@ CHECK: bic r1, r1, #256 @ encoding: [0x21,0xf4,0x80,0x71] - - diff --git a/test/MC/ARM/thumb2_instructions.s b/test/MC/ARM/thumb2_instructions.s deleted file mode 100644 index 71cd4ae..0000000 --- a/test/MC/ARM/thumb2_instructions.s +++ /dev/null @@ -1,12 +0,0 @@ -@ RUN: llvm-mc -triple thumbv7-unknown-unknown -show-encoding %s > %t -@ RUN: FileCheck < %t %s - - .syntax unified - .text - -@ FIXME: This is not the correct instruction representation, but at least we are -@ parsing the ldr to something. -@ -@ CHECK: ldr r0, [r7, #258] - ldr r0, [r7, #-8] - diff --git a/test/MC/ARM/xscale-attributes.ll b/test/MC/ARM/xscale-attributes.ll index e576278..3ccf02b 100644 --- a/test/MC/ARM/xscale-attributes.ll +++ b/test/MC/ARM/xscale-attributes.ll @@ -17,7 +17,7 @@ entry: ; ASM-NEXT: .eabi_attribute 8, 1 ; ASM-NEXT: .eabi_attribute 9, 1 -; OBJ: Section 0x00000004 +; OBJ: Section 4 ; OBJ-NEXT: 'sh_name', 0x0000000c ; OBJ-NEXT: 'sh_type', 0x70000003 ; OBJ-NEXT: 'sh_flags', 0x00000000 |
