Vendor import of clang trunk r162107:

http://llvm.org/svn/llvm-project/cfe/trunk@162107

5 files changed, 208 insertions, 4 deletions

diff --git a/test/CodeGen/align-global-large.c b/test/CodeGen/align-global-large.c
new file mode 100644
index 0000000..fcbe758
--- /dev/null
+++ b/test/CodeGen/align-global-large.c
@@ -0,0 +1,18 @@
+// PR13606 - Clang crashes with large alignment attribute
+// RUN: %clang -S -emit-llvm %s -o - | FileCheck %s
+
+// CHECK: x
+// CHECK: align
+// CHECK: 1048576
+volatile char x[4000] __attribute__((aligned(0x100000)));
+
+int
+main (int argc, char ** argv) {
+  // CHECK: y
+  // CHECK: align
+  // CHECK: 1048576
+  volatile char y[4000] __attribute__((aligned(0x100000)));
+
+  return y[argc];
+}
+
diff --git a/test/CodeGen/alignment.c b/test/CodeGen/alignment.c
index 8882c91..98ea01b 100644
--- a/test/CodeGen/alignment.c
+++ b/test/CodeGen/alignment.c
@@ -43,7 +43,8 @@ void test3(packedfloat3 *p) {
   *p = (packedfloat3) { 3.2f, 2.3f, 0.1f };
 }
 // CHECK: @test3(
-// CHECK: store <3 x float> {{.*}}, align 4
+// CHECK: %{{.*}} = bitcast <3 x float>* %{{.*}} to <4 x float>*
+// CHECK: store <4 x float> {{.*}}, align 4
 // CHECK: ret void
 
 
diff --git a/test/CodeGen/arm-neon-misc.c b/test/CodeGen/arm-neon-misc.c
new file mode 100644
index 0000000..56ce316
--- /dev/null
+++ b/test/CodeGen/arm-neon-misc.c
@@ -0,0 +1,34 @@
+// REQUIRES: arm-registered-target
+// RUN: %clang_cc1 -triple thumbv7-apple-darwin \
+// RUN:   -target-abi apcs-gnu \
+// RUN:   -target-cpu cortex-a8 \
+// RUN:   -mfloat-abi soft \
+// RUN:   -target-feature +soft-float-abi \
+// RUN:   -ffreestanding \
+// RUN:   -emit-llvm -w -o - %s | FileCheck %s
+
+#include <arm_neon.h>
+
+// Radar 11998303: Avoid using i64 types for vld1q_lane and vst1q_lane Neon
+// intrinsics with <2 x i64> vectors to avoid poor code for i64 in the backend.
+void t1(uint64_t *src, uint8_t *dst) {
+// CHECK: @t1
+  uint64x2_t q = vld1q_u64(src);
+// CHECK: call <2 x i64> @llvm.arm.neon.vld1.v2i64
+  vst1q_lane_u64(dst, q, 1);
+// CHECK: bitcast <16 x i8> %{{.*}} to <2 x i64>
+// CHECK: shufflevector <2 x i64>
+// CHECK: call void @llvm.arm.neon.vst1.v1i64
+}
+
+void t2(uint64_t *src1, uint8_t *src2, uint64x2_t *dst) {
+// CHECK: @t2
+    uint64x2_t q = vld1q_u64(src1);
+// CHECK: call <2 x i64> @llvm.arm.neon.vld1.v2i64
+    q = vld1q_lane_u64(src2, q, 0);
+// CHECK: shufflevector <2 x i64>
+// CHECK: call <1 x i64> @llvm.arm.neon.vld1.v1i64
+// CHECK: shufflevector <1 x i64>
+    *dst = q;
+// CHECK: store <2 x i64>
+}
diff --git a/test/CodeGen/complex-builtints.c b/test/CodeGen/complex-builtints.c
new file mode 100644
index 0000000..09219cf
--- /dev/null
+++ b/test/CodeGen/complex-builtints.c
@@ -0,0 +1,71 @@
+// RUN: %clang_cc1 %s -O1 -emit-llvm -o - | FileCheck %s
+// rdar://8315199
+
+/* Test for builtin conj, creal, cimag.  */
+/* Origin: Joseph Myers <jsm28@cam.ac.uk> */
+
+extern float _Complex conjf (float _Complex);
+extern double _Complex conj (double _Complex);
+extern long double _Complex conjl (long double _Complex);
+
+extern float crealf (float _Complex);
+extern double creal (double _Complex);
+extern long double creall (long double _Complex);
+
+extern float cimagf (float _Complex);
+extern double cimag (double _Complex);
+extern long double cimagl (long double _Complex);
+
+extern void abort (void);
+extern void link_error (void);
+
+int
+main ()
+{
+  /* For each type, test both runtime and compile time (constant folding)
+     optimization.  */
+  volatile float _Complex fc = 1.0F + 2.0iF;
+  volatile double _Complex dc = 1.0 + 2.0i;
+  volatile long double _Complex ldc = 1.0L + 2.0iL;
+  /* Test floats.  */
+  if (__builtin_conjf (fc) != 1.0F - 2.0iF)
+    abort ();
+  if (__builtin_conjf (1.0F + 2.0iF) != 1.0F - 2.0iF)
+    link_error ();
+  if (__builtin_crealf (fc) != 1.0F)
+    abort ();
+  if (__builtin_crealf (1.0F + 2.0iF) != 1.0F)
+    link_error ();
+  if (__builtin_cimagf (fc) != 2.0F)
+    abort ();
+  if (__builtin_cimagf (1.0F + 2.0iF) != 2.0F)
+    link_error ();
+  /* Test doubles.  */
+  if (__builtin_conj (dc) != 1.0 - 2.0i)
+    abort ();
+  if (__builtin_conj (1.0 + 2.0i) != 1.0 - 2.0i)
+    link_error ();
+  if (__builtin_creal (dc) != 1.0)
+    abort ();
+  if (__builtin_creal (1.0 + 2.0i) != 1.0)
+    link_error ();
+  if (__builtin_cimag (dc) != 2.0)
+    abort ();
+  if (__builtin_cimag (1.0 + 2.0i) != 2.0)
+    link_error ();
+  /* Test long doubles.  */
+  if (__builtin_conjl (ldc) != 1.0L - 2.0iL)
+    abort ();
+  if (__builtin_conjl (1.0L + 2.0iL) != 1.0L - 2.0iL)
+    link_error ();
+  if (__builtin_creall (ldc) != 1.0L)
+    abort ();
+  if (__builtin_creall (1.0L + 2.0iL) != 1.0L)
+    link_error ();
+  if (__builtin_cimagl (ldc) != 2.0L)
+    abort ();
+  if (__builtin_cimagl (1.0L + 2.0iL) != 2.0L)
+    link_error ();
+}
+
+// CHECK-NOT: link_error
diff --git a/test/CodeGen/ms-inline-asm.c b/test/CodeGen/ms-inline-asm.c
index 8c3e5f7..c140d60 100644
--- a/test/CodeGen/ms-inline-asm.c
+++ b/test/CodeGen/ms-inline-asm.c
@@ -9,7 +9,9 @@ void t1() {
 
 void t2() {
 // CHECK: @t2
-// CHECK: call void asm sideeffect "nop\0Anop\0Anop", "~{dirflag},~{fpsr},~{flags}"() nounwind ia_nsdialect
+// CHECK: call void asm sideeffect "nop", "~{dirflag},~{fpsr},~{flags}"() nounwind ia_nsdialect
+// CHECK: call void asm sideeffect "nop", "~{dirflag},~{fpsr},~{flags}"() nounwind ia_nsdialect
+// CHECK: call void asm sideeffect "nop", "~{dirflag},~{fpsr},~{flags}"() nounwind ia_nsdialect
 // CHECK: ret void
   __asm nop
   __asm nop
@@ -25,7 +27,8 @@ void t3() {
 
 void t4(void) {
 // CHECK: @t4
-// CHECK: call void asm sideeffect "mov ebx, eax\0Amov ecx, ebx", "~{dirflag},~{fpsr},~{flags}"() nounwind ia_nsdialect
+// CHECK: call void asm sideeffect "mov ebx, eax", "~{ebx},~{dirflag},~{fpsr},~{flags}"() nounwind ia_nsdialect
+// CHECK: call void asm sideeffect "mov ecx, ebx", "~{ecx},~{dirflag},~{fpsr},~{flags}"() nounwind ia_nsdialect
 // CHECK: ret void
   __asm mov ebx, eax
   __asm mov ecx, ebx
@@ -33,8 +36,85 @@ void t4(void) {
 
 void t5(void) {
 // CHECK: @t5
-// CHECK: call void asm sideeffect "mov ebx, eax\0Amov ecx, ebx", "~{dirflag},~{fpsr},~{flags}"() nounwind ia_nsdialect
+// CHECK: call void asm sideeffect "mov ebx, eax\0Amov ecx, ebx", "~{ebx},~{ecx},~{dirflag},~{fpsr},~{flags}"() nounwind ia_nsdialect
 // CHECK: ret void
   __asm mov ebx, eax __asm mov ecx, ebx
 }
 
+void t6(void) {
+  __asm int 0x2c
+// CHECK: t6
+// CHECK: call void asm sideeffect "int 0x2c", "~{dirflag},~{fpsr},~{flags}"() nounwind ia_nsdialect
+}
+
+void* t7(void) {
+  __asm mov eax, fs:[0x10]
+// CHECK: t7
+// CHECK: call void asm sideeffect "mov eax, fs:[0x10]", "~{dirflag},~{fpsr},~{flags}"() nounwind ia_nsdialect
+}
+
+void t8() {
+  __asm {
+    int 0x2c ; } asm comments are fun! }{
+  }
+  __asm {}
+// CHECK: t8
+// CHECK: call void asm sideeffect "int 0x2c", "~{dirflag},~{fpsr},~{flags}"() nounwind ia_nsdialect
+// CHECK: call void asm sideeffect "", "~{dirflag},~{fpsr},~{flags}"() nounwind ia_nsdialect
+}
+int t9() {
+  __asm int 3 ; } comments for single-line asm
+  __asm {}
+  __asm int 4
+  return 10;
+// CHECK: t9
+// CHECK: call void asm sideeffect "int 3", "~{dirflag},~{fpsr},~{flags}"() nounwind ia_nsdialect
+// CHECK: call void asm sideeffect "", "~{dirflag},~{fpsr},~{flags}"() nounwind ia_nsdialect
+// CHECK: call void asm sideeffect "int 4", "~{dirflag},~{fpsr},~{flags}"() nounwind ia_nsdialect
+// CHECK: ret i32 10
+}
+void t10() {
+  __asm {
+    push ebx
+    mov ebx, 0x07
+    pop ebx
+  }
+// CHECK: t10
+// CHECK: call void asm sideeffect "push ebx\0Amov ebx, 0x07\0Apop ebx", "~{ebx},~{dirflag},~{fpsr},~{flags}"() nounwind ia_nsdialect
+}
+
+unsigned t11(void) {
+  unsigned i = 1, j;
+  __asm {
+    mov eax, i
+    mov j, eax
+  }
+  return j;
+// CHECK: t11
+// CHECK: [[I:%[a-zA-Z0-9]+]] = alloca i32, align 4
+// CHECK: [[J:%[a-zA-Z0-9]+]] = alloca i32, align 4
+// CHECK: store i32 1, i32* [[I]], align 4
+// CHECK: call void asm sideeffect "mov eax, i\0Amov j, eax", "~{dirflag},~{fpsr},~{flags}"() nounwind ia_nsdialect
+// CHECK: [[RET:%[a-zA-Z0-9]+]] = load i32* [[J]], align 4
+// CHECK: ret i32 [[RET]]
+}
+
+void t12(void) {
+  __asm EVEN
+  __asm ALIGN
+}
+
+void t13(void) {
+  __asm {
+    _emit 0x4A
+    _emit 0x43
+    _emit 0x4B
+  }
+}
+
+void t14(void) {
+  unsigned arr[10];
+  __asm LENGTH arr ; sizeof(arr)/sizeof(arr[0])
+  __asm SIZE arr   ; sizeof(arr)
+  __asm TYPE arr   ; sizeof(arr[0])
+}