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author | dim <dim@FreeBSD.org> | 2011-10-20 21:10:27 +0000 |
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committer | dim <dim@FreeBSD.org> | 2011-10-20 21:10:27 +0000 |
commit | 7b3392326c40c3c20697816acae597ba7b3144eb (patch) | |
tree | 2cbcf22585e99f8a87d12d5ff94f392c0d266819 /test/CodeGen/X86/avx-blend.ll | |
parent | 1176aa52646fe641a4243a246aa7f960c708a274 (diff) | |
download | FreeBSD-src-7b3392326c40c3c20697816acae597ba7b3144eb.zip FreeBSD-src-7b3392326c40c3c20697816acae597ba7b3144eb.tar.gz |
Vendor import of llvm release_30 branch r142614:
http://llvm.org/svn/llvm-project/llvm/branches/release_30@142614
Diffstat (limited to 'test/CodeGen/X86/avx-blend.ll')
-rw-r--r-- | test/CodeGen/X86/avx-blend.ll | 104 |
1 files changed, 104 insertions, 0 deletions
diff --git a/test/CodeGen/X86/avx-blend.ll b/test/CodeGen/X86/avx-blend.ll new file mode 100644 index 0000000..7729491 --- /dev/null +++ b/test/CodeGen/X86/avx-blend.ll @@ -0,0 +1,104 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -promote-elements -mattr=+avx | FileCheck %s + +; AVX128 tests: + +;CHECK: vsel_float +;CHECK: vblendvps +;CHECK: ret +define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) { + %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %v1, <4 x float> %v2 + ret <4 x float> %vsel +} + + +;CHECK: vsel_i32 +;CHECK: vblendvps +;CHECK: ret +define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) { + %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i32> %v1, <4 x i32> %v2 + ret <4 x i32> %vsel +} + + +;CHECK: vsel_double +;CHECK: vblendvpd +;CHECK: ret +define <2 x double> @vsel_double(<2 x double> %v1, <2 x double> %v2) { + %vsel = select <2 x i1> <i1 true, i1 false>, <2 x double> %v1, <2 x double> %v2 + ret <2 x double> %vsel +} + + +;CHECK: vsel_i64 +;CHECK: vblendvpd +;CHECK: ret +define <2 x i64> @vsel_i64(<2 x i64> %v1, <2 x i64> %v2) { + %vsel = select <2 x i1> <i1 true, i1 false>, <2 x i64> %v1, <2 x i64> %v2 + ret <2 x i64> %vsel +} + + +;CHECK: vsel_i8 +;CHECK: vpblendvb +;CHECK: ret +define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) { + %vsel = select <16 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <16 x i8> %v1, <16 x i8> %v2 + ret <16 x i8> %vsel +} + + +; AVX256 tests: + + +;CHECK: vsel_float +;CHECK: vblendvps +;CHECK: ret +define <8 x float> @vsel_float8(<8 x float> %v1, <8 x float> %v2) { + %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x float> %v1, <8 x float> %v2 + ret <8 x float> %vsel +} + +;CHECK: vsel_i32 +;CHECK: vblendvps +;CHECK: ret +define <8 x i32> @vsel_i328(<8 x i32> %v1, <8 x i32> %v2) { + %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i32> %v1, <8 x i32> %v2 + ret <8 x i32> %vsel +} + +;CHECK: vsel_double +;CHECK: vblendvpd +;CHECK: ret +define <8 x double> @vsel_double8(<8 x double> %v1, <8 x double> %v2) { + %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x double> %v1, <8 x double> %v2 + ret <8 x double> %vsel +} + +;CHECK: vsel_i64 +;CHECK: vblendvpd +;CHECK: ret +define <8 x i64> @vsel_i648(<8 x i64> %v1, <8 x i64> %v2) { + %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i64> %v1, <8 x i64> %v2 + ret <8 x i64> %vsel +} + +;; TEST blend + compares +; CHECK: A +define <2 x double> @A(<2 x double> %x, <2 x double> %y) { + ; CHECK: vcmplepd + ; CHECK: vblendvpd + %max_is_x = fcmp oge <2 x double> %x, %y + %max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y + ret <2 x double> %max +} + +; CHECK: B +define <2 x double> @B(<2 x double> %x, <2 x double> %y) { + ; CHECK: vcmpnlepd + ; CHECK: vblendvpd + %min_is_x = fcmp ult <2 x double> %x, %y + %min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y + ret <2 x double> %min +} + + |