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| author | dim <dim@FreeBSD.org> | 2012-08-15 19:34:23 +0000 |
|---|---|---|
| committer | dim <dim@FreeBSD.org> | 2012-08-15 19:34:23 +0000 |
| commit | 721c201bd55ffb73cb2ba8d39e0570fa38c44e15 (patch) | |
| tree | eacfc83d988e4b9d11114387ae7dc41243f2a363 /test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll | |
| parent | 2b2816e083a455f7a656ae88b0fd059d1688bb36 (diff) | |
| download | FreeBSD-src-721c201bd55ffb73cb2ba8d39e0570fa38c44e15.zip FreeBSD-src-721c201bd55ffb73cb2ba8d39e0570fa38c44e15.tar.gz | |
Vendor import of llvm trunk r161861:
http://llvm.org/svn/llvm-project/llvm/trunk@161861
Diffstat (limited to 'test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll')
| -rw-r--r-- | test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll b/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll new file mode 100644 index 0000000..94ded30 --- /dev/null +++ b/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll @@ -0,0 +1,44 @@ +; Positive test for inline register constraints +; +; RUN: llc -march=mipsel < %s | FileCheck %s + +define i32 @main() nounwind { +entry: + +; r with char +;CHECK: #APP +;CHECK: addi ${{[0-9]+}},${{[0-9]+}},23 +;CHECK: #NO_APP + tail call i8 asm sideeffect "addi $0,$1,$2", "=r,r,n"(i8 27, i8 23) nounwind + +; r with short +;CHECK: #APP +;CHECK: addi ${{[0-9]+}},${{[0-9]+}},13 +;CHECK: #NO_APP + tail call i16 asm sideeffect "addi $0,$1,$2", "=r,r,n"(i16 17, i16 13) nounwind + +; r with int +;CHECK: #APP +;CHECK: addi ${{[0-9]+}},${{[0-9]+}},3 +;CHECK: #NO_APP + tail call i32 asm sideeffect "addi $0,$1,$2", "=r,r,n"(i32 7, i32 3) nounwind + +; Now c with 1024: make sure register $25 is picked +; CHECK: #APP +; CHECK: addi $25,${{[0-9]+}},1024 +; CHECK: #NO_APP + tail call i32 asm sideeffect "addi $0,$1,$2", "=c,c,I"(i32 4194304, i32 1024) nounwind + +; Now l with 1024: make sure register lo is picked. We do this by checking the instruction +; after the inline expression for a mflo to pull the value out of lo. +; CHECK: #APP +; CHECK-NEXT: mtlo ${{[0-9]+}} +; CHECK-NEXT: madd ${{[0-9]+}},${{[0-9]+}} +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: mflo ${{[0-9]+}} + %bosco = alloca i32, align 4 + call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1,$2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind + store volatile i32 %4, i32* %bosco, align 4 + + ret i32 0 +} |
