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| author | dim <dim@FreeBSD.org> | 2012-08-15 19:34:23 +0000 |
|---|---|---|
| committer | dim <dim@FreeBSD.org> | 2012-08-15 19:34:23 +0000 |
| commit | 721c201bd55ffb73cb2ba8d39e0570fa38c44e15 (patch) | |
| tree | eacfc83d988e4b9d11114387ae7dc41243f2a363 /test/CodeGen/Mips/atomic.ll | |
| parent | 2b2816e083a455f7a656ae88b0fd059d1688bb36 (diff) | |
| download | FreeBSD-src-721c201bd55ffb73cb2ba8d39e0570fa38c44e15.zip FreeBSD-src-721c201bd55ffb73cb2ba8d39e0570fa38c44e15.tar.gz | |
Vendor import of llvm trunk r161861:
http://llvm.org/svn/llvm-project/llvm/trunk@161861
Diffstat (limited to 'test/CodeGen/Mips/atomic.ll')
| -rw-r--r-- | test/CodeGen/Mips/atomic.ll | 34 |
1 files changed, 25 insertions, 9 deletions
diff --git a/test/CodeGen/Mips/atomic.ll b/test/CodeGen/Mips/atomic.ll index a4763b1..050689d 100644 --- a/test/CodeGen/Mips/atomic.ll +++ b/test/CodeGen/Mips/atomic.ll @@ -8,7 +8,7 @@ entry: ret i32 %0 ; CHECK: AtomicLoadAdd32: -; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp) +; CHECK: lw $[[R0:[0-9]+]], %got(x) ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]]) ; CHECK: addu $[[R2:[0-9]+]], $[[R1]], $4 @@ -22,7 +22,7 @@ entry: ret i32 %0 ; CHECK: AtomicLoadNand32: -; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp) +; CHECK: lw $[[R0:[0-9]+]], %got(x) ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]]) ; CHECK: and $[[R3:[0-9]+]], $[[R1]], $4 @@ -40,7 +40,7 @@ entry: ret i32 %0 ; CHECK: AtomicSwap32: -; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp) +; CHECK: lw $[[R0:[0-9]+]], %got(x) ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll ${{[0-9]+}}, 0($[[R0]]) ; CHECK: sc $[[R2:[0-9]+]], 0($[[R0]]) @@ -56,7 +56,7 @@ entry: ret i32 %0 ; CHECK: AtomicCmpSwap32: -; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp) +; CHECK: lw $[[R0:[0-9]+]], %got(x) ; CHECK: $[[BB0:[A-Z_0-9]+]]: ; CHECK: ll $2, 0($[[R0]]) ; CHECK: bne $2, $4, $[[BB1:[A-Z_0-9]+]] @@ -75,7 +75,7 @@ entry: ret i8 %0 ; CHECK: AtomicLoadAdd8: -; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp) +; CHECK: lw $[[R0:[0-9]+]], %got(y) ; CHECK: addiu $[[R1:[0-9]+]], $zero, -4 ; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] ; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 @@ -106,7 +106,7 @@ entry: ret i8 %0 ; CHECK: AtomicLoadSub8: -; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp) +; CHECK: lw $[[R0:[0-9]+]], %got(y) ; CHECK: addiu $[[R1:[0-9]+]], $zero, -4 ; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] ; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 @@ -137,7 +137,7 @@ entry: ret i8 %0 ; CHECK: AtomicLoadNand8: -; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp) +; CHECK: lw $[[R0:[0-9]+]], %got(y) ; CHECK: addiu $[[R1:[0-9]+]], $zero, -4 ; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] ; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 @@ -169,7 +169,7 @@ entry: ret i8 %0 ; CHECK: AtomicSwap8: -; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp) +; CHECK: lw $[[R0:[0-9]+]], %got(y) ; CHECK: addiu $[[R1:[0-9]+]], $zero, -4 ; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] ; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 @@ -198,7 +198,7 @@ entry: ret i8 %0 ; CHECK: AtomicCmpSwap8: -; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp) +; CHECK: lw $[[R0:[0-9]+]], %got(y) ; CHECK: addiu $[[R1:[0-9]+]], $zero, -4 ; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] ; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 @@ -242,3 +242,19 @@ entry: ; CHECK: sync 0 } +; make sure that this assertion in +; TwoAddressInstructionPass::TryInstructionTransform does not fail: +; +; line 1203: assert(TargetRegisterInfo::isVirtualRegister(regB) && +; +; it failed when MipsDAGToDAGISel::ReplaceUsesWithZeroReg replaced an +; operand of an atomic instruction with register $zero. +@a = external global i32 + +define i32 @zeroreg() nounwind { +entry: + %0 = cmpxchg i32* @a, i32 1, i32 0 seq_cst + %1 = icmp eq i32 %0, 1 + %conv = zext i1 %1 to i32 + ret i32 %conv +} |
