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authored <ed@FreeBSD.org>2009-06-23 14:50:01 +0000
committered <ed@FreeBSD.org>2009-06-23 14:50:01 +0000
commit4d74f68bdcfeab629970a41b69b96ac709b08a2b (patch)
tree6be075b410677415707e0987e3a49123130cef22 /test/CodeGen/ARM/vtst.ll
parenta4c19d68f13cf0a83bc0da53bd6d547fcaf635fe (diff)
downloadFreeBSD-src-4d74f68bdcfeab629970a41b69b96ac709b08a2b.zip
FreeBSD-src-4d74f68bdcfeab629970a41b69b96ac709b08a2b.tar.gz
Import LLVM r73954.
Diffstat (limited to 'test/CodeGen/ARM/vtst.ll')
-rw-r--r--test/CodeGen/ARM/vtst.ll52
1 files changed, 52 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/vtst.ll b/test/CodeGen/ARM/vtst.ll
new file mode 100644
index 0000000..d4f7d2a
--- /dev/null
+++ b/test/CodeGen/ARM/vtst.ll
@@ -0,0 +1,52 @@
+; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
+; RUN: grep {vtst\\.i8} %t | count 2
+; RUN: grep {vtst\\.i16} %t | count 2
+; RUN: grep {vtst\\.i32} %t | count 2
+
+define <8 x i8> @vtsti8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+ %tmp1 = load <8 x i8>* %A
+ %tmp2 = load <8 x i8>* %B
+ %tmp3 = and <8 x i8> %tmp1, %tmp2
+ %tmp4 = vicmp ne <8 x i8> %tmp3, zeroinitializer
+ ret <8 x i8> %tmp4
+}
+
+define <4 x i16> @vtsti16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+ %tmp1 = load <4 x i16>* %A
+ %tmp2 = load <4 x i16>* %B
+ %tmp3 = and <4 x i16> %tmp1, %tmp2
+ %tmp4 = vicmp ne <4 x i16> %tmp3, zeroinitializer
+ ret <4 x i16> %tmp4
+}
+
+define <2 x i32> @vtsti32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+ %tmp1 = load <2 x i32>* %A
+ %tmp2 = load <2 x i32>* %B
+ %tmp3 = and <2 x i32> %tmp1, %tmp2
+ %tmp4 = vicmp ne <2 x i32> %tmp3, zeroinitializer
+ ret <2 x i32> %tmp4
+}
+
+define <16 x i8> @vtstQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+ %tmp1 = load <16 x i8>* %A
+ %tmp2 = load <16 x i8>* %B
+ %tmp3 = and <16 x i8> %tmp1, %tmp2
+ %tmp4 = vicmp ne <16 x i8> %tmp3, zeroinitializer
+ ret <16 x i8> %tmp4
+}
+
+define <8 x i16> @vtstQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
+ %tmp1 = load <8 x i16>* %A
+ %tmp2 = load <8 x i16>* %B
+ %tmp3 = and <8 x i16> %tmp1, %tmp2
+ %tmp4 = vicmp ne <8 x i16> %tmp3, zeroinitializer
+ ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vtstQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
+ %tmp1 = load <4 x i32>* %A
+ %tmp2 = load <4 x i32>* %B
+ %tmp3 = and <4 x i32> %tmp1, %tmp2
+ %tmp4 = vicmp ne <4 x i32> %tmp3, zeroinitializer
+ ret <4 x i32> %tmp4
+}
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