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| author | ed <ed@FreeBSD.org> | 2009-06-23 14:50:01 +0000 |
|---|---|---|
| committer | ed <ed@FreeBSD.org> | 2009-06-23 14:50:01 +0000 |
| commit | 4d74f68bdcfeab629970a41b69b96ac709b08a2b (patch) | |
| tree | 6be075b410677415707e0987e3a49123130cef22 /test/CodeGen/ARM/vand.ll | |
| parent | a4c19d68f13cf0a83bc0da53bd6d547fcaf635fe (diff) | |
| download | FreeBSD-src-4d74f68bdcfeab629970a41b69b96ac709b08a2b.zip FreeBSD-src-4d74f68bdcfeab629970a41b69b96ac709b08a2b.tar.gz | |
Import LLVM r73954.
Diffstat (limited to 'test/CodeGen/ARM/vand.ll')
| -rw-r--r-- | test/CodeGen/ARM/vand.ll | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/vand.ll b/test/CodeGen/ARM/vand.ll new file mode 100644 index 0000000..b3eaf1c --- /dev/null +++ b/test/CodeGen/ARM/vand.ll @@ -0,0 +1,59 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t +; RUN: grep vand %t | count 8 +; Note: function names do not include "vand" to allow simple grep for opcodes + +define <8 x i8> @v_andi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = and <8 x i8> %tmp1, %tmp2 + ret <8 x i8> %tmp3 +} + +define <4 x i16> @v_andi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = and <4 x i16> %tmp1, %tmp2 + ret <4 x i16> %tmp3 +} + +define <2 x i32> @v_andi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = and <2 x i32> %tmp1, %tmp2 + ret <2 x i32> %tmp3 +} + +define <1 x i64> @v_andi64(<1 x i64>* %A, <1 x i64>* %B) nounwind { + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = and <1 x i64> %tmp1, %tmp2 + ret <1 x i64> %tmp3 +} + +define <16 x i8> @v_andQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = and <16 x i8> %tmp1, %tmp2 + ret <16 x i8> %tmp3 +} + +define <8 x i16> @v_andQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = and <8 x i16> %tmp1, %tmp2 + ret <8 x i16> %tmp3 +} + +define <4 x i32> @v_andQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = and <4 x i32> %tmp1, %tmp2 + ret <4 x i32> %tmp3 +} + +define <2 x i64> @v_andQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = and <2 x i64> %tmp1, %tmp2 + ret <2 x i64> %tmp3 +} |
