summaryrefslogtreecommitdiffstats
path: root/test/CodeGen/ARM/misched-copy-arm.ll
diff options
context:
space:
mode:
authordim <dim@FreeBSD.org>2013-06-10 20:36:52 +0000
committerdim <dim@FreeBSD.org>2013-06-10 20:36:52 +0000
commitaa45f148926e3461a1fd8b10c990f0a51a908cc9 (patch)
tree909310b2e05119d1d6efda049977042abbb58bb1 /test/CodeGen/ARM/misched-copy-arm.ll
parent169d2bd06003c39970bc94c99669a34b61bb7e45 (diff)
downloadFreeBSD-src-aa45f148926e3461a1fd8b10c990f0a51a908cc9.zip
FreeBSD-src-aa45f148926e3461a1fd8b10c990f0a51a908cc9.tar.gz
Vendor import of llvm tags/RELEASE_33/final r183502 (effectively, 3.3
release): http://llvm.org/svn/llvm-project/llvm/tags/RELEASE_33/final@183502
Diffstat (limited to 'test/CodeGen/ARM/misched-copy-arm.ll')
-rw-r--r--test/CodeGen/ARM/misched-copy-arm.ll30
1 files changed, 30 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/misched-copy-arm.ll b/test/CodeGen/ARM/misched-copy-arm.ll
new file mode 100644
index 0000000..4b15326
--- /dev/null
+++ b/test/CodeGen/ARM/misched-copy-arm.ll
@@ -0,0 +1,30 @@
+; REQUIRES: asserts
+; RUN: llc < %s -march=thumb -mcpu=swift -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
+;
+; Loop counter copies should be eliminated.
+; There is also a MUL here, but we don't care where it is scheduled.
+; CHECK: postinc
+; CHECK: *** Final schedule for BB#2 ***
+; CHECK: t2LDRs
+; CHECK: t2ADDrr
+; CHECK: t2CMPrr
+; CHECK: COPY
+define i32 @postinc(i32 %a, i32* nocapture %d, i32 %s) nounwind {
+entry:
+ %cmp4 = icmp eq i32 %a, 0
+ br i1 %cmp4, label %for.end, label %for.body
+
+for.body: ; preds = %entry, %for.body
+ %indvars.iv = phi i32 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
+ %s.05 = phi i32 [ %mul, %for.body ], [ 0, %entry ]
+ %indvars.iv.next = add i32 %indvars.iv, %s
+ %arrayidx = getelementptr inbounds i32* %d, i32 %indvars.iv
+ %0 = load i32* %arrayidx, align 4
+ %mul = mul nsw i32 %0, %s.05
+ %exitcond = icmp eq i32 %indvars.iv.next, %a
+ br i1 %exitcond, label %for.end, label %for.body
+
+for.end: ; preds = %for.body, %entry
+ %s.0.lcssa = phi i32 [ 0, %entry ], [ %mul, %for.body ]
+ ret i32 %s.0.lcssa
+}
OpenPOWER on IntegriCloud