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author | dim <dim@FreeBSD.org> | 2012-04-14 13:54:10 +0000 |
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committer | dim <dim@FreeBSD.org> | 2012-04-14 13:54:10 +0000 |
commit | 1fc08f5e9ef733ef1ce6f363fecedc2260e78974 (patch) | |
tree | 19c69a04768629f2d440944b71cbe90adae0b615 /test/CodeGen/ARM/fast-isel-fold.ll | |
parent | 07637c87f826cdf411f0673595e9bc92ebd793f2 (diff) | |
download | FreeBSD-src-1fc08f5e9ef733ef1ce6f363fecedc2260e78974.zip FreeBSD-src-1fc08f5e9ef733ef1ce6f363fecedc2260e78974.tar.gz |
Vendor import of llvm trunk r154661:
http://llvm.org/svn/llvm-project/llvm/trunk@r154661
Diffstat (limited to 'test/CodeGen/ARM/fast-isel-fold.ll')
-rw-r--r-- | test/CodeGen/ARM/fast-isel-fold.ll | 80 |
1 files changed, 80 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/fast-isel-fold.ll b/test/CodeGen/ARM/fast-isel-fold.ll new file mode 100644 index 0000000..61bd185 --- /dev/null +++ b/test/CodeGen/ARM/fast-isel-fold.ll @@ -0,0 +1,80 @@ +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB + +@a = global i8 1, align 1 +@b = global i16 2, align 2 + +define void @t1() nounwind uwtable ssp { +; ARM: t1 +; ARM: ldrb +; ARM-NOT: uxtb +; THUMB: t1 +; THUMB: ldrb +; THUMB-NOT: uxtb + %1 = load i8* @a, align 1 + call void @foo1(i8 zeroext %1) + ret void +} + +define void @t2() nounwind uwtable ssp { +; ARM: t2 +; ARM: ldrh +; ARM-NOT: uxth +; THUMB: t2 +; THUMB: ldrh +; THUMB-NOT: uxth + %1 = load i16* @b, align 2 + call void @foo2(i16 zeroext %1) + ret void +} + +declare void @foo1(i8 zeroext) +declare void @foo2(i16 zeroext) + +define i32 @t3() nounwind uwtable ssp { +; ARM: t3 +; ARM: ldrb +; ARM-NOT: uxtb +; THUMB: t3 +; THUMB: ldrb +; THUMB-NOT: uxtb + %1 = load i8* @a, align 1 + %2 = zext i8 %1 to i32 + ret i32 %2 +} + +define i32 @t4() nounwind uwtable ssp { +; ARM: t4 +; ARM: ldrh +; ARM-NOT: uxth +; THUMB: t4 +; THUMB: ldrh +; THUMB-NOT: uxth + %1 = load i16* @b, align 2 + %2 = zext i16 %1 to i32 + ret i32 %2 +} + +define i32 @t5() nounwind uwtable ssp { +; ARM: t5 +; ARM: ldrsh +; ARM-NOT: sxth +; THUMB: t5 +; THUMB: ldrsh +; THUMB-NOT: sxth + %1 = load i16* @b, align 2 + %2 = sext i16 %1 to i32 + ret i32 %2 +} + +define i32 @t6() nounwind uwtable ssp { +; ARM: t6 +; ARM: ldrsb +; ARM-NOT: sxtb +; THUMB: t6 +; THUMB: ldrsb +; THUMB-NOT: sxtb + %1 = load i8* @a, align 2 + %2 = sext i8 %1 to i32 + ret i32 %2 +} |