Workaround buggy BIOS code in USB regard. By doing the BIOS to OS handover for

all host controllers at the same time, we avoid problems where the BIOS will
actually write to the USB registers of all the USB host controllers every time
we handover one of them, and consequently reset the OS programmed values.

Submitted by:	avg
Reviewed by:	jhb

16 files changed, 535 insertions, 282 deletions

diff --git a/sys/dev/pci/pci.c b/sys/dev/pci/pci.c
index 47aedbd..e60ee23 100644
--- a/sys/dev/pci/pci.c
+++ b/sys/dev/pci/pci.c
@@ -62,6 +62,10 @@ __FBSDID("$FreeBSD$");
 #include <dev/pci/pcivar.h>
 #include <dev/pci/pci_private.h>
 
+#include <dev/usb/controller/ehcireg.h>
+#include <dev/usb/controller/ohcireg.h>
+#include <dev/usb/controller/uhcireg.h>
+
 #include "pcib_if.h"
 #include "pci_if.h"
 
@@ -270,6 +274,13 @@ TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
     &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI");
 
+static int pci_usb_takeover = 1;
+TUNABLE_INT("hw.pci.usb_early_takeover", &pci_usb_takeover);
+SYSCTL_INT(_hw_pci, OID_AUTO, usb_early_takeover, CTLFLAG_RD | CTLFLAG_TUN,
+    &pci_usb_takeover, 1, "Enable early takeover of USB controllers.\n\
+Disable this if you depend on BIOS emulation of USB devices, that is\n\
+you use USB devices (like keyboard or mouse) but do not load USB drivers");
+
 /* Find a device_t by bus/slot/function in domain 0 */
 
 device_t
@@ -2569,6 +2580,106 @@ pci_assign_interrupt(device_t bus, device_t dev, int force_route)
 	resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
 }
 
+/* Perform early OHCI takeover from SMM. */
+static void
+ohci_early_takeover(device_t self)
+{
+	struct resource *res;
+	uint32_t ctl;
+	int rid;
+	int i;
+
+	rid = PCIR_BAR(0);
+	res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
+	if (res == NULL)
+		return;
+
+	ctl = bus_read_4(res, OHCI_CONTROL);
+	if (ctl & OHCI_IR) {
+		if (bootverbose)
+			printf("ohci early: "
+			    "SMM active, request owner change\n");
+		bus_write_4(res, OHCI_COMMAND_STATUS, OHCI_OCR);
+		for (i = 0; (i < 100) && (ctl & OHCI_IR); i++) {
+			DELAY(1000);
+			ctl = bus_read_4(res, OHCI_CONTROL);
+		}
+		if (ctl & OHCI_IR) {
+			if (bootverbose)
+				printf("ohci early: "
+				    "SMM does not respond, resetting\n");
+			bus_write_4(res, OHCI_CONTROL, OHCI_HCFS_RESET);
+		}
+	}
+
+	bus_release_resource(self, SYS_RES_MEMORY, rid, res);
+}
+
+/* Perform early UHCI takeover from SMM. */
+static void
+uhci_early_takeover(device_t self)
+{
+	/*
+	 * Set the PIRQD enable bit and switch off all the others. We don't
+	 * want legacy support to interfere with us XXX Does this also mean
+	 * that the BIOS won't touch the keyboard anymore if it is connected
+	 * to the ports of the root hub?
+	 */
+	pci_write_config(self, PCI_LEGSUP, PCI_LEGSUP_USBPIRQDEN, 2);
+}
+
+/* Perform early EHCI takeover from SMM. */
+static void
+ehci_early_takeover(device_t self)
+{
+	struct resource *res;
+	uint32_t cparams;
+	uint32_t eec;
+	uint8_t eecp;
+	uint8_t bios_sem;
+	int rid;
+	int i;
+
+	rid = PCIR_BAR(0);
+	res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
+	if (res == NULL)
+		return;
+
+	cparams = bus_read_4(res, EHCI_HCCPARAMS);
+
+	/* Synchronise with the BIOS if it owns the controller. */
+	for (eecp = EHCI_HCC_EECP(cparams); eecp != 0;
+	    eecp = EHCI_EECP_NEXT(eec)) {
+		eec = pci_read_config(self, eecp, 4);
+		if (EHCI_EECP_ID(eec) != EHCI_EC_LEGSUP) {
+			continue;
+		}
+		bios_sem = pci_read_config(self, eecp +
+		    EHCI_LEGSUP_BIOS_SEM, 1);
+		if (bios_sem == 0) {
+			continue;
+		}
+		if (bootverbose)
+			printf("ehci early: "
+			    "SMM active, request owner change\n");
+
+		pci_write_config(self, eecp + EHCI_LEGSUP_OS_SEM, 1, 1);
+
+		for (i = 0; (i < 100) && (bios_sem != 0); i++) {
+			DELAY(1000);
+			bios_sem = pci_read_config(self, eecp +
+			    EHCI_LEGSUP_BIOS_SEM, 1);
+		}
+
+		if (bios_sem != 0) {
+			if (bootverbose)
+				printf("ehci early: "
+				    "SMM does not respond\n");
+		}
+	}
+	bus_release_resource(self, SYS_RES_MEMORY, rid, res);
+}
+
 void
 pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask)
 {
@@ -2612,6 +2723,16 @@ pci_add_resources(device_t bus, device_t dev, int force, uint32_t prefetchmask)
 		pci_assign_interrupt(bus, dev, 0);
 #endif
 	}
+
+	if (pci_usb_takeover && pci_get_class(dev) == PCIC_SERIALBUS &&
+	    pci_get_subclass(dev) == PCIS_SERIALBUS_USB) {
+		if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_EHCI)
+			ehci_early_takeover(dev);
+		else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_OHCI)
+			ohci_early_takeover(dev);
+		else if (pci_get_progif(dev) == PCIP_SERIALBUS_USB_UHCI)
+			uhci_early_takeover(dev);
+	}
 }
 
 void
diff --git a/sys/dev/usb/controller/ehci.c b/sys/dev/usb/controller/ehci.c
index 7dc5d31..42b78c3 100644
--- a/sys/dev/usb/controller/ehci.c
+++ b/sys/dev/usb/controller/ehci.c
@@ -83,6 +83,7 @@ __FBSDID("$FreeBSD$");
 #include <dev/usb/usb_controller.h>
 #include <dev/usb/usb_bus.h>
 #include <dev/usb/controller/ehci.h>
+#include <dev/usb/controller/ehcireg.h>
 
 #define	EHCI_BUS2SC(bus) \
    ((ehci_softc_t *)(((uint8_t *)(bus)) - \
diff --git a/sys/dev/usb/controller/ehci.h b/sys/dev/usb/controller/ehci.h
index 0868bc8..32c0835 100644
--- a/sys/dev/usb/controller/ehci.h
+++ b/sys/dev/usb/controller/ehci.h
@@ -40,139 +40,6 @@
 
 #define	EHCI_MAX_DEVICES MIN(USB_MAX_DEVICES, 128)
 
-/* PCI config registers  */
-#define	PCI_CBMEM		0x10	/* configuration base MEM */
-#define	PCI_INTERFACE_EHCI	0x20
-#define	PCI_USBREV		0x60	/* RO USB protocol revision */
-#define	PCI_USB_REV_MASK	0xff
-#define	PCI_USB_REV_PRE_1_0	0x00
-#define	PCI_USB_REV_1_0		0x10
-#define	PCI_USB_REV_1_1		0x11
-#define	PCI_USB_REV_2_0		0x20
-#define	PCI_EHCI_FLADJ		0x61	/* RW Frame len adj, SOF=59488+6*fladj */
-#define	PCI_EHCI_PORTWAKECAP	0x62	/* RW Port wake caps (opt)  */
-
-/* EHCI Extended Capabilities */
-#define	EHCI_EC_LEGSUP		0x01
-#define	EHCI_EECP_NEXT(x)	(((x) >> 8) & 0xff)
-#define	EHCI_EECP_ID(x)		((x) & 0xff)
-
-/* Legacy support extended capability */
-#define	EHCI_LEGSUP_BIOS_SEM		0x02
-#define	EHCI_LEGSUP_OS_SEM		0x03
-#define	EHCI_LEGSUP_USBLEGCTLSTS	0x04
-
-/* EHCI capability registers */
-#define	EHCI_CAPLENGTH		0x00	/* RO Capability register length field */
-/* reserved			0x01 */
-#define	EHCI_HCIVERSION		0x02	/* RO Interface version number */
-#define	EHCI_HCSPARAMS		0x04	/* RO Structural parameters */
-#define	EHCI_HCS_DEBUGPORT(x)	(((x) >> 20) & 0xf)
-#define	EHCI_HCS_P_INDICATOR(x) ((x) & 0x10000)
-#define	EHCI_HCS_N_CC(x)	(((x) >> 12) & 0xf)	/* # of companion ctlrs */
-#define	EHCI_HCS_N_PCC(x)	(((x) >> 8) & 0xf)	/* # of ports per comp. */
-#define	EHCI_HCS_PPC(x)		((x) & 0x10)	/* port power control */
-#define	EHCI_HCS_N_PORTS(x)	((x) & 0xf)	/* # of ports */
-#define	EHCI_HCCPARAMS		0x08	/* RO Capability parameters */
-#define	EHCI_HCC_EECP(x)	(((x) >> 8) & 0xff)	/* extended ports caps */
-#define	EHCI_HCC_IST(x)		(((x) >> 4) & 0xf)	/* isoc sched threshold */
-#define	EHCI_HCC_ASPC(x)	((x) & 0x4)	/* async sched park cap */
-#define	EHCI_HCC_PFLF(x)	((x) & 0x2)	/* prog frame list flag */
-#define	EHCI_HCC_64BIT(x)	((x) & 0x1)	/* 64 bit address cap */
-#define	EHCI_HCSP_PORTROUTE	0x0c	/* RO Companion port route description */
-
-/* EHCI operational registers.  Offset given by EHCI_CAPLENGTH register */
-#define	EHCI_USBCMD		0x00	/* RO, RW, WO Command register */
-#define	EHCI_CMD_ITC_M		0x00ff0000	/* RW interrupt threshold ctrl */
-#define	EHCI_CMD_ITC_1		0x00010000
-#define	EHCI_CMD_ITC_2		0x00020000
-#define	EHCI_CMD_ITC_4		0x00040000
-#define	EHCI_CMD_ITC_8		0x00080000
-#define	EHCI_CMD_ITC_16		0x00100000
-#define	EHCI_CMD_ITC_32		0x00200000
-#define	EHCI_CMD_ITC_64		0x00400000
-#define	EHCI_CMD_ASPME		0x00000800	/* RW/RO async park enable */
-#define	EHCI_CMD_ASPMC		0x00000300	/* RW/RO async park count */
-#define	EHCI_CMD_LHCR		0x00000080	/* RW light host ctrl reset */
-#define	EHCI_CMD_IAAD		0x00000040	/* RW intr on async adv door
-						 * bell */
-#define	EHCI_CMD_ASE		0x00000020	/* RW async sched enable */
-#define	EHCI_CMD_PSE		0x00000010	/* RW periodic sched enable */
-#define	EHCI_CMD_FLS_M		0x0000000c	/* RW/RO frame list size */
-#define	EHCI_CMD_FLS(x)		(((x) >> 2) & 3)	/* RW/RO frame list size */
-#define	EHCI_CMD_HCRESET	0x00000002	/* RW reset */
-#define	EHCI_CMD_RS		0x00000001	/* RW run/stop */
-#define	EHCI_USBSTS		0x04	/* RO, RW, RWC Status register */
-#define	EHCI_STS_ASS		0x00008000	/* RO async sched status */
-#define	EHCI_STS_PSS		0x00004000	/* RO periodic sched status */
-#define	EHCI_STS_REC		0x00002000	/* RO reclamation */
-#define	EHCI_STS_HCH		0x00001000	/* RO host controller halted */
-#define	EHCI_STS_IAA		0x00000020	/* RWC interrupt on async adv */
-#define	EHCI_STS_HSE		0x00000010	/* RWC host system error */
-#define	EHCI_STS_FLR		0x00000008	/* RWC frame list rollover */
-#define	EHCI_STS_PCD		0x00000004	/* RWC port change detect */
-#define	EHCI_STS_ERRINT		0x00000002	/* RWC error interrupt */
-#define	EHCI_STS_INT		0x00000001	/* RWC interrupt */
-#define	EHCI_STS_INTRS(x)	((x) & 0x3f)
-
-/*
- * NOTE: the doorbell interrupt is enabled, but the doorbell is never
- * used! SiS chipsets require this.
- */
-#define	EHCI_NORMAL_INTRS	(EHCI_STS_IAA | EHCI_STS_HSE |	\
-				EHCI_STS_PCD | EHCI_STS_ERRINT | EHCI_STS_INT)
-
-#define	EHCI_USBINTR		0x08	/* RW Interrupt register */
-#define	EHCI_INTR_IAAE		0x00000020	/* interrupt on async advance
-						 * ena */
-#define	EHCI_INTR_HSEE		0x00000010	/* host system error ena */
-#define	EHCI_INTR_FLRE		0x00000008	/* frame list rollover ena */
-#define	EHCI_INTR_PCIE		0x00000004	/* port change ena */
-#define	EHCI_INTR_UEIE		0x00000002	/* USB error intr ena */
-#define	EHCI_INTR_UIE		0x00000001	/* USB intr ena */
-
-#define	EHCI_FRINDEX		0x0c	/* RW Frame Index register */
-
-#define	EHCI_CTRLDSSEGMENT	0x10	/* RW Control Data Structure Segment */
-
-#define	EHCI_PERIODICLISTBASE	0x14	/* RW Periodic List Base */
-#define	EHCI_ASYNCLISTADDR	0x18	/* RW Async List Base */
-
-#define	EHCI_CONFIGFLAG		0x40	/* RW Configure Flag register */
-#define	EHCI_CONF_CF		0x00000001	/* RW configure flag */
-
-#define	EHCI_PORTSC(n)		(0x40+(4*(n)))	/* RO, RW, RWC Port Status reg */
-#define	EHCI_PS_WKOC_E		0x00400000	/* RW wake on over current ena */
-#define	EHCI_PS_WKDSCNNT_E	0x00200000	/* RW wake on disconnect ena */
-#define	EHCI_PS_WKCNNT_E	0x00100000	/* RW wake on connect ena */
-#define	EHCI_PS_PTC		0x000f0000	/* RW port test control */
-#define	EHCI_PS_PIC		0x0000c000	/* RW port indicator control */
-#define	EHCI_PS_PO		0x00002000	/* RW port owner */
-#define	EHCI_PS_PP		0x00001000	/* RW,RO port power */
-#define	EHCI_PS_LS		0x00000c00	/* RO line status */
-#define	EHCI_PS_IS_LOWSPEED(x)	(((x) & EHCI_PS_LS) == 0x00000400)
-#define	EHCI_PS_PR		0x00000100	/* RW port reset */
-#define	EHCI_PS_SUSP		0x00000080	/* RW suspend */
-#define	EHCI_PS_FPR		0x00000040	/* RW force port resume */
-#define	EHCI_PS_OCC		0x00000020	/* RWC over current change */
-#define	EHCI_PS_OCA		0x00000010	/* RO over current active */
-#define	EHCI_PS_PEC		0x00000008	/* RWC port enable change */
-#define	EHCI_PS_PE		0x00000004	/* RW port enable */
-#define	EHCI_PS_CSC		0x00000002	/* RWC connect status change */
-#define	EHCI_PS_CS		0x00000001	/* RO connect status */
-#define	EHCI_PS_CLEAR		(EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
-
-#define	EHCI_USBMODE		0x68	/* RW USB Device mode register */
-#define	EHCI_UM_CM		0x00000003	/* R/WO Controller Mode */
-#define	EHCI_UM_CM_IDLE		0x0	/* Idle */
-#define	EHCI_UM_CM_HOST		0x3	/* Host Controller */
-#define	EHCI_UM_ES		0x00000004	/* R/WO Endian Select */
-#define	EHCI_UM_ES_LE		0x0	/* Little-endian byte alignment */
-#define	EHCI_UM_ES_BE		0x4	/* Big-endian byte alignment */
-#define	EHCI_UM_SDIS		0x00000010	/* R/WO Stream Disable Mode */
-
-#define	EHCI_PORT_RESET_COMPLETE	2	/* ms */
-
 /*
  * Alignment NOTE: structures must be aligned so that the hardware can index
  * without performing addition.
diff --git a/sys/dev/usb/controller/ehci_ixp4xx.c b/sys/dev/usb/controller/ehci_ixp4xx.c
index 7668d86..9f86614 100644
--- a/sys/dev/usb/controller/ehci_ixp4xx.c
+++ b/sys/dev/usb/controller/ehci_ixp4xx.c
@@ -62,6 +62,7 @@ __FBSDID("$FreeBSD$");
 #include <dev/usb/usb_controller.h>
 #include <dev/usb/usb_bus.h>
 #include <dev/usb/controller/ehci.h>
+#include <dev/usb/controller/ehcireg.h>
 
 #include <arm/xscale/ixp425/ixp425reg.h>
 #include <arm/xscale/ixp425/ixp425var.h>
diff --git a/sys/dev/usb/controller/ehci_mbus.c b/sys/dev/usb/controller/ehci_mbus.c
index 7076854..d3c0f4c 100644
--- a/sys/dev/usb/controller/ehci_mbus.c
+++ b/sys/dev/usb/controller/ehci_mbus.c
@@ -69,6 +69,7 @@ __FBSDID("$FreeBSD$");
 #include <dev/usb/usb_controller.h>
 #include <dev/usb/usb_bus.h>
 #include <dev/usb/controller/ehci.h>
+#include <dev/usb/controller/ehcireg.h>
 
 #include <arm/mv/mvreg.h>
 #include <arm/mv/mvvar.h>
diff --git a/sys/dev/usb/controller/ehci_pci.c b/sys/dev/usb/controller/ehci_pci.c
index 7978f4f..fc2035b 100644
--- a/sys/dev/usb/controller/ehci_pci.c
+++ b/sys/dev/usb/controller/ehci_pci.c
@@ -84,6 +84,7 @@ __FBSDID("$FreeBSD$");
 #include <dev/usb/usb_bus.h>
 #include <dev/usb/usb_pci.h>
 #include <dev/usb/controller/ehci.h>
+#include <dev/usb/controller/ehcireg.h>
 
 #define	PCI_EHCI_VENDORID_ACERLABS	0x10b9
 #define	PCI_EHCI_VENDORID_AMD		0x1022
diff --git a/sys/dev/usb/controller/ehcireg.h b/sys/dev/usb/controller/ehcireg.h
new file mode 100644
index 0000000..182d9d6
--- /dev/null
+++ b/sys/dev/usb/controller/ehcireg.h
@@ -0,0 +1,174 @@
+/* $FreeBSD$ */
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Lennart Augustsson (lennart@augustsson.net).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _EHCIREG_H_
+#define	_EHCIREG_H_
+
+/* PCI config registers  */
+#define	PCI_CBMEM		0x10	/* configuration base MEM */
+#define	PCI_INTERFACE_EHCI	0x20
+#define	PCI_USBREV		0x60	/* RO USB protocol revision */
+#define	PCI_USB_REV_MASK	0xff
+#define	PCI_USB_REV_PRE_1_0	0x00
+#define	PCI_USB_REV_1_0		0x10
+#define	PCI_USB_REV_1_1		0x11
+#define	PCI_USB_REV_2_0		0x20
+#define	PCI_EHCI_FLADJ		0x61	/* RW Frame len adj, SOF=59488+6*fladj */
+#define	PCI_EHCI_PORTWAKECAP	0x62	/* RW Port wake caps (opt)  */
+
+/* EHCI Extended Capabilities */
+#define	EHCI_EC_LEGSUP		0x01
+#define	EHCI_EECP_NEXT(x)	(((x) >> 8) & 0xff)
+#define	EHCI_EECP_ID(x)		((x) & 0xff)
+
+/* Legacy support extended capability */
+#define	EHCI_LEGSUP_BIOS_SEM		0x02
+#define	EHCI_LEGSUP_OS_SEM		0x03
+#define	EHCI_LEGSUP_USBLEGCTLSTS	0x04
+
+/* EHCI capability registers */
+#define	EHCI_CAPLENGTH		0x00	/* RO Capability register length field */
+/* reserved			0x01 */
+#define	EHCI_HCIVERSION		0x02	/* RO Interface version number */
+#define	EHCI_HCSPARAMS		0x04	/* RO Structural parameters */
+#define	EHCI_HCS_DEBUGPORT(x)	(((x) >> 20) & 0xf)
+#define	EHCI_HCS_P_INDICATOR(x) ((x) & 0x10000)
+#define	EHCI_HCS_N_CC(x)	(((x) >> 12) & 0xf)	/* # of companion ctlrs */
+#define	EHCI_HCS_N_PCC(x)	(((x) >> 8) & 0xf)	/* # of ports per comp. */
+#define	EHCI_HCS_PPC(x)		((x) & 0x10)	/* port power control */
+#define	EHCI_HCS_N_PORTS(x)	((x) & 0xf)	/* # of ports */
+#define	EHCI_HCCPARAMS		0x08	/* RO Capability parameters */
+#define	EHCI_HCC_EECP(x)	(((x) >> 8) & 0xff)	/* extended ports caps */
+#define	EHCI_HCC_IST(x)		(((x) >> 4) & 0xf)	/* isoc sched threshold */
+#define	EHCI_HCC_ASPC(x)	((x) & 0x4)	/* async sched park cap */
+#define	EHCI_HCC_PFLF(x)	((x) & 0x2)	/* prog frame list flag */
+#define	EHCI_HCC_64BIT(x)	((x) & 0x1)	/* 64 bit address cap */
+#define	EHCI_HCSP_PORTROUTE	0x0c	/* RO Companion port route description */
+
+/* EHCI operational registers.  Offset given by EHCI_CAPLENGTH register */
+#define	EHCI_USBCMD		0x00	/* RO, RW, WO Command register */
+#define	EHCI_CMD_ITC_M		0x00ff0000	/* RW interrupt threshold ctrl */
+#define	EHCI_CMD_ITC_1		0x00010000
+#define	EHCI_CMD_ITC_2		0x00020000
+#define	EHCI_CMD_ITC_4		0x00040000
+#define	EHCI_CMD_ITC_8		0x00080000
+#define	EHCI_CMD_ITC_16		0x00100000
+#define	EHCI_CMD_ITC_32		0x00200000
+#define	EHCI_CMD_ITC_64		0x00400000
+#define	EHCI_CMD_ASPME		0x00000800	/* RW/RO async park enable */
+#define	EHCI_CMD_ASPMC		0x00000300	/* RW/RO async park count */
+#define	EHCI_CMD_LHCR		0x00000080	/* RW light host ctrl reset */
+#define	EHCI_CMD_IAAD		0x00000040	/* RW intr on async adv door
+						 * bell */
+#define	EHCI_CMD_ASE		0x00000020	/* RW async sched enable */
+#define	EHCI_CMD_PSE		0x00000010	/* RW periodic sched enable */
+#define	EHCI_CMD_FLS_M		0x0000000c	/* RW/RO frame list size */
+#define	EHCI_CMD_FLS(x)		(((x) >> 2) & 3)	/* RW/RO frame list size */
+#define	EHCI_CMD_HCRESET	0x00000002	/* RW reset */
+#define	EHCI_CMD_RS		0x00000001	/* RW run/stop */
+#define	EHCI_USBSTS		0x04	/* RO, RW, RWC Status register */
+#define	EHCI_STS_ASS		0x00008000	/* RO async sched status */
+#define	EHCI_STS_PSS		0x00004000	/* RO periodic sched status */
+#define	EHCI_STS_REC		0x00002000	/* RO reclamation */
+#define	EHCI_STS_HCH		0x00001000	/* RO host controller halted */
+#define	EHCI_STS_IAA		0x00000020	/* RWC interrupt on async adv */
+#define	EHCI_STS_HSE		0x00000010	/* RWC host system error */
+#define	EHCI_STS_FLR		0x00000008	/* RWC frame list rollover */
+#define	EHCI_STS_PCD		0x00000004	/* RWC port change detect */
+#define	EHCI_STS_ERRINT		0x00000002	/* RWC error interrupt */
+#define	EHCI_STS_INT		0x00000001	/* RWC interrupt */
+#define	EHCI_STS_INTRS(x)	((x) & 0x3f)
+
+/*
+ * NOTE: the doorbell interrupt is enabled, but the doorbell is never
+ * used! SiS chipsets require this.
+ */
+#define	EHCI_NORMAL_INTRS	(EHCI_STS_IAA | EHCI_STS_HSE |	\
+				EHCI_STS_PCD | EHCI_STS_ERRINT | EHCI_STS_INT)
+
+#define	EHCI_USBINTR		0x08	/* RW Interrupt register */
+#define	EHCI_INTR_IAAE		0x00000020	/* interrupt on async advance
+						 * ena */
+#define	EHCI_INTR_HSEE		0x00000010	/* host system error ena */
+#define	EHCI_INTR_FLRE		0x00000008	/* frame list rollover ena */
+#define	EHCI_INTR_PCIE		0x00000004	/* port change ena */
+#define	EHCI_INTR_UEIE		0x00000002	/* USB error intr ena */
+#define	EHCI_INTR_UIE		0x00000001	/* USB intr ena */
+
+#define	EHCI_FRINDEX		0x0c	/* RW Frame Index register */
+
+#define	EHCI_CTRLDSSEGMENT	0x10	/* RW Control Data Structure Segment */
+
+#define	EHCI_PERIODICLISTBASE	0x14	/* RW Periodic List Base */
+#define	EHCI_ASYNCLISTADDR	0x18	/* RW Async List Base */
+
+#define	EHCI_CONFIGFLAG		0x40	/* RW Configure Flag register */
+#define	EHCI_CONF_CF		0x00000001	/* RW configure flag */
+
+#define	EHCI_PORTSC(n)		(0x40+(4*(n)))	/* RO, RW, RWC Port Status reg */
+#define	EHCI_PS_WKOC_E		0x00400000	/* RW wake on over current ena */
+#define	EHCI_PS_WKDSCNNT_E	0x00200000	/* RW wake on disconnect ena */
+#define	EHCI_PS_WKCNNT_E	0x00100000	/* RW wake on connect ena */
+#define	EHCI_PS_PTC		0x000f0000	/* RW port test control */
+#define	EHCI_PS_PIC		0x0000c000	/* RW port indicator control */
+#define	EHCI_PS_PO		0x00002000	/* RW port owner */
+#define	EHCI_PS_PP		0x00001000	/* RW,RO port power */
+#define	EHCI_PS_LS		0x00000c00	/* RO line status */
+#define	EHCI_PS_IS_LOWSPEED(x)	(((x) & EHCI_PS_LS) == 0x00000400)
+#define	EHCI_PS_PR		0x00000100	/* RW port reset */
+#define	EHCI_PS_SUSP		0x00000080	/* RW suspend */
+#define	EHCI_PS_FPR		0x00000040	/* RW force port resume */
+#define	EHCI_PS_OCC		0x00000020	/* RWC over current change */
+#define	EHCI_PS_OCA		0x00000010	/* RO over current active */
+#define	EHCI_PS_PEC		0x00000008	/* RWC port enable change */
+#define	EHCI_PS_PE		0x00000004	/* RW port enable */
+#define	EHCI_PS_CSC		0x00000002	/* RWC connect status change */
+#define	EHCI_PS_CS		0x00000001	/* RO connect status */
+#define	EHCI_PS_CLEAR		(EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
+
+#define	EHCI_USBMODE		0x68	/* RW USB Device mode register */
+#define	EHCI_UM_CM		0x00000003	/* R/WO Controller Mode */
+#define	EHCI_UM_CM_IDLE		0x0	/* Idle */
+#define	EHCI_UM_CM_HOST		0x3	/* Host Controller */
+#define	EHCI_UM_ES		0x00000004	/* R/WO Endian Select */
+#define	EHCI_UM_ES_LE		0x0	/* Little-endian byte alignment */
+#define	EHCI_UM_ES_BE		0x4	/* Big-endian byte alignment */
+#define	EHCI_UM_SDIS		0x00000010	/* R/WO Stream Disable Mode */
+
+#define	EHCI_PORT_RESET_COMPLETE	2	/* ms */
+
+#endif	/* _EHCIREG_H_ */
diff --git a/sys/dev/usb/controller/ohci.c b/sys/dev/usb/controller/ohci.c
index 30592c1..637b639 100644
--- a/sys/dev/usb/controller/ohci.c
+++ b/sys/dev/usb/controller/ohci.c
@@ -72,6 +72,7 @@ __FBSDID("$FreeBSD$");
 #include <dev/usb/usb_controller.h>
 #include <dev/usb/usb_bus.h>
 #include <dev/usb/controller/ohci.h>
+#include <dev/usb/controller/ohcireg.h>
 
 #define	OHCI_BUS2SC(bus) \
    ((ohci_softc_t *)(((uint8_t *)(bus)) - \
diff --git a/sys/dev/usb/controller/ohci.h b/sys/dev/usb/controller/ohci.h
index eeb49aa..60574bb 100644
--- a/sys/dev/usb/controller/ohci.h
+++ b/sys/dev/usb/controller/ohci.h
@@ -41,95 +41,6 @@
 
 #define	OHCI_MAX_DEVICES MIN(USB_MAX_DEVICES, 128)
 
-/* PCI config registers  */
-#define	PCI_CBMEM		0x10	/* configuration base memory */
-#define	PCI_INTERFACE_OHCI	0x10
-
-/* OHCI registers */
-#define	OHCI_REVISION		0x00	/* OHCI revision */
-#define	OHCI_REV_LO(rev)	((rev) & 0xf)
-#define	OHCI_REV_HI(rev)	(((rev)>>4) & 0xf)
-#define	OHCI_REV_LEGACY(rev)	((rev) & 0x100)
-#define	OHCI_CONTROL		0x04
-#define	OHCI_CBSR_MASK		0x00000003	/* Control/Bulk Service Ratio */
-#define	OHCI_RATIO_1_1		0x00000000
-#define	OHCI_RATIO_1_2		0x00000001
-#define	OHCI_RATIO_1_3		0x00000002
-#define	OHCI_RATIO_1_4		0x00000003
-#define	OHCI_PLE		0x00000004	/* Periodic List Enable */
-#define	OHCI_IE			0x00000008	/* Isochronous Enable */
-#define	OHCI_CLE		0x00000010	/* Control List Enable */
-#define	OHCI_BLE		0x00000020	/* Bulk List Enable */
-#define	OHCI_HCFS_MASK		0x000000c0	/* HostControllerFunctionalStat
-						 * e */
-#define	OHCI_HCFS_RESET		0x00000000
-#define	OHCI_HCFS_RESUME	0x00000040
-#define	OHCI_HCFS_OPERATIONAL	0x00000080
-#define	OHCI_HCFS_SUSPEND	0x000000c0
-#define	OHCI_IR			0x00000100	/* Interrupt Routing */
-#define	OHCI_RWC		0x00000200	/* Remote Wakeup Connected */
-#define	OHCI_RWE		0x00000400	/* Remote Wakeup Enabled */
-#define	OHCI_COMMAND_STATUS	0x08
-#define	OHCI_HCR		0x00000001	/* Host Controller Reset */
-#define	OHCI_CLF		0x00000002	/* Control List Filled */
-#define	OHCI_BLF		0x00000004	/* Bulk List Filled */
-#define	OHCI_OCR		0x00000008	/* Ownership Change Request */
-#define	OHCI_SOC_MASK		0x00030000	/* Scheduling Overrun Count */
-#define	OHCI_INTERRUPT_STATUS	0x0c
-#define	OHCI_SO			0x00000001	/* Scheduling Overrun */
-#define	OHCI_WDH		0x00000002	/* Writeback Done Head */
-#define	OHCI_SF			0x00000004	/* Start of Frame */
-#define	OHCI_RD			0x00000008	/* Resume Detected */
-#define	OHCI_UE			0x00000010	/* Unrecoverable Error */
-#define	OHCI_FNO		0x00000020	/* Frame Number Overflow */
-#define	OHCI_RHSC		0x00000040	/* Root Hub Status Change */
-#define	OHCI_OC			0x40000000	/* Ownership Change */
-#define	OHCI_MIE		0x80000000	/* Master Interrupt Enable */
-#define	OHCI_INTERRUPT_ENABLE	0x10
-#define	OHCI_INTERRUPT_DISABLE	0x14
-#define	OHCI_HCCA		0x18
-#define	OHCI_PERIOD_CURRENT_ED	0x1c
-#define	OHCI_CONTROL_HEAD_ED	0x20
-#define	OHCI_CONTROL_CURRENT_ED	0x24
-#define	OHCI_BULK_HEAD_ED	0x28
-#define	OHCI_BULK_CURRENT_ED	0x2c
-#define	OHCI_DONE_HEAD		0x30
-#define	OHCI_FM_INTERVAL	0x34
-#define	OHCI_GET_IVAL(s)	((s) & 0x3fff)
-#define	OHCI_GET_FSMPS(s)	(((s) >> 16) & 0x7fff)
-#define	OHCI_FIT		0x80000000
-#define	OHCI_FM_REMAINING	0x38
-#define	OHCI_FM_NUMBER		0x3c
-#define	OHCI_PERIODIC_START	0x40
-#define	OHCI_LS_THRESHOLD	0x44
-#define	OHCI_RH_DESCRIPTOR_A	0x48
-#define	OHCI_GET_NDP(s)		((s) & 0xff)
-#define	OHCI_PSM		0x0100	/* Power Switching Mode */
-#define	OHCI_NPS		0x0200	/* No Power Switching */
-#define	OHCI_DT			0x0400	/* Device Type */
-#define	OHCI_OCPM		0x0800	/* Overcurrent Protection Mode */
-#define	OHCI_NOCP		0x1000	/* No Overcurrent Protection */
-#define	OHCI_GET_POTPGT(s)	((s) >> 24)
-#define	OHCI_RH_DESCRIPTOR_B	0x4c
-#define	OHCI_RH_STATUS		0x50
-#define	OHCI_LPS		0x00000001	/* Local Power Status */
-#define	OHCI_OCI		0x00000002	/* OverCurrent Indicator */
-#define	OHCI_DRWE		0x00008000	/* Device Remote Wakeup Enable */
-#define	OHCI_LPSC		0x00010000	/* Local Power Status Change */
-#define	OHCI_CCIC		0x00020000	/* OverCurrent Indicator
-						 * Change */
-#define	OHCI_CRWE		0x80000000	/* Clear Remote Wakeup Enable */
-#define	OHCI_RH_PORT_STATUS(n)	(0x50 + ((n)*4))	/* 1 based indexing */
-
-#define	OHCI_LES		(OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE)
-#define	OHCI_ALL_INTRS		(OHCI_SO | OHCI_WDH | OHCI_SF |		\
-				OHCI_RD | OHCI_UE | OHCI_FNO |		\
-				OHCI_RHSC | OHCI_OC)
-#define	OHCI_NORMAL_INTRS	(OHCI_WDH | OHCI_RD | OHCI_UE | OHCI_RHSC)
-
-#define	OHCI_FSMPS(i)		(((i-210)*6/7) << 16)
-#define	OHCI_PERIODIC(i)	((i)*9/10)
-
 #define	OHCI_NO_INTRS		32
 #define	OHCI_HCCA_SIZE		256
 
diff --git a/sys/dev/usb/controller/ohci_atmelarm.c b/sys/dev/usb/controller/ohci_atmelarm.c
index a4fe9f3..c235a8b 100644
--- a/sys/dev/usb/controller/ohci_atmelarm.c
+++ b/sys/dev/usb/controller/ohci_atmelarm.c
@@ -56,6 +56,7 @@ __FBSDID("$FreeBSD$");
 #include <dev/usb/usb_controller.h>
 #include <dev/usb/usb_bus.h>
 #include <dev/usb/controller/ohci.h>
+#include <dev/usb/controller/ohcireg.h>
 
 #include <sys/rman.h>
 
diff --git a/sys/dev/usb/controller/ohci_pci.c b/sys/dev/usb/controller/ohci_pci.c
index 3be6e42..7189158 100644
--- a/sys/dev/usb/controller/ohci_pci.c
+++ b/sys/dev/usb/controller/ohci_pci.c
@@ -81,6 +81,7 @@ __FBSDID("$FreeBSD$");
 #include <dev/usb/usb_bus.h>
 #include <dev/usb/usb_pci.h>
 #include <dev/usb/controller/ohci.h>
+#include <dev/usb/controller/ohcireg.h>
 
 #define	PCI_OHCI_VENDORID_ACERLABS	0x10b9
 #define	PCI_OHCI_VENDORID_AMD		0x1022
diff --git a/sys/dev/usb/controller/ohcireg.h b/sys/dev/usb/controller/ohcireg.h
new file mode 100644
index 0000000..9127a02
--- /dev/null
+++ b/sys/dev/usb/controller/ohcireg.h
@@ -0,0 +1,131 @@
+/* $FreeBSD$ */
+/*-
+ * Copyright (c) 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Lennart Augustsson (lennart@augustsson.net) at
+ * Carlstedt Research & Technology.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _OHCIREG_H_
+#define	_OHCIREG_H_
+
+/* PCI config registers  */
+#define	PCI_CBMEM		0x10	/* configuration base memory */
+#define	PCI_INTERFACE_OHCI	0x10
+
+/* OHCI registers */
+#define	OHCI_REVISION		0x00	/* OHCI revision */
+#define	OHCI_REV_LO(rev)	((rev) & 0xf)
+#define	OHCI_REV_HI(rev)	(((rev)>>4) & 0xf)
+#define	OHCI_REV_LEGACY(rev)	((rev) & 0x100)
+#define	OHCI_CONTROL		0x04
+#define	OHCI_CBSR_MASK		0x00000003	/* Control/Bulk Service Ratio */
+#define	OHCI_RATIO_1_1		0x00000000
+#define	OHCI_RATIO_1_2		0x00000001
+#define	OHCI_RATIO_1_3		0x00000002
+#define	OHCI_RATIO_1_4		0x00000003
+#define	OHCI_PLE		0x00000004	/* Periodic List Enable */
+#define	OHCI_IE			0x00000008	/* Isochronous Enable */
+#define	OHCI_CLE		0x00000010	/* Control List Enable */
+#define	OHCI_BLE		0x00000020	/* Bulk List Enable */
+#define	OHCI_HCFS_MASK		0x000000c0	/* HostControllerFunctionalStat
+						 * e */
+#define	OHCI_HCFS_RESET		0x00000000
+#define	OHCI_HCFS_RESUME	0x00000040
+#define	OHCI_HCFS_OPERATIONAL	0x00000080
+#define	OHCI_HCFS_SUSPEND	0x000000c0
+#define	OHCI_IR			0x00000100	/* Interrupt Routing */
+#define	OHCI_RWC		0x00000200	/* Remote Wakeup Connected */
+#define	OHCI_RWE		0x00000400	/* Remote Wakeup Enabled */
+#define	OHCI_COMMAND_STATUS	0x08
+#define	OHCI_HCR		0x00000001	/* Host Controller Reset */
+#define	OHCI_CLF		0x00000002	/* Control List Filled */
+#define	OHCI_BLF		0x00000004	/* Bulk List Filled */
+#define	OHCI_OCR		0x00000008	/* Ownership Change Request */
+#define	OHCI_SOC_MASK		0x00030000	/* Scheduling Overrun Count */
+#define	OHCI_INTERRUPT_STATUS	0x0c
+#define	OHCI_SO			0x00000001	/* Scheduling Overrun */
+#define	OHCI_WDH		0x00000002	/* Writeback Done Head */
+#define	OHCI_SF			0x00000004	/* Start of Frame */
+#define	OHCI_RD			0x00000008	/* Resume Detected */
+#define	OHCI_UE			0x00000010	/* Unrecoverable Error */
+#define	OHCI_FNO		0x00000020	/* Frame Number Overflow */
+#define	OHCI_RHSC		0x00000040	/* Root Hub Status Change */
+#define	OHCI_OC			0x40000000	/* Ownership Change */
+#define	OHCI_MIE		0x80000000	/* Master Interrupt Enable */
+#define	OHCI_INTERRUPT_ENABLE	0x10
+#define	OHCI_INTERRUPT_DISABLE	0x14
+#define	OHCI_HCCA		0x18
+#define	OHCI_PERIOD_CURRENT_ED	0x1c
+#define	OHCI_CONTROL_HEAD_ED	0x20
+#define	OHCI_CONTROL_CURRENT_ED	0x24
+#define	OHCI_BULK_HEAD_ED	0x28
+#define	OHCI_BULK_CURRENT_ED	0x2c
+#define	OHCI_DONE_HEAD		0x30
+#define	OHCI_FM_INTERVAL	0x34
+#define	OHCI_GET_IVAL(s)	((s) & 0x3fff)
+#define	OHCI_GET_FSMPS(s)	(((s) >> 16) & 0x7fff)
+#define	OHCI_FIT		0x80000000
+#define	OHCI_FM_REMAINING	0x38
+#define	OHCI_FM_NUMBER		0x3c
+#define	OHCI_PERIODIC_START	0x40
+#define	OHCI_LS_THRESHOLD	0x44
+#define	OHCI_RH_DESCRIPTOR_A	0x48
+#define	OHCI_GET_NDP(s)		((s) & 0xff)
+#define	OHCI_PSM		0x0100	/* Power Switching Mode */
+#define	OHCI_NPS		0x0200	/* No Power Switching */
+#define	OHCI_DT			0x0400	/* Device Type */
+#define	OHCI_OCPM		0x0800	/* Overcurrent Protection Mode */
+#define	OHCI_NOCP		0x1000	/* No Overcurrent Protection */
+#define	OHCI_GET_POTPGT(s)	((s) >> 24)
+#define	OHCI_RH_DESCRIPTOR_B	0x4c
+#define	OHCI_RH_STATUS		0x50
+#define	OHCI_LPS		0x00000001	/* Local Power Status */
+#define	OHCI_OCI		0x00000002	/* OverCurrent Indicator */
+#define	OHCI_DRWE		0x00008000	/* Device Remote Wakeup Enable */
+#define	OHCI_LPSC		0x00010000	/* Local Power Status Change */
+#define	OHCI_CCIC		0x00020000	/* OverCurrent Indicator
+						 * Change */
+#define	OHCI_CRWE		0x80000000	/* Clear Remote Wakeup Enable */
+#define	OHCI_RH_PORT_STATUS(n)	(0x50 + ((n)*4))	/* 1 based indexing */
+
+#define	OHCI_LES		(OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE)
+#define	OHCI_ALL_INTRS		(OHCI_SO | OHCI_WDH | OHCI_SF |		\
+				OHCI_RD | OHCI_UE | OHCI_FNO |		\
+				OHCI_RHSC | OHCI_OC)
+#define	OHCI_NORMAL_INTRS	(OHCI_WDH | OHCI_RD | OHCI_UE | OHCI_RHSC)
+
+#define	OHCI_FSMPS(i)		(((i-210)*6/7) << 16)
+#define	OHCI_PERIODIC(i)	((i)*9/10)
+
+#endif	/* _OHCIREG_H_ */
diff --git a/sys/dev/usb/controller/uhci.c b/sys/dev/usb/controller/uhci.c
index 2a2ff1c..4e2659c 100644
--- a/sys/dev/usb/controller/uhci.c
+++ b/sys/dev/usb/controller/uhci.c
@@ -75,6 +75,7 @@ __FBSDID("$FreeBSD$");
 #include <dev/usb/usb_controller.h>
 #include <dev/usb/usb_bus.h>
 #include <dev/usb/controller/uhci.h>
+#include <dev/usb/controller/uhcireg.h>
 
 #define	alt_next next
 #define	UHCI_BUS2SC(bus) \
diff --git a/sys/dev/usb/controller/uhci.h b/sys/dev/usb/controller/uhci.h
index f2ea246..f526431 100644
--- a/sys/dev/usb/controller/uhci.h
+++ b/sys/dev/usb/controller/uhci.h
@@ -41,64 +41,6 @@
 
 #define	UHCI_MAX_DEVICES MIN(USB_MAX_DEVICES, 128)
 
-/* PCI config registers  */
-#define	PCI_USBREV		0x60	/* USB protocol revision */
-#define	PCI_USB_REV_MASK		0xff
-#define	PCI_USB_REV_PRE_1_0	0x00
-#define	PCI_USB_REV_1_0		0x10
-#define	PCI_USB_REV_1_1		0x11
-#define	PCI_LEGSUP		0xc0	/* Legacy Support register */
-#define	PCI_LEGSUP_USBPIRQDEN	0x2000	/* USB PIRQ D Enable */
-#define	PCI_CBIO		0x20	/* configuration base IO */
-#define	PCI_INTERFACE_UHCI	0x00
-
-/* UHCI registers */
-#define	UHCI_CMD		0x00
-#define	UHCI_CMD_RS		0x0001
-#define	UHCI_CMD_HCRESET	0x0002
-#define	UHCI_CMD_GRESET		0x0004
-#define	UHCI_CMD_EGSM		0x0008
-#define	UHCI_CMD_FGR		0x0010
-#define	UHCI_CMD_SWDBG		0x0020
-#define	UHCI_CMD_CF		0x0040
-#define	UHCI_CMD_MAXP		0x0080
-#define	UHCI_STS		0x02
-#define	UHCI_STS_USBINT		0x0001
-#define	UHCI_STS_USBEI		0x0002
-#define	UHCI_STS_RD		0x0004
-#define	UHCI_STS_HSE		0x0008
-#define	UHCI_STS_HCPE		0x0010
-#define	UHCI_STS_HCH		0x0020
-#define	UHCI_STS_ALLINTRS	0x003f
-#define	UHCI_INTR		0x04
-#define	UHCI_INTR_TOCRCIE	0x0001
-#define	UHCI_INTR_RIE		0x0002
-#define	UHCI_INTR_IOCE		0x0004
-#define	UHCI_INTR_SPIE		0x0008
-#define	UHCI_FRNUM		0x06
-#define	UHCI_FRNUM_MASK		0x03ff
-#define	UHCI_FLBASEADDR		0x08
-#define	UHCI_SOF		0x0c
-#define	UHCI_SOF_MASK		0x7f
-#define	UHCI_PORTSC1      	0x010
-#define	UHCI_PORTSC2      	0x012
-#define	UHCI_PORTSC_CCS		0x0001
-#define	UHCI_PORTSC_CSC		0x0002
-#define	UHCI_PORTSC_PE		0x0004
-#define	UHCI_PORTSC_POEDC	0x0008
-#define	UHCI_PORTSC_LS		0x0030
-#define	UHCI_PORTSC_LS_SHIFT	4
-#define	UHCI_PORTSC_RD		0x0040
-#define	UHCI_PORTSC_LSDA	0x0100
-#define	UHCI_PORTSC_PR		0x0200
-#define	UHCI_PORTSC_OCI		0x0400
-#define	UHCI_PORTSC_OCIC	0x0800
-#define	UHCI_PORTSC_SUSP	0x1000
-
-#define	URWMASK(x)		((x) & (UHCI_PORTSC_SUSP |		\
-				UHCI_PORTSC_PR | UHCI_PORTSC_RD |	\
-				UHCI_PORTSC_PE))
-
 #define	UHCI_FRAMELIST_COUNT	1024	/* units */
 #define	UHCI_FRAMELIST_ALIGN	4096	/* bytes */
 
@@ -118,8 +60,6 @@ typedef uint32_t uhci_physaddr_t;
 #define	UHCI_PTR_QH		0x00000002
 #define	UHCI_PTR_VF		0x00000004
 
-#define	UHCI_QH_REMOVE_DELAY	5	/* us - QH remove delay */
-
 /*
  * The Queue Heads (QH) and Transfer Descriptors (TD) are accessed by
  * both the CPU and the USB-controller which run concurrently. Great
diff --git a/sys/dev/usb/controller/uhci_pci.c b/sys/dev/usb/controller/uhci_pci.c
index ba155be..3956ead 100644
--- a/sys/dev/usb/controller/uhci_pci.c
+++ b/sys/dev/usb/controller/uhci_pci.c
@@ -81,6 +81,7 @@ __FBSDID("$FreeBSD$");
 #include <dev/usb/usb_bus.h>
 #include <dev/usb/usb_pci.h>
 #include <dev/usb/controller/uhci.h>
+#include <dev/usb/controller/uhcireg.h>
 
 #define	PCI_UHCI_VENDORID_INTEL		0x8086
 #define	PCI_UHCI_VENDORID_VIA		0x1106
diff --git a/sys/dev/usb/controller/uhcireg.h b/sys/dev/usb/controller/uhcireg.h
new file mode 100644
index 0000000..eeabbf0
--- /dev/null
+++ b/sys/dev/usb/controller/uhcireg.h
@@ -0,0 +1,100 @@
+/* $FreeBSD$ */
+/*-
+ * Copyright (c) 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Lennart Augustsson (lennart@augustsson.net) at
+ * Carlstedt Research & Technology.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _UHCIREG_H_
+#define	_UHCIREG_H_
+
+/* PCI config registers  */
+#define	PCI_USBREV		0x60	/* USB protocol revision */
+#define	PCI_USB_REV_MASK		0xff
+#define	PCI_USB_REV_PRE_1_0	0x00
+#define	PCI_USB_REV_1_0		0x10
+#define	PCI_USB_REV_1_1		0x11
+#define	PCI_LEGSUP		0xc0	/* Legacy Support register */
+#define	PCI_LEGSUP_USBPIRQDEN	0x2000	/* USB PIRQ D Enable */
+#define	PCI_CBIO		0x20	/* configuration base IO */
+#define	PCI_INTERFACE_UHCI	0x00
+
+/* UHCI registers */
+#define	UHCI_CMD		0x00
+#define	UHCI_CMD_RS		0x0001
+#define	UHCI_CMD_HCRESET	0x0002
+#define	UHCI_CMD_GRESET		0x0004
+#define	UHCI_CMD_EGSM		0x0008
+#define	UHCI_CMD_FGR		0x0010
+#define	UHCI_CMD_SWDBG		0x0020
+#define	UHCI_CMD_CF		0x0040
+#define	UHCI_CMD_MAXP		0x0080
+#define	UHCI_STS		0x02
+#define	UHCI_STS_USBINT		0x0001
+#define	UHCI_STS_USBEI		0x0002
+#define	UHCI_STS_RD		0x0004
+#define	UHCI_STS_HSE		0x0008
+#define	UHCI_STS_HCPE		0x0010
+#define	UHCI_STS_HCH		0x0020
+#define	UHCI_STS_ALLINTRS	0x003f
+#define	UHCI_INTR		0x04
+#define	UHCI_INTR_TOCRCIE	0x0001
+#define	UHCI_INTR_RIE		0x0002
+#define	UHCI_INTR_IOCE		0x0004
+#define	UHCI_INTR_SPIE		0x0008
+#define	UHCI_FRNUM		0x06
+#define	UHCI_FRNUM_MASK		0x03ff
+#define	UHCI_FLBASEADDR		0x08
+#define	UHCI_SOF		0x0c
+#define	UHCI_SOF_MASK		0x7f
+#define	UHCI_PORTSC1      	0x010
+#define	UHCI_PORTSC2      	0x012
+#define	UHCI_PORTSC_CCS		0x0001
+#define	UHCI_PORTSC_CSC		0x0002
+#define	UHCI_PORTSC_PE		0x0004
+#define	UHCI_PORTSC_POEDC	0x0008
+#define	UHCI_PORTSC_LS		0x0030
+#define	UHCI_PORTSC_LS_SHIFT	4
+#define	UHCI_PORTSC_RD		0x0040
+#define	UHCI_PORTSC_LSDA	0x0100
+#define	UHCI_PORTSC_PR		0x0200
+#define	UHCI_PORTSC_OCI		0x0400
+#define	UHCI_PORTSC_OCIC	0x0800
+#define	UHCI_PORTSC_SUSP	0x1000
+
+#define	URWMASK(x)		((x) & (UHCI_PORTSC_SUSP |		\
+				UHCI_PORTSC_PR | UHCI_PORTSC_RD |	\
+				UHCI_PORTSC_PE))
+
+#endif	/* _UHCIREG_H_ */