This is the IBM/National PCMCIA ethernet driver from Keith Moore,

based originally on work by David Greenman and adapted to FreeBSD
(and cleaned up a bit) by myself.  It supports the IBM Credit Card
Adapter for the IBM Thinkpad, and I've had no trouble making it work
on my Toshiba T1910 with a National `InfoMover' NE4100 PCMCIA ethernet
card (I'm commiting this message through it right now :-).

This is actually sneaking it in after feature-freeze, but it's just
too useful to pass up!  As always, necessity is a mother.

3 files changed, 3000 insertions, 0 deletions

diff --git a/sys/i386/isa/ic/i82365.h b/sys/i386/isa/ic/i82365.h
new file mode 100644
index 0000000..ab38125
--- /dev/null
+++ b/sys/i386/isa/ic/i82365.h
@@ -0,0 +1,190 @@
+#ifndef __83265_H__
+#define __83265_H__
+
+/***********************************************************************
+ * 82365.h -- information necessary for direct manipulation of PCMCIA
+ * cards and controllers
+ *
+ * Support is included for Intel 82365SL PCIC controllers and clones
+ * thereof.
+ *
+ * originally by Barry Jaspan; hacked over by Keith Moore
+ *
+ ***********************************************************************/
+
+/*
+ * PCIC Registers
+ *     Each register is given a name, and most of the bits are named too.
+ *     I should really name them all.
+ * 
+ *     Finally, since the banks can be addressed with a regular syntax,
+ *     some macros are provided for that purpose.
+ */
+
+#define PCIC_BASE 0x03e0	/* base adddress of pcic register set */
+
+/* First, all the registers */
+#define PCIC_ID_REV	0x00	/* Identification and Revision */
+#define PCIC_STATUS	0x01	/* Interface Status */
+#define PCIC_POWER	0x02	/* Power and RESETDRV control */
+#define PCIC_INT_GEN	0x03	/* Interrupt and General Control */
+#define PCIC_STAT_CHG	0x04	/* Card Status Change */
+#define PCIC_STAT_INT	0x05	/* Card Status Change Interrupt Config */
+#define PCIC_ADDRWINE	0x06	/* Address Window Enable */
+#define PCIC_IOCTL	0x07	/* I/O Control */
+#define PCIC_IO0_STL	0x08	/* I/O Address 0 Start Low Byte */
+#define PCIC_IO0_STH	0x09	/* I/O Address 0 Start High Byte */
+#define PCIC_IO0_SPL	0x0a	/* I/O Address 0 Stop Low Byte */
+#define PCIC_IO0_SPH	0x0b	/* I/O Address 0 Stop High Byte */
+#define PCIC_IO1_STL	0x0c	/* I/O Address 1 Start Low Byte */
+#define PCIC_IO1_STH	0x0d	/* I/O Address 1 Start High Byte */
+#define PCIC_IO1_SPL	0x0e	/* I/O Address 1 Stop Low Byte */
+#define PCIC_IO1_SPH	0x0f	/* I/O Address 1 Stop High Byte */
+#define PCIC_SM0_STL	0x10	/* System Memory Address 0 Mapping Start Low Byte */
+#define PCIC_SM0_STH	0x11	/* System Memory Address 0 Mapping Start High Byte */
+#define PCIC_SM0_SPL	0x12	/* System Memory Address 0 Mapping Stop Low Byte */
+#define PCIC_SM0_SPH	0x13	/* System Memory Address 0 Mapping Stop High Byte */
+#define PCIC_CM0_L	0x14	/* Card Memory Offset Address 0 Low Byte */
+#define PCIC_CM0_H	0x15	/* Card Memory Offset Address 0 High Byte */
+#define PCIC_CDGC	0x16	/* Card Detect and General Control */
+#define PCIC_RES17	0x17	/* Reserved */
+#define PCIC_SM1_STL	0x18	/* System Memory Address 1 Mapping Start Low Byte */
+#define PCIC_SM1_STH	0x19	/* System Memory Address 1 Mapping Start High Byte */
+#define PCIC_SM1_SPL	0x1a	/* System Memory Address 1 Mapping Stop Low Byte */
+#define PCIC_SM1_SPH	0x1b	/* System Memory Address 1 Mapping Stop High Byte */
+#define PCIC_CM1_L	0x1c	/* Card Memory Offset Address 1 Low Byte */
+#define PCIC_CM1_H	0x1d	/* Card Memory Offset Address 1 High Byte */
+#define PCIC_GLO_CTRL	0x1e	/* Global Control Register */
+#define PCIC_RES1F	0x1f	/* Reserved */
+#define PCIC_SM2_STL	0x20	/* System Memory Address 2 Mapping Start Low Byte */
+#define PCIC_SM2_STH	0x21	/* System Memory Address 2 Mapping Start High Byte */
+#define PCIC_SM2_SPL	0x22	/* System Memory Address 2 Mapping Stop Low Byte */
+#define PCIC_SM2_SPH	0x23	/* System Memory Address 2 Mapping Stop High Byte */
+#define PCIC_CM2_L	0x24	/* Card Memory Offset Address 2 Low Byte */
+#define PCIC_CM2_H	0x25	/* Card Memory Offset Address 2 High Byte */
+#define PCIC_RES26	0x26	/* Reserved */
+#define PCIC_RES27	0x27	/* Reserved */
+#define PCIC_SM3_STL	0x28	/* System Memory Address 3 Mapping Start Low Byte */
+#define PCIC_SM3_STH	0x29	/* System Memory Address 3 Mapping Start High Byte */
+#define PCIC_SM3_SPL	0x2a	/* System Memory Address 3 Mapping Stop Low Byte */
+#define PCIC_SM3_SPH	0x2b	/* System Memory Address 3 Mapping Stop High Byte */
+#define PCIC_CM3_L	0x2c	/* Card Memory Offset Address 3 Low Byte */
+#define PCIC_CM3_H	0x2d	/* Card Memory Offset Address 3 High Byte */
+#define PCIC_RES2E	0x2e	/* Reserved */
+#define PCIC_RES2F	0x2f	/* Reserved */
+#define PCIC_SM4_STL	0x30	/* System Memory Address 4 Mapping Start Low Byte */
+#define PCIC_SM4_STH	0x31	/* System Memory Address 4 Mapping Start High Byte */
+#define PCIC_SM4_SPL	0x32	/* System Memory Address 4 Mapping Stop Low Byte */
+#define PCIC_SM4_SPH	0x33	/* System Memory Address 4 Mapping Stop High Byte */
+#define PCIC_CM4_L	0x34	/* Card Memory Offset Address 4 Low Byte */
+#define PCIC_CM4_H	0x35	/* Card Memory Offset Address 4 High Byte */
+#define PCIC_RES36	0x36	/* Reserved */
+#define PCIC_RES37	0x37	/* Reserved */
+#define PCIC_RES38	0x38	/* Reserved */
+#define PCIC_RES39	0x39	/* Reserved */
+#define PCIC_RES3A	0x3a	/* Reserved */
+#define PCIC_RES3B	0x3b	/* Reserved */
+#define PCIC_RES3C	0x3c	/* Reserved */
+#define PCIC_RES3D	0x3d	/* Reserved */
+#define PCIC_RES3E	0x3e	/* Reserved */
+#define PCIC_RES3F	0x3f	/* Reserved */
+
+/* Now register bits, ordered by reg # */
+
+/* For Identification and Revision (PCIC_ID_REV) */
+#define PCIC_INTEL0	0x82	/* Intel 82365SL Rev. 0; Both Memory and I/O */
+#define PCIC_INTEL1	0x83	/* Intel 82365SL Rev. 1; Both Memory and I/O */
+#define PCIC_IBM1	0x88	/* IBM PCIC clone; Both Memory and I/O */
+#define PCIC_IBM2	0x89	/* IBM PCIC clone; Both Memory and I/O */
+
+/* For Interface Status register (PCIC_STATUS) */
+#define PCIC_VPPV	0x80	/* Vpp_valid */
+#define PCIC_POW	0x40	/* PC Card power active */
+#define PCIC_READY	0x20	/* Ready/~Busy */
+#define PCIC_MWP	0x10	/* Memory Write Protect */
+#define PCIC_CD		0x0C	/* Both card detect bits */
+#define PCIC_BVD	0x03	/* Both Battery Voltage Detect bits */
+
+/* For the Power and RESETDRV register (PCIC_POWER) */
+#define PCIC_OUTENA	0x80	/* Output Enable */
+#define PCIC_DISRST	0x40	/* Disable RESETDRV */
+#define PCIC_APSENA	0x20	/* Auto Pwer Switch Enable */
+#define PCIC_PCPWRE	0x10	/* PC Card Power Enable */
+
+/* For the Interrupt and General Control register (PCIC_INT_GEN) */
+#define PCIC_CARDTYPE	0x20	/* Card Type 0 = memory, 1 = I/O */
+#define		PCIC_IOCARD	0x20
+#define		PCIC_MEMCARD	0x00
+#define PCIC_CARDRESET	0x40	/* Card reset 0 = Reset, 1 = Normal */
+
+/* For the Card Status Change register (PCIC_STAT_CHG) */
+#define PCIC_CDTCH	0x08	/* Card Detect Change */
+#define PCIC_RDYCH	0x04	/* Ready Change */
+#define PCIC_BATWRN	0x02	/* Battery Warning */
+#define PCIC_BATDED	0x01	/* Battery Dead */
+
+/* For the Address Window Enable Register (PCIC_ADDRWINE) */
+#define PCIC_SM0_EN	0x01	/* Memory Window 0 Enable */
+#define PCIC_SM1_EN	0x02	/* Memory Window 1 Enable */
+#define PCIC_SM2_EN	0x04	/* Memory Window 2 Enable */
+#define PCIC_SM3_EN	0x08	/* Memory Window 3 Enable */
+#define PCIC_SM4_EN	0x10	/* Memory Window 4 Enable */
+#define PCIC_MEMCS16	0x20	/* ~MEMCS16 Decode A23-A12 */
+#define PCIC_IO0_EN	0x40	/* I/O Window 0 Enable */
+#define PCIC_IO1_EN	0x80	/* I/O Window 1 Enable */
+
+/* For the I/O Control Register (PCIC_IOCTL) */
+#define PCIC_IO0_16BIT	0x01	/* I/O to this segment is 16 bit */
+#define PCIC_IO0_CS16	0x02	/* I/O cs16 source is the card */
+#define PCIC_IO0_0WS	0x04	/* zero wait states added on 8 bit cycles */
+#define PCIC_IO0_WS	0x08	/* Wait states added for 16 bit cycles */
+#define PCIC_IO1_16BIT	0x10	/* I/O to this segment is 16 bit */
+#define PCIC_IO1_CS16	0x20	/* I/O cs16 source is the card */
+#define PCIC_IO1_0WS	0x04	/* zero wait states added on 8 bit cycles */
+#define PCIC_IO1_WS	0x80	/* Wait states added for 16 bit cycles */
+
+/* For the various I/O and Memory windows */
+#define PCIC_ADDR_LOW	0
+#define PCIC_ADDR_HIGH	1
+#define PCIC_START	0x00	/* Start of mapping region */
+#define PCIC_END	0x02	/* End of mapping region */
+#define PCIC_MOFF	0x04	/* Card Memory Mapping region offset */
+#define PCIC_IO0	0x08	/* I/O Address 0 */
+#define PCIC_IO1	0x0c	/* I/O Address 1 */
+#define PCIC_SM0	0x10	/* System Memory Address 0 Mapping */
+#define PCIC_SM1	0x18	/* System Memory Address 1 Mapping */
+#define PCIC_SM2	0x20	/* System Memory Address 2 Mapping */
+#define PCIC_SM3	0x28	/* System Memory Address 3 Mapping */
+#define PCIC_SM4	0x30	/* System Memory Address 4 Mapping */
+
+/* For System Memory Window start registers
+   (PCIC_SMx|PCIC_START|PCIC_ADDR_HIGH) */
+#define PCIC_ZEROWS	0x40	/* Zero wait states */
+#define PCIC_DATA16	0x80	/* Data width is 16 bits */
+
+/* For System Memory Window stop registers
+   (PCIC_SMx|PCIC_END|PCIC_ADDR_HIGH) */
+#define PCIC_MW0	0x40	/* Wait state bit 0 */
+#define PCIC_MW1	0x80	/* Wait state bit 1 */
+
+/* For System Memory Window offset registers
+   (PCIC_SMx|PCIC_MOFF|PCIC_ADDR_HIGH) */
+#define PCIC_REG	0x40	/* Attribute/Common select (why called Reg?) */
+#define PCIC_WP		0x80	/* Write-protect this window */
+
+/* For Card Detect and General Control register (PCIC_CDGC) */
+#define PCIC_16_DL_INH	0x01	/* 16-bit memory delay inhibit */
+#define PCIC_CNFG_RST_EN 0x02	/* configuration reset enable */
+#define PCIC_GPI_EN	0x04	/* GPI Enable */
+#define PCIC_GPI_TRANS	0x08	/* GPI Transition Control */
+#define PCIC_CDRES_EN	0x10	/* card detect resume enable */
+#define PCIC_SW_CD_INT	0x20	/* s/w card detect interrupt */
+
+/* For Global Control register (PCIC_GLO_CTRL) */
+#define PCIC_PWR_DOWN	0x01	/* power down */
+#define PCIC_LVL_MODE	0x02	/* level mode interrupt enable */
+#define PCIC_WB_CSCINT	0x04	/* explicit write-back csc intr */
+#define PCIC_IRQ14_PULSE 0x08	/* irq 14 pulse mode enable */
+
+/* DON'T ADD ANYTHING AFTER THIS #endif */
+#endif /* __83265_H__ */
diff --git a/sys/i386/isa/if_ze.c b/sys/i386/isa/if_ze.c
new file mode 100644
index 0000000..6ffb96c
--- /dev/null
+++ b/sys/i386/isa/if_ze.c
@@ -0,0 +1,1951 @@
+/*-
+ * TODO:
+ * [1] integrate into current if_ed.c
+ * [2] parse tuples to find out where to map the shared memory buffer,
+ *     and what to write into the configuration register
+ * [3] move pcic-specific code into a separate module.
+ * 
+ * Device driver for IBM PCMCIA Credit Card Adapter for Ethernet,
+ * if_ze.c
+ *
+ * Based on the Device driver for National Semiconductor DS8390 ethernet
+ * adapters by David Greenman.  Modifications for PCMCIA by Keith Moore.
+ * Adapted for FreeBSD 1.1.5 by Jordan Hubbard.
+ *
+ * Currently supports only the IBM Credit Card Adapter for Ethernet, but
+ * could probably work with other PCMCIA cards also, if it were modified
+ * to get the locations of the PCMCIA configuration option register (COR)
+ * by parsing the configuration tuples, rather than by hard-coding in
+ * the value expected by IBM's card.
+ *
+ * Sources for data on the PCMCIA/IBM CCAE specific portions of the driver:
+ *
+ * [1] _Local Area Network Credit Card Adapters Technical Reference_,
+ *     IBM Corp., SC30-3585-00, part # 33G9243.
+ * [2] "pre-alpha" PCMCIA support code for Linux by Barry Jaspan.
+ * [3] Intel 82536SL PC Card Interface Controller Data Sheet, Intel
+ *     Order Number 290423-002
+ * [4] National Semiconductor DP83902A ST-NIC (tm) Serial Network
+ *     Interface Controller for Twisted Pair data sheet.
+ *
+ *
+ * Copyright (C) 1993, David Greenman. This software may be used, modified,
+ *   copied, distributed, and sold, in both source and binary form provided
+ *   that the above copyright and these terms are retained. Under no
+ *   circumstances is the author responsible for the proper functioning
+ *   of this software, nor does the author assume any responsibility
+ *   for damages incurred with its use.
+ */
+
+#include "ze.h"
+#if	NZE > 0
+#include "bpfilter.h"
+
+#include "param.h"
+#include "systm.h"
+#include "errno.h"
+#include "ioctl.h"
+#include "mbuf.h"
+#include "socket.h"
+#include "syslog.h"
+
+#include "net/if.h"
+#include "net/if_dl.h"
+#include "net/if_types.h"
+#include "net/netisr.h"
+
+#ifdef INET
+#include "netinet/in.h"
+#include "netinet/in_systm.h"
+#include "netinet/in_var.h"
+#include "netinet/ip.h"
+#include "netinet/if_ether.h"
+#endif
+
+#ifdef NS
+#include "netns/ns.h"
+#include "netns/ns_if.h"
+#endif
+
+#if NBPFILTER > 0
+#include "net/bpf.h"
+#include "net/bpfdesc.h"
+#endif
+
+#include "i386/isa/isa.h"
+#include "i386/isa/isa_device.h"
+#include "i386/isa/icu.h"
+#include "i386/isa/if_zereg.h"
+
+#include "i386/include/pio.h"
+
+ 
+
+/*****************************************************************************
+ *                 pcmcia controller chip (PCIC) support                     *
+ *               (eventually, move this to a separate file)                  *
+ *****************************************************************************/
+#include "ic/i82365.h"
+
+/*
+ * Each PCIC chip (82365SL or clone) can handle two card slots, and there
+ * can be up to four PCICs in a system.  (On some machines, not all of the
+ * address lines are decoded, so a card may appear to be in more than one 
+ * slot.)
+ */
+#define MAXSLOT 8
+
+/*
+ * To access a register on the PCIC for a particular slot, you
+ * first write the correct OFFSET value for that slot in the
+ * INDEX register for the PCIC controller.  You then read or write
+ * the value from or to the DATA register for that controller.
+ *
+ * The first pair of chips shares I/O addresss for DATA and INDEX,
+ * as does the second pair.   (To the programmer, it looks like each 
+ * pair is a single chip.)  The i/o port addresses are hard-wired 
+ * into the PCIC; so the following addresses should be valid for
+ * any machine that uses this chip.
+ */
+
+#define PCIC_INDEX_0	0x3E0	/* index reg, chips 0 and 1 */
+#define PCIC_DATA_0	0x3E1	/* data register, chips 0 and 1 */
+#define PCIC_INDEX_1	0x3E2	/* index reg, chips 1 and 2 */
+#define PCIC_DATA_1	0x3E3	/* data register, chips 1 and 2 */
+
+/*
+ * Given a slot number, calculate the INDEX and DATA registers
+ * to talk to that slot.  OFFSET is added to the register number
+ * to address the registers for a particular slot.
+ */
+#define INDEX(slot) ((slot) < 4 ? PCIC_INDEX_0 : PCIC_INDEX_1)
+#define DATA(slot) ((slot) < 4 ? PCIC_DATA_0 : PCIC_DATA_1)
+#define OFFSET(slot) ((slot) % 4 * 0x40)
+
+/*
+ * There are 5 sets (windows) of memory mapping registers on the PCIC chip
+ * for each slot, numbered 0..4.
+ *
+ * They start at 10/50 hex within the chip's register space (not system
+ * I/O space), and are eight addresses apart.  These are actually pairs of
+ * 8-bit-wide registers (low byte first, then high byte) since the
+ * address fields are actually 12 bits long.  The upper bits are used
+ * for other things like 8/16-bit select and wait states.
+ *
+ * Memory mapping registers include start/stop addresses to define the
+ * region to be mapped (in terms of system memory addresses), and
+ * an offset register to allow for translation from system space
+ * to card space.  The lower 12 bits aren't included in these, so memory is
+ * mapped in 4K chunks.
+ */
+#define MEM_START_ADDR(window) (((window) * 0x08) + 0x10)
+#define MEM_STOP_ADDR(window) (((window) * 0x08) + 0x12)
+#define MEM_OFFSET(window) (((window) * 0x08) + 0x14)
+/*
+ * this bit gets set in the address window enable register (PCIC_ADDRWINE)
+ * to enable a particular address window.
+ */
+#define MEM_ENABLE_BIT(window) ((1) << (window))
+
+/*
+ * There are two i/o port addressing windows.  I/O ports cannot be
+ * relocated within system i/o space (unless the card doesn't decode
+ * all of the address bits); unlike card memory, there is no address
+ * translation offset.
+ */
+#define IO_START_ADDR(window) ((window) ? PCIC_IO1_STL : PCIC_IO0_STL)
+#define IO_STOP_ADDR(window) ((window) ? PCIC_IO1_SPL : PCIC_IO0_SPL)
+#define IO_ENABLE_BIT(window) ((window) ? PCIC_IO1_EN : PCIC_IO0_EN)
+#define IO_CS16_BIT(window) ((window) ? PCIC_IO1_CS16 : PCIC_IO0_CS16)
+
+/*
+ * read a byte from a pcic register for a particular slot
+ */
+static inline unsigned char
+pcic_getb (int slot, int reg)
+{
+    outb (INDEX(slot), OFFSET (slot) + reg);
+    return inb (DATA (slot));
+}
+
+/*
+ * write a byte to a pcic register for a particular slot
+ */
+static inline void
+pcic_putb (int slot, int reg, unsigned char val)
+{
+    outb (INDEX(slot), OFFSET (slot) + reg);
+    outb (DATA (slot), val);
+}
+
+/*
+ * read a word from a pcic register for a particular slot
+ */
+static inline unsigned short
+pcic_getw (int slot, int reg)
+{
+    return pcic_getb (slot, reg) | (pcic_getb (slot, reg+1) << 8);
+}
+
+/*
+ * write a word to a pcic register at a particular slot
+ */
+static inline void
+pcic_putw (int slot, int reg, unsigned short val)
+{
+    pcic_putb (slot, reg, val & 0xff);
+    pcic_putb (slot, reg + 1, (val >> 8) & 0xff);
+}
+
+static void
+pcic_print_regs (int slot)
+{
+    int i, j;
+
+    for (i = 0; i < 0x40; i += 16) {
+	for (j = 0; j < 16; ++j)
+	    printf ("%02x ", pcic_getb (slot, i + j));
+	printf ("\n");
+    }
+}
+
+/*
+ * map a portion of the card's memory space into system memory
+ * space.
+ *
+ * slot = # of the slot the card is plugged into
+ * window = which pcic memory map registers to use (0..4)
+ * sys_addr = base system PHYSICAL memory address where we want it.  must
+ *	      be on an appropriate boundary (lower 12 bits are zero).
+ * card_addr = the base address of the card's memory to correspond
+ *             to sys_addr
+ * length = length of the segment to map (may be rounded up as necessary)
+ * type = which card memory space to map (attribute or shared)
+ * width = 1 for byte-wide mapping; 2 for word (16-bit) mapping.
+ */
+
+enum memtype { COMMON, ATTRIBUTE };
+
+static void
+pcic_map_memory (int slot, int window, unsigned long sys_addr,
+		 unsigned long card_addr, unsigned long length,
+		 enum memtype type, int width)
+{
+    unsigned short offset;
+    unsigned short mem_start_addr;
+    unsigned short mem_stop_addr;
+
+    sys_addr >>= 12;
+    card_addr >>= 12;
+    length >>= 12;
+    /*
+     * compute an offset for the chip such that
+     * (sys_addr + offset) = card_addr
+     * but the arithmetic is done modulo 2^14
+     */
+    offset = (card_addr - sys_addr) & 0x3FFF;
+    /*
+     * now OR in the bit for "attribute memory" if necessary
+     */
+    if (type == ATTRIBUTE) {
+	offset |= (PCIC_REG << 8);
+	/* REG == "region active" pin on card */
+    }
+    /*
+     * okay, set up the chip memory mapping registers, and turn
+     * on the enable bit for this window.
+     * if we are doing 16-bit wide accesses (width == 2),
+     * turn on the appropriate bit.
+     *
+     * XXX for now, we set all of the wait state bits to zero.
+     * Not really sure how they should be set.
+     */
+    mem_start_addr = sys_addr & 0xFFF;
+    if (width == 2)
+	mem_start_addr |= (PCIC_DATA16 << 8);
+    mem_stop_addr = (sys_addr + length) & 0xFFF;
+
+    pcic_putw (slot, MEM_START_ADDR(window), mem_start_addr);
+    pcic_putw (slot, MEM_STOP_ADDR(window), mem_stop_addr);
+    pcic_putw (slot, MEM_OFFSET(window), offset);
+    /*
+     * Assert the bit (PCIC_MEMCS16) that says to decode all of
+     * the address lines.
+     */
+    pcic_putb (slot, PCIC_ADDRWINE,
+	       pcic_getb (slot, PCIC_ADDRWINE) |
+	       MEM_ENABLE_BIT(window) | PCIC_MEMCS16);
+}
+
+static void
+pcic_unmap_memory (int slot, int window)
+{
+    /*
+     * seems like we need to turn off the enable bit first, after which
+     * we can clear the registers out just to be sure.
+     */
+    pcic_putb (slot, PCIC_ADDRWINE,
+	       pcic_getb (slot, PCIC_ADDRWINE) & ~MEM_ENABLE_BIT(window));
+    pcic_putw (slot, MEM_START_ADDR(window), 0);
+    pcic_putw (slot, MEM_STOP_ADDR(window), 0);
+    pcic_putw (slot, MEM_OFFSET(window), 0);
+}
+
+/*
+ * map a range of addresses into system i/o space
+ * (no translation of i/o addresses is possible)
+ *
+ * 'width' is:
+ * + 0 to tell the PCIC to generate the ISA IOCS16* signal from
+ *   the PCMCIA IOIS16* signal.
+ * + 1 to select 8-bit width
+ * + 2 to select 16-bit width
+ */
+
+static void
+pcic_map_io (int slot, int window, unsigned short base, unsigned short length,
+	     unsigned short width)
+{
+    unsigned char x;
+
+    pcic_putw (slot, IO_START_ADDR(window), base);
+    pcic_putw (slot, IO_STOP_ADDR(window), base+length-1);
+    /*
+     * select the bits that determine whether
+     * an i/o operation is 8 or 16 bits wide
+     */
+    x = pcic_getb (slot, PCIC_IOCTL);
+    switch (width) {
+    case 0:			/* PCMCIA card decides */
+	if (window)
+	    x = (x & 0xf0) | PCIC_IO1_CS16;
+	else
+	    x = (x & 0x0f) | PCIC_IO0_CS16;
+	break;
+    case 1:			/* 8 bits wide */
+	break;
+    case 2:			/* 16 bits wide */
+	if (window)
+	    x = (x & 0xf0) | PCIC_IO1_16BIT;
+	else
+	    x = (x & 0x0f) | PCIC_IO0_16BIT;
+	break;
+    }
+    pcic_putb (slot, PCIC_IOCTL, x);
+    pcic_putb (slot, PCIC_ADDRWINE,
+	       pcic_getb (slot, PCIC_ADDRWINE) | IO_ENABLE_BIT(window));
+}
+
+#ifdef TEST
+static void
+pcic_unmap_io (int slot, int window)
+{
+    pcic_putb (slot, PCIC_ADDRWINE,
+	       pcic_getb (slot, PCIC_ADDRWINE) & ~IO_ENABLE_BIT(window));
+    pcic_putw (slot, IO_START_ADDR(window), 0);
+    pcic_putw (slot, IO_STOP_ADDR(window), 0);
+}
+#endif /* TEST */
+
+/*
+ * tell the PCIC which irq we want to use.  only the following are legal:
+ * 3, 4, 5, 7, 9, 10, 11, 12, 14, 15
+ *
+ * NB: 'irq' is an interrupt NUMBER, not a MASK as in struct isa_device.
+ */
+
+static void
+pcic_map_irq (int slot, int irq)
+{
+    if (irq < 3 || irq == 6 || irq == 8 || irq == 13 || irq > 15) {
+	printf ("ze: pcic_map_irq (slot %d): illegal irq %d\n", slot, irq);
+	return;
+    }
+    pcic_putb (slot, PCIC_INT_GEN,
+	       pcic_getb (slot, PCIC_INT_GEN) | (irq & 0x0F));
+}
+
+static void
+pcic_power_on (int slot)
+{
+    pcic_putb (slot, PCIC_POWER,
+	       pcic_getb (slot, PCIC_POWER) | PCIC_DISRST | PCIC_PCPWRE);
+    DELAY (50000);
+    pcic_putb (slot, PCIC_POWER,
+	       pcic_getb (slot, PCIC_POWER) | PCIC_OUTENA);
+}
+
+static void
+pcic_reset (int slot)
+{
+    /* assert RESET (by clearing a bit!), wait a bit, and de-assert it */
+    pcic_putb (slot, PCIC_INT_GEN,
+	       pcic_getb (slot, PCIC_INT_GEN) & ~PCIC_CARDRESET);
+    DELAY (50000);
+    pcic_putb (slot, PCIC_INT_GEN,
+	       pcic_getb (slot, PCIC_INT_GEN) | PCIC_CARDRESET);
+}
+
+
+/*****************************************************************************
+ *                       Driver for Ethernet Adapter                         *
+ *****************************************************************************/
+/*
+ * ze_softc: per line info and status
+ */
+struct	ze_softc {
+	struct	arpcom arpcom;	/* ethernet common */
+
+	char	*type_str;	/* pointer to type string */
+	char    *mau;		/* type of media access unit */
+#if 0
+	u_char	vendor;		/* interface vendor */
+	u_char	type;		/* interface type code */
+#endif
+
+#if 0
+	u_short	vector;		/* interrupt vector */
+#endif
+	u_short	nic_addr;	/* NIC (DS8390) I/O bus address */
+
+	caddr_t	smem_start;	/* shared memory start address */
+	caddr_t	smem_end;	/* shared memory end address */
+	u_long	smem_size;	/* total shared memory size */
+	caddr_t	smem_ring;	/* start of RX ring-buffer (in smem) */
+
+	caddr_t	bpf;		/* BPF "magic cookie" */
+
+	u_char	memwidth;	/* width of access to card mem 8 or 16 */
+	u_char	xmit_busy;	/* transmitter is busy */
+	u_char	txb_cnt;	/* Number of transmit buffers */
+	u_char	txb_next;	/* Pointer to next buffer ready to xmit */
+	u_short	txb_next_len;	/* next xmit buffer length */
+	u_char	data_buffered;	/* data has been buffered in interface memory */
+	u_char	tx_page_start;	/* first page of TX buffer area */
+
+	u_char	rec_page_start;	/* first page of RX ring-buffer */
+	u_char	rec_page_stop;	/* last page of RX ring-buffer */
+	u_char	next_packet;	/* pointer to next unread RX packet */
+} ze_softc[NZE];
+
+int	ze_attach(), ze_ioctl(), ze_probe();
+void	ze_init(), ze_start(), ze_stop(), ze_intr();
+void	ze_reset(), ze_watchdog(), ze_get_packet();
+
+static inline void ze_rint();
+static inline void ze_xmit();
+static inline char *ze_ring_copy();
+
+extern int ether_output();
+
+struct isa_driver zedriver = {
+	ze_probe,
+	ze_attach,
+	"ze"
+};
+
+#define	ETHER_MIN_LEN	64
+#define ETHER_MAX_LEN	1518
+#define	ETHER_ADDR_LEN	6
+#define	ETHER_HDR_SIZE	14
+
+static unsigned char enet_addr[6];
+static unsigned char card_info[256];
+ 
+#define CARD_INFO  "IBM Corp.~Ethernet~0933495"
+
+/*
+ * scan the card information structure looking for the version/product info
+ * tuple.  when we find it, compare it to the string we are looking for.
+ * return 1 if we find it, 0 otherwise.
+ */
+
+static int
+ze_check_cis (unsigned char *scratch)
+{
+    int i,j,k;
+
+    card_info[0] = '\0';
+    i = 0;
+    while (scratch[i] != 0xff && i < 1024) {
+	unsigned char link = scratch[i+2];
+
+#if 0
+	printf ("[%02x] %02x ", i, link);
+	for (j = 4; j < 2 * link + 4 && j < 32; j += 2)
+	    printf ("%02x ", scratch[j + i]);
+	printf ("\n");
+#endif
+	if (scratch[i] == 0x15) {
+	    /*
+	     * level 1 version/product info
+	     * copy to card_info, translating '\0' to '~'
+	     */
+	    k = 0;
+	    for (j = i+8; scratch[j] != 0xff; j += 2)
+		card_info[k++] = scratch[j] == '\0' ? '~' : scratch[j];
+	    card_info[k++] = '\0';
+	    return (memcmp (card_info, CARD_INFO, sizeof(CARD_INFO)-1) == 0);
+	}
+	i += 4 + 2 * link;
+    }
+    return 0;
+}
+
+/*
+ * Probe each slot looking for an IBM Credit Card Adapter for Ethernet
+ * For each card that we find, map its card information structure
+ * into system memory at 'scratch' and see whether it's one of ours.
+ * Return the slot number if we find a card, or -1 otherwise. 
+ *
+ * Side effects:
+ * + On success, leaves CIS mapped into memory at 'scratch';
+ *   caller must free it.
+ * + On success, leaves ethernet address in enet_addr.
+ * + Leaves product/vendor id of last card probed in 'card_info'
+ */
+
+static int
+ze_find_adapter (unsigned char *scratch)
+{
+    int slot;
+
+    for (slot = 0; slot < MAXSLOT; ++slot) {
+	/*
+	 * see if there's a PCMCIA controller here
+	 * Intel PCMCIA controllers use 0x82 and 0x83
+	 * IBM clone chips use 0x88 and 0x89, apparently
+	 */
+	unsigned char idbyte = pcic_getb (slot, PCIC_ID_REV);
+
+	if (idbyte != 0x82 && idbyte != 0x83 &&
+	    idbyte != 0x88 && idbyte != 0x89) {
+#if 0
+	    printf ("ibmccae: pcic slot %d: wierd id/rev code 0x%02x\n",
+		    slot, idbyte);
+#endif
+	    continue;
+	}
+	if ((pcic_getb (slot, PCIC_STATUS) & PCIC_CD) != PCIC_CD) {
+	    printf ("ze: slot %d: no card in slot\n", slot);
+	    /* no card in slot */
+	    continue;
+	}
+	pcic_power_on (slot);
+	pcic_reset (slot);
+	/*
+	 * map the card's attribute memory and examine its 
+	 * card information structure tuples for something
+	 * we recognize.
+	 */
+	pcic_map_memory (slot, 0, kvtop (scratch), 0L,
+			 0xFFFL, ATTRIBUTE, 1);
+	
+	if ((ze_check_cis (scratch)) > 0) {
+	    /* found it */
+	    printf ("ze: found card in slot %d\n", slot);
+	    return slot;
+	}
+	else
+	    printf ("ze: pcmcia slot %d: %s\n", slot, card_info);
+	pcic_unmap_memory (slot, 0);
+    }
+    return -1;
+}
+
+
+/*
+ * macros to handle casting unsigned long to (char *) so we can
+ * read/write into physical memory space.
+ */
+
+#define PEEK(addr) (*((unsigned char *)(addr)))
+#define POKE(addr,val) do { PEEK(addr) = (val); } while (0)
+
+/*
+ * Determine if the device is present
+ *
+ *   on entry:
+ * 	a pointer to an isa_device struct
+ *   on exit:
+ *	NULL if device not found
+ *	or # of i/o addresses used (if found)
+ */
+int
+ze_probe(isa_dev)
+	struct isa_device *isa_dev;
+{
+	struct ze_softc *sc = &ze_softc[isa_dev->id_unit];
+	int i, x;
+	u_int memsize;
+	u_char iptr, memwidth, sum, tmp;
+	int slot;
+
+        if ((slot = ze_find_adapter (isa_dev->id_maddr)) < 0)
+	    return NULL;
+
+	/*
+	 * okay, we found a card, so set it up
+	 */
+	/*
+	 * Inhibit 16 bit memory delay.
+	 * POINTETH.SYS apparently does this, for what reason I don't know.
+	 */
+	pcic_putb (slot, PCIC_CDGC,
+		   pcic_getb (slot, PCIC_CDGC) | PCIC_16_DL_INH);
+	/*
+	 * things to map
+	 * (1) card's EEPROM is already mapped by the find_adapter routine
+	 *     but we still need to get the card's ethernet address.
+	 *     after that we unmap that part of attribute memory.
+	 * (2) card configuration registers need to be mapped in so we
+	 *     can set the configuration and socket # registers.
+	 * (3) shared memory packet buffer
+	 * (4) i/o ports
+	 * (5) IRQ
+	 */
+	/*
+	 * Sigh.  Location of the ethernet address isn't documented in [1].
+	 * It was derived by doing a hex dump of all of attribute memory
+	 * and looking for the IBM vendor prefix.
+	 */
+	enet_addr[0] = PEEK(isa_dev->id_maddr+0xff0);
+	enet_addr[1] = PEEK(isa_dev->id_maddr+0xff2);
+	enet_addr[2] = PEEK(isa_dev->id_maddr+0xff4);
+	enet_addr[3] = PEEK(isa_dev->id_maddr+0xff6);
+	enet_addr[4] = PEEK(isa_dev->id_maddr+0xff8);
+	enet_addr[5] = PEEK(isa_dev->id_maddr+0xffa);
+	pcic_unmap_memory (slot, 0);
+
+	/*
+	 * (2) map card configuration registers.  these are offset
+	 * in card memory space by 0x20000.  normally we could get
+	 * this offset from the card information structure, but I'm
+	 * too lazy and am not quite sure if I understand the CIS anyway.
+	 *
+	 * XXX IF YOU'RE TRYING TO PORT THIS DRIVER FOR A DIFFERENT
+	 * PCMCIA CARD, the most likely thing to change is the constant
+	 * 0x20000 in the next statement.  Oh yes, also change the
+	 * card id string that we probe for.
+	 */
+	pcic_map_memory (slot, 0, kvtop (isa_dev->id_maddr), 0x20000, 8L,
+			 ATTRIBUTE, 1);
+	POKE(isa_dev->id_maddr, 0x80);	/* reset the card (how long?) */
+	DELAY (10000);
+	/*
+	 * Set the configuration index.  According to [1], the adapter won't
+	 * respond to any i/o signals until we do this; it uses the
+	 * Memory Only interface (whatever that is; it's not documented).
+	 * Also turn on "level" (not pulse) interrupts.
+	 *
+	 * XXX probably should init the socket and copy register also,
+	 * so that we can deal with multiple instances of the same card.
+	 */
+	POKE(isa_dev->id_maddr, 0x41);
+	pcic_unmap_memory (slot, 0);
+
+	/*
+	 * (3) now map in the shared memory buffer.  This has to be mapped
+	 * as words, not bytes, and on a 16k boundary.  The offset value
+	 * was derived by installing IBM's POINTETH.SYS under DOS and
+	 * looking at the PCIC registers; it's not documented in IBM's
+	 * tech ref manual ([1]).
+	 */
+	pcic_map_memory (slot, 0, kvtop (isa_dev->id_maddr), 0x4000L, 0x4000L,
+			 COMMON, 2);
+
+	/*
+	 * (4) map i/o ports.
+	 *
+	 * XXX is it possible that the config file leaves this unspecified,
+	 * in which case we have to pick one?
+	 *
+	 * At least one PCMCIA device driver I'v seen maps a block
+	 * of 32 consecutive i/o ports as two windows of 16 ports each.
+	 * Maybe some other pcic chips are restricted to 16-port windows;
+	 * the 82365SL doesn't seem to have that problem.  But since
+	 * we have an extra window anyway...
+	 */
+#ifdef SHARED_MEMORY
+	pcic_map_io (slot, 0, isa_dev->id_iobase, 32, 1);
+#else
+	pcic_map_io (slot, 0, isa_dev->id_iobase, 16, 1);
+	pcic_map_io (slot, 1, isa_dev->id_iobase+16, 16, 2);
+#endif /* SHARED_MEMORY */
+
+	/*
+	 * (5) configure the card for the desired interrupt
+	 *
+	 * XXX is it possible that the config file leaves this unspecified?
+	 */
+	pcic_map_irq (slot, ffs (isa_dev->id_irq) - 1);
+
+	/* tell the PCIC that this is an I/O card (not memory) */
+	pcic_putb (slot, PCIC_INT_GEN,
+		   pcic_getb (slot, PCIC_INT_GEN) | PCIC_CARDTYPE);
+
+#if 0
+	/* tell the PCIC to use level-mode interrupts */
+	/* XXX this register may not be present on all controllers */
+	pcic_putb (slot, PCIC_GLO_CTRL,
+		   pcic_getb (slot, PCIC_GLO_CTRL) | PCIC_LVL_MODE);
+#endif
+	
+#if 0
+	pcic_print_regs (slot);
+#endif
+	/*
+	 * Setup i/o addresses
+	 */
+	sc->nic_addr = isa_dev->id_iobase;
+#if 0
+	sc->vector = isa_dev->id_irq;
+#endif
+	sc->smem_start = (caddr_t)isa_dev->id_maddr;
+ 
+#if 0
+	sc->vendor = ZE_VENDOR_IBM;
+	sc->type = xxx;
+#endif
+
+	/* reset card to force it into a known state */
+	tmp = inb (isa_dev->id_iobase + ZE_RESET);
+	DELAY(5000);
+	outb (isa_dev->id_iobase + ZE_RESET, tmp);
+	DELAY(5000);
+
+	/*
+	 * query MAM bit in misc register for 10base2
+	 */
+	tmp = inb (isa_dev->id_iobase + ZE_MISC);
+	sc->mau = tmp & 0x09 ? "10base2" : "10baseT";
+
+	/* set width/size */
+	sc->type_str = "IBM PCMCIA";
+	memsize = 16*1024;
+	sc->memwidth = 16;
+
+	/* allocate 1 xmit buffer */
+	sc->smem_ring = sc->smem_start + (ZE_PAGE_SIZE * ZE_TXBUF_SIZE);
+	sc->txb_cnt = 1;
+	sc->rec_page_start = ZE_TXBUF_SIZE + ZE_PAGE_OFFSET;
+	sc->smem_size = memsize;
+	sc->smem_end = sc->smem_start + memsize;
+	sc->rec_page_stop = memsize / ZE_PAGE_SIZE + ZE_PAGE_OFFSET;
+	sc->tx_page_start = ZE_PAGE_OFFSET;
+
+	/* get station address */
+	for (i = 0; i < ETHER_ADDR_LEN; ++i)
+		sc->arpcom.ac_enaddr[i] = enet_addr[i];
+	
+	isa_dev->id_msize = memsize;
+	return 32;
+}
+ 
+/*
+ * Install interface into kernel networking data structures
+ */
+int
+ze_attach(isa_dev)
+	struct isa_device *isa_dev;
+{
+	struct ze_softc *sc = &ze_softc[isa_dev->id_unit];
+	struct ifnet *ifp = &sc->arpcom.ac_if;
+	struct ifaddr *ifa;
+	struct sockaddr_dl *sdl;
+ 
+	/*
+	 * Set interface to stopped condition (reset)
+	 */
+	ze_stop(isa_dev->id_unit);
+
+	/*
+	 * Initialize ifnet structure
+	 */
+	ifp->if_unit = isa_dev->id_unit;
+	ifp->if_name = "ze" ;
+	ifp->if_mtu = ETHERMTU;
+	ifp->if_init = ze_init;
+	ifp->if_output = ether_output;
+	ifp->if_start = ze_start;
+	ifp->if_ioctl = ze_ioctl;
+	ifp->if_reset = ze_reset;
+	ifp->if_watchdog = ze_watchdog;
+
+	/*
+	 * Set default state for LLC0 flag (used to disable the tranceiver
+	 *	for AUI operation), based on compile-time config option.
+	 */
+	if (isa_dev->id_flags & ZE_FLAGS_DISABLE_TRANCEIVER)
+		ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS
+			| IFF_LLC0);
+	else
+		ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS);
+
+	/*
+	 * Attach the interface
+	 */
+	if_attach(ifp);
+
+	/*
+	 * Search down the ifa address list looking for the AF_LINK type entry
+	 */
+ 	ifa = ifp->if_addrlist;
+	while ((ifa != 0) && (ifa->ifa_addr != 0) &&
+	    (ifa->ifa_addr->sa_family != AF_LINK))
+		ifa = ifa->ifa_next;
+	/*
+	 * If we find an AF_LINK type entry we fill in the hardware address.
+	 *	This is useful for netstat(1) to keep track of which interface
+	 *	is which.
+	 */
+	if ((ifa != 0) && (ifa->ifa_addr != 0)) {
+		/*
+		 * Fill in the link-level address for this interface
+		 */
+		sdl = (struct sockaddr_dl *)ifa->ifa_addr;
+		sdl->sdl_type = IFT_ETHER;
+		sdl->sdl_alen = ETHER_ADDR_LEN;
+		sdl->sdl_slen = 0;
+		bcopy(sc->arpcom.ac_enaddr, LLADDR(sdl), ETHER_ADDR_LEN);
+	}
+
+	/*
+	 * Print additional info when attached
+	 */
+	printf("ze%d: address %s, type %s (%dbit)%s, MAU %s\n",
+	       isa_dev->id_unit,
+	       ether_sprintf(sc->arpcom.ac_enaddr), sc->type_str,
+	       sc->memwidth,
+	       (ifp->if_flags & IFF_LLC0 ? " [tranceiver disabled]" : ""),
+	       sc->mau);
+
+	/*
+	 * If BPF is in the kernel, call the attach for it
+	 */
+#if NBPFILTER > 0
+	bpfattach(&sc->bpf, ifp, DLT_EN10MB, sizeof(struct ether_header));
+#endif
+	return 1;
+}
+ 
+/*
+ * Reset interface.
+ */
+void
+ze_reset(unit)
+	int unit;
+{
+	int s;
+
+	s = splnet();
+
+	/*
+	 * Stop interface and re-initialize.
+	 */
+	ze_stop(unit);
+	ze_init(unit);
+
+	(void) splx(s);
+}
+ 
+/*
+ * Take interface offline.
+ */
+void
+ze_stop(unit)
+	int unit;
+{
+	struct ze_softc *sc = &ze_softc[unit];
+	int n = 5000;
+ 
+	/*
+	 * Stop everything on the interface, and select page 0 registers.
+	 */
+	outb(sc->nic_addr + ZE_P0_CR, ZE_CR_RD2|ZE_CR_STP);
+
+	/*
+	 * Wait for interface to enter stopped state, but limit # of checks
+	 *	to 'n' (about 5ms). It shouldn't even take 5us on modern
+	 *	DS8390's, but just in case it's an old one.
+	 */
+	while (((inb(sc->nic_addr + ZE_P0_ISR) & ZE_ISR_RST) == 0) && --n);
+
+}
+
+/*
+ * Device timeout/watchdog routine. Entered if the device neglects to
+ *	generate an interrupt after a transmit has been started on it.
+ */
+void
+ze_watchdog(unit)
+	int unit;
+{
+#if 1
+    struct ze_softc *sc = &ze_softc[unit];
+    u_char isr, imr;
+    u_short imask;
+
+    /* select page zero */
+    outb (sc->nic_addr + ZE_P0_CR, 
+	  (inb (sc->nic_addr + ZE_P0_CR) & 0x3f) | ZE_CR_PAGE_0);
+
+    /* read interrupt status register */
+    isr = inb (sc->nic_addr + ZE_P0_ISR) & 0xff;
+
+    /* select page two */
+    outb (sc->nic_addr + ZE_P0_CR, 
+	  (inb (sc->nic_addr + ZE_P0_CR) & 0x3f) | ZE_CR_PAGE_2); 
+
+    /* read interrupt mask register */
+    imr = inb (sc->nic_addr + ZE_P2_IMR) & 0xff;
+
+    imask = inb(IO_ICU2) << 8 | inb(IO_ICU1);
+
+    log (LOG_ERR, "ze%d: device timeout, isr=%02x, imr=%02x, imask=%04x\n",
+	 unit, isr, imr, imask);
+#else
+    log(LOG_ERR, "ze%d: device timeout\n", unit);
+#endif
+
+    ze_reset(unit);
+}
+
+/*
+ * Initialize device. 
+ */
+void
+ze_init(unit)
+	int unit;
+{
+	struct ze_softc *sc = &ze_softc[unit];
+	struct ifnet *ifp = &sc->arpcom.ac_if;
+	int i, s;
+	u_char	command;
+
+
+	/* address not known */
+	if (ifp->if_addrlist == (struct ifaddr *)0) return;
+
+	/*
+	 * Initialize the NIC in the exact order outlined in the NS manual.
+	 *	This init procedure is "mandatory"...don't change what or when
+	 *	things happen.
+	 */
+	s = splnet();
+
+	/* reset transmitter flags */
+	sc->data_buffered = 0;
+	sc->xmit_busy = 0;
+	sc->arpcom.ac_if.if_timer = 0;
+
+	sc->txb_next = 0;
+
+	/* This variable is used below - don't move this assignment */
+	sc->next_packet = sc->rec_page_start + 1;
+
+	/*
+	 * Set interface for page 0, Remote DMA complete, Stopped
+	 */
+	outb(sc->nic_addr + ZE_P0_CR, ZE_CR_RD2|ZE_CR_STP);
+
+	if (sc->memwidth == 16) {
+		/*
+		 * Set FIFO threshold to 8, No auto-init Remote DMA,
+		 *	byte order=80x86, word-wide DMA xfers
+		 */
+		outb(sc->nic_addr + ZE_P0_DCR, ZE_DCR_FT1|ZE_DCR_WTS);
+	} else {
+		/*
+		 * Same as above, but byte-wide DMA xfers
+		 */
+		outb(sc->nic_addr + ZE_P0_DCR, ZE_DCR_FT1);
+	}
+
+	/*
+	 * Clear Remote Byte Count Registers
+	 */
+	outb(sc->nic_addr + ZE_P0_RBCR0, 0);
+	outb(sc->nic_addr + ZE_P0_RBCR1, 0);
+
+	/*
+	 * Enable reception of broadcast packets
+	 */
+	outb(sc->nic_addr + ZE_P0_RCR, ZE_RCR_AB);
+
+	/*
+	 * Place NIC in internal loopback mode
+	 */
+	outb(sc->nic_addr + ZE_P0_TCR, ZE_TCR_LB0);
+
+	/*
+	 * Initialize transmit/receive (ring-buffer) Page Start
+	 */
+	outb(sc->nic_addr + ZE_P0_TPSR, sc->tx_page_start);
+	outb(sc->nic_addr + ZE_P0_PSTART, sc->rec_page_start);
+
+	/*
+	 * Initialize Receiver (ring-buffer) Page Stop and Boundry
+	 */
+	outb(sc->nic_addr + ZE_P0_PSTOP, sc->rec_page_stop);
+	outb(sc->nic_addr + ZE_P0_BNRY, sc->rec_page_start);
+
+	/*
+	 * Clear all interrupts. A '1' in each bit position clears the
+	 *	corresponding flag.
+	 */
+	outb(sc->nic_addr + ZE_P0_ISR, 0xff);
+
+	/*
+	 * Enable the following interrupts: receive/transmit complete,
+	 *	receive/transmit error, and Receiver OverWrite.
+	 *
+	 * Counter overflow and Remote DMA complete are *not* enabled.
+	 */
+	outb(sc->nic_addr + ZE_P0_IMR,
+		ZE_IMR_PRXE|ZE_IMR_PTXE|ZE_IMR_RXEE|ZE_IMR_TXEE|ZE_IMR_OVWE);
+
+	/*
+	 * Program Command Register for page 1
+	 */
+	outb(sc->nic_addr + ZE_P0_CR, ZE_CR_PAGE_1|ZE_CR_RD2|ZE_CR_STP);
+
+	/*
+	 * Copy out our station address
+	 */
+	for (i = 0; i < ETHER_ADDR_LEN; ++i)
+		outb(sc->nic_addr + ZE_P1_PAR0 + i, sc->arpcom.ac_enaddr[i]);
+
+#if NBPFILTER > 0
+	/*
+	 * Initialize multicast address hashing registers to accept
+	 *	 all multicasts (only used when in promiscuous mode)
+	 */
+	for (i = 0; i < 8; ++i)
+		outb(sc->nic_addr + ZE_P1_MAR0 + i, 0xff);
+#endif
+
+	/*
+	 * Set Current Page pointer to next_packet (initialized above)
+	 */
+	outb(sc->nic_addr + ZE_P1_CURR, sc->next_packet);
+
+	/*
+	 * Set Command Register for page 0, Remote DMA complete,
+	 * 	and interface Start.
+	 */
+	outb(sc->nic_addr + ZE_P1_CR, ZE_CR_RD2|ZE_CR_STA);
+
+	/*
+	 * Take interface out of loopback
+	 */
+	outb(sc->nic_addr + ZE_P0_TCR, 0);
+
+#if 0
+	/*
+	 * If this is a 3Com board, the tranceiver must be software enabled
+	 *	(there is no settable hardware default).
+	 */
+	if (sc->vendor == ZE_VENDOR_3COM) {
+		if (ifp->if_flags & IFF_LLC0) {
+			outb(sc->asic_addr + ZE_3COM_CR, 0);
+		} else {
+			outb(sc->asic_addr + ZE_3COM_CR, ZE_3COM_CR_XSEL);
+		}
+	}
+#endif
+
+	/*
+	 * Set 'running' flag, and clear output active flag.
+	 */
+	ifp->if_flags |= IFF_RUNNING;
+	ifp->if_flags &= ~IFF_OACTIVE;
+
+	/*
+	 * ...and attempt to start output
+	 */
+	ze_start(ifp);
+
+	(void) splx(s);
+}
+ 
+/*
+ * This routine actually starts the transmission on the interface
+ */
+static inline void
+ze_xmit(ifp)
+	struct ifnet *ifp;
+{
+	struct ze_softc *sc = &ze_softc[ifp->if_unit];
+	u_short len = sc->txb_next_len;
+
+	/*
+	 * Set NIC for page 0 register access
+	 */
+	outb(sc->nic_addr + ZE_P0_CR, ZE_CR_RD2|ZE_CR_STA);
+
+	/*
+	 * Set TX buffer start page
+	 */
+	outb(sc->nic_addr + ZE_P0_TPSR, sc->tx_page_start +
+		sc->txb_next * ZE_TXBUF_SIZE);
+
+	/*
+	 * Set TX length
+	 */
+	outb(sc->nic_addr + ZE_P0_TBCR0, len & 0xff);
+	outb(sc->nic_addr + ZE_P0_TBCR1, len >> 8);
+
+	/*
+	 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
+	 */
+	outb(sc->nic_addr + ZE_P0_CR, ZE_CR_RD2|ZE_CR_TXP|ZE_CR_STA);
+
+	sc->xmit_busy = 1;
+	sc->data_buffered = 0;
+	
+	/*
+	 * Switch buffers if we are doing double-buffered transmits
+	 */
+	if ((sc->txb_next == 0) && (sc->txb_cnt > 1)) 
+		sc->txb_next = 1;
+	else
+		sc->txb_next = 0;
+
+	/*
+	 * Set a timer just in case we never hear from the board again
+	 */
+	ifp->if_timer = 2;
+}
+
+/*
+ * Start output on interface.
+ * We make two assumptions here:
+ *  1) that the current priority is set to splnet _before_ this code
+ *     is called *and* is returned to the appropriate priority after
+ *     return
+ *  2) that the IFF_OACTIVE flag is checked before this code is called
+ *     (i.e. that the output part of the interface is idle)
+ */
+void
+ze_start(ifp)
+	struct ifnet *ifp;
+{
+	struct ze_softc *sc = &ze_softc[ifp->if_unit];
+	struct mbuf *m0, *m;
+	caddr_t buffer;
+	int len;
+	u_char laar_tmp;
+
+outloop:
+	/*
+	 * See if there is room to send more data (i.e. one or both of the
+	 *	buffers is empty).
+	 */
+	if (sc->data_buffered)
+		if (sc->xmit_busy) {
+			/*
+			 * No room. Indicate this to the outside world
+			 *	and exit.
+			 */
+			ifp->if_flags |= IFF_OACTIVE;
+			return;
+		} else {
+			/*
+			 * Data is buffered, but we're not transmitting, so
+			 *	start the xmit on the buffered data.
+			 * Note that ze_xmit() resets the data_buffered flag
+			 *	before returning.
+			 */
+			ze_xmit(ifp);
+		}
+
+	IF_DEQUEUE(&sc->arpcom.ac_if.if_snd, m);
+	if (m == NULL) {
+	/*
+	 * The following isn't pretty; we are using the !OACTIVE flag to
+	 * indicate to the outside world that we can accept an additional
+	 * packet rather than that the transmitter is _actually_
+	 * active. Indeed, the transmitter may be active, but if we haven't
+	 * filled the secondary buffer with data then we still want to
+	 * accept more.
+	 * Note that it isn't necessary to test the data_buffered flag -
+	 * we wouldn't have tried to de-queue the packet in the first place
+	 * if it was set.
+	 */
+		ifp->if_flags &= ~IFF_OACTIVE;
+		return;
+	}
+
+	/*
+	 * Copy the mbuf chain into the transmit buffer
+	 */
+#if 0
+	/*
+	 * Enable 16bit access to shared memory on WD/SMC boards
+	 */
+	if (sc->memwidth == 16)
+		if (sc->vendor == ZE_VENDOR_WD_SMC) {
+			laar_tmp = inb(sc->asic_addr + ZE_WD_LAAR);
+			outb(sc->asic_addr + ZE_WD_LAAR, laar_tmp | ZE_WD_LAAR_M16EN);
+		}
+#endif
+
+	buffer = sc->smem_start + (sc->txb_next * ZE_TXBUF_SIZE * ZE_PAGE_SIZE);
+	len = 0;
+	for (m0 = m; m != 0; m = m->m_next) {
+		bcopy(mtod(m, caddr_t), buffer, m->m_len);
+		buffer += m->m_len;
+        	len += m->m_len;
+	}
+
+#if 0
+	/*
+	 * Restore previous shared mem access type
+	 */
+	if (sc->memwidth == 16)
+		if (sc->vendor == ZE_VENDOR_WD_SMC) {
+			outb(sc->asic_addr + ZE_WD_LAAR, laar_tmp);
+		}
+#endif
+
+	sc->txb_next_len = MAX(len, ETHER_MIN_LEN);
+
+	if (sc->txb_cnt > 1)
+		/*
+		 * only set 'buffered' flag if doing multiple buffers
+		 */
+		sc->data_buffered = 1;
+
+	if (sc->xmit_busy == 0)
+		ze_xmit(ifp);
+	/*
+	 * If there is BPF support in the configuration, tap off here.
+	 *   The following has support for converting trailer packets
+	 *   back to normal.
+	 */
+#if NBPFILTER > 0
+	if (sc->bpf) {
+		u_short etype;
+		int off, datasize, resid;
+		struct ether_header *eh;
+		struct trailer_header {
+			u_short ether_type;
+			u_short ether_residual;
+		} trailer_header;
+		char ether_packet[ETHER_MAX_LEN];
+		char *ep;
+
+		ep = ether_packet;
+
+		/*
+		 * We handle trailers below:
+		 * Copy ether header first, then residual data,
+		 * then data. Put all this in a temporary buffer
+		 * 'ether_packet' and send off to bpf. Since the
+		 * system has generated this packet, we assume
+		 * that all of the offsets in the packet are
+		 * correct; if they're not, the system will almost
+		 * certainly crash in m_copydata.
+		 * We make no assumptions about how the data is
+		 * arranged in the mbuf chain (i.e. how much
+		 * data is in each mbuf, if mbuf clusters are
+		 * used, etc.), which is why we use m_copydata
+		 * to get the ether header rather than assume
+		 * that this is located in the first mbuf.
+		 */
+		/* copy ether header */
+		m_copydata(m0, 0, sizeof(struct ether_header), ep);
+		eh = (struct ether_header *) ep;
+		ep += sizeof(struct ether_header);
+		etype = ntohs(eh->ether_type);
+		if (etype >= ETHERTYPE_TRAIL &&
+		    etype < ETHERTYPE_TRAIL+ETHERTYPE_NTRAILER) {
+			datasize = ((etype - ETHERTYPE_TRAIL) << 9);
+			off = datasize + sizeof(struct ether_header);
+
+			/* copy trailer_header into a data structure */
+			m_copydata(m0, off, sizeof(struct trailer_header),
+				&trailer_header.ether_type);
+
+			/* copy residual data */
+			m_copydata(m0, off+sizeof(struct trailer_header),
+				resid = ntohs(trailer_header.ether_residual) -
+				sizeof(struct trailer_header), ep);
+			ep += resid;
+
+			/* copy data */
+			m_copydata(m0, sizeof(struct ether_header),
+				datasize, ep);
+			ep += datasize;
+
+			/* restore original ether packet type */
+			eh->ether_type = trailer_header.ether_type;
+
+			bpf_tap(sc->bpf, ether_packet, ep - ether_packet);
+		} else
+			bpf_mtap(sc->bpf, m0);
+	}
+#endif
+
+	m_freem(m0);
+
+	/*
+	 * If we are doing double-buffering, a buffer might be free to
+	 *	fill with another packet, so loop back to the top.
+	 */
+	if (sc->txb_cnt > 1)
+		goto outloop;
+	else {
+		ifp->if_flags |= IFF_OACTIVE;
+		return;
+	}
+}
+ 
+/*
+ * Ethernet interface receiver interrupt.
+ */
+static inline void /* only called from one place, so may as well integrate */
+ze_rint(unit)
+	int unit;
+{
+	register struct ze_softc *sc = &ze_softc[unit];
+	u_char boundry, current;
+	u_short len;
+	struct ze_ring *packet_ptr;
+
+	/*
+	 * Set NIC to page 1 registers to get 'current' pointer
+	 */
+	outb(sc->nic_addr + ZE_P0_CR, ZE_CR_PAGE_1|ZE_CR_RD2|ZE_CR_STA);
+
+	/*
+	 * 'sc->next_packet' is the logical beginning of the ring-buffer - i.e.
+	 *	it points to where new data has been buffered. The 'CURR'
+	 *	(current) register points to the logical end of the ring-buffer
+	 *	- i.e. it points to where additional new data will be added.
+	 *	We loop here until the logical beginning equals the logical
+	 *	end (or in other words, until the ring-buffer is empty).
+	 */
+	while (sc->next_packet != inb(sc->nic_addr + ZE_P1_CURR)) {
+
+		/* get pointer to this buffer header structure */
+		packet_ptr = (struct ze_ring *)(sc->smem_ring +
+			 (sc->next_packet - sc->rec_page_start) * ZE_PAGE_SIZE);
+
+		/*
+		 * The byte count includes the FCS - Frame Check Sequence (a
+		 *	32 bit CRC).
+		 */
+		len = packet_ptr->count;
+		if ((len >= ETHER_MIN_LEN) && (len <= ETHER_MAX_LEN)) {
+			/*
+			 * Go get packet. len - 4 removes CRC from length.
+			 * (packet_ptr + 1) points to data just after the packet ring
+			 *	header (+4 bytes)
+			 */
+			ze_get_packet(sc, (caddr_t)(packet_ptr + 1), len - 4);
+			++sc->arpcom.ac_if.if_ipackets;
+		} else {
+			/*
+			 * Really BAD...probably indicates that the ring pointers
+			 *	are corrupted. Also seen on early rev chips under
+			 *	high load - the byte order of the length gets switched.
+			 */
+			log(LOG_ERR,
+				"ze%d: shared memory corrupt - invalid packet length %d\n",
+				unit, len);
+			ze_reset(unit);
+			return;
+		}
+
+		/*
+		 * Update next packet pointer
+		 */
+		sc->next_packet = packet_ptr->next_packet;
+
+		/*
+		 * Update NIC boundry pointer - being careful to keep it
+		 *	one buffer behind. (as recommended by NS databook)
+		 */
+		boundry = sc->next_packet - 1;
+		if (boundry < sc->rec_page_start)
+			boundry = sc->rec_page_stop - 1;
+
+		/*
+		 * Set NIC to page 0 registers to update boundry register
+		 */
+		outb(sc->nic_addr + ZE_P0_CR, ZE_CR_RD2|ZE_CR_STA);
+
+		outb(sc->nic_addr + ZE_P0_BNRY, boundry);
+
+		/*
+		 * Set NIC to page 1 registers before looping to top (prepare to
+		 *	get 'CURR' current pointer)
+		 */
+		outb(sc->nic_addr + ZE_P0_CR, ZE_CR_PAGE_1|ZE_CR_RD2|ZE_CR_STA);
+	}
+}
+
+/*
+ * Ethernet interface interrupt processor
+ */
+void
+zeintr(unit)
+	int unit;
+{
+	struct ze_softc *sc = &ze_softc[unit];
+	u_char isr;
+
+	/*
+	 * Set NIC to page 0 registers
+	 */
+	outb(sc->nic_addr + ZE_P0_CR, ZE_CR_RD2|ZE_CR_STA);
+
+	/*
+	 * loop until there are no more new interrupts
+	 */
+	while (isr = inb(sc->nic_addr + ZE_P0_ISR)) {
+
+		/*
+		 * reset all the bits that we are 'acknowleging'
+		 *	by writing a '1' to each bit position that was set
+		 * (writing a '1' *clears* the bit)
+		 */
+		outb(sc->nic_addr + ZE_P0_ISR, isr);
+
+		/*
+		 * Transmit error. If a TX completed with an error, we end up
+		 *	throwing the packet away. Really the only error that is
+		 *	possible is excessive collisions, and in this case it is
+		 *	best to allow the automatic mechanisms of TCP to backoff
+		 *	the flow. Of course, with UDP we're screwed, but this is
+		 *	expected when a network is heavily loaded.
+		 */
+		if (isr & ZE_ISR_TXE) {
+			u_char tsr = inb(sc->nic_addr + ZE_P0_TSR);
+			u_char ncr = inb(sc->nic_addr + ZE_P0_NCR);
+
+			/*
+			 * Excessive collisions (16)
+			 */
+			if ((tsr & ZE_TSR_ABT) && (ncr == 0)) {
+				/*
+				 *    When collisions total 16, the P0_NCR will
+				 * indicate 0, and the TSR_ABT is set.
+				 */
+				sc->arpcom.ac_if.if_collisions += 16;
+			} else
+				sc->arpcom.ac_if.if_collisions += ncr;
+
+			/*
+			 * update output errors counter
+			 */
+			++sc->arpcom.ac_if.if_oerrors;
+
+			/*
+			 * reset tx busy and output active flags
+			 */
+			sc->xmit_busy = 0;
+			sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE;
+
+			/*
+			 * clear watchdog timer
+			 */
+			sc->arpcom.ac_if.if_timer = 0;
+		}
+				
+			
+		/*
+		 * Receiver Error. One or more of: CRC error, frame alignment error
+		 *	FIFO overrun, or missed packet.
+		 */
+		if (isr & ZE_ISR_RXE) {
+			++sc->arpcom.ac_if.if_ierrors;
+#ifdef ZE_DEBUG
+#if 0
+			printf("ze%d: receive error %x\n", unit,
+				inb(sc->nic_addr + ZE_P0_RSR));
+#else
+			printf("ze%d: receive error %b\n", unit,
+				inb(sc->nic_addr + ZE_P0_RSR),
+			       "\20\8DEF\7REC DISAB\6PHY/MC\5MISSED\4OVR\3ALIGN\2FCS\1RCVD");
+#endif
+#endif
+		}
+
+		/*
+		 * Overwrite warning. In order to make sure that a lockup
+		 *	of the local DMA hasn't occurred, we reset and
+		 *	re-init the NIC. The NSC manual suggests only a
+		 *	partial reset/re-init is necessary - but some
+		 *	chips seem to want more. The DMA lockup has been
+		 *	seen only with early rev chips - Methinks this
+		 *	bug was fixed in later revs. -DG
+		 */
+		if (isr & ZE_ISR_OVW) {
+			++sc->arpcom.ac_if.if_ierrors;
+#if 0
+			/* sigh.  this happens too often on our net */
+			log(LOG_WARNING,
+				"ze%d: warning - receiver ring buffer overrun\n",
+				unit);
+#endif
+			/*
+			 * Stop/reset/re-init NIC
+			 */
+			ze_reset(unit);
+		}
+
+		/*
+		 * Transmission completed normally.
+		 */
+		if (isr & ZE_ISR_PTX) {
+
+			/*
+			 * reset tx busy and output active flags
+			 */
+			sc->xmit_busy = 0;
+			sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE;
+
+			/*
+			 * clear watchdog timer
+			 */
+			sc->arpcom.ac_if.if_timer = 0;
+
+			/*
+			 * Update total number of successfully transmitted
+			 *	packets.
+			 */
+			++sc->arpcom.ac_if.if_opackets;
+
+			/*
+			 * Add in total number of collisions on last
+			 *	transmission.
+			 */
+			sc->arpcom.ac_if.if_collisions += inb(sc->nic_addr +
+				ZE_P0_TBCR0);
+		}
+
+		/*
+		 * Receive Completion. Go and get the packet. 
+		 *	XXX - Doing this on an error is dubious because there
+		 *	   shouldn't be any data to get (we've configured the
+		 *	   interface to not accept packets with errors).
+		 */
+		if (isr & (ZE_ISR_PRX|ZE_ISR_RXE)) {
+#if 0
+			/*
+			 * Enable access to shared memory on WD/SMC boards
+			 */
+			if (sc->memwidth == 16)
+				if (sc->vendor == ZE_VENDOR_WD_SMC) {
+					outb(sc->asic_addr + ZE_WD_LAAR,
+						inb(sc->asic_addr + ZE_WD_LAAR)
+						| ZE_WD_LAAR_M16EN);
+				}
+#endif
+			ze_rint (unit);
+
+#if 0
+			/*
+			 * Disable access to shared memory
+			 */
+			if (sc->memwidth == 16)
+				if (sc->vendor == ZE_VENDOR_WD_SMC) {
+					outb(sc->asic_addr + ZE_WD_LAAR,
+						inb(sc->asic_addr + ZE_WD_LAAR)
+						& ~ZE_WD_LAAR_M16EN);
+				}
+#endif
+		}
+
+		/*
+		 * If it looks like the transmitter can take more data,
+		 *	attempt to start output on the interface. If data is
+		 *	already buffered and ready to go, send it first.
+		 */
+		if ((sc->arpcom.ac_if.if_flags & IFF_OACTIVE) == 0) {
+			if (sc->data_buffered)
+				ze_xmit(&sc->arpcom.ac_if);
+			ze_start(&sc->arpcom.ac_if);
+		}
+
+		/*
+		 * return NIC CR to standard state: page 0, remote DMA complete,
+		 * 	start (toggling the TXP bit off, even if was just set
+		 *	in the transmit routine, is *okay* - it is 'edge'
+		 *	triggered from low to high)
+		 */
+		outb(sc->nic_addr + ZE_P0_CR, ZE_CR_RD2|ZE_CR_STA);
+
+		/*
+		 * If the Network Talley Counters overflow, read them to
+		 *	reset them. It appears that old 8390's won't
+		 *	clear the ISR flag otherwise - resulting in an
+		 *	infinite loop.
+		 */
+		if (isr & ZE_ISR_CNT) {
+			(void) inb(sc->nic_addr + ZE_P0_CNTR0);
+			(void) inb(sc->nic_addr + ZE_P0_CNTR1);
+			(void) inb(sc->nic_addr + ZE_P0_CNTR2);
+		}
+	}
+}
+ 
+/*
+ * Process an ioctl request. This code needs some work - it looks
+ *	pretty ugly.
+ */
+int
+ze_ioctl(ifp, command, data)
+	register struct ifnet *ifp;
+	int command;
+	caddr_t data;
+{
+	register struct ifaddr *ifa = (struct ifaddr *)data;
+	struct ze_softc *sc = &ze_softc[ifp->if_unit];
+	struct ifreq *ifr = (struct ifreq *)data;
+	int s, error = 0;
+
+	s = splnet();
+
+	switch (command) {
+
+	case SIOCSIFADDR:
+		ifp->if_flags |= IFF_UP;
+
+		switch (ifa->ifa_addr->sa_family) {
+#ifdef INET
+		case AF_INET:
+			ze_init(ifp->if_unit);	/* before arpwhohas */
+			/*
+			 * See if another station has *our* IP address.
+			 * i.e.: There is an address conflict! If a
+			 * conflict exists, a message is sent to the
+			 * console.
+			 */
+			((struct arpcom *)ifp)->ac_ipaddr =
+				IA_SIN(ifa)->sin_addr;
+			arpwhohas((struct arpcom *)ifp, &IA_SIN(ifa)->sin_addr);
+			break;
+#endif
+#ifdef NS
+		/*
+		 * XXX - This code is probably wrong
+		 */
+		case AF_NS:
+		    {
+			register struct ns_addr *ina = &(IA_SNS(ifa)->sns_addr);
+
+			if (ns_nullhost(*ina))
+				ina->x_host =
+					*(union ns_host *)(sc->arpcom.ac_enaddr);
+			else {
+				/* 
+				 * 
+				 */
+				bcopy((caddr_t)ina->x_host.c_host,
+				    (caddr_t)sc->arpcom.ac_enaddr,
+					sizeof(sc->arpcom.ac_enaddr));
+			}
+			/*
+			 * Set new address
+			 */
+			ze_init(ifp->if_unit);
+			break;
+		    }
+#endif
+		default:
+			ze_init(ifp->if_unit);
+			break;
+		}
+		break;
+
+	case SIOCSIFFLAGS:
+		/*
+		 * If interface is marked down and it is running, then stop it
+		 */
+		if (((ifp->if_flags & IFF_UP) == 0) &&
+		    (ifp->if_flags & IFF_RUNNING)) {
+			ze_stop(ifp->if_unit);
+			ifp->if_flags &= ~IFF_RUNNING;
+		} else {
+		/*
+		 * If interface is marked up and it is stopped, then start it
+		 */
+			if ((ifp->if_flags & IFF_UP) &&
+		    	    ((ifp->if_flags & IFF_RUNNING) == 0))
+				ze_init(ifp->if_unit);
+		}
+#if NBPFILTER > 0
+		if (ifp->if_flags & IFF_PROMISC) {
+			/*
+			 * Set promiscuous mode on interface.
+			 *	XXX - for multicasts to work, we would need to
+			 *		write 1's in all bits of multicast
+			 *		hashing array. For now we assume that
+			 *		this was done in ze_init().
+			 */
+			outb(sc->nic_addr + ZE_P0_RCR,
+				ZE_RCR_PRO|ZE_RCR_AM|ZE_RCR_AB);
+		} else {
+			/*
+			 * XXX - for multicasts to work, we would need to
+			 *	rewrite the multicast hashing array with the
+			 *	proper hash (would have been destroyed above).
+			 */
+			outb(sc->nic_addr + ZE_P0_RCR, ZE_RCR_AB);
+		}
+#endif
+#if 0
+		/*
+		 * An unfortunate hack to provide the (required) software control
+		 *	of the tranceiver for 3Com boards. The LLC0 flag disables
+		 *	the tranceiver if set.
+		 */
+		if (sc->vendor == ZE_VENDOR_3COM) {
+			if (ifp->if_flags & IFF_LLC0) {
+				outb(sc->asic_addr + ZE_3COM_CR, 0);
+			} else {
+				outb(sc->asic_addr + ZE_3COM_CR, ZE_3COM_CR_XSEL);
+			}
+		}
+#endif
+
+		break;
+
+	default:
+		error = EINVAL;
+	}
+	(void) splx(s);
+	return (error);
+}
+ 
+/*
+ * Macro to calculate a new address within shared memory when given an offset
+ *	from an address, taking into account ring-wrap.
+ */
+#define	ringoffset(sc, start, off, type) \
+	((type)( ((caddr_t)(start)+(off) >= (sc)->smem_end) ? \
+		(((caddr_t)(start)+(off))) - (sc)->smem_end \
+		+ (sc)->smem_ring: \
+		((caddr_t)(start)+(off)) ))
+
+/*
+ * Retreive packet from shared memory and send to the next level up via
+ *	ether_input(). If there is a BPF listener, give a copy to BPF, too.
+ */
+void
+ze_get_packet(sc, buf, len)
+	struct ze_softc *sc;
+	char *buf;
+	u_short len;
+{
+	struct ether_header *eh;
+    	struct mbuf *m, *head = NULL, *ze_ring_to_mbuf();
+	u_short off;
+	int resid;
+	u_short etype;
+	struct trailer_header {
+		u_short	trail_type;
+		u_short trail_residual;
+	} trailer_header;
+
+	/* Allocate a header mbuf */
+	MGETHDR(m, M_DONTWAIT, MT_DATA);
+	if (m == NULL)
+		goto bad;
+	m->m_pkthdr.rcvif = &sc->arpcom.ac_if;
+	m->m_pkthdr.len = len;
+	m->m_len = 0;
+	head = m;
+
+	eh = (struct ether_header *)buf;
+
+	/* The following sillines is to make NFS happy */
+#define EROUND	((sizeof(struct ether_header) + 3) & ~3)
+#define EOFF	(EROUND - sizeof(struct ether_header))
+
+	/*
+	 * The following assumes there is room for
+	 * the ether header in the header mbuf
+	 */
+	head->m_data += EOFF;
+	bcopy(buf, mtod(head, caddr_t), sizeof(struct ether_header));
+	buf += sizeof(struct ether_header);
+	head->m_len += sizeof(struct ether_header);
+	len -= sizeof(struct ether_header);
+
+	etype = ntohs((u_short)eh->ether_type);
+
+	/*
+	 * Deal with trailer protocol:
+	 * If trailer protocol, calculate the datasize as 'off',
+	 * which is also the offset to the trailer header.
+	 * Set resid to the amount of packet data following the
+	 * trailer header.
+	 * Finally, copy residual data into mbuf chain.
+	 */
+	if (etype >= ETHERTYPE_TRAIL &&
+	    etype < ETHERTYPE_TRAIL+ETHERTYPE_NTRAILER) {
+
+		off = (etype - ETHERTYPE_TRAIL) << 9;
+		if ((off + sizeof(struct trailer_header)) > len)
+			goto bad;	/* insanity */
+
+		eh->ether_type = *ringoffset(sc, buf, off, u_short *);
+		resid = ntohs(*ringoffset(sc, buf, off+2, u_short *));
+
+		if ((off + resid) > len) goto bad;	/* insanity */
+
+		resid -= sizeof(struct trailer_header);
+		if (resid < 0) goto bad;	/* insanity */
+
+		m = ze_ring_to_mbuf(sc, ringoffset(sc, buf, off+4, char *), head, resid);
+		if (m == NULL) goto bad;
+
+		len = off;
+		head->m_pkthdr.len -= 4; /* subtract trailer header */
+	}
+
+	/*
+	 * Pull packet off interface. Or if this was a trailer packet,
+	 * the data portion is appended.
+	 */
+	m = ze_ring_to_mbuf(sc, buf, m, len);
+	if (m == NULL) goto bad;
+
+#if NBPFILTER > 0
+	/*
+	 * Check if there's a BPF listener on this interface.
+	 * If so, hand off the raw packet to bpf. 
+	 */
+	if (sc->bpf) {
+		bpf_mtap(sc->bpf, head);
+
+		/*
+		 * Note that the interface cannot be in promiscuous mode if
+		 * there are no BPF listeners.  And if we are in promiscuous
+		 * mode, we have to check if this packet is really ours.
+		 *
+		 * XXX This test does not support multicasts.
+		 */
+		if ((sc->arpcom.ac_if.if_flags & IFF_PROMISC) &&
+			bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
+				sizeof(eh->ether_dhost)) != 0 &&
+			bcmp(eh->ether_dhost, etherbroadcastaddr,
+				sizeof(eh->ether_dhost)) != 0) {
+
+			m_freem(head);
+			return;
+		}
+	}
+#endif
+
+	/*
+	 * Fix up data start offset in mbuf to point past ether header
+	 */
+	m_adj(head, sizeof(struct ether_header));
+
+	/*
+	 * silly ether_input routine needs 'type' in host byte order
+	 */
+	eh->ether_type = ntohs(eh->ether_type);
+
+	ether_input(&sc->arpcom.ac_if, eh, head);
+	return;
+
+bad:	if (head)
+		m_freem(head);
+	return;
+}
+
+/*
+ * Supporting routines
+ */
+
+/*
+ * Given a source and destination address, copy 'amount' of a packet from
+ *	the ring buffer into a linear destination buffer. Takes into account
+ *	ring-wrap.
+ */
+static inline char *
+ze_ring_copy(sc,src,dst,amount)
+	struct ze_softc *sc;
+	char	*src;
+	char	*dst;
+	u_short	amount;
+{
+	u_short	tmp_amount;
+
+	/* does copy wrap to lower addr in ring buffer? */
+	if (src + amount > sc->smem_end) {
+		tmp_amount = sc->smem_end - src;
+		bcopy(src,dst,tmp_amount); /* copy amount up to end of smem */
+		amount -= tmp_amount;
+		src = sc->smem_ring;
+		dst += tmp_amount;
+	}
+
+	bcopy(src, dst, amount);
+
+	return(src + amount);
+}
+
+/*
+ * Copy data from receive buffer to end of mbuf chain
+ * allocate additional mbufs as needed. return pointer
+ * to last mbuf in chain.
+ * sc = ze info (softc)
+ * src = pointer in ze ring buffer
+ * dst = pointer to last mbuf in mbuf chain to copy to
+ * amount = amount of data to copy
+ */
+struct mbuf *
+ze_ring_to_mbuf(sc,src,dst,total_len)
+	struct ze_softc *sc;
+	char *src;
+	struct mbuf *dst;
+	u_short total_len;
+{
+	register struct mbuf *m = dst;
+
+	while (total_len) {
+		register u_short amount = min(total_len, M_TRAILINGSPACE(m));
+
+		if (amount == 0) { /* no more data in this mbuf, alloc another */
+			/*
+			 * If there is enough data for an mbuf cluster, attempt
+			 * 	to allocate one of those, otherwise, a regular
+			 *	mbuf will do.
+			 * Note that a regular mbuf is always required, even if
+			 *	we get a cluster - getting a cluster does not
+			 *	allocate any mbufs, and one is needed to assign
+			 *	the cluster to. The mbuf that has a cluster
+			 *	extension can not be used to contain data - only
+			 *	the cluster can contain data.
+			 */ 
+			dst = m;
+			MGET(m, M_DONTWAIT, MT_DATA);
+			if (m == NULL)
+				return (0);
+
+			if (total_len >= MINCLSIZE)
+				MCLGET(m, M_DONTWAIT);
+
+			m->m_len = 0;
+			dst->m_next = m;
+			amount = min(total_len, M_TRAILINGSPACE(m));
+		}
+
+		src = ze_ring_copy(sc, src, mtod(m, caddr_t) + m->m_len, amount);
+
+		m->m_len += amount;
+		total_len -= amount;
+
+	}
+	return (m);
+}
+#endif
+
diff --git a/sys/i386/isa/if_zereg.h b/sys/i386/isa/if_zereg.h
new file mode 100644
index 0000000..3cd501f
--- /dev/null
+++ b/sys/i386/isa/if_zereg.h
@@ -0,0 +1,859 @@
+/*
+ * National Semiconductor DS8390 NIC register definitions 
+ *
+ * if_edreg.h,v
+ * Revision 1.1.2.1  1993/07/21  13:50:04  cgd
+ * from davidg:
+ *    Added config file override for memory size and added flags to force
+ * 8bit or 16bit operation, and a flag to disable transmitter double buffering.
+ *    See the updated "ed.relnotes" file for information about how to set
+ * the flags.
+ *    This should be considered the first "production"  release. It still
+ * needs a manual page, though.
+ *
+ * Revision 1.1  1993/07/03  12:21:07  cgd
+ * add support for David Greenman "ed" driver
+ *
+ * Revision 1.2  93/06/23  03:03:05  davidg
+ * added some additional definitions for the 83C584 bus interface
+ * chip (SMC/WD boards)
+ * 
+ * Revision 1.1  93/06/23  03:01:07  davidg
+ * Initial revision
+ * 
+ */
+
+/*
+ * Page 0 register offsets
+ */
+#define ZE_P0_CR	0x00	/* Command Register */
+
+#define ZE_P0_CLDA0	0x01	/* Current Local DMA Addr low (read) */
+#define ZE_P0_PSTART	0x01	/* Page Start register (write) */
+
+#define ZE_P0_CLDA1	0x02	/* Current Local DMA Addr high (read) */
+#define ZE_P0_PSTOP	0x02	/* Page Stop register (write) */
+
+#define ZE_P0_BNRY	0x03	/* Boundary Pointer */
+
+#define ZE_P0_TSR	0x04	/* Transmit Status Register (read) */
+#define ZE_P0_TPSR	0x04	/* Transmit Page Start (write) */
+
+#define ZE_P0_NCR	0x05	/* Number of Collisions Reg (read) */
+#define ZE_P0_TBCR0	0x05	/* Transmit Byte count, low (write) */
+
+#define ZE_P0_FIFO	0x06	/* FIFO register (read) */
+#define ZE_P0_TBCR1	0x06	/* Transmit Byte count, high (write) */
+
+#define ZE_P0_ISR	0x07	/* Interrupt Status Register */
+
+#define ZE_P0_CRDA0	0x08	/* Current Remote DMA Addr low (read) */
+#define ZE_P0_RSAR0	0x08	/* Remote Start Address low (write) */
+
+#define ZE_P0_CRDA1	0x09	/* Current Remote DMA Addr high (read) */
+#define ZE_P0_RSAR1	0x09	/* Remote Start Address high (write) */
+
+#define ZE_P0_RBCR0	0x0a	/* Remote Byte Count low (write) */
+
+#define ZE_P0_RBCR1	0x0b	/* Remote Byte Count high (write) */
+
+#define ZE_P0_RSR	0x0c	/* Receive Status (read) */
+#define ZE_P0_RCR	0x0c	/* Receive Configuration Reg (write) */
+
+#define ZE_P0_CNTR0	0x0d	/* frame alignment error counter (read) */
+#define ZE_P0_TCR	0x0d	/* Transmit Configuration Reg (write) */
+
+#define ZE_P0_CNTR1	0x0e	/* CRC error counter (read) */
+#define ZE_P0_DCR	0x0e	/* Data Configuration Reg (write) */
+
+#define ZE_P0_CNTR2	0x0f	/* missed packet counter (read) */
+#define ZE_P0_IMR	0x0f	/* Interrupt Mask Register (write) */
+
+/*
+ * Page 1 register offsets
+ */
+#define ZE_P1_CR	0x00	/* Command Register */
+#define ZE_P1_PAR0	0x01	/* Physical Address Register 0 */
+#define ZE_P1_PAR1	0x02	/* Physical Address Register 1 */
+#define ZE_P1_PAR2	0x03	/* Physical Address Register 2 */
+#define ZE_P1_PAR3	0x04	/* Physical Address Register 3 */
+#define ZE_P1_PAR4	0x05	/* Physical Address Register 4 */
+#define ZE_P1_PAR5	0x06	/* Physical Address Register 5 */
+#define ZE_P1_CURR	0x07	/* Current RX ring-buffer page */
+#define ZE_P1_MAR0	0x08	/* Multicast Address Register 0 */
+#define ZE_P1_MAR1	0x09	/* Multicast Address Register 1 */
+#define ZE_P1_MAR2	0x0a	/* Multicast Address Register 2 */
+#define ZE_P1_MAR3	0x0b	/* Multicast Address Register 3 */
+#define ZE_P1_MAR4	0x0c	/* Multicast Address Register 4 */
+#define ZE_P1_MAR5	0x0d	/* Multicast Address Register 5 */
+#define ZE_P1_MAR6	0x0e	/* Multicast Address Register 6 */
+#define ZE_P1_MAR7	0x0f	/* Multicast Address Register 7 */
+
+/*
+ * Page 2 register offsets
+ */
+#define ZE_P2_CR	0x00	/* Command Register */
+#define ZE_P2_PSTART	0x01	/* Page Start (read) */
+#define ZE_P2_CLDA0	0x01	/* Current Local DMA Addr 0 (write) */
+#define ZE_P2_PSTOP	0x02	/* Page Stop (read) */
+#define ZE_P2_CLDA1	0x02	/* Current Local DMA Addr 1 (write) */
+#define ZE_P2_RNPP	0x03	/* Remote Next Packet Pointer */
+#define ZE_P2_TPSR	0x04	/* Transmit Page Start (read) */
+#define ZE_P2_LNPP	0x05	/* Local Next Packet Pointer */
+#define ZE_P2_ACU	0x06	/* Address Counter Upper */
+#define ZE_P2_ACL	0x07	/* Address Counter Lower */
+#define ZE_P2_RCR	0x0c	/* Receive Configuration Register (read) */
+#define ZE_P2_TCR	0x0d	/* Transmit Configuration Register (read) */
+#define ZE_P2_DCR	0x0e	/* Data Configuration Register (read) */
+#define ZE_P2_IMR	0x0f	/* Interrupt Mask Register (read) */
+
+/*
+ *		Command Register (CR) definitions
+ */
+
+/*
+ * STP: SToP. Software reset command. Takes the controller offline. No
+ *	packets will be received or transmitted. Any reception or
+ *	transmission in progress will continue to completion before
+ *	entering reset state. To exit this state, the STP bit must
+ *	reset and the STA bit must be set. The software reset has
+ *	executed only when indicated by the RST bit in the ISR being
+ *	set.
+ */
+#define ZE_CR_STP	0x01
+
+/*
+ * STA: STArt. This bit is used to activate the NIC after either power-up,
+ *	or when the NIC has been put in reset mode by software command
+ *	or error.
+ */
+#define ZE_CR_STA	0x02
+
+/*
+ * TXP: Transmit Packet. This bit must be set to indicate transmission of
+ *	a packet. TXP is internally reset either after the transmission is
+ *	completed or aborted. This bit should be set only after the Transmit
+ *	Byte Count and Transmit Page Start register have been programmed.
+ */
+#define ZE_CR_TXP	0x04
+
+/*
+ * RD0, RD1, RD2: Remote DMA Command. These three bits control the operation
+ *	of the remote DMA channel. RD2 can be set to abort any remote DMA
+ *	command in progress. The Remote Byte Count registers should be cleared
+ *	when a remote DMA has been aborted. The Remote Start Addresses are not
+ *	restored to the starting address if the remote DMA is aborted.
+ *
+ *	RD2 RD1 RD0	function
+ *	 0   0   0	not allowed
+ *	 0   0   1	remote read
+ *	 0   1   0	remote write
+ *	 0   1   1	send packet
+ *	 1   X   X	abort
+ */
+#define ZE_CR_RD0	0x08
+#define ZE_CR_RD1	0x10
+#define ZE_CR_RD2	0x20
+
+/*
+ * PS0, PS1: Page Select. The two bits select which register set or 'page' to
+ *	access.
+ *
+ *	PS1 PS0		page
+ *	 0   0		0
+ *	 0   1		1
+ *	 1   0		2
+ *	 1   1		reserved
+ */
+#define ZE_CR_PS0	0x40
+#define ZE_CR_PS1	0x80
+/* bit encoded aliases */
+#define ZE_CR_PAGE_0	0x00 /* (for consistency) */
+#define ZE_CR_PAGE_1	0x40
+#define ZE_CR_PAGE_2	0x80
+
+/*
+ *		Interrupt Status Register (ISR) definitions
+ */
+
+/*
+ * PRX: Packet Received. Indicates packet received with no errors.
+ */
+#define ZE_ISR_PRX	0x01
+
+/*
+ * PTX: Packet Transmitted. Indicates packet transmitted with no errors.
+ */
+#define ZE_ISR_PTX	0x02
+
+/*
+ * RXE: Receive Error. Indicates that a packet was received with one or more
+ *	the following errors: CRC error, frame alignment error, FIFO overrun,
+ *	missed packet.
+ */
+#define ZE_ISR_RXE	0x04
+
+/*
+ * TXE: Transmission Error. Indicates that an attempt to transmit a packet
+ *	resulted in one or more of the following errors: excessive
+ *	collisions, FIFO underrun.
+ */
+#define ZE_ISR_TXE	0x08
+
+/*
+ * OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network
+ *	would exceed (has exceeded?) the boundry pointer, resulting in data
+ *	that was previously received and not yet read from the buffer to be
+ *	overwritten.
+ */
+#define ZE_ISR_OVW	0x10
+
+/*
+ * CNT: Counter Overflow. Set when the MSB of one or more of the Network Talley
+ *	Counters has been set.
+ */
+#define ZE_ISR_CNT	0x20
+
+/*
+ * RDC: Remote Data Complete. Indicates that a Remote DMA operation has completed.
+ */
+#define ZE_ISR_RDC	0x40
+
+/*
+ * RST: Reset status. Set when the NIC enters the reset state and cleared when a
+ *	Start Command is issued to the CR. This bit is also set when a receive
+ *	ring-buffer overrun (OverWrite) occurs and is cleared when one or more
+ *	packets have been removed from the ring. This is a read-only bit.
+ */
+#define ZE_ISR_RST	0x80
+
+/*
+ *		Interrupt Mask Register (IMR) definitions
+ */
+
+/*
+ * PRXE: Packet Received interrupt Enable. If set, a received packet will cause
+ *	an interrupt.
+ */
+#define ZE_IMR_PRXE	0x01
+
+/*
+ * PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated when
+ *	a packet transmission completes.
+ */
+#define ZE_IMR_PTXE	0x02
+
+/*
+ * RXEE: Receive Error interrupt Enable. If set, an interrupt will occur whenever a
+ *	packet is received with an error.
+ */
+#define ZE_IMR_RXEE 	0x04
+
+/*
+ * TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur whenever
+ *	a transmission results in an error.
+ */
+#define ZE_IMR_TXEE	0x08
+
+/*
+ * OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated whenever
+ *	the receive ring-buffer is overrun. i.e. when the boundry pointer is exceeded.
+ */
+#define ZE_IMR_OVWE	0x10
+
+/*
+ * CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated whenever
+ *	the MSB of one or more of the Network Statistics counters has been set.
+ */
+#define ZE_IMR_CNTE	0x20
+
+/*
+ * RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is generated
+ *	when a remote DMA transfer has completed.
+ */
+#define ZE_IMR_RDCE	0x40
+
+/*
+ * bit 7 is unused/reserved
+ */
+
+/*
+ *		Data Configuration Register (DCR) definitions
+ */
+
+/*
+ * WTS: Word Transfer Select. WTS establishes byte or word transfers for
+ *	both remote and local DMA transfers
+ */
+#define ZE_DCR_WTS	0x01
+
+/*
+ * BOS: Byte Order Select. BOS sets the byte order for the host.
+ *	Should be 0 for 80x86, and 1 for 68000 series processors
+ */
+#define ZE_DCR_BOS	0x02
+
+/*
+ * LAS: Long Address Select. When LAS is 1, the contents of the remote
+ *	DMA registers RSAR0 and RSAR1 are used to provide A16-A31
+ */
+#define ZE_DCR_LAS	0x04
+
+/*
+ * LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2
+ *	of the TCR must also be programmed for loopback operation.
+ *	When 1, normal operation is selected.
+ */
+#define ZE_DCR_LS	0x08
+
+/*
+ * AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer
+ *	under program control. When 1, remote DMA is automatically initiated
+ *	and the boundry pointer is automatically updated
+ */
+#define ZE_DCR_AR	0x10
+
+/*
+ * FT0, FT1: Fifo Threshold select.
+ *		FT1	FT0	Word-width	Byte-width
+ *		 0	 0	1 word		2 bytes
+ *		 0	 1	2 words		4 bytes
+ *		 1	 0	4 words		8 bytes
+ *		 1	 1	8 words		12 bytes
+ *
+ *	During transmission, the FIFO threshold indicates the number of bytes
+ *	or words that the FIFO has filled from the local DMA before BREQ is
+ *	asserted. The transmission threshold is 16 bytes minus the receiver
+ *	threshold.
+ */
+#define ZE_DCR_FT0	0x20
+#define ZE_DCR_FT1	0x40
+
+/*
+ * bit 7 (0x80) is unused/reserved
+ */
+
+/*
+ *		Transmit Configuration Register (TCR) definitions
+ */
+
+/*
+ * CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC
+ *	is not appended by the transmitter.
+ */
+#define ZE_TCR_CRC	0x01
+
+/*
+ * LB0, LB1: Loopback control. These two bits set the type of loopback that is
+ *	to be performed.
+ *
+ *	LB1 LB0		mode
+ *	 0   0		0 - normal operation (DCR_LS = 0)
+ *	 0   1		1 - internal loopback (DCR_LS = 0)
+ *	 1   0		2 - external loopback (DCR_LS = 1)
+ *	 1   1		3 - external loopback (DCR_LS = 0)
+ */
+#define ZE_TCR_LB0	0x02
+#define ZE_TCR_LB1	0x04
+
+/*
+ * ATD: Auto Transmit Disable. Clear for normal operation. When set, allows
+ *	another station to disable the NIC's transmitter by transmitting to
+ *	a multicast address hashing to bit 62. Reception of a multicast address
+ *	hashing to bit 63 enables the transmitter.
+ */
+#define ZE_TCR_ATD	0x08
+
+/*
+ * OFST: Collision Offset enable. This bit when set modifies the backoff
+ *	algorithm to allow prioritization of nodes.
+ */
+#define ZE_TCR_OFST	0x10
+ 
+/*
+ * bits 5, 6, and 7 are unused/reserved
+ */
+
+/*
+ *		Transmit Status Register (TSR) definitions
+ */
+
+/*
+ * PTX: Packet Transmitted. Indicates successful transmission of packet.
+ */
+#define ZE_TSR_PTX	0x01
+
+/*
+ * bit 1 (0x02) is unused/reserved
+ */
+
+/*
+ * COL: Transmit Collided. Indicates that the transmission collided at least
+ *	once with another station on the network.
+ */
+#define ZE_TSR_COL	0x04
+
+/*
+ * ABT: Transmit aborted. Indicates that the transmission was aborted due to
+ *	excessive collisions.
+ */
+#define ZE_TSR_ABT	0x08
+
+/*
+ * CRS: Carrier Sense Lost. Indicates that carrier was lost during the
+ *	transmission of the packet. (Transmission is not aborted because
+ *	of a loss of carrier)
+ */
+#define ZE_TSR_CRS	0x10
+
+/*
+ * FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/
+ *	transmission memory before the FIFO emptied. Transmission of the
+ *	packet was aborted.
+ */
+#define ZE_TSR_FU	0x20
+
+/*
+ * CDH: CD Heartbeat. Indicates that the collision detection circuitry
+ *	isn't working correctly during a collision heartbeat test.
+ */
+#define ZE_TSR_CDH	0x40
+
+/*
+ * OWC: Out of Window Collision: Indicates that a collision occurred after
+ *	a slot time (51.2us). The transmission is rescheduled just as in
+ *	normal collisions.
+ */
+#define ZE_TSR_OWC	0x80
+
+/*
+ *		Receiver Configuration Register (RCR) definitions
+ */
+
+/*
+ * SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1,
+ *	packets with CRC and frame errors are not discarded.
+ */
+#define ZE_RCR_SEP	0x01
+
+/*
+ * AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded.
+ *	If set to 1, packets with less than 64 byte are not discarded.
+ */
+#define ZE_RCR_AR	0x02
+
+/*
+ * AB: Accept Broadcast. If set, packets sent to the broadcast address will be
+ *	accepted.
+ */
+#define ZE_RCR_AB	0x04
+
+/*
+ * AM: Accept Multicast. If set, packets sent to a multicast address are checked
+ *	for a match in the hashing array. If clear, multicast packets are ignored.
+ */
+#define ZE_RCR_AM	0x08
+
+/*
+ * PRO: Promiscuous Physical. If set, all packets with a physical addresses are
+ *	accepted. If clear, a physical destination address must match this
+ *	station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM
+ *	must also be set. In addition, the multicast hashing array must be set
+ *	to all 1's so that all multicast addresses are accepted.
+ */
+#define ZE_RCR_PRO	0x10
+
+/*
+ * MON: Monitor Mode. If set, packets will be checked for good CRC and framing,
+ *	but are not stored in the ring-buffer. If clear, packets are stored (normal
+ *	operation).
+ */
+#define ZE_RCR_MON	0x20
+
+/*
+ * bits 6 and 7 are unused/reserved.
+ */
+
+/*
+ *		Receiver Status Register (RSR) definitions
+ */
+
+/*
+ * PRX: Packet Received without error.
+ */
+#define ZE_RSR_PRX	0x01
+
+/*
+ * CRC: CRC error. Indicates that a packet has a CRC error. Also set for frame
+ *	alignment errors.
+ */
+#define ZE_RSR_CRC	0x02
+
+/*
+ * FAE: Frame Alignment Error. Indicates that the incoming packet did not end on
+ *	a byte boundry and the CRC did not match at the last byte boundry.
+ */
+#define ZE_RSR_FAE	0x04
+
+/*
+ * FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local DMA)
+ *	causing it to overrun. Reception of the packet is aborted.
+ */
+#define ZE_RSR_FO	0x08
+
+/*
+ * MPA: Missed Packet. Indicates that the received packet couldn't be stored in
+ *	the ring-buffer because of insufficient buffer space (exceeding the
+ *	boundry pointer), or because the transfer to the ring-buffer was inhibited
+ *	by RCR_MON - monitor mode.
+ */
+#define ZE_RSR_MPA	0x10
+
+/*
+ * PHY: Physical address. If 0, the packet received was sent to a physical address.
+ *	If 1, the packet was accepted because of a multicast/broadcast address
+ *	match.
+ */
+#define ZE_RSR_PHY	0x20
+
+/*
+ * DIS: Receiver Disabled. Set to indicate that the receiver has enetered monitor
+ *	mode. Cleared when the receiver exits monitor mode.
+ */
+#define ZE_RSR_DIS	0x40
+
+/*
+ * DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL inputs
+ *	are active, and the transceiver has set the CD line as a result of the
+ *	jabber.
+ */
+#define ZE_RSR_DFR	0x80
+
+/*
+ * receive ring discriptor
+ *
+ * The National Semiconductor DS8390 Network interface controller uses
+ * the following receive ring headers.  The way this works is that the
+ * memory on the interface card is chopped up into 256 bytes blocks.
+ * A contiguous portion of those blocks are marked for receive packets
+ * by setting start and end block #'s in the NIC.  For each packet that
+ * is put into the receive ring, one of these headers (4 bytes each) is
+ * tacked onto the front.
+ */
+struct ze_ring	{
+	struct edr_status {		/* received packet status	*/
+	    u_char rs_prx:1,		/* packet received intack	*/
+		   rs_crc:1,		/* crc error		*/
+	           rs_fae:1,		/* frame alignment error	*/
+	           rs_fo:1,		/* fifo overrun		*/
+	           rs_mpa:1,		/* packet received intack	*/
+	           rs_phy:1,		/* packet received intack	*/
+	           rs_dis:1,		/* packet received intack	*/
+	           rs_dfr:1;		/* packet received intack	*/
+	} ze_rcv_status;		/* received packet status	*/
+	u_char	next_packet;		/* pointer to next packet	*/
+	u_short	count;			/* bytes in packet (length + 4)	*/
+};
+
+/*
+ * 				Common constants
+ */
+#define ZE_PAGE_SIZE		256		/* Size of RAM pages in bytes */
+#define ZE_TXBUF_SIZE		6		/* Size of TX buffer in pages */
+#define ZE_PAGE_OFFSET		0x40		/* mem buffer starts at 0x4000 */
+
+/*
+ * Vendor types
+ */
+#define ZE_VENDOR_WD_SMC	0x00		/* Western Digital/SMC */
+#define ZE_VENDOR_3COM		0x01		/* 3Com */
+
+/*
+ * Compile-time config flags
+ */
+/*
+ * this sets the default for enabling/disablng the tranceiver
+ */
+#define ZE_FLAGS_DISABLE_TRANCEIVER	0x01
+
+/*
+ * This forces the board to be used in 8/16bit mode even if it
+ *	autoconfigs differently
+ */
+#define ZE_FLAGS_FORCE_8BIT_MODE	0x02
+#define ZE_FLAGS_FORCE_16BIT_MODE	0x04
+
+/*
+ * This disables the use of double transmit buffers.
+ */
+#define ZE_FLAGS_NO_DOUBLE_BUFFERING	0x08
+
+/*
+ * definitions for IBM credit card adapter for ethernet
+ */
+
+#define ZE_DATA_IO	0x10
+#define ZE_MISC		0x18
+#define ZE_RESET	0x1F
+
+#if 0
+/*
+ *		Definitions for Western digital/SMC WD80x3 series ASIC
+ */
+/*
+ * Memory Select Register (MSR)
+ */
+#define ZE_WD_MSR	0
+
+#define ZE_WD_MSR_ADDR	0x3f	/* Memory decode bits 18-13 */
+#define ZE_WD_MSR_MENB	0x40	/* Memory enable */
+#define ZE_WD_MSR_RST	0x80	/* Reset board */
+
+/*
+ * Interface Configuration Register (ICR)
+ */
+#define ZE_WD_ICR	1
+
+#define ZE_WD_ICR_16BIT	0x01	/* 16-bit interface */
+#define ZE_WD_ICR_OAR	0x02	/* select register. 0=BIO 1=EAR */
+#define ZE_WD_ICR_IR2	0x04	/* high order bit of encoded IRQ */
+#define ZE_WD_ICR_MSZ	0x08	/* memory size (0=8k 1=32k) */
+#define ZE_WD_ICR_RLA	0x10	/* recall LAN address */
+#define ZE_WD_ICR_RX7	0x20	/* recall all but i/o and LAN address */
+#define	ZE_WD_ICR_RIO	0x40	/* recall i/o address */
+#define ZE_WD_ICR_STO	0x80	/* store to non-volatile memory */
+
+/*
+ * IO Address Register (IAR)
+ */
+#define ZE_WD_IAR	2
+
+/*
+ * EEROM Address Register
+ */
+#define ZE_WD_EAR	3
+
+/*
+ * Interrupt Request Register (IRR)
+ */
+#define ZE_WD_IRR	4
+
+#define	ZE_WD_IRR_0WS	0x01	/* use 0 wait-states on 8 bit bus */
+#define ZE_WD_IRR_OUT1	0x02	/* WD83C584 pin 1 output */
+#define ZE_WD_IRR_OUT2	0x04	/* WD83C584 pin 2 output */
+#define ZE_WD_IRR_OUT3	0x08	/* WD83C584 pin 3 output */
+#define ZE_WD_IRR_FLASH	0x10	/* Flash RAM is in the ROM socket */
+
+/*
+ * The three bit of the encoded IRQ are decoded as follows:
+ *
+ *	IR2 IR1 IR0	IRQ
+ *	 0   0   0	 2/9
+ *	 0   0   1	 3
+ *	 0   1   0	 5
+ *	 0   1   1	 7
+ *	 1   0   0	 10
+ *	 1   0   1	 11
+ *	 1   1   0	 15
+ *	 1   1   1	 4
+ */
+#define ZE_WD_IRR_IR0	0x20	/* bit 0 of encoded IRQ */
+#define ZE_WD_IRR_IR1	0x40	/* bit 1 of encoded IRQ */
+#define ZE_WD_IRR_IEN	0x80	/* Interrupt enable */
+
+/*
+ * LA Address Register (LAAR)
+ */
+#define ZE_WD_LAAR	5
+
+#define ZE_WD_LAAR_ADDRHI	0x1f	/* bits 23-19 of RAM address */
+#define ZE_WD_LAAR_0WS16	0x20	/* enable 0 wait-states on 16 bit bus */
+#define ZE_WD_LAAR_L16EN	0x40	/* enable 16-bit operation */
+#define ZE_WD_LAAR_M16EN	0x80	/* enable 16-bit memory access */
+
+/* i/o base offset to station address/card-ID PROM */
+#define ZE_WD_PROM	8
+
+/* i/o base offset to CARD ID */
+#define ZE_WD_CARD_ID	ZE_WD_PROM+6
+
+#define ZE_TYPE_WD8003S		0x02
+#define ZE_TYPE_WD8003E		0x03
+#define ZE_TYPE_WD8013EBT	0x05
+#define ZE_TYPE_WD8013EB	0x27
+#define ZE_TYPE_WD8013EBP	0x2c
+#define ZE_TYPE_WD8013EPC	0x29
+
+/* Bit definitions in card ID */
+#define	ZE_WD_REV_MASK		0x1f		/* Revision mask */
+#define	ZE_WD_SOFTCONFIG	0x20		/* Soft config */
+#define	ZE_WD_LARGERAM		0x40		/* Large RAM */
+#define	ZE_MICROCHANEL		0x80		/* Microchannel bus (vs. isa) */
+
+/*
+ * Checksum total. All 8 bytes in station address PROM will add up to this
+ */
+#define ZE_WD_ROM_CHECKSUM_TOTAL	0xFF
+
+#define ZE_WD_NIC_OFFSET	0x10		/* I/O base offset to NIC */
+#define ZE_WD_ASIC_OFFSET	0		/* I/O base offset to ASIC */
+#define ZE_WD_IO_PORTS		32		/* # of i/o addresses used */
+
+#define ZE_WD_PAGE_OFFSET	0	/* page offset for NIC access to mem */
+
+/*
+ *			Definitions for 3Com 3c503
+ */
+#define ZE_3COM_NIC_OFFSET	0
+#define ZE_3COM_ASIC_OFFSET	0x400		/* offset to nic i/o regs */
+
+/*
+ * XXX - The I/O address range is fragmented in the 3c503; this is the
+ *	number of regs at iobase.
+ */
+#define ZE_3COM_IO_PORTS	16		/* # of i/o addresses used */
+
+#define ZE_3COM_PAGE_OFFSET	0x20		/* memory starts in second bank */
+
+/*
+ *	Page Start Register. Must match PSTART in NIC
+ */
+#define ZE_3COM_PSTR		0
+
+/*
+ *	Page Stop Register. Must match PSTOP in NIC
+ */
+#define ZE_3COM_PSPR		1
+
+/*
+ *	Drq Timer Register. Determines number of bytes to be transfered during
+ *		a DMA burst.
+ */
+#define ZE_3COM_DQTR		2
+
+/*
+ *	Base Configuration Register. Read-only register which contains the
+ *		board-configured I/O base address of the adapter. Bit encoded.
+ */
+#define ZE_3COM_BCFR		3
+
+#define ZE_3COM_BCFR_2E0	0x01
+#define ZE_3COM_BCFR_2A0	0x02
+#define ZE_3COM_BCFR_280	0x04
+#define ZE_3COM_BCFR_250	0x08
+#define ZE_3COM_BCFR_350	0x10
+#define ZE_3COM_BCFR_330	0x20
+#define ZE_3COM_BCFR_310	0x40
+#define ZE_3COM_BCFR_300	0x80
+
+/*
+ *	EPROM Configuration Register. Read-only register which contains the
+ *		board-configured memory base address. Bit encoded.
+ */
+#define ZE_3COM_PCFR		4
+
+#define ZE_3COM_PCFR_C8000	0x10
+#define ZE_3COM_PCFR_CC000	0x20
+#define ZE_3COM_PCFR_D8000	0x40
+#define ZE_3COM_PCFR_DC000	0x80
+
+/*
+ *	GA Configuration Register. Gate-Array Configuration Register.
+ */
+#define ZE_3COM_GACFR		5
+
+/*
+ * mbs2  mbs1  mbs0		start address
+ *  0     0     0		0x0000
+ *  0     0     1		0x2000
+ *  0     1     0		0x4000
+ *  0     1     1		0x6000
+ *
+ *	Note that with adapters with only 8K, the setting for 0x2000 must
+ *		always be used.
+ */
+#define ZE_3COM_GACFR_MBS0	0x01
+#define ZE_3COM_GACFR_MBS1	0x02
+#define ZE_3COM_GACFR_MBS2	0x04
+
+#define ZE_3COM_GACFR_RSEL	0x08	/* enable shared memory */
+#define ZE_3COM_GACFR_TEST	0x10	/* for GA testing */
+#define ZE_3COM_GACFR_OWS	0x20	/* select 0WS access to GA */
+#define ZE_3COM_GACFR_TCM	0x40	/* Mask DMA interrupts */
+#define ZE_3COM_GACFR_NIM	0x80	/* Mask NIC interrupts */
+
+/*
+ *	Control Register. Miscellaneous control functions.
+ */
+#define ZE_3COM_CR		6
+
+#define ZE_3COM_CR_RST		0x01	/* Reset GA and NIC */
+#define ZE_3COM_CR_XSEL		0x02	/* Transceiver select. BNC=1(def) AUI=0 */
+#define ZE_3COM_CR_EALO		0x04	/* window EA PROM 0-15 to I/O base */
+#define ZE_3COM_CR_EAHI		0x08	/* window EA PROM 16-31 to I/O base */
+#define ZE_3COM_CR_SHARE	0x10	/* select interrupt sharing option */
+#define ZE_3COM_CR_DBSEL	0x20	/* Double buffer select */
+#define ZE_3COM_CR_DDIR		0x40	/* DMA direction select */
+#define ZE_3COM_CR_START	0x80	/* Start DMA controller */
+
+/*
+ *	Status Register. Miscellaneous status information.
+ */
+#define ZE_3COM_STREG		7
+
+#define ZE_3COM_STREG_REV	0x07	/* GA revision */
+#define ZE_3COM_STREG_DIP	0x08	/* DMA in progress */
+#define ZE_3COM_STREG_DTC	0x10	/* DMA terminal count */
+#define ZE_3COM_STREG_OFLW	0x20	/* Overflow */
+#define ZE_3COM_STREG_UFLW	0x40	/* Underflow */
+#define ZE_3COM_STREG_DPRDY	0x80	/* Data port ready */
+
+/*
+ *	Interrupt/DMA Configuration Register
+ */
+#define ZE_3COM_IDCFR		8
+
+#define ZE_3COM_IDCFR_DRQ0	0x01	/* DMA request 1 select */
+#define ZE_3COM_IDCFR_DRQ1	0x02	/* DMA request 2 select */
+#define ZE_3COM_IDCFR_DRQ2	0x04	/* DMA request 3 select */
+#define ZE_3COM_IDCFR_UNUSED	0x08	/* not used */
+#define ZE_3COM_IDCFR_IRQ2	0x10	/* Interrupt request 2 select */
+#define ZE_3COM_IDCFR_IRQ3	0x20	/* Interrupt request 3 select */
+#define ZE_3COM_IDCFR_IRQ4	0x40	/* Interrupt request 4 select */
+#define ZE_3COM_IDCFR_IRQ5	0x80	/* Interrupt request 5 select */
+
+/*
+ *	DMA Address Register MSB
+ */
+#define ZE_3COM_DAMSB		9
+
+/*
+ *	DMA Address Register LSB
+ */
+#define ZE_3COM_DALSB		0x0a
+
+/*
+ *	Vector Pointer Register 2
+ */
+#define ZE_3COM_VPTR2		0x0b
+
+/*
+ *	Vector Pointer Register 1
+ */
+#define ZE_3COM_VPTR1		0x0c
+
+/*
+ *	Vector Pointer Register 0
+ */
+#define ZE_3COM_VPTR0		0x0d
+
+/*
+ *	Register File Access MSB
+ */
+#define ZE_3COM_RFMSB		0x0e
+
+/*
+ *	Register File Access LSB
+ */
+#define ZE_3COM_RFLSB		0x0f
+#endif