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authorneel <neel@FreeBSD.org>2010-09-15 05:10:50 +0000
committerneel <neel@FreeBSD.org>2010-09-15 05:10:50 +0000
commit310427c33e7d4bd3df3c7c5a08499afbac0736df (patch)
tree1961e26f310e8cc87db629c9886a6e7024d7b00b /sys
parent2773ca57a0a72cdd7d5dcb692cb53f725d7415d5 (diff)
downloadFreeBSD-src-310427c33e7d4bd3df3c7c5a08499afbac0736df.zip
FreeBSD-src-310427c33e7d4bd3df3c7c5a08499afbac0736df.tar.gz
Make the meaning of the 'mask' argument to 'set_intr_mask(mask)' consistent
with the meaning of IM bits in the status register. Reviewed by: jmallett, jchandra
Diffstat (limited to 'sys')
-rw-r--r--sys/mips/cavium/octeon_mp.c2
-rw-r--r--sys/mips/include/cpufunc.h2
-rw-r--r--sys/mips/mips/machdep.c2
-rw-r--r--sys/mips/mips/trap.c2
-rw-r--r--sys/mips/sibyte/sb_machdep.c2
5 files changed, 5 insertions, 5 deletions
diff --git a/sys/mips/cavium/octeon_mp.c b/sys/mips/cavium/octeon_mp.c
index a0eae2c..34de442 100644
--- a/sys/mips/cavium/octeon_mp.c
+++ b/sys/mips/cavium/octeon_mp.c
@@ -96,7 +96,7 @@ platform_init_ap(int cpuid)
*/
clock_int_mask = hard_int_mask(5);
ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
- set_intr_mask(MIPS_SR_INT_MASK & ~(ipi_int_mask | clock_int_mask));
+ set_intr_mask(ipi_int_mask | clock_int_mask);
mips_wbflush();
}
diff --git a/sys/mips/include/cpufunc.h b/sys/mips/include/cpufunc.h
index efaa3f4..a1715c9 100644
--- a/sys/mips/include/cpufunc.h
+++ b/sys/mips/include/cpufunc.h
@@ -272,7 +272,7 @@ set_intr_mask(uint32_t mask)
uint32_t ostatus;
ostatus = mips_rd_status();
- mask = (ostatus & ~MIPS_SR_INT_MASK) | (~mask & MIPS_SR_INT_MASK);
+ mask = (ostatus & ~MIPS_SR_INT_MASK) | (mask & MIPS_SR_INT_MASK);
mips_wr_status(mask);
return (ostatus);
}
diff --git a/sys/mips/mips/machdep.c b/sys/mips/mips/machdep.c
index 8c16051..120fde7 100644
--- a/sys/mips/mips/machdep.c
+++ b/sys/mips/mips/machdep.c
@@ -356,7 +356,7 @@ mips_vector_init(void)
* Mask all interrupts. Each interrupt will be enabled
* when handler is installed for it
*/
- set_intr_mask(MIPS_SR_INT_MASK);
+ set_intr_mask(0);
/* Clear BEV in SR so we start handling our own exceptions */
mips_wr_status(mips_rd_status() & ~MIPS_SR_BEV);
diff --git a/sys/mips/mips/trap.c b/sys/mips/mips/trap.c
index 2323c66..009db7c 100644
--- a/sys/mips/mips/trap.c
+++ b/sys/mips/mips/trap.c
@@ -304,7 +304,7 @@ trap(struct trapframe *trapframe)
* return to userland.
*/
if (trapframe->sr & MIPS_SR_INT_IE) {
- set_intr_mask(~(trapframe->sr & MIPS_SR_INT_MASK));
+ set_intr_mask(trapframe->sr & MIPS_SR_INT_MASK);
intr_enable();
} else {
intr_disable();
diff --git a/sys/mips/sibyte/sb_machdep.c b/sys/mips/sibyte/sb_machdep.c
index 45f39e8..ba4b62e9 100644
--- a/sys/mips/sibyte/sb_machdep.c
+++ b/sys/mips/sibyte/sb_machdep.c
@@ -370,7 +370,7 @@ platform_init_ap(int cpuid)
*/
clock_int_mask = hard_int_mask(5);
ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
- set_intr_mask(MIPS_SR_INT_MASK & ~(ipi_int_mask | clock_int_mask));
+ set_intr_mask(ipi_int_mask | clock_int_mask);
}
int
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