Rework and extend PowerPC headers definitons towards Book-E/e500 CPUs support.

Approved by:	cognet (mentor)
Obtained from:	Juniper, Semihalf
MFp4:		e500

10 files changed, 730 insertions, 139 deletions

diff --git a/sys/powerpc/include/pmap.h b/sys/powerpc/include/pmap.h
index d02f8d6..50f9761 100644
--- a/sys/powerpc/include/pmap.h
+++ b/sys/powerpc/include/pmap.h
@@ -1,4 +1,34 @@
 /*-
+ * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
+ * All rights reserved.
+ *
+ * Adapted for Freescale's e500 core CPUs.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+/*-
  * Copyright (C) 1995, 1996 Wolfgang Solfrank.
  * Copyright (C) 1995, 1996 TooLs GmbH.
  * All rights reserved.
@@ -28,8 +58,7 @@
  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- *	$NetBSD: pmap.h,v 1.17 2000/03/30 16:18:24 jdolecek Exp $
- * $FreeBSD$
+ *	from: $NetBSD: pmap.h,v 1.17 2000/03/30 16:18:24 jdolecek Exp $
  */
 
 #ifndef	_MACHINE_PMAP_H_
@@ -40,6 +69,9 @@
 #include <sys/_mutex.h>
 #include <machine/sr.h>
 #include <machine/pte.h>
+#include <machine/tlb.h>
+
+#if defined(AIM)
 
 #if !defined(NPMAPS)
 #define	NPMAPS		32768
@@ -69,11 +101,44 @@ struct	md_page {
 	struct	pvo_head mdpg_pvoh;
 };
 
+#define	pmap_page_is_mapped(m)	(!LIST_EMPTY(&(m)->md.mdpg_pvoh))
+
+#else
+
+struct pmap {
+	struct mtx pm_mtx;		/* pmap mutex */
+	tlbtid_t pm_tid;		/* TID to identify this pmap entries in TLB */
+	u_int pm_active;		/* active on cpus */
+	int pm_refs;			/* ref count */
+	struct pmap_statistics pm_stats;/* pmap statistics */
+
+	/* Page table directory, array of pointers to page tables. */
+	pte_t *pm_pdir[PDIR_NENTRIES];
+
+	/* List of allocated ptbl bufs (ptbl kva regions). */
+	TAILQ_HEAD(, ptbl_buf) ptbl_list;
+};
+typedef	struct pmap *pmap_t;
+
+struct pv_entry {
+	pmap_t pv_pmap;
+	vm_offset_t pv_va;
+	TAILQ_ENTRY(pv_entry) pv_link;
+};
+typedef struct pv_entry *pv_entry_t;
+
+struct md_page {
+	TAILQ_HEAD(, pv_entry) pv_list;
+};
+
+#define MEM_REGIONS	8
+#define	pmap_page_is_mapped(m)	(!TAILQ_EMPTY(&(m)->md.pv_list))
+
+#endif /* AIM */
+
 extern	struct pmap kernel_pmap_store;
 #define	kernel_pmap	(&kernel_pmap_store)
 
-#define	pmap_page_is_mapped(m)	(!LIST_EMPTY(&(m)->md.mdpg_pvoh))
-
 #ifdef _KERNEL
 
 #define	PMAP_LOCK(pmap)		mtx_lock(&(pmap)->pm_mtx)
@@ -91,11 +156,11 @@ void		pmap_bootstrap(vm_offset_t, vm_offset_t);
 void		pmap_kenter(vm_offset_t va, vm_offset_t pa);
 void		pmap_kremove(vm_offset_t);
 void		*pmap_mapdev(vm_offset_t, vm_size_t);
+boolean_t	pmap_page_executable(vm_page_t);
 void		pmap_unmapdev(vm_offset_t, vm_size_t);
 void		pmap_deactivate(struct thread *);
 vm_offset_t	pmap_kextract(vm_offset_t);
 int		pmap_dev_direct_mapped(vm_offset_t, vm_size_t);
-boolean_t	pmap_page_executable(vm_page_t);
 boolean_t	pmap_mmu_install(char *name, int prio);
 
 #define	vtophys(va)	pmap_kextract((vm_offset_t)(va))
diff --git a/sys/powerpc/include/psl.h b/sys/powerpc/include/psl.h
index a7ab6f1..6de0334 100644
--- a/sys/powerpc/include/psl.h
+++ b/sys/powerpc/include/psl.h
@@ -35,6 +35,37 @@
 #ifndef	_MACHINE_PSL_H_
 #define	_MACHINE_PSL_H_
 
+#if defined(E500)
+/*
+ * Machine State Register (MSR) - e500 core
+ *
+ * The PowerPC e500 does not implement the following bits:
+ *
+ * FP, FE0, FE1 - reserved, always cleared, setting has no effect.
+ *
+ */
+#define PSL_UCLE	0x04000000	/* User mode cache lock enable */
+#define PSL_SPE		0x02000000	/* SPE enable */
+#define PSL_WE		0x00040000	/* Wait state enable */
+#define PSL_CE		0x00020000	/* Critical interrupt enable */
+#define PSL_EE		0x00008000	/* External interrupt enable */
+#define PSL_PR		0x00004000	/* User mode */
+#define PSL_FP		0x00002000	/* Floating point available */
+#define PSL_ME		0x00001000	/* Machine check interrupt enable */
+#define PSL_FE0		0x00000800	/* Floating point exception mode 0 */
+#define PSL_UBLE	0x00000400	/* BTB lock enable */
+#define PSL_DE		0x00000200	/* Debug interrupt enable */
+#define PSL_FE1		0x00000100	/* Floating point exception mode 1 */
+#define PSL_IS		0x00000020	/* Instruction address space */
+#define PSL_DS		0x00000010	/* Data address space */
+#define PSL_PMM		0x00000004	/* Performance monitor mark */
+
+/* Initial kernel MSR, use IS=1 ad DS=1. */
+#define PSL_KERNSET_INIT	(PSL_IS | PSL_DS)
+#define PSL_KERNSET		(PSL_CE | PSL_ME | PSL_EE)
+#define PSL_USERSET		(PSL_KERNSET | PSL_PR)
+
+#else	/* if defined(E500) */
 /*
  * Machine State Register (MSR)
  *
@@ -83,4 +114,5 @@
 
 #define	PSL_USERSTATIC	(PSL_USERSET | PSL_IP | 0x87c0008c)
 
+#endif	/* if defined(E500) */
 #endif	/* _MACHINE_PSL_H_ */
diff --git a/sys/powerpc/include/pte.h b/sys/powerpc/include/pte.h
index 391c82e..1658ff4 100644
--- a/sys/powerpc/include/pte.h
+++ b/sys/powerpc/include/pte.h
@@ -35,6 +35,8 @@
 #ifndef	_MACHINE_PTE_H_
 #define	_MACHINE_PTE_H_
 
+#if defined(AIM)
+
 /*
  * Page Table Entries
  */
@@ -156,4 +158,102 @@ typedef	struct lpte lpte_t;
 extern u_int dsisr(void);
 #endif	/* _KERNEL */
 #endif	/* LOCORE */
-#endif	/* _MACHINE_PTE_H_ */
+
+#else
+
+#include <machine/tlb.h>
+
+/*
+ * 1st level - page table directory (pdir)
+ *
+ * pdir consists of 1024 entries, each being a pointer to
+ * second level entity, i.e. the actual page table (ptbl).
+ */
+#define PDIR_SHIFT	22
+#define PDIR_SIZE	(1 << PDIR_SHIFT)	/* va range mapped by pdir */
+#define PDIR_MASK	(~(PDIR_SIZE - 1))
+#define PDIR_NENTRIES	1024			/* number of page tables in pdir */
+
+/* Returns pdir entry number for given va */
+#define PDIR_IDX(va)	((va) >> PDIR_SHIFT)
+
+#define PDIR_ENTRY_SHIFT 2	/* entry size is 2^2 = 4 bytes */
+
+/*
+ * 2nd level - page table (ptbl)
+ *
+ * Page table covers 1024 page table entries. Page
+ * table entry (pte) is 32 bit wide and defines mapping
+ * for a single page.
+ */
+#define PTBL_SHIFT	PAGE_SHIFT
+#define PTBL_SIZE	PAGE_SIZE		/* va range mapped by ptbl entry */
+#define PTBL_MASK	((PDIR_SIZE - 1) & ~PAGE_MASK)
+#define PTBL_NENTRIES	1024			/* number of pages mapped by ptbl */
+
+/* Returns ptbl entry number for given va */
+#define PTBL_IDX(va)	(((va) & PTBL_MASK) >> PTBL_SHIFT)
+
+/* Size of ptbl in pages, 1024 entries, each sizeof(struct pte_entry). */
+#define PTBL_PAGES	2
+#define PTBL_ENTRY_SHIFT 3	/* entry size is 2^3 = 8 bytes */
+
+/*
+ * Flags for pte_remove() routine.
+ */
+#define PTBL_HOLD	0x00000001	/* do not unhold ptbl pages */
+#define PTBL_UNHOLD	0x00000002	/* unhold and attempt to free ptbl pages */
+
+#define PTBL_HOLD_FLAG(pmap)	(((pmap) == kernel_pmap) ? PTBL_HOLD : PTBL_UNHOLD)
+
+/*
+ * Page Table Entry definitions and macros.
+ */
+#ifndef	LOCORE
+struct pte_entry {
+	vm_offset_t rpn;
+	u_int32_t flags;
+};
+typedef struct pte_entry pte_t;
+#endif
+
+/* RPN mask, TLB0 4K pages */
+#define PTE_PA_MASK	PAGE_MASK
+
+/* PTE bits assigned to MAS2, MAS3 flags */
+#define PTE_W		MAS2_W
+#define PTE_I		MAS2_I
+#define PTE_M		MAS2_M
+#define PTE_G		MAS2_G
+#define PTE_MAS2_MASK	(MAS2_G | MAS2_M | MAS2_I | MAS2_W)
+
+#define PTE_MAS3_SHIFT	8
+#define PTE_UX		(MAS3_UX << PTE_MAS3_SHIFT)
+#define PTE_SX		(MAS3_SX << PTE_MAS3_SHIFT)
+#define PTE_UW		(MAS3_UW << PTE_MAS3_SHIFT)
+#define PTE_SW		(MAS3_SW << PTE_MAS3_SHIFT)
+#define PTE_UR		(MAS3_UR << PTE_MAS3_SHIFT)
+#define PTE_SR		(MAS3_SR << PTE_MAS3_SHIFT)
+#define PTE_MAS3_MASK	((MAS3_UX | MAS3_SX | MAS3_UW	\
+			| MAS3_SW | MAS3_UR | MAS3_SR) << PTE_MAS3_SHIFT)
+
+/* Other PTE flags */
+#define PTE_VALID	0x80000000	/* Valid */
+#define PTE_MODIFIED	0x40000000	/* Modified */
+#define PTE_WIRED	0x20000000	/* Wired */
+#define PTE_MANAGED	0x10000000	/* Managed */
+#define PTE_FAKE	0x08000000	/* Ficticious */
+#define PTE_REFERENCED	0x04000000	/* Referenced */
+
+/* Macro argument must of pte_t type. */
+#define PTE_PA(pte)		((pte)->rpn & ~PTE_PA_MASK)
+#define PTE_ISVALID(pte)	((pte)->flags & PTE_VALID)
+#define PTE_ISWIRED(pte)	((pte)->flags & PTE_WIRED)
+#define PTE_ISMANAGED(pte)	((pte)->flags & PTE_MANAGED)
+#define PTE_ISFAKE(pte)		((pte)->flags & PTE_FAKE)
+#define PTE_ISMODIFIED(pte)	((pte)->flags & PTE_MODIFIED)
+#define PTE_ISREFERENCED(pte)	((pte)->flags & PTE_REFERENCED)
+
+#endif /* #elif defined(E500) */
+
+#endif /* _MACHINE_PTE_H_ */
diff --git a/sys/powerpc/include/sf_buf.h b/sys/powerpc/include/sf_buf.h
index 6997419..162f5a6 100644
--- a/sys/powerpc/include/sf_buf.h
+++ b/sys/powerpc/include/sf_buf.h
@@ -32,7 +32,9 @@
 #include <vm/vm.h>
 #include <vm/vm_param.h>
 #include <vm/vm_page.h>
+#include <sys/queue.h>
 
+#if defined(AIM)
 /*
  * On this machine, the only purpose for which sf_buf is used is to implement
  * an opaque pointer required by the machine-independent parts of the kernel.
@@ -55,4 +57,32 @@ sf_buf_page(struct sf_buf *sf)
 	return ((vm_page_t)sf);
 }
 
+#elif defined(E500)
+
+struct vm_page;
+
+struct sf_buf {
+	LIST_ENTRY(sf_buf) list_entry;	/* list of buffers */
+	TAILQ_ENTRY(sf_buf) free_entry;	/* list of buffers */
+	struct		vm_page *m;	/* currently mapped page */
+	vm_offset_t	kva;		/* va of mapping */
+	int		ref_count;	/* usage of this mapping */
+};
+
+static __inline vm_offset_t
+sf_buf_kva(struct sf_buf *sf)
+{
+
+	return (sf->kva);
+}
+
+static __inline struct vm_page *
+sf_buf_page(struct sf_buf *sf)
+{
+
+	return (sf->m);
+}
+
+#endif
+
 #endif /* !_MACHINE_SF_BUF_H_ */
diff --git a/sys/powerpc/include/spr.h b/sys/powerpc/include/spr.h
index 12c6f7d..9bede7a 100644
--- a/sys/powerpc/include/spr.h
+++ b/sys/powerpc/include/spr.h
@@ -75,6 +75,7 @@
 #define	SPR_SDR1		0x019	/* .68 Page table base address register */
 #define	SPR_SRR0		0x01a	/* 468 Save/Restore Register 0 */
 #define	SPR_SRR1		0x01b	/* 468 Save/Restore Register 1 */
+#define	SPR_DECAR		0x036	/* ..8 Decrementer auto reload */
 #define SPR_EIE			0x050	/* ..8 Exception Interrupt ??? */
 #define SPR_EID			0x051	/* ..8 Exception Interrupt ??? */
 #define SPR_NRI			0x052	/* ..8 Exception Interrupt ??? */
@@ -292,7 +293,6 @@
 #define	  SPR_MMCR1_PMC6SEL(x)	  ((x) << 11) /* PMC 6 selector */
 
 #define	SPR_SU0R		0x3bc	/* 4.. Storage User-defined 0 Register */
-#define	SPR_DBCR1		0x3bd	/* 4.. Debug Control Register 1 */
 #define	SPR_PMC3		0x3bd	/* .6. Performance Counter Register 3 */
 #define	SPR_PMC4		0x3be	/* .6. Performance Counter Register 4 */
 #define	SPR_DMISS		0x3d0	/* .68 Data TLB Miss Address Register */
@@ -300,14 +300,6 @@
 #define	SPR_HASH1		0x3d2	/* .68 Primary Hash Address Register */
 #define	SPR_ICDBDR		0x3d3	/* 4.. Instruction Cache Debug Data Register */
 #define	SPR_HASH2		0x3d3	/* .68 Secondary Hash Address Register */
-#define	SPR_ESR			0x3d4	/* 4.. Exception Syndrome Register */
-#define	  ESR_MCI		  0x80000000 /* Machine check - instruction */
-#define	  ESR_PIL		  0x08000000 /* Program interrupt - illegal */
-#define	  ESR_PPR		  0x04000000 /* Program interrupt - privileged */
-#define	  ESR_PTR		  0x02000000 /* Program interrupt - trap */
-#define	  ESR_DST		  0x00800000 /* Data storage interrupt - store fault */
-#define	  ESR_DIZ		  0x00800000 /* Data/instruction storage interrupt - zone fault */
-#define	  ESR_U0F		  0x00008000 /* Data storage interrupt - U0 fault */
 #define	SPR_IMISS		0x3d4	/* .68 Instruction TLB Miss Address Register */
 #define	SPR_TLBMISS		0x3d4	/* .6. TLB Miss Address Register */
 #define	SPR_DEAR		0x3d5	/* 4.. Data Error Address Register */
@@ -316,7 +308,15 @@
 #define	SPR_EVPR		0x3d6	/* 4.. Exception Vector Prefix Register */
 #define	SPR_RPA			0x3d6	/* .68 Required Physical Address Register */
 #define	SPR_PTELO		0x3d6	/* .6. Required Physical Address Register */
+
+#if defined(AIM)
 #define	SPR_TSR			0x3d8	/* 4.. Timer Status Register */
+#define	SPR_TCR			0x3da	/* 4.. Timer Control Register */
+#elif defined(E500)
+#define	SPR_TSR			0x150	/* ..8 Timer Status Register */
+#define	SPR_TCR			0x154	/* ..8 Timer Control Register */
+#endif
+
 #define	  TSR_ENW		  0x80000000 /* Enable Next Watchdog */
 #define	  TSR_WIS		  0x40000000 /* Watchdog Interrupt Status */
 #define	  TSR_WRS_MASK		  0x30000000 /* Watchdog Reset Status */
@@ -325,8 +325,9 @@
 #define	  TSR_WRS_CHIP		  0x20000000 /* Chip reset was forced by the watchdog */
 #define	  TSR_WRS_SYSTEM	  0x30000000 /* System reset was forced by the watchdog */
 #define	  TSR_PIS		  0x08000000 /* PIT Interrupt Status */
+#define	  TSR_DIS		  0x08000000 /* Decrementer Interrupt Status */
 #define	  TSR_FIS		  0x04000000 /* FIT Interrupt Status */
-#define	SPR_TCR			0x3da	/* 4.. Timer Control Register */
+
 #define	  TCR_WP_MASK		  0xc0000000 /* Watchdog Period mask */
 #define	  TCR_WP_2_17		  0x00000000 /* 2**17 clocks */
 #define	  TCR_WP_2_21		  0x40000000 /* 2**21 clocks */
@@ -339,6 +340,7 @@
 #define	  TCR_WRC_SYSTEM	  0x30000000 /* System reset */
 #define	  TCR_WIE		  0x08000000 /* Watchdog Interrupt Enable */
 #define	  TCR_PIE		  0x04000000 /* PIT Interrupt Enable */
+#define	  TCR_DIE		  0x04000000 /* Pecrementer Interrupt Enable */
 #define	  TCR_FP_MASK		  0x03000000 /* FIT Period */
 #define	  TCR_FP_2_9		  0x00000000 /* 2**9 clocks */
 #define	  TCR_FP_2_13		  0x01000000 /* 2**13 clocks */
@@ -346,9 +348,14 @@
 #define	  TCR_FP_2_21		  0x03000000 /* 2**21 clocks */
 #define	  TCR_FIE		  0x00800000 /* FIT Interrupt Enable */
 #define	  TCR_ARE		  0x00400000 /* Auto Reload Enable */
+
 #define	SPR_PIT			0x3db	/* 4.. Programmable Interval Timer */
 #define	SPR_SRR2		0x3de	/* 4.. Save/Restore Register 2 */
 #define	SPR_SRR3		0x3df	/* 4.. Save/Restore Register 3 */
+#define	SPR_HID0		0x3f0	/* ..8 Hardware Implementation Register 0 */
+#define	SPR_HID1		0x3f1	/* ..8 Hardware Implementation Register 1 */
+
+#if defined(AIM)
 #define	SPR_DBSR		0x3f0	/* 4.. Debug Status Register */
 #define	  DBSR_IC		  0x80000000 /* Instruction completion debug event */
 #define	  DBSR_BT		  0x40000000 /* Branch Taken debug event */
@@ -365,9 +372,39 @@
 #define	  DBSR_IA3		  0x00080000 /* IAC3 debug event */
 #define	  DBSR_IA4		  0x00040000 /* IAC4 debug event */
 #define	  DBSR_MRR		  0x00000300 /* Most recent reset */
-#define	SPR_HID0		0x3f0	/* ..8 Hardware Implementation Register 0 */
-#define	SPR_HID1		0x3f1	/* ..8 Hardware Implementation Register 1 */
 #define	SPR_DBCR0		0x3f2	/* 4.. Debug Control Register 0 */
+#define	SPR_DBCR1		0x3bd	/* 4.. Debug Control Register 1 */
+#define	SPR_IAC1		0x3f4	/* 4.. Instruction Address Compare 1 */
+#define	SPR_IAC2		0x3f5	/* 4.. Instruction Address Compare 2 */
+#define	SPR_DAC1		0x3f6	/* 4.. Data Address Compare 1 */
+#define	SPR_DAC2		0x3f7	/* 4.. Data Address Compare 2 */
+#define	SPR_PIR			0x3ff	/* .6. Processor Identification Register */
+#elif defined(E500)
+#define	SPR_DBSR		0x130	/* ..8 Debug Status Register */
+#define	  DBSR_IDE		  0x80000000 /* Imprecise debug event. */
+#define	  DBSR_UDE		  0x40000000 /* Unconditional debug event. */
+#define	  DBSR_MRR		  0x30000000 /* Most recent Reset (mask). */
+#define	  DBSR_ICMP		  0x08000000 /* Instr. complete debug event. */
+#define	  DBSR_BRT		  0x04000000 /* Branch taken debug event. */
+#define	  DBSR_IRPT		  0x02000000 /* Interrupt taken debug event. */
+#define	  DBSR_TRAP		  0x01000000 /* Trap instr. debug event. */
+#define	  DBSR_IAC1		  0x00800000 /* Instr. address compare #1. */
+#define	  DBSR_IAC2		  0x00400000 /* Instr. address compare #2. */
+#define	  DBSR_IAC3		  0x00200000 /* Instr. address compare #3. */
+#define	  DBSR_IAC4		  0x00100000 /* Instr. address compare #4. */
+#define	  DBSR_DAC1R		  0x00080000 /* Data addr. read compare #1. */
+#define	  DBSR_DAC1W		  0x00040000 /* Data addr. write compare #1. */
+#define	  DBSR_DAC2R		  0x00020000 /* Data addr. read compare #2. */
+#define	  DBSR_DAC2W		  0x00010000 /* Data addr. write compare #2. */
+#define	  DBSR_RET		  0x00008000 /* Return debug event. */
+#define	SPR_DBCR0		0x134	/* ..8 Debug Control Register 0 */
+#define	SPR_DBCR1		0x135	/* ..8 Debug Control Register 1 */
+#define	SPR_IAC1		0x138	/* ..8 Instruction Address Compare 1 */
+#define	SPR_IAC2		0x139	/* ..8 Instruction Address Compare 2 */
+#define	SPR_DAC1		0x13c	/* ..8 Data Address Compare 1 */
+#define	SPR_DAC2		0x13d	/* ..8 Data Address Compare 2 */
+#endif
+
 #define	  DBCR0_EDM		  0x80000000 /* External Debug Mode */
 #define	  DBCR0_IDM		  0x40000000 /* Internal Debug Mode */
 #define	  DBCR0_RST_MASK	  0x30000000 /* ReSeT */
@@ -390,12 +427,10 @@
 #define	  DBCR0_IA12T		  0x00008000 /* Instruction Address Range Compare 1-2 range Toggle */
 #define	  DBCR0_IA34T		  0x00004000 /* Instruction Address Range Compare 3-4 range Toggle */
 #define	  DBCR0_FT		  0x00000001 /* Freeze Timers on debug event */
+
 #define	SPR_IABR		0x3f2	/* ..8 Instruction Address Breakpoint Register 0 */
 #define	SPR_HID2		0x3f3	/* ..8 Hardware Implementation Register 2 */
-#define	SPR_IAC1		0x3f4	/* 4.. Instruction Address Compare 1 */
-#define	SPR_IAC2		0x3f5	/* 4.. Instruction Address Compare 2 */
 #define	SPR_DABR		0x3f5	/* .6. Data Address Breakpoint Register */
-#define	SPR_DAC1		0x3f6	/* 4.. Data Address Compare 1 */
 #define	SPR_MSSCR0		0x3f6	/* .6. Memory SubSystem Control Register */
 #define	  MSSCR0_SHDEN		  0x80000000 /* 0: Shared-state enable */
 #define	  MSSCR0_SHDPEN3	  0x40000000 /* 1: ~SHD[01] signal enable in MEI mode */
@@ -406,7 +441,6 @@
 #define	  MSSCR0_EMODE		  0x00200000 /* 10: MPX bus mode (read-only) */
 #define	  MSSCR0_ABD		  0x00100000 /* 11: address bus driven (read-only) */
 #define	  MSSCR0_MBZ		  0x000fffff /* 12-31: must be zero */
-#define	SPR_DAC2		0x3f7	/* 4.. Data Address Compare 2 */
 #define	SPR_L2PM		0x3f8	/* .6. L2 Private Memory Control Register */
 #define	SPR_L2CR		0x3f9	/* .6. L2 Control Register */
 #define	  L2CR_L2E		  0x80000000 /* 0: L2 enable */
@@ -464,11 +498,12 @@
 #define	 SPR_THRM_TIMER(x)	  ((x) << 1) /* Sampling interval timer */
 #define	 SPR_THRM_ENABLE       	  0x00000001 /* TAU Enable */
 #define	SPR_FPECR		0x3fe	/* .6. Floating-Point Exception Cause Register */
-#define	SPR_PIR			0x3ff	/* .6. Processor Identification Register */
 
 /* Time Base Register declarations */
-#define	TBR_TBL			0x10c	/* 468 Time Base Lower */
-#define	TBR_TBU			0x10d	/* 468 Time Base Upper */
+#define	TBR_TBL			0x10c	/* 468 Time Base Lower - read */
+#define	TBR_TBU			0x10d	/* 468 Time Base Upper - read */
+#define	TBR_TBWL		0x11c	/* 468 Time Base Lower - supervisor, write */
+#define	TBR_TBWU		0x11d	/* 468 Time Base Upper - supervisor, write */
 
 /* Performance counter declarations */
 #define	PMC_OVERFLOW	  	0x80000000 /* Counter has overflowed */
@@ -480,4 +515,98 @@
 #define	PMCN_TBLTRANS		 3 /* TBL bit transitions */
 #define	PCMN_IDISPATCH		 4 /* Instructions dispatched */
 
+#if defined(AIM)
+
+#define SPR_ESR			0x3d4	/* 4.. Exception Syndrome Register */
+#define	  ESR_MCI		  0x80000000 /* Machine check - instruction */
+#define	  ESR_PIL		  0x08000000 /* Program interrupt - illegal */
+#define	  ESR_PPR		  0x04000000 /* Program interrupt - privileged */
+#define	  ESR_PTR		  0x02000000 /* Program interrupt - trap */
+#define	  ESR_ST		  0x01000000 /* Store operation */
+#define	  ESR_DST		  0x00800000 /* Data storage interrupt - store fault */
+#define	  ESR_DIZ		  0x00800000 /* Data/instruction storage interrupt - zone fault */
+#define	  ESR_U0F		  0x00008000 /* Data storage interrupt - U0 fault */
+
+#elif defined(E500)
+
+#define	SPR_ESR			0x003e	/* ..8 Exception Syndrome Register */
+#define	  ESR_PIL		  0x08000000 /* Program interrupt - illegal */
+#define	  ESR_PPR		  0x04000000 /* Program interrupt - privileged */
+#define	  ESR_PTR		  0x02000000 /* Program interrupt - trap */
+#define	  ESR_ST		  0x00800000 /* Store operation */
+#define	  ESR_DLK		  0x00200000 /* Data storage, D cache locking */
+#define	  ESR_ILK		  0x00100000 /* Data storage, I cache locking */
+#define	  ESR_BO		  0x00020000 /* Data/instruction storage, byte ordering */
+#define	  ESR_SPE		  0x00000080 /* SPE exception bit */
+
+#define	SPR_CSRR0		0x03a	/* ..8 58 Critical SRR0 */
+#define	SPR_CSRR1		0x03b	/* ..8 59 Critical SRR1 */
+#define	SPR_MCSRR0		0x23a	/* ..8 570 Machine check SRR0 */
+#define	SPR_MCSRR1		0x23b	/* ..8 571 Machine check SRR1 */
+
+#define	SPR_SVR			0x3ff	/* ..8 1023 System Version Register */
+#define	SPR_PID0		0x030	/* ..8 Process ID Register 0 */
+#define	SPR_PID1		0x279	/* ..8 Process ID Register 1 */
+#define	SPR_PID2		0x27a	/* ..8 Process ID Register 2 */
+
+#define	SPR_TLB0CFG		0x2B0	/* ..8 TLB 0 Config Register */
+#define	SPR_TLB1CFG		0x2B1	/* ..8 TLB 1 Config Register */
+#define	  TLBCFG_ASSOC_MASK	0xff000000 /* Associativity of TLB */
+#define	  TLBCFG_ASSOC_SHIFT	24
+#define	  TLBCFG_NENTRY_MASK	0x00000fff /* Number of entries in TLB */
+
+#define	SPR_IVPR		0x03f	/* ..8 Interrupt Vector Prefix Register */
+#define	SPR_IVOR0		0x190	/* ..8 Critical input */
+#define	SPR_IVOR1		0x191	/* ..8 Machine check */
+#define	SPR_IVOR2		0x192
+#define	SPR_IVOR3		0x193
+#define	SPR_IVOR4		0x194
+#define	SPR_IVOR5		0x195
+#define	SPR_IVOR6		0x196
+#define	SPR_IVOR7		0x197
+#define	SPR_IVOR8		0x198
+#define	SPR_IVOR9		0x199
+#define	SPR_IVOR10		0x19a
+#define	SPR_IVOR11		0x19b
+#define	SPR_IVOR12		0x19c
+#define	SPR_IVOR13		0x19d
+#define	SPR_IVOR14		0x19e
+#define	SPR_IVOR15		0x19f
+#define	SPR_IVOR32		0x210
+#define	SPR_IVOR33		0x211
+#define	SPR_IVOR34		0x212
+#define	SPR_IVOR35		0x213
+
+#define	SPR_MAS0		0x270	/* ..8 MMU Assist Register 0 Book-E/e500 */
+#define	SPR_MAS1		0x271	/* ..8 MMU Assist Register 1 Book-E/e500 */
+#define	SPR_MAS2		0x272	/* ..8 MMU Assist Register 2 Book-E/e500 */
+#define	SPR_MAS3		0x273	/* ..8 MMU Assist Register 3 Book-E/e500 */
+#define	SPR_MAS4		0x274	/* ..8 MMU Assist Register 4 Book-E/e500 */
+#define	SPR_MAS5		0x275	/* ..8 MMU Assist Register 5 Book-E */
+#define	SPR_MAS6		0x276	/* ..8 MMU Assist Register 6 Book-E/e500 */
+#define	SPR_MAS7		0x3B0	/* ..8 MMU Assist Register 7 Book-E/e500 */
+
+#define	SPR_L1CSR0		0x3F2	/* ..8 L1 Cache Control and Status Register 0 */
+#define	  L1CSR0_DCPE		0x00010000	/* Data Cache Parity Enable */
+#define	  L1CSR0_DCLFR		0x00000100	/* Data Cache Lock Bits Flash Reset */
+#define	  L1CSR0_DCFI		0x00000002	/* Data Cache Flash Invalidate */
+#define	  L1CSR0_DCE		0x00000001	/* Data Cache Enable */
+#define	SPR_L1CSR1		0x3F3	/* ..8 L1 Cache Control and Status Register 1 */
+#define	  L1CSR1_ICPE		0x00010000	/* Instruction Cache Parity Enable */
+#define	  L1CSR1_ICLFR		0x00000100	/* Instruction Cache Lock Bits Flash Reset */
+#define	  L1CSR1_ICFI		0x00000002	/* Instruction Cache Flash Invalidate */
+#define	  L1CSR1_ICE		0x00000001	/* Instruction Cache Enable */
+
+#endif /* #elif defined(E500) */
+
+/*
+ * Definitions for system version register.
+ */
+#define	SVR_MPC8533	0x803c0010
+#define	SVR_MPC8533E	0x80340010
+#define	SVR_MPC8541	0x80720011
+#define	SVR_MPC8541E	0x807a0011
+#define	SVR_MPC8555	0x80710011
+#define	SVR_MPC8555E	0x80790011
+
 #endif /* !_POWERPC_SPR_H_ */
diff --git a/sys/powerpc/include/tlb.h b/sys/powerpc/include/tlb.h
new file mode 100644
index 0000000..a6859fc
--- /dev/null
+++ b/sys/powerpc/include/tlb.h
@@ -0,0 +1,144 @@
+/*-
+ * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef	_MACHINE_TLB_H_
+#define	_MACHINE_TLB_H_
+
+/*  PowerPC E500 MAS registers */
+#define MAS0_TLBSEL(x)		((x << 28) & 0x10000000)
+#define MAS0_ESEL(x)		((x << 16) & 0x000F0000)
+
+#define MAS0_TLBSEL1		0x10000000
+#define MAS0_TLBSEL0		0x00000000
+#define MAS0_ESEL_TLB1MASK	0x000F0000
+#define MAS0_ESEL_TLB0MASK	0x00030000
+#define MAS0_ESEL_SHIFT		16
+#define MAS0_NV_MASK		0x00000003
+#define MAS0_NV_SHIFT		0
+
+#define MAS1_VALID		0x80000000
+#define MAS1_IPROT		0x40000000
+#define MAS1_TID_MASK		0x00FF0000
+#define MAS1_TID_SHIFT		16
+#define MAS1_TS			0x00001000
+#define MAS1_TSIZE_MASK		0x00000F00
+#define MAS1_TSIZE_SHIFT	8
+
+#define	TLB_SIZE_4K		1
+#define	TLB_SIZE_16K		2
+#define	TLB_SIZE_64K		3
+#define	TLB_SIZE_256K		4
+#define	TLB_SIZE_1M		5
+#define	TLB_SIZE_4M		6
+#define	TLB_SIZE_16M		7
+#define	TLB_SIZE_64M		8
+#define	TLB_SIZE_256M		9
+#define	TLB_SIZE_1G		10
+#define	TLB_SIZE_4G		11
+
+#define	MAS2_EPN		0xFFFFF000
+#define	MAS2_EPN_SHIFT		12
+#define	MAS2_X0			0x00000040
+#define	MAS2_X1			0x00000020
+#define	MAS2_W			0x00000010
+#define	MAS2_I			0x00000008
+#define	MAS2_M			0x00000004
+#define	MAS2_G			0x00000002
+#define	MAS2_E			0x00000001
+
+#define	MAS3_RPN		0xFFFFF000
+#define	MAS3_RPN_SHIFT		12
+#define	MAS3_U0			0x00000200
+#define	MAS3_U1			0x00000100
+#define	MAS3_U2			0x00000080
+#define	MAS3_U3			0x00000040
+#define	MAS3_UX			0x00000020
+#define	MAS3_SX			0x00000010
+#define	MAS3_UW			0x00000008
+#define	MAS3_SW			0x00000004
+#define	MAS3_UR			0x00000002
+#define	MAS3_SR			0x00000001
+
+#define MAS4_TLBSELD1		0x10000000
+#define MAS4_TLBSELD0		0x00000000
+#define MAS4_TIDSELD_MASK	0x00030000
+#define MAS4_TIDSELD_SHIFT	16
+#define MAS4_TSIZED_MASK	0x00000F00
+#define MAS4_TSIZED_SHIFT	8
+#define MAS4_X0D		0x00000040
+#define MAS4_X1D		0x00000020
+#define MAS4_WD			0x00000010
+#define MAS4_ID			0x00000008
+#define MAS4_MD			0x00000004
+#define MAS4_GD			0x00000002
+#define MAS4_ED			0x00000001
+
+#define MAS6_SPID0_MASK		0x00FF0000
+#define MAS6_SPID0_SHIFT	16
+#define MAS6_SAS		0x00000001
+
+#define MAS1_GETTID(mas1)	(((mas1) & MAS1_TID_MASK) >> MAS1_TID_SHIFT)
+
+#define MAS2_TLB0_ENTRY_IDX_MASK	0x0007f000
+#define MAS2_TLB0_ENTRY_IDX_SHIFT	12
+
+/*
+ * Maximum number of TLB1 entries used for a permanat
+ * mapping of kernel region (kernel image plus statically
+ * allocated data.
+ */
+#define KERNEL_REGION_MAX_TLB_ENTRIES   4
+
+#define _TLB_ENTRY_IO	(MAS2_I | MAS2_G)
+#define _TLB_ENTRY_MEM	(0)
+
+#define KERNEL_TID	0	/* TLB TID to use for kernel translations */
+#define TID_KRESERVED	1	/* Number of TIDs reserved for kernel */
+#define TID_URESERVED	0	/* Number of TIDs reserve for user */
+#define TID_MIN		(TID_KRESERVED + TID_URESERVED)
+#define TID_MAX		255
+
+#if !defined(LOCORE)
+typedef struct tlb_entry {
+	u_int32_t mas1;
+	u_int32_t mas2;
+	u_int32_t mas3;
+} tlb_entry_t;
+
+typedef u_int8_t tlbtid_t;
+struct pmap;
+
+void tlb1_inval_entry(unsigned int);
+void tlb1_init(vm_offset_t);
+void tlb1_print_entries(void);
+void tlb1_print_tlbentries(void);
+
+#endif /* !LOCORE */
+
+#endif	/* _MACHINE_TLB_H_ */
diff --git a/sys/powerpc/include/trap.h b/sys/powerpc/include/trap.h
index 18778a8..271092a 100644
--- a/sys/powerpc/include/trap.h
+++ b/sys/powerpc/include/trap.h
@@ -1,113 +1,12 @@
-/*-
- * Copyright (C) 1995, 1996 Wolfgang Solfrank.
- * Copyright (C) 1995, 1996 TooLs GmbH.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by TooLs GmbH.
- * 4. The name of TooLs GmbH may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * $NetBSD: trap.h,v 1.7 2002/02/22 13:51:40 kleink Exp $
- * $FreeBSD$ 
- */
+/* $FreeBSD$ */
 
-#ifndef	_POWERPC_TRAP_H_
-#define	_POWERPC_TRAP_H_
-
-#define	EXC_RSVD	0x0000		/* Reserved */
-#define	EXC_RST		0x0100		/* Reset; all but IBM4xx */
-#define	EXC_MCHK	0x0200		/* Machine Check */
-#define	EXC_DSI		0x0300		/* Data Storage Interrupt */
-#define	EXC_ISI		0x0400		/* Instruction Storage Interrupt */
-#define	EXC_EXI		0x0500		/* External Interrupt */
-#define	EXC_ALI		0x0600		/* Alignment Interrupt */
-#define	EXC_PGM		0x0700		/* Program Interrupt */
-#define	EXC_FPU		0x0800		/* Floating-point Unavailable */
-#define	EXC_DECR	0x0900		/* Decrementer Interrupt */
-#define	EXC_SC		0x0c00		/* System Call */
-#define	EXC_TRC		0x0d00		/* Trace */
-#define	EXC_FPA		0x0e00		/* Floating-point Assist */
-
-/* The following is only available on the 601: */
-#define	EXC_RUNMODETRC	0x2000		/* Run Mode/Trace Exception */
-
-/* The following are only available on 7400(G4): */
-#define	EXC_VEC		0x0f20		/* AltiVec Unavailable */
-#define	EXC_VECAST	0x1600		/* AltiVec Assist */
-
-/* The following are only available on 604/750/7400: */
-#define	EXC_PERF	0x0f00		/* Performance Monitoring */
-#define	EXC_BPT		0x1300		/* Instruction Breakpoint */
-#define	EXC_SMI		0x1400		/* System Managment Interrupt */
-
-/* The following are only available on 750/7400: */
-#define	EXC_THRM	0x1700		/* Thermal Management Interrupt */
-
-/* And these are only on the 603: */
-#define	EXC_IMISS	0x1000		/* Instruction translation miss */
-#define	EXC_DLMISS	0x1100		/* Data load translation miss */
-#define	EXC_DSMISS	0x1200		/* Data store translation miss */
-
-/* The following are only available on 405 (and 403?) */
-#define	EXC_CII		0x0100		/* Critical Input Interrupt */
-#define	EXC_PIT		0x1000		/* Programmable Interval Timer */
-#define	EXC_FIT		0x1010		/* Fixed Interval Timer */
-#define	EXC_WDOG	0x1020		/* Watchdog Timer */
-#define	EXC_DTMISS	0x1100		/* Data TLB Miss */
-#define	EXC_ITMISS	0x1200		/* Instruction TLB Miss */
-#define	EXC_DEBUG	0x2000		/* Debug trap */
-
-#define	EXC_LAST	0x2f00		/* Last possible exception vector */
-
-#define	EXC_AST		0x3000		/* Fake AST vector */
-
-/* Trap was in user mode */
-#define	EXC_USER	0x10000
-
-
-/*
- * EXC_ALI sets bits in the DSISR and DAR to provide enough
- * information to recover from the unaligned access without needing to
- * parse the offending instruction. This includes certain bits of the
- * opcode, and information about what registers are used. The opcode
- * indicator values below come from Appendix F of Book III of "The
- * PowerPC Architecture".
- */
-
-#define EXC_ALI_OPCODE_INDICATOR(dsisr) ((dsisr >> 10) & 0x7f)
-#define EXC_ALI_LFD	0x09
-#define EXC_ALI_STFD	0x0b
-
-/* Macros to extract register information */
-#define EXC_ALI_RST(dsisr) ((dsisr >> 5) & 0x1f)   /* source or target */
-#define EXC_ALI_RA(dsisr) (dsisr & 0x1f)
+#if defined(AIM)
+#include <machine/trap_aim.h>
+#elif defined(E500)
+#include <machine/trap_booke.h>
+#endif
 
 #ifndef LOCORE
-
 struct trapframe;
 void    trap(struct trapframe *);
-
 #endif
-
-#endif	/* _POWERPC_TRAP_H_ */
diff --git a/sys/powerpc/include/trap_aim.h b/sys/powerpc/include/trap_aim.h
new file mode 100644
index 0000000..753693b
--- /dev/null
+++ b/sys/powerpc/include/trap_aim.h
@@ -0,0 +1,106 @@
+/*-
+ * Copyright (C) 1995, 1996 Wolfgang Solfrank.
+ * Copyright (C) 1995, 1996 TooLs GmbH.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by TooLs GmbH.
+ * 4. The name of TooLs GmbH may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $NetBSD: trap.h,v 1.7 2002/02/22 13:51:40 kleink Exp $
+ * $FreeBSD$
+ */
+
+#ifndef	_POWERPC_TRAP_H_
+#define	_POWERPC_TRAP_H_
+
+#define	EXC_RSVD	0x0000		/* Reserved */
+#define	EXC_RST		0x0100		/* Reset; all but IBM4xx */
+#define	EXC_MCHK	0x0200		/* Machine Check */
+#define	EXC_DSI		0x0300		/* Data Storage Interrupt */
+#define	EXC_ISI		0x0400		/* Instruction Storage Interrupt */
+#define	EXC_EXI		0x0500		/* External Interrupt */
+#define	EXC_ALI		0x0600		/* Alignment Interrupt */
+#define	EXC_PGM		0x0700		/* Program Interrupt */
+#define	EXC_FPU		0x0800		/* Floating-point Unavailable */
+#define	EXC_DECR	0x0900		/* Decrementer Interrupt */
+#define	EXC_SC		0x0c00		/* System Call */
+#define	EXC_TRC		0x0d00		/* Trace */
+#define	EXC_FPA		0x0e00		/* Floating-point Assist */
+
+/* The following is only available on the 601: */
+#define	EXC_RUNMODETRC	0x2000		/* Run Mode/Trace Exception */
+
+/* The following are only available on 7400(G4): */
+#define	EXC_VEC		0x0f20		/* AltiVec Unavailable */
+#define	EXC_VECAST	0x1600		/* AltiVec Assist */
+
+/* The following are only available on 604/750/7400: */
+#define	EXC_PERF	0x0f00		/* Performance Monitoring */
+#define	EXC_BPT		0x1300		/* Instruction Breakpoint */
+#define	EXC_SMI		0x1400		/* System Managment Interrupt */
+
+/* The following are only available on 750/7400: */
+#define	EXC_THRM	0x1700		/* Thermal Management Interrupt */
+
+/* And these are only on the 603: */
+#define	EXC_IMISS	0x1000		/* Instruction translation miss */
+#define	EXC_DLMISS	0x1100		/* Data load translation miss */
+#define	EXC_DSMISS	0x1200		/* Data store translation miss */
+
+/* The following are available on 4xx and 85xx */
+#define	EXC_CII		0x0100		/* Critical Input Interrupt */
+#define	EXC_PIT		0x1000		/* Programmable Interval Timer */
+#define	EXC_FIT		0x1010		/* Fixed Interval Timer */
+#define	EXC_WDOG	0x1020		/* Watchdog Timer */
+#define	EXC_DTMISS	0x1100		/* Data TLB Miss */
+#define	EXC_ITMISS	0x1200		/* Instruction TLB Miss */
+#define	EXC_DEBUG	0x2000		/* Debug trap */
+
+#define	EXC_LAST	0x2f00		/* Last possible exception vector */
+
+#define	EXC_AST		0x3000		/* Fake AST vector */
+
+/* Trap was in user mode */
+#define	EXC_USER	0x10000
+
+
+/*
+ * EXC_ALI sets bits in the DSISR and DAR to provide enough
+ * information to recover from the unaligned access without needing to
+ * parse the offending instruction. This includes certain bits of the
+ * opcode, and information about what registers are used. The opcode
+ * indicator values below come from Appendix F of Book III of "The
+ * PowerPC Architecture".
+ */
+
+#define EXC_ALI_OPCODE_INDICATOR(dsisr) ((dsisr >> 10) & 0x7f)
+#define EXC_ALI_LFD	0x09
+#define EXC_ALI_STFD	0x0b
+
+/* Macros to extract register information */
+#define EXC_ALI_RST(dsisr) ((dsisr >> 5) & 0x1f)   /* source or target */
+#define EXC_ALI_RA(dsisr) (dsisr & 0x1f)
+
+#endif	/* _POWERPC_TRAP_H_ */
diff --git a/sys/powerpc/include/trap_booke.h b/sys/powerpc/include/trap_booke.h
new file mode 100644
index 0000000..b6dbc64
--- /dev/null
+++ b/sys/powerpc/include/trap_booke.h
@@ -0,0 +1,55 @@
+/*-
+ * Copyright (C) 2006 Semihalf, Rafal Jaworowski <raj@semihalf.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef	_POWERPC_TRAP_H_
+#define	_POWERPC_TRAP_H_
+
+#define	EXC_CRIT	0
+#define	EXC_MCHK	1
+#define	EXC_DSI		2
+#define	EXC_ISI		3
+#define	EXC_EXI		4
+#define	EXC_ALI		5
+#define	EXC_PGM		6
+#define	EXC_FPU		7	/* e500: not supported */
+#define	EXC_SC		8
+#define	EXC_APU		9	/* e500: not supported */
+#define	EXC_DECR	10
+#define	EXC_FIT		11
+#define	EXC_WDOG	12
+#define	EXC_DTMISS	13
+#define	EXC_ITMISS	14
+#define	EXC_DEBUG	15
+
+#define	EXC_SAU		32	/* e500-specific: SPE APU unavailable */
+#define	EXC_PERF	35	/* e500-specific: Performance monitor */
+
+#define	EXC_LAST	255
+
+#endif	/* _POWERPC_TRAP_H_ */
diff --git a/sys/powerpc/include/vmparam.h b/sys/powerpc/include/vmparam.h
index 212624f..489159d 100644
--- a/sys/powerpc/include/vmparam.h
+++ b/sys/powerpc/include/vmparam.h
@@ -76,31 +76,62 @@
 #define	MAXSLP 		20
 
 /*
- * Use the direct-mapped BAT registers for UMA small allocs. This
- * takes pressure off the small amount of available KVA.
- */
-#define UMA_MD_SMALL_ALLOC
-
-/*
  * Would like to have MAX addresses = 0, but this doesn't (currently) work
  */
+#if !defined(LOCORE)
 #define	VM_MIN_ADDRESS		((vm_offset_t)0)
+
 #define	VM_MAXUSER_ADDRESS	((vm_offset_t)0x7ffff000)
+
+#else
+#define	VM_MIN_ADDRESS		0
+
+#define	VM_MAXUSER_ADDRESS	0x7ffff000
+
+#endif /* LOCORE */
+
 #define	VM_MAX_ADDRESS		VM_MAXUSER_ADDRESS
+
+
+#if defined(AIM)	/* AIM */
+
+#define	KERNBASE		0x00100000	/* start of kernel virtual */
+
 #define	VM_MIN_KERNEL_ADDRESS	((vm_offset_t)(KERNEL_SR << ADDR_SR_SHFT))
 #define	VM_MAX_KERNEL_ADDRESS	(VM_MIN_KERNEL_ADDRESS + 2*SEGMENT_LENGTH - 1)
 
-#define	KERNBASE	0x100000	/* start of kernel virtual */
+/*
+ * Use the direct-mapped BAT registers for UMA small allocs. This
+ * takes pressure off the small amount of available KVA.
+ */
+#define UMA_MD_SMALL_ALLOC
+
+#else
+
+/*
+ * Kernel CCSRBAR location. We make this the reset location.
+ */
+#define	CCSRBAR_VA		0xfef00000
+#define	CCSRBAR_SIZE		0x00100000
+
+#define	KERNBASE		0xc0000000	/* start of kernel virtual */
+
+#define	VM_MIN_KERNEL_ADDRESS	KERNBASE
+#define	VM_MAX_KERNEL_ADDRESS	CCSRBAR_VA
+
+#endif /* AIM/E500 */
 
 /* XXX max. amount of KVM to be used by buffers. */
 #ifndef VM_MAX_KERNEL_BUF
 #define	VM_MAX_KERNEL_BUF	(SEGMENT_LENGTH * 7 / 10)
 #endif
 
+#if !defined(LOCORE)
 struct pmap_physseg {
 	struct pv_entry *pvent;
 	char *attrs;
 };
+#endif
 
 #define	VM_PHYSSEG_MAX		16	/* 1? */