Prevent wedging of the stat clock because of missed interrupts.

This should cure the "alternate system clock has died!" problem.

Discussed with: bde, joerg

5 files changed, 50 insertions, 25 deletions

diff --git a/sys/amd64/amd64/tsc.c b/sys/amd64/amd64/tsc.c
index d7ffe6e..b942553 100644
--- a/sys/amd64/amd64/tsc.c
+++ b/sys/amd64/amd64/tsc.c
@@ -34,7 +34,7 @@
  * SUCH DAMAGE.
  *
  *	from: @(#)clock.c	7.2 (Berkeley) 5/12/91
- *	$Id: clock.c,v 1.78 1997/03/05 00:54:00 gpalmer Exp $
+ *	$Id: clock.c,v 1.79 1997/03/05 08:08:48 bde Exp $
  */
 
 /*
@@ -311,15 +311,20 @@ release_timer2()
  *
  * The RTC chip requires that we read status register C (RTC_INTR)
  * to acknowledge an interrupt, before it will generate the next one.
+ * Under high interrupt load, rtcintr() can be indefinitely delayed and
+ * the clock can tick immediately after the read from RTC_INTR.  In this
+ * case, the mc146818A interrupt signal will not drop for long enough
+ * to register with the 8259 PIC.  If an interrupt is missed, the stat
+ * clock will halt, considerably degrading system performance.  This is
+ * why we use 'while' rather than a more straightforward 'if' below.
+ * Stat clock ticks can still be lost, causing minor loss of accuracy
+ * in the statistics, but the stat clock will no longer stop.
  */
 static void
 rtcintr(struct clockframe frame)
 {
-	u_char stat;
-	stat = rtcin(RTC_INTR);
-	if(stat & RTCIR_PERIOD) {
+	while (rtcin(RTC_INTR) & RTCIR_PERIOD)
 		statclock(&frame);
-	}
 }
 
 #include "opt_ddb.h"
diff --git a/sys/amd64/isa/clock.c b/sys/amd64/isa/clock.c
index d7ffe6e..b942553 100644
--- a/sys/amd64/isa/clock.c
+++ b/sys/amd64/isa/clock.c
@@ -34,7 +34,7 @@
  * SUCH DAMAGE.
  *
  *	from: @(#)clock.c	7.2 (Berkeley) 5/12/91
- *	$Id: clock.c,v 1.78 1997/03/05 00:54:00 gpalmer Exp $
+ *	$Id: clock.c,v 1.79 1997/03/05 08:08:48 bde Exp $
  */
 
 /*
@@ -311,15 +311,20 @@ release_timer2()
  *
  * The RTC chip requires that we read status register C (RTC_INTR)
  * to acknowledge an interrupt, before it will generate the next one.
+ * Under high interrupt load, rtcintr() can be indefinitely delayed and
+ * the clock can tick immediately after the read from RTC_INTR.  In this
+ * case, the mc146818A interrupt signal will not drop for long enough
+ * to register with the 8259 PIC.  If an interrupt is missed, the stat
+ * clock will halt, considerably degrading system performance.  This is
+ * why we use 'while' rather than a more straightforward 'if' below.
+ * Stat clock ticks can still be lost, causing minor loss of accuracy
+ * in the statistics, but the stat clock will no longer stop.
  */
 static void
 rtcintr(struct clockframe frame)
 {
-	u_char stat;
-	stat = rtcin(RTC_INTR);
-	if(stat & RTCIR_PERIOD) {
+	while (rtcin(RTC_INTR) & RTCIR_PERIOD)
 		statclock(&frame);
-	}
 }
 
 #include "opt_ddb.h"
diff --git a/sys/i386/i386/tsc.c b/sys/i386/i386/tsc.c
index d7ffe6e..b942553 100644
--- a/sys/i386/i386/tsc.c
+++ b/sys/i386/i386/tsc.c
@@ -34,7 +34,7 @@
  * SUCH DAMAGE.
  *
  *	from: @(#)clock.c	7.2 (Berkeley) 5/12/91
- *	$Id: clock.c,v 1.78 1997/03/05 00:54:00 gpalmer Exp $
+ *	$Id: clock.c,v 1.79 1997/03/05 08:08:48 bde Exp $
  */
 
 /*
@@ -311,15 +311,20 @@ release_timer2()
  *
  * The RTC chip requires that we read status register C (RTC_INTR)
  * to acknowledge an interrupt, before it will generate the next one.
+ * Under high interrupt load, rtcintr() can be indefinitely delayed and
+ * the clock can tick immediately after the read from RTC_INTR.  In this
+ * case, the mc146818A interrupt signal will not drop for long enough
+ * to register with the 8259 PIC.  If an interrupt is missed, the stat
+ * clock will halt, considerably degrading system performance.  This is
+ * why we use 'while' rather than a more straightforward 'if' below.
+ * Stat clock ticks can still be lost, causing minor loss of accuracy
+ * in the statistics, but the stat clock will no longer stop.
  */
 static void
 rtcintr(struct clockframe frame)
 {
-	u_char stat;
-	stat = rtcin(RTC_INTR);
-	if(stat & RTCIR_PERIOD) {
+	while (rtcin(RTC_INTR) & RTCIR_PERIOD)
 		statclock(&frame);
-	}
 }
 
 #include "opt_ddb.h"
diff --git a/sys/i386/isa/clock.c b/sys/i386/isa/clock.c
index d7ffe6e..b942553 100644
--- a/sys/i386/isa/clock.c
+++ b/sys/i386/isa/clock.c
@@ -34,7 +34,7 @@
  * SUCH DAMAGE.
  *
  *	from: @(#)clock.c	7.2 (Berkeley) 5/12/91
- *	$Id: clock.c,v 1.78 1997/03/05 00:54:00 gpalmer Exp $
+ *	$Id: clock.c,v 1.79 1997/03/05 08:08:48 bde Exp $
  */
 
 /*
@@ -311,15 +311,20 @@ release_timer2()
  *
  * The RTC chip requires that we read status register C (RTC_INTR)
  * to acknowledge an interrupt, before it will generate the next one.
+ * Under high interrupt load, rtcintr() can be indefinitely delayed and
+ * the clock can tick immediately after the read from RTC_INTR.  In this
+ * case, the mc146818A interrupt signal will not drop for long enough
+ * to register with the 8259 PIC.  If an interrupt is missed, the stat
+ * clock will halt, considerably degrading system performance.  This is
+ * why we use 'while' rather than a more straightforward 'if' below.
+ * Stat clock ticks can still be lost, causing minor loss of accuracy
+ * in the statistics, but the stat clock will no longer stop.
  */
 static void
 rtcintr(struct clockframe frame)
 {
-	u_char stat;
-	stat = rtcin(RTC_INTR);
-	if(stat & RTCIR_PERIOD) {
+	while (rtcin(RTC_INTR) & RTCIR_PERIOD)
 		statclock(&frame);
-	}
 }
 
 #include "opt_ddb.h"
diff --git a/sys/isa/atrtc.c b/sys/isa/atrtc.c
index d7ffe6e..b942553 100644
--- a/sys/isa/atrtc.c
+++ b/sys/isa/atrtc.c
@@ -34,7 +34,7 @@
  * SUCH DAMAGE.
  *
  *	from: @(#)clock.c	7.2 (Berkeley) 5/12/91
- *	$Id: clock.c,v 1.78 1997/03/05 00:54:00 gpalmer Exp $
+ *	$Id: clock.c,v 1.79 1997/03/05 08:08:48 bde Exp $
  */
 
 /*
@@ -311,15 +311,20 @@ release_timer2()
  *
  * The RTC chip requires that we read status register C (RTC_INTR)
  * to acknowledge an interrupt, before it will generate the next one.
+ * Under high interrupt load, rtcintr() can be indefinitely delayed and
+ * the clock can tick immediately after the read from RTC_INTR.  In this
+ * case, the mc146818A interrupt signal will not drop for long enough
+ * to register with the 8259 PIC.  If an interrupt is missed, the stat
+ * clock will halt, considerably degrading system performance.  This is
+ * why we use 'while' rather than a more straightforward 'if' below.
+ * Stat clock ticks can still be lost, causing minor loss of accuracy
+ * in the statistics, but the stat clock will no longer stop.
  */
 static void
 rtcintr(struct clockframe frame)
 {
-	u_char stat;
-	stat = rtcin(RTC_INTR);
-	if(stat & RTCIR_PERIOD) {
+	while (rtcin(RTC_INTR) & RTCIR_PERIOD)
 		statclock(&frame);
-	}
 }
 
 #include "opt_ddb.h"