Add some missing DFS chipset functionality to the FreeBSD HAL.

Please note - this doesn't in any way constitute a full DFS
implementation, it merely adds the relevant capability bits and
radar detection threshold register access.

The particulars:

* Add new capability bits outlining what the DFS capabilities
  are of the various chipsets.
* Add HAL methods to set and get the radar related register values.
* Add AR5212 and AR5416+ DFS radar related register value
  routines.
* Add a missing HAL phy error code that's related to radar event
  processing.
* Add HAL_PHYERR_PARAM, a data type that encapsulates the radar
  register values.

The AR5212 routines are just for completeness. The AR5416 routines
are a super-set of those; I may later on do a drive-by pass to
tidy up duplicate code.

Obtained from:	Linux, Atheros

16 files changed, 242 insertions, 1 deletions

diff --git a/sys/dev/ath/ath_hal/ah.c b/sys/dev/ath/ath_hal/ah.c
index e84f9b3..647f322 100644
--- a/sys/dev/ath/ath_hal/ah.c
+++ b/sys/dev/ath/ath_hal/ah.c
@@ -610,6 +610,10 @@ ath_hal_getcapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
 		return HAL_OK;
 	case HAL_CAP_4ADDR_AGGR:
 		return pCap->hal4AddrAggrSupport ? HAL_OK : HAL_ENOTSUPP;
+	case HAL_CAP_EXT_CHAN_DFS:
+		return pCap->halExtChanDfsSupport ? HAL_OK : HAL_ENOTSUPP;
+	case HAL_CAP_COMBINED_RADAR_RSSI:
+		return pCap->halUseCombinedRadarRssi ? HAL_OK : HAL_ENOTSUPP;
 	case HAL_CAP_AUTO_SLEEP:
 		return pCap->halAutoSleepSupport ? HAL_OK : HAL_ENOTSUPP;
 	case HAL_CAP_MBSSID_AGGR_SUPPORT:
@@ -626,6 +630,8 @@ ath_hal_getcapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
 	case HAL_CAP_RXTSTAMP_PREC:	/* rx desc tstamp precision (bits) */
 		*result = pCap->halTstampPrecision;
 		return HAL_OK;
+	case HAL_CAP_ENHANCED_DFS_SUPPORT:
+		return pCap->halEnhancedDfsSupport ? HAL_OK : HAL_ENOTSUPP;
 
 	/* FreeBSD-specific entries for now */
 	case HAL_CAP_RXORN_FATAL:	/* HAL_INT_RXORN treated as fatal  */
diff --git a/sys/dev/ath/ath_hal/ah.h b/sys/dev/ath/ath_hal/ah.h
index 7bf2843..bbea10a 100644
--- a/sys/dev/ath/ath_hal/ah.h
+++ b/sys/dev/ath/ath_hal/ah.h
@@ -121,6 +121,9 @@ typedef enum {
 
 	HAL_CAP_RTS_AGGR_LIMIT	= 42,	/* aggregation limit with RTS */
 	HAL_CAP_4ADDR_AGGR	= 43,	/* hardware is capable of 4addr aggregation */
+	HAL_CAP_DFS_DMN		= 44,	/* current DFS domain */
+	HAL_CAP_EXT_CHAN_DFS	= 45,	/* DFS support for extension channel */
+	HAL_CAP_COMBINED_RADAR_RSSI	= 46,	/* Is combined RSSI for radar accurate */
 
 	HAL_CAP_AUTO_SLEEP	= 48,	/* hardware can go to network sleep
 					   automatically after waking up to receive TIM */
@@ -133,6 +136,7 @@ typedef enum {
 	HAL_CAP_HT20_SGI	= 96,	/* hardware supports HT20 short GI */
 
 	HAL_CAP_RXTSTAMP_PREC	= 100,	/* rx desc tstamp precision (bits) */
+	HAL_CAP_ENHANCED_DFS_SUPPORT	= 117,	/* hardware supports enhanced DFS */
 
 	/* The following are private to the FreeBSD HAL (224 onward) */
 
@@ -703,6 +707,34 @@ typedef enum {
 	HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL = 6
 } HAL_CAP_INTMIT_CMD;
 
+typedef struct {
+	int32_t		pe_firpwr;	/* FIR pwr out threshold */
+	int32_t		pe_rrssi;	/* Radar rssi thresh */
+	int32_t		pe_height;	/* Pulse height thresh */
+	int32_t		pe_prssi;	/* Pulse rssi thresh */
+	int32_t		pe_inband;	/* Inband thresh */
+
+	/* The following params are only for AR5413 and later */
+	u_int32_t	pe_relpwr;	/* Relative power threshold in 0.5dB steps */
+	u_int32_t	pe_relstep;	/* Pulse Relative step threshold in 0.5dB steps */
+	u_int32_t	pe_maxlen;	/* Max length of radar sign in 0.8us units */
+	HAL_BOOL	pe_usefir128;	/* Use the average in-band power measured over 128 cycles */
+	HAL_BOOL	pe_blockradar;	/*
+					 * Enable to block radar check if pkt detect is done via OFDM
+					 * weak signal detect or pkt is detected immediately after tx
+					 * to rx transition
+					 */
+	HAL_BOOL	pe_enmaxrssi;	/*
+					 * Enable to use the max rssi instead of the last rssi during
+					 * fine gain changes for radar detection
+					 */
+	HAL_BOOL	pe_extchannel;	/* Enable DFS on ext channel */
+} HAL_PHYERR_PARAM;
+
+#define	HAL_PHYERR_PARAM_NOVAL	65535
+#define	HAL_PHYERR_PARAM_ENABLE	0x8000	/* Enable/Disable if applicable */
+
+
 /*
  * Hardware Access Layer (HAL) API.
  *
@@ -878,6 +910,12 @@ struct ath_hal {
 	HAL_BOOL  __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int);
 	void	  __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int);
 
+	/* DFS functions */
+	void	  __ahdecl(*ah_enableDfs)(struct ath_hal *ah,
+				HAL_PHYERR_PARAM *pe);
+	void	  __ahdecl(*ah_getDfsThresh)(struct ath_hal *ah,
+				HAL_PHYERR_PARAM *pe);
+
 	/* Key Cache Functions */
 	uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*);
 	HAL_BOOL  __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t);
diff --git a/sys/dev/ath/ath_hal/ah_desc.h b/sys/dev/ath/ath_hal/ah_desc.h
index ff6f40c..bd3e6a8 100644
--- a/sys/dev/ath/ath_hal/ah_desc.h
+++ b/sys/dev/ath/ath_hal/ah_desc.h
@@ -144,7 +144,7 @@ enum {
 	HAL_PHYERR_RADAR		= 5,	/* Radar detect */
 	HAL_PHYERR_SERVICE		= 6,	/* Illegal service */
 	HAL_PHYERR_TOR			= 7,	/* Transmit override receive */
-	/* NB: these are specific to the 5212 */
+	/* NB: these are specific to the 5212 and later */
 	HAL_PHYERR_OFDM_TIMING		= 17,	/* */
 	HAL_PHYERR_OFDM_SIGNAL_PARITY	= 18,	/* */
 	HAL_PHYERR_OFDM_RATE_ILLEGAL	= 19,	/* */
@@ -152,6 +152,7 @@ enum {
 	HAL_PHYERR_OFDM_POWER_DROP	= 21,	/* */
 	HAL_PHYERR_OFDM_SERVICE		= 22,	/* */
 	HAL_PHYERR_OFDM_RESTART		= 23,	/* */
+	HAL_PHYERR_FALSE_RADAR_EXT	= 24,	/* */
 	HAL_PHYERR_CCK_TIMING		= 25,	/* */
 	HAL_PHYERR_CCK_HEADER_CRC	= 26,	/* */
 	HAL_PHYERR_CCK_RATE_ILLEGAL	= 27,	/* */
diff --git a/sys/dev/ath/ath_hal/ah_internal.h b/sys/dev/ath/ath_hal/ah_internal.h
index b994eab..d66c9d8 100644
--- a/sys/dev/ath/ath_hal/ah_internal.h
+++ b/sys/dev/ath/ath_hal/ah_internal.h
@@ -200,8 +200,10 @@ typedef struct {
 			halRifsTxSupport		: 1,
 			hal4AddrAggrSupport		: 1,
 			halExtChanDfsSupport		: 1,
+			halUseCombinedRadarRssi		: 1,
 			halForcePpmSupport		: 1,
 			halEnhancedPmSupport		: 1,
+			halEnhancedDfsSupport		: 1,
 			halMbssidAggrSupport		: 1,
 			halBssidMatchSupport		: 1,
 			hal4kbSplitTransSupport		: 1,
diff --git a/sys/dev/ath/ath_hal/ar5212/ar5212.h b/sys/dev/ath/ath_hal/ar5212/ar5212.h
index 5bdfcb4..a9ea4ef 100644
--- a/sys/dev/ath/ath_hal/ar5212/ar5212.h
+++ b/sys/dev/ath/ath_hal/ar5212/ar5212.h
@@ -618,5 +618,7 @@ extern	void ar5212AniReset(struct ath_hal *, const struct ieee80211_channel *,
 
 extern	HAL_BOOL ar5212IsNFCalInProgress(struct ath_hal *ah);
 extern	HAL_BOOL ar5212WaitNFCalComplete(struct ath_hal *ah, int i);
+extern	void ar5212EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe);
+extern	void ar5212GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe);
 
 #endif	/* _ATH_AR5212_H_ */
diff --git a/sys/dev/ath/ath_hal/ar5212/ar5212_attach.c b/sys/dev/ath/ath_hal/ar5212/ar5212_attach.c
index 5f85522..90605cf 100644
--- a/sys/dev/ath/ath_hal/ar5212/ar5212_attach.c
+++ b/sys/dev/ath/ath_hal/ar5212/ar5212_attach.c
@@ -128,6 +128,10 @@ static const struct ath_hal_private ar5212hal = {{
 	.ah_setDecompMask               = ar5212SetDecompMask,
 	.ah_setCoverageClass            = ar5212SetCoverageClass,
 
+	/* DFS Functions */
+	.ah_enableDfs			= ar5212EnableDfs,
+	.ah_getDfsThresh		= ar5212GetDfsThresh,
+
 	/* Key Cache Functions */
 	.ah_getKeyCacheSize		= ar5212GetKeyCacheSize,
 	.ah_resetKeyCacheEntry		= ar5212ResetKeyCacheEntry,
diff --git a/sys/dev/ath/ath_hal/ar5212/ar5212_misc.c b/sys/dev/ath/ath_hal/ar5212/ar5212_misc.c
index 518d079..ad1b7eb 100644
--- a/sys/dev/ath/ath_hal/ar5212/ar5212_misc.c
+++ b/sys/dev/ath/ath_hal/ar5212/ar5212_misc.c
@@ -1115,3 +1115,54 @@ ar5212WaitNFCalComplete(struct ath_hal *ah, int i)
 	}
 	return AH_FALSE;
 }
+
+void
+ar5212EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
+{
+	uint32_t val;
+	val = OS_REG_READ(ah, AR_PHY_RADAR_0);
+
+	if (pe->pe_firpwr != HAL_PHYERR_PARAM_NOVAL) {
+		val &= ~AR_PHY_RADAR_0_FIRPWR;
+		val |= SM(pe->pe_firpwr, AR_PHY_RADAR_0_FIRPWR);
+	}
+	if (pe->pe_rrssi != HAL_PHYERR_PARAM_NOVAL) {
+		val &= ~AR_PHY_RADAR_0_RRSSI;
+		val |= SM(pe->pe_rrssi, AR_PHY_RADAR_0_RRSSI);
+	}
+	if (pe->pe_height != HAL_PHYERR_PARAM_NOVAL) {
+		val &= ~AR_PHY_RADAR_0_HEIGHT;
+		val |= SM(pe->pe_height, AR_PHY_RADAR_0_HEIGHT);
+	}
+	if (pe->pe_prssi != HAL_PHYERR_PARAM_NOVAL) {
+		val &= ~AR_PHY_RADAR_0_PRSSI;
+		val |= SM(pe->pe_prssi, AR_PHY_RADAR_0_PRSSI);
+	}
+	if (pe->pe_inband != HAL_PHYERR_PARAM_NOVAL) {
+		val &= ~AR_PHY_RADAR_0_INBAND;
+		val |= SM(pe->pe_inband, AR_PHY_RADAR_0_INBAND);
+	}
+	OS_REG_WRITE(ah, AR_PHY_RADAR_0, val | AR_PHY_RADAR_0_ENA);
+}
+
+void
+ar5212GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
+{
+	uint32_t val,temp;
+
+	val = OS_REG_READ(ah, AR_PHY_RADAR_0);
+
+	temp = MS(val,AR_PHY_RADAR_0_FIRPWR);
+	temp |= 0xFFFFFF80;
+	pe->pe_firpwr = temp;
+	pe->pe_rrssi = MS(val, AR_PHY_RADAR_0_RRSSI);
+	pe->pe_height =  MS(val, AR_PHY_RADAR_0_HEIGHT);
+	pe->pe_prssi = MS(val, AR_PHY_RADAR_0_PRSSI);
+	pe->pe_inband = MS(val, AR_PHY_RADAR_0_INBAND);
+
+	pe->pe_relpwr = 0;
+	pe->pe_relstep = 0;
+	pe->pe_maxlen = 0;
+	pe->pe_extchannel = AH_FALSE;
+}
+
diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416.h b/sys/dev/ath/ath_hal/ar5416/ar5416.h
index 5327296..984b5e8 100644
--- a/sys/dev/ath/ath_hal/ar5416/ar5416.h
+++ b/sys/dev/ath/ath_hal/ar5416/ar5416.h
@@ -201,6 +201,8 @@ extern	HAL_BOOL ar5416GetDiagState(struct ath_hal *ah, int request,
 	    void **result, uint32_t *resultsize);
 extern	HAL_BOOL ar5416SetRifsDelay(struct ath_hal *ah,
 	    const struct ieee80211_channel *chan, HAL_BOOL enable);
+extern	void ar5416EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe);
+extern	void ar5416GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe);
 
 extern	HAL_BOOL ar5416SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode,
 		int setChip);
diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c b/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c
index dc1a5ff..aa9d97b 100644
--- a/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c
+++ b/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c
@@ -143,6 +143,10 @@ ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc,
 	ah->ah_resetKeyCacheEntry	= ar5416ResetKeyCacheEntry;
 	ah->ah_setKeyCacheEntry		= ar5416SetKeyCacheEntry;
 
+	/* DFS Functions */
+	ah->ah_enableDfs		= ar5416EnableDfs;
+	ah->ah_getDfsThresh		= ar5416GetDfsThresh;
+
 	/* Power Management Functions */
 	ah->ah_setPowerMode		= ar5416SetPowerMode;
 
@@ -878,6 +882,7 @@ ar5416FillCapabilityInfo(struct ath_hal *ah)
 	pCap->halBssidMatchSupport = AH_TRUE;
 	pCap->halGTTSupport = AH_TRUE;
 	pCap->halCSTSupport = AH_TRUE;
+	pCap->halEnhancedDfsSupport = AH_FALSE;
 
 	if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) &&
 	    ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) {
diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_misc.c b/sys/dev/ath/ath_hal/ar5416/ar5416_misc.c
index 8f18c46..4b1ba22 100644
--- a/sys/dev/ath/ath_hal/ar5416/ar5416_misc.c
+++ b/sys/dev/ath/ath_hal/ar5416/ar5416_misc.c
@@ -560,3 +560,106 @@ ar5416DetectBBHang(struct ath_hal *ah)
 #undef N
 }
 #undef NUM_STATUS_READS
+
+/*
+ * Get the radar parameter values and return them in the pe
+ * structure
+ */
+void
+ar5416GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
+{
+	uint32_t val, temp;
+
+	val = OS_REG_READ(ah, AR_PHY_RADAR_0);
+
+	temp = MS(val,AR_PHY_RADAR_0_FIRPWR);
+	temp |= 0xFFFFFF80;
+	pe->pe_firpwr = temp;
+	pe->pe_rrssi = MS(val, AR_PHY_RADAR_0_RRSSI);
+	pe->pe_height =  MS(val, AR_PHY_RADAR_0_HEIGHT);
+	pe->pe_prssi = MS(val, AR_PHY_RADAR_0_PRSSI);
+	pe->pe_inband = MS(val, AR_PHY_RADAR_0_INBAND);
+
+	val = OS_REG_READ(ah, AR_PHY_RADAR_1);
+	temp = val & AR_PHY_RADAR_1_RELPWR_ENA;
+	pe->pe_relpwr = MS(val, AR_PHY_RADAR_1_RELPWR_THRESH);
+	if (temp)
+		pe->pe_relpwr |= HAL_PHYERR_PARAM_ENABLE;
+	temp = val & AR_PHY_RADAR_1_RELSTEP_CHECK;
+	pe->pe_relstep = MS(val, AR_PHY_RADAR_1_RELSTEP_THRESH);
+	if (temp)
+		pe->pe_relstep |= HAL_PHYERR_PARAM_ENABLE;
+	pe->pe_maxlen = MS(val, AR_PHY_RADAR_1_MAXLEN);
+	pe->pe_extchannel = !! (OS_REG_READ(ah, AR_PHY_RADAR_EXT) &
+	    AR_PHY_RADAR_EXT_ENA);
+}
+
+/*
+ * Enable radar detection and set the radar parameters per the
+ * values in pe
+ */
+void
+ar5416EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
+{
+	uint32_t val;
+
+	val = OS_REG_READ(ah, AR_PHY_RADAR_0);
+
+	if (pe->pe_firpwr != HAL_PHYERR_PARAM_NOVAL) {
+		val &= ~AR_PHY_RADAR_0_FIRPWR;
+		val |= SM(pe->pe_firpwr, AR_PHY_RADAR_0_FIRPWR);
+	}
+	if (pe->pe_rrssi != HAL_PHYERR_PARAM_NOVAL) {
+		val &= ~AR_PHY_RADAR_0_RRSSI;
+		val |= SM(pe->pe_rrssi, AR_PHY_RADAR_0_RRSSI);
+	}
+	if (pe->pe_height != HAL_PHYERR_PARAM_NOVAL) {
+		val &= ~AR_PHY_RADAR_0_HEIGHT;
+		val |= SM(pe->pe_height, AR_PHY_RADAR_0_HEIGHT);
+	}
+	if (pe->pe_prssi != HAL_PHYERR_PARAM_NOVAL) {
+		val &= ~AR_PHY_RADAR_0_PRSSI;
+		val |= SM(pe->pe_prssi, AR_PHY_RADAR_0_PRSSI);
+	}
+	if (pe->pe_inband != HAL_PHYERR_PARAM_NOVAL) {
+		val &= ~AR_PHY_RADAR_0_INBAND;
+		val |= SM(pe->pe_inband, AR_PHY_RADAR_0_INBAND);
+	}
+
+	/*Enable FFT data*/
+	val |= AR_PHY_RADAR_0_FFT_ENA;
+
+	OS_REG_WRITE(ah, AR_PHY_RADAR_0, val | AR_PHY_RADAR_0_ENA);
+
+	val = OS_REG_READ(ah, AR_PHY_RADAR_1);
+	val |= (AR_PHY_RADAR_1_MAX_RRSSI | AR_PHY_RADAR_1_BLOCK_CHECK);
+
+	if (pe->pe_maxlen != HAL_PHYERR_PARAM_NOVAL) {
+		val &= ~AR_PHY_RADAR_1_MAXLEN;
+		val |= SM(pe->pe_maxlen, AR_PHY_RADAR_1_MAXLEN);
+	}
+	OS_REG_WRITE(ah, AR_PHY_RADAR_1, val);
+
+	/*
+	 * Enable HT/40 if the upper layer asks;
+	 * it should check the channel is HT/40 and HAL_CAP_EXT_CHAN_DFS
+	 * is available.
+	 */
+	if (pe->pe_extchannel)
+		OS_REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
+	else
+		OS_REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
+
+	if (pe->pe_relstep != HAL_PHYERR_PARAM_NOVAL) {
+		val = OS_REG_READ(ah, AR_PHY_RADAR_1);
+		val &= ~AR_PHY_RADAR_1_RELSTEP_THRESH;
+		val |= SM(pe->pe_relstep, AR_PHY_RADAR_1_RELSTEP_THRESH);
+		OS_REG_WRITE(ah, AR_PHY_RADAR_1, val);
+	}
+	if (pe->pe_relpwr != HAL_PHYERR_PARAM_NOVAL) {
+		val = OS_REG_READ(ah, AR_PHY_RADAR_1);
+		val &= ~AR_PHY_RADAR_1_RELPWR_THRESH;
+		val |= SM(pe->pe_relpwr, AR_PHY_RADAR_1_RELPWR_THRESH);
+		OS_REG_WRITE(ah, AR_PHY_RADAR_1, val);
+	}
+}
diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416phy.h b/sys/dev/ath/ath_hal/ar5416/ar5416phy.h
index 2c419d7..d7a5e0b 100644
--- a/sys/dev/ath/ath_hal/ar5416/ar5416phy.h
+++ b/sys/dev/ath/ath_hal/ar5416/ar5416phy.h
@@ -21,6 +21,25 @@
 
 #include "ar5212/ar5212phy.h"
 
+/* For AR_PHY_RADAR0 */
+#define	AR_PHY_RADAR_0_FFT_ENA		0x80000000
+
+#define	AR_PHY_RADAR_EXT		0x9940
+#define	AR_PHY_RADAR_EXT_ENA		0x00004000
+
+#define	AR_PHY_RADAR_1			0x9958
+#define	AR_PHY_RADAR_1_RELPWR_ENA	0x00800000
+#define	AR_PHY_RADAR_1_USE_FIR128	0x00400000
+#define	AR_PHY_RADAR_1_RELPWR_THRESH	0x003F0000
+#define	AR_PHY_RADAR_1_RELPWR_THRESH_S	16
+#define	AR_PHY_RADAR_1_BLOCK_CHECK	0x00008000
+#define	AR_PHY_RADAR_1_MAX_RRSSI	0x00004000
+#define	AR_PHY_RADAR_1_RELSTEP_CHECK	0x00002000
+#define	AR_PHY_RADAR_1_RELSTEP_THRESH	0x00001F00
+#define	AR_PHY_RADAR_1_RELSTEP_THRESH_S	8
+#define	AR_PHY_RADAR_1_MAXLEN		0x000000FF
+#define	AR_PHY_RADAR_1_MAXLEN_S		0
+
 #define AR_PHY_CHIP_ID_REV_0    0x80        /* 5416 Rev 0 (owl 1.0) BB */
 #define AR_PHY_CHIP_ID_REV_1    0x81        /* 5416 Rev 1 (owl 2.0) BB */
 
diff --git a/sys/dev/ath/ath_hal/ar9001/ar9130_attach.c b/sys/dev/ath/ath_hal/ar9001/ar9130_attach.c
index 49a5f5e..2a3f3f0 100644
--- a/sys/dev/ath/ath_hal/ar9001/ar9130_attach.c
+++ b/sys/dev/ath/ath_hal/ar9001/ar9130_attach.c
@@ -289,6 +289,7 @@ ar9130FillCapabilityInfo(struct ath_hal *ah)
 	pCap->halRifsTxSupport = AH_TRUE;
 	pCap->halRtsAggrLimit = 64*1024;	/* 802.11n max */
 	pCap->halExtChanDfsSupport = AH_TRUE;
+	pCap->halUseCombinedRadarRssi = AH_TRUE;
 	pCap->halAutoSleepSupport = AH_FALSE;	/* XXX? */
 	/*
 	 * MBSSID aggregation is broken in Howl v1.1, v1.2, v1.3
diff --git a/sys/dev/ath/ath_hal/ar9001/ar9160_attach.c b/sys/dev/ath/ath_hal/ar9001/ar9160_attach.c
index 0d950d2..44a549d 100644
--- a/sys/dev/ath/ath_hal/ar9001/ar9160_attach.c
+++ b/sys/dev/ath/ath_hal/ar9001/ar9160_attach.c
@@ -293,6 +293,7 @@ ar9160FillCapabilityInfo(struct ath_hal *ah)
 	pCap->halRifsTxSupport = AH_TRUE;
 	pCap->halRtsAggrLimit = 64*1024;	/* 802.11n max */
 	pCap->halExtChanDfsSupport = AH_TRUE;
+	pCap->halUseCombinedRadarRssi = AH_TRUE;
 	pCap->halAutoSleepSupport = AH_FALSE;	/* XXX? */
 	pCap->halMbssidAggrSupport = AH_TRUE;
 	pCap->hal4AddrAggrSupport = AH_TRUE;
diff --git a/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c b/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c
index 77b9f58..ebe3be1 100644
--- a/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c
+++ b/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c
@@ -783,6 +783,7 @@ ar9280FillCapabilityInfo(struct ath_hal *ah)
 	pCap->halRifsTxSupport = AH_TRUE;
 	pCap->halRtsAggrLimit = 64*1024;	/* 802.11n max */
 	pCap->halExtChanDfsSupport = AH_TRUE;
+	pCap->halUseCombinedRadarRssi = AH_TRUE;
 #if 0
 	/* XXX bluetooth */
 	pCap->halBtCoexSupport = AH_TRUE;
@@ -804,6 +805,7 @@ ar9280FillCapabilityInfo(struct ath_hal *ah)
 	}
 	pCap->halRxStbcSupport = 1;
 	pCap->halTxStbcSupport = 1;
+	pCap->halEnhancedDfsSupport = AH_TRUE;
 
 	return AH_TRUE;
 }
diff --git a/sys/dev/ath/ath_hal/ar9002/ar9285_attach.c b/sys/dev/ath/ath_hal/ar9002/ar9285_attach.c
index 111bea2..9120313 100644
--- a/sys/dev/ath/ath_hal/ar9002/ar9285_attach.c
+++ b/sys/dev/ath/ath_hal/ar9002/ar9285_attach.c
@@ -414,6 +414,7 @@ ar9285FillCapabilityInfo(struct ath_hal *ah)
 	pCap->halRifsTxSupport = AH_TRUE;
 	pCap->halRtsAggrLimit = 64*1024;	/* 802.11n max */
 	pCap->halExtChanDfsSupport = AH_TRUE;
+	pCap->halUseCombinedRadarRssi = AH_TRUE;
 #if 0
 	/* XXX bluetooth */
 	pCap->halBtCoexSupport = AH_TRUE;
diff --git a/sys/dev/ath/ath_hal/ar9002/ar9287_attach.c b/sys/dev/ath/ath_hal/ar9002/ar9287_attach.c
index fdf1f96..9cbe0a5 100644
--- a/sys/dev/ath/ath_hal/ar9002/ar9287_attach.c
+++ b/sys/dev/ath/ath_hal/ar9002/ar9287_attach.c
@@ -430,6 +430,7 @@ ar9287FillCapabilityInfo(struct ath_hal *ah)
 	pCap->halRifsTxSupport = AH_TRUE;
 	pCap->halRtsAggrLimit = 64*1024;	/* 802.11n max */
 	pCap->halExtChanDfsSupport = AH_TRUE;
+	pCap->halUseCombinedRadarRssi = AH_TRUE;
 #if 0
 	/* XXX bluetooth */
 	pCap->halBtCoexSupport = AH_TRUE;
@@ -447,6 +448,8 @@ ar9287FillCapabilityInfo(struct ath_hal *ah)
 	/* Hardware supports short-GI w/ 20MHz */
 	pCap->halHTSGI20Support = 1;
 
+	pCap->halEnhancedDfsSupport = AH_TRUE;
+
 	return AH_TRUE;
 }