Added CPU_DIRECT_MAPPED_CACHE option which sets L1 cache in direct

mapped mode on Cyrix 486DLC box.

5 files changed, 26 insertions, 5 deletions

diff --git a/sys/amd64/amd64/initcpu.c b/sys/amd64/amd64/initcpu.c
index c5e8a18..624c366 100644
--- a/sys/amd64/amd64/initcpu.c
+++ b/sys/amd64/amd64/initcpu.c
@@ -26,7 +26,7 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- *		$Id: initcpu.c,v 1.4 1997/04/26 04:08:45 kato Exp $
+ *		$Id: initcpu.c,v 1.5 1997/05/31 08:45:24 kato Exp $
  */
 
 #include "opt_cpu.h"
@@ -119,6 +119,9 @@ init_486dlc(void)
 #else
 	ccr0 |= CCR0_NC1;
 #endif
+#ifdef CPU_DIRECT_MAPPED_CACHE
+	ccr0 |= CCR0_CO;			/* Direct mapped mode. */
+#endif
 	write_cyrix_reg(CCR0, ccr0);
 
 	/* Clear non-cacheable region. */
diff --git a/sys/conf/NOTES b/sys/conf/NOTES
index 3d62526..5d1a2d9 100644
--- a/sys/conf/NOTES
+++ b/sys/conf/NOTES
@@ -2,7 +2,7 @@
 # LINT -- config file for checking all the sources, tries to pull in
 #	as much of the source tree as it can.
 #
-#	$Id: LINT,v 1.345 1997/06/17 05:58:15 kjc Exp $
+#	$Id: LINT,v 1.346 1997/06/22 16:02:55 peter Exp $
 #
 # NB: You probably don't want to try running a kernel built from this
 # file.  Instead, you should start from GENERIC, and add options from
@@ -138,6 +138,9 @@ cpu		"I686_CPU"		# aka Pentium Pro(tm)
 #
 # CPU_BTB_EN enables branch target buffer on Cyrix 5x86 (NOTE 1).
 #
+# CPU_DIRECT_MAPPED_CACHE sets L1 cache of Cyrix 486DLC CPU in direct
+# mapped mode.  Default is 2-way set associative mode.
+#
 # CPU_DISABLE_5X86_LSSER disables load store serialize (i.e. enables
 # reorder).  This option should not be used if you use memory mapped
 # I/O device(s). 
@@ -146,6 +149,7 @@ cpu		"I686_CPU"		# aka Pentium Pro(tm)
 #
 # CPU_I486_ON_386 enables CPU cache on i486 based CPU upgrade products
 # for i386 machines. 
+#
 # CPU_IORT defines I/O clock delay time (NOTE 1).  Default vaules of
 # I/O clock delay time on Cyrix 5x86 and 6x86 are 0 and 7,respectively
 # (no clock delay).
@@ -177,6 +181,7 @@ cpu		"I686_CPU"		# aka Pentium Pro(tm)
 options		"CPU_BLUELIGHTNING_FPU_OP_CACHE"
 options		"CPU_BLUELIGHTNING_3X"
 options		"CPU_BTB_EN"
+options		"CPU_DIRECT_MAPPED_CACHE"
 options		"CPU_DISABLE_5X86_LSSER"
 options		"CPU_FASTER_5X86_FPU"
 options		"CPU_I486_ON_386"
diff --git a/sys/i386/conf/LINT b/sys/i386/conf/LINT
index 3d62526..5d1a2d9 100644
--- a/sys/i386/conf/LINT
+++ b/sys/i386/conf/LINT
@@ -2,7 +2,7 @@
 # LINT -- config file for checking all the sources, tries to pull in
 #	as much of the source tree as it can.
 #
-#	$Id: LINT,v 1.345 1997/06/17 05:58:15 kjc Exp $
+#	$Id: LINT,v 1.346 1997/06/22 16:02:55 peter Exp $
 #
 # NB: You probably don't want to try running a kernel built from this
 # file.  Instead, you should start from GENERIC, and add options from
@@ -138,6 +138,9 @@ cpu		"I686_CPU"		# aka Pentium Pro(tm)
 #
 # CPU_BTB_EN enables branch target buffer on Cyrix 5x86 (NOTE 1).
 #
+# CPU_DIRECT_MAPPED_CACHE sets L1 cache of Cyrix 486DLC CPU in direct
+# mapped mode.  Default is 2-way set associative mode.
+#
 # CPU_DISABLE_5X86_LSSER disables load store serialize (i.e. enables
 # reorder).  This option should not be used if you use memory mapped
 # I/O device(s). 
@@ -146,6 +149,7 @@ cpu		"I686_CPU"		# aka Pentium Pro(tm)
 #
 # CPU_I486_ON_386 enables CPU cache on i486 based CPU upgrade products
 # for i386 machines. 
+#
 # CPU_IORT defines I/O clock delay time (NOTE 1).  Default vaules of
 # I/O clock delay time on Cyrix 5x86 and 6x86 are 0 and 7,respectively
 # (no clock delay).
@@ -177,6 +181,7 @@ cpu		"I686_CPU"		# aka Pentium Pro(tm)
 options		"CPU_BLUELIGHTNING_FPU_OP_CACHE"
 options		"CPU_BLUELIGHTNING_3X"
 options		"CPU_BTB_EN"
+options		"CPU_DIRECT_MAPPED_CACHE"
 options		"CPU_DISABLE_5X86_LSSER"
 options		"CPU_FASTER_5X86_FPU"
 options		"CPU_I486_ON_386"
diff --git a/sys/i386/conf/NOTES b/sys/i386/conf/NOTES
index 3d62526..5d1a2d9 100644
--- a/sys/i386/conf/NOTES
+++ b/sys/i386/conf/NOTES
@@ -2,7 +2,7 @@
 # LINT -- config file for checking all the sources, tries to pull in
 #	as much of the source tree as it can.
 #
-#	$Id: LINT,v 1.345 1997/06/17 05:58:15 kjc Exp $
+#	$Id: LINT,v 1.346 1997/06/22 16:02:55 peter Exp $
 #
 # NB: You probably don't want to try running a kernel built from this
 # file.  Instead, you should start from GENERIC, and add options from
@@ -138,6 +138,9 @@ cpu		"I686_CPU"		# aka Pentium Pro(tm)
 #
 # CPU_BTB_EN enables branch target buffer on Cyrix 5x86 (NOTE 1).
 #
+# CPU_DIRECT_MAPPED_CACHE sets L1 cache of Cyrix 486DLC CPU in direct
+# mapped mode.  Default is 2-way set associative mode.
+#
 # CPU_DISABLE_5X86_LSSER disables load store serialize (i.e. enables
 # reorder).  This option should not be used if you use memory mapped
 # I/O device(s). 
@@ -146,6 +149,7 @@ cpu		"I686_CPU"		# aka Pentium Pro(tm)
 #
 # CPU_I486_ON_386 enables CPU cache on i486 based CPU upgrade products
 # for i386 machines. 
+#
 # CPU_IORT defines I/O clock delay time (NOTE 1).  Default vaules of
 # I/O clock delay time on Cyrix 5x86 and 6x86 are 0 and 7,respectively
 # (no clock delay).
@@ -177,6 +181,7 @@ cpu		"I686_CPU"		# aka Pentium Pro(tm)
 options		"CPU_BLUELIGHTNING_FPU_OP_CACHE"
 options		"CPU_BLUELIGHTNING_3X"
 options		"CPU_BTB_EN"
+options		"CPU_DIRECT_MAPPED_CACHE"
 options		"CPU_DISABLE_5X86_LSSER"
 options		"CPU_FASTER_5X86_FPU"
 options		"CPU_I486_ON_386"
diff --git a/sys/i386/i386/initcpu.c b/sys/i386/i386/initcpu.c
index c5e8a18..624c366 100644
--- a/sys/i386/i386/initcpu.c
+++ b/sys/i386/i386/initcpu.c
@@ -26,7 +26,7 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- *		$Id: initcpu.c,v 1.4 1997/04/26 04:08:45 kato Exp $
+ *		$Id: initcpu.c,v 1.5 1997/05/31 08:45:24 kato Exp $
  */
 
 #include "opt_cpu.h"
@@ -119,6 +119,9 @@ init_486dlc(void)
 #else
 	ccr0 |= CCR0_NC1;
 #endif
+#ifdef CPU_DIRECT_MAPPED_CACHE
+	ccr0 |= CCR0_CO;			/* Direct mapped mode. */
+#endif
 	write_cyrix_reg(CCR0, ccr0);
 
 	/* Clear non-cacheable region. */