diff options
| author | tmm <tmm@FreeBSD.org> | 2002-03-11 03:04:28 +0000 |
|---|---|---|
| committer | tmm <tmm@FreeBSD.org> | 2002-03-11 03:04:28 +0000 |
| commit | aababfffd53cac2ef2f52367c14698f6e5710fd9 (patch) | |
| tree | 4414e278c4cd797a419863462dfbe3a2a017d951 /sys | |
| parent | 4667cf8132c0234b67f21d702b03eb7c79fc38ae (diff) | |
| download | FreeBSD-src-aababfffd53cac2ef2f52367c14698f6e5710fd9.zip FreeBSD-src-aababfffd53cac2ef2f52367c14698f6e5710fd9.tar.gz | |
Fix the type of some constants, and make some macros safer by casting
the argument.
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/sparc64/include/fsr.h | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/sys/sparc64/include/fsr.h b/sys/sparc64/include/fsr.h index 1a713b4..bac37d6 100644 --- a/sys/sparc64/include/fsr.h +++ b/sys/sparc64/include/fsr.h @@ -32,49 +32,49 @@ #define FPRS_FEF (1 << 2) #define FSR_EXC_BITS 5 -#define FSR_EXC_MASK ((1 << FSR_EXC_BITS) - 1) +#define FSR_EXC_MASK ((1UL << FSR_EXC_BITS) - 1) #define FSR_CEXC_SHIFT 0 #define FSR_CEXC_MASK (FSR_EXC_MASK << FSR_CEXC_SHIFT) -#define FSR_CEXC(b) ((b) << FSR_CEXC_SHIFT) +#define FSR_CEXC(b) ((u_long)(b) << FSR_CEXC_SHIFT) #define FSR_AEXC_SHIFT 5 #define FSR_AEXC_MASK (FSR_EXC_MASK << FSR_AEXC_SHIFT) -#define FSR_AEXC(b) ((b) << FSR_AEXC_SHIFT) -#define FSR_QNE (1 << 13) -#define FSR_NS (1 << 22) +#define FSR_AEXC(b) ((u_long)(b) << FSR_AEXC_SHIFT) +#define FSR_QNE (1UL << 13) +#define FSR_NS (1UL << 22) #define FSR_TEM_SHIFT 23 #define FSR_TEM_MASK (FSR_EXC_MASK << FSR_TEM_SHIFT) -#define FSR_TEM(b) ((b) << FSR_TEM_SHIFT) +#define FSR_TEM(b) ((u_long)(b) << FSR_TEM_SHIFT) #define FSR_FCC0_SHIFT 10 #define FSR_FCC0_BITS 2 -#define FSR_FCC0_MASK (((1 << FSR_FCC0_BITS) - 1) << FSR_FCC0_SHIFT) -#define FSR_FCC0(x) ((x) << FSR_FCC0_SHIFT) +#define FSR_FCC0_MASK (((1UL << FSR_FCC0_BITS) - 1) << FSR_FCC0_SHIFT) +#define FSR_FCC0(x) ((u_long)(x) << FSR_FCC0_SHIFT) #define FSR_GET_FCC0(x) (((x) >> FSR_FCC0_SHIFT) & 3) #define FSR_FTT_SHIFT 14 #define FSR_FTT_BITS 3 -#define FSR_FTT_MASK (((1 << FSR_FTT_BITS) - 1) << FSR_FTT_SHIFT) -#define FSR_FTT(x) ((x) << FSR_FTT_SHIFT) +#define FSR_FTT_MASK (((1UL << FSR_FTT_BITS) - 1) << FSR_FTT_SHIFT) +#define FSR_FTT(x) ((u_long)(x) << FSR_FTT_SHIFT) #define FSR_GET_FTT(x) (((x) & FSR_FTT_MASK) >> FSR_FTT_SHIFT) #define FSR_VER_SHIFT 17 #define FSR_GET_VER(x) (((x) >> FSR_VER_SHIFT) & 7) #define FSR_RD_SHIFT 30 #define FSR_RD_BITS 2 -#define FSR_RD_MASK (((1 << FSR_RD_BITS) - 1) << FSR_RD_SHIFT) -#define FSR_RD(x) ((x) << FSR_RD_SHIFT) +#define FSR_RD_MASK (((1UL << FSR_RD_BITS) - 1) << FSR_RD_SHIFT) +#define FSR_RD(x) ((u_long)(x) << FSR_RD_SHIFT) #define FSR_GET_RD(x) (((x) >> FSR_RD_SHIFT) & 3) #define FSR_FCC1_SHIFT 32 #define FSR_FCC1_BITS 2 -#define FSR_FCC1_MASK (((1 << FSR_FCC1_BITS) - 1) << FSR_FCC1_SHIFT) -#define FSR_FCC1(x) ((x) << FSR_FCC1_SHIFT) +#define FSR_FCC1_MASK (((1UL << FSR_FCC1_BITS) - 1) << FSR_FCC1_SHIFT) +#define FSR_FCC1(x) ((u_long)(x) << FSR_FCC1_SHIFT) #define FSR_GET_FCC1(x) (((x) >> FSR_FCC1_SHIFT) & 3) #define FSR_FCC2_SHIFT 34 #define FSR_FCC2_BITS 2 -#define FSR_FCC2_MASK (((1 << FSR_FCC2_BITS) - 1) << FSR_FCC2_SHIFT) -#define FSR_FCC2(x) ((x) << FSR_FCC2_SHIFT) +#define FSR_FCC2_MASK (((1UL << FSR_FCC2_BITS) - 1) << FSR_FCC2_SHIFT) +#define FSR_FCC2(x) ((u_long)(x) << FSR_FCC2_SHIFT) #define FSR_GET_FCC2(x) (((x) >> FSR_FCC2_SHIFT) & 3) #define FSR_FCC3_SHIFT 36 #define FSR_FCC3_BITS 2 -#define FSR_FCC3_MASK (((1 << FSR_FCC3_BITS) - 1) << FSR_FCC3_SHIFT) -#define FSR_FCC3(x) ((x) << FSR_FCC3_SHIFT) +#define FSR_FCC3_MASK (((1UL << FSR_FCC3_BITS) - 1) << FSR_FCC3_SHIFT) +#define FSR_FCC3(x) ((u_long)(x) << FSR_FCC3_SHIFT) #define FSR_GET_FCC3(x) (((x) >> FSR_FCC3_SHIFT) & 3) /* CEXC/AEXC/TEM exception values */ |
