Switch some PCI register reads from using magic numbers to using the names

defined in pcireg.h

MFC after:	1 week

5 files changed, 11 insertions, 11 deletions

diff --git a/sys/dev/ahci/ahci.c b/sys/dev/ahci/ahci.c
index d661416..4a3c355 100644
--- a/sys/dev/ahci/ahci.c
+++ b/sys/dev/ahci/ahci.c
@@ -543,7 +543,7 @@ ahci_ctlr_reset(device_t dev)
 	struct ahci_controller *ctlr = device_get_softc(dev);
 	int timeout;
 
-	if (pci_read_config(dev, 0x00, 4) == 0x28298086 &&
+	if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == 0x28298086 &&
 	    (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04)
 		pci_write_config(dev, 0x92, 0x01, 1);
 	/* Enable AHCI mode */
diff --git a/sys/dev/alc/if_alc.c b/sys/dev/alc/if_alc.c
index 2a0ddb2..9fa29b8 100644
--- a/sys/dev/alc/if_alc.c
+++ b/sys/dev/alc/if_alc.c
@@ -694,10 +694,10 @@ alc_aspm(struct alc_softc *sc, int media)
 
 	if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
 		/* Disable extended sync except AR8152 B v1.0 */
-		linkcfg &= ~0x80;
+		linkcfg &= ~PCIEM_LINK_CTL_EXTENDED_SYNC;
 		if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B &&
 		    sc->alc_rev == ATHEROS_AR8152_B_V10)
-			linkcfg |= 0x80;
+			linkcfg |= PCIEM_LINK_CTL_EXTENDED_SYNC;
 		CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL,
 		    linkcfg);
 		pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB |
@@ -834,15 +834,15 @@ alc_attach(device_t dev)
 		cap = CSR_READ_2(sc, base + PCIER_LINK_CAP);
 		if ((cap & PCIEM_LINK_CAP_ASPM) != 0) {
 			ctl = CSR_READ_2(sc, base + PCIER_LINK_CTL);
-			if ((ctl & 0x08) != 0)
+			if ((ctl & PCIEM_LINK_CTL_RCB) != 0)
 				sc->alc_rcb = DMA_CFG_RCB_128;
 			if (bootverbose)
 				device_printf(dev, "RCB %u bytes\n",
 				    sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128);
-			state = ctl & 0x03;
-			if (state & 0x01)
+			state = ctl & PCIEM_LINK_CTL_ASPMC;
+			if (state & PCIEM_LINK_CTL_ASPMC_L0S)
 				sc->alc_flags |= ALC_FLAG_L0S;
-			if (state & 0x02)
+			if (state & PCIEM_LINK_CTL_ASPMC_L1)
 				sc->alc_flags |= ALC_FLAG_L1S;
 			if (bootverbose)
 				device_printf(sc->alc_dev, "ASPM %s %s\n",
diff --git a/sys/dev/cxgbe/osdep.h b/sys/dev/cxgbe/osdep.h
index a8c68c2..87d683f 100644
--- a/sys/dev/cxgbe/osdep.h
+++ b/sys/dev/cxgbe/osdep.h
@@ -125,7 +125,7 @@ typedef boolean_t bool;
 #define PCI_EXP_LNKSTA		PCIER_LINK_STA
 #define PCI_EXP_LNKSTA_CLS	PCIEM_LINK_STA_SPEED
 #define PCI_EXP_LNKSTA_NLW	PCIEM_LINK_STA_WIDTH
-#define PCI_EXP_DEVCTL2		0x28
+#define PCI_EXP_DEVCTL2		PCIER_DEVICE_CTL2
 
 static inline int
 ilog2(long x)
diff --git a/sys/dev/e1000/if_em.c b/sys/dev/e1000/if_em.c
index a4f43e7..60e6708 100644
--- a/sys/dev/e1000/if_em.c
+++ b/sys/dev/e1000/if_em.c
@@ -5119,7 +5119,7 @@ em_disable_aspm(struct adapter *adapter)
 		return;
 	reg = base + PCIER_LINK_CTL;
 	link_ctrl = pci_read_config(dev, reg, 2);
-	link_ctrl &= 0xFFFC; /* turn off bit 1 and 2 */
+	link_ctrl &= ~PCIEM_LINK_CTL_ASPMC;
 	pci_write_config(dev, reg, link_ctrl, 2);
 	return;
 }
diff --git a/sys/dev/re/if_re.c b/sys/dev/re/if_re.c
index 0067310..82f56c3 100644
--- a/sys/dev/re/if_re.c
+++ b/sys/dev/re/if_re.c
@@ -1347,8 +1347,8 @@ re_attach(device_t dev)
 		if ((cap & PCIEM_LINK_CAP_ASPM) != 0) {
 			ctl = pci_read_config(dev, sc->rl_expcap +
 			    PCIER_LINK_CTL, 2);
-			if ((ctl & 0x0003) != 0) {
-				ctl &= ~0x0003;
+			if ((ctl & PCIEM_LINK_CTL_ASPMC) != 0) {
+				ctl &= ~PCIEM_LINK_CTL_ASPMC;
 				pci_write_config(dev, sc->rl_expcap +
 				    PCIER_LINK_CTL, ctl, 2);
 				device_printf(dev, "ASPM disabled\n");