Remove this abortive attempt.

3 files changed, 0 insertions, 526 deletions

diff --git a/sys/conf/files b/sys/conf/files
index 710f215..0d5be0d 100644
--- a/sys/conf/files
+++ b/sys/conf/files
@@ -526,7 +526,6 @@ dev/ray/if_ray.c	optional ray pccard
 dev/rp/rp.c		optional rp
 dev/rp/rp_isa.c		optional rp isa
 dev/rp/rp_pci.c		optional rp pci
-dev/se/se_console.c	optional se ebus
 dev/si/si.c		optional si
 dev/si/si2_z280.c	optional si
 dev/si/si3_t225.c	optional si
diff --git a/sys/dev/se/se_console.c b/sys/dev/se/se_console.c
deleted file mode 100644
index e1bb299..0000000
--- a/sys/dev/se/se_console.c
+++ /dev/null
@@ -1,320 +0,0 @@
-/*-
- * Copyright (c) 2002 Jake Burkholder.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-#include <sys/param.h>
-#include <sys/kernel.h>
-#include <sys/systm.h>
-#include <sys/bus.h>
-#include <sys/types.h>
-#include <sys/conf.h>
-#include <sys/cons.h>
-#include <sys/consio.h>
-#include <sys/reboot.h>
-#include <machine/bus.h>
-#include <sys/rman.h>
-#include <sys/tty.h>
-#include <sys/ktr.h>
-
-#ifdef __sparc64__
-
-#include <ofw/openfirm.h>
-#include <ofw/ofw_pci.h>
-
-#include <machine/ofw_upa.h>
-#include <machine/resource.h>
-
-#include <sparc64/pci/ofw_pci.h>
-#include <sparc64/isa/ofw_isa.h>
-#include <sparc64/ebus/ebusvar.h>
-
-#include <dev/se/sereg.h>
-
-#define	SE_CNREAD_1(off) \
-	bus_space_read_1(&se_cntag, se_cnhandle, se_cnchan + (off))
-#define	SE_CNWRITE_1(off, val) \
-	bus_space_write_1(&se_cntag, se_cnhandle, se_cnchan + (off), (val))
-
-#define	SE_CONSOLE(flags)	((flags) & 0x10)
-#define	SE_FORCECONSOLE(flags)	((flags) & 0x20)
-
-#define	SE_CHANNELS	2
-
-#define	KTR_SE	KTR_CT4
-
-#define	CDEV_MAJOR	168
-
-static	cn_probe_t	se_cnprobe;
-static	cn_init_t	se_cninit;
-static	cn_getc_t	se_cngetc;
-static	cn_checkc_t	se_cncheckc;
-static	cn_putc_t	se_cnputc;
-
-static	void se_cnregdump(void);
-
-static	u_char se_cnchan;
-static	struct bus_space_tag se_cntag;
-static	bus_space_handle_t se_cnhandle;
-
-CONS_DRIVER(se, se_cnprobe, se_cninit, NULL, se_cngetc, se_cncheckc,
-	    se_cnputc, NULL);
-
-static int
-OF_traverse(phandle_t root, phandle_t *node,
-    int (*func)(phandle_t, phandle_t *))
-{
-	phandle_t child;
-
-	for (child = OF_child(root); child != 0; child = OF_peer(child)) {
-		if (func(child, node) == 0 ||
-		    OF_traverse(child, node, func) == 0)
-			return (0);
-	}
-	return (-1);
-}
-
-static int
-se_cnfind(phandle_t child, phandle_t *node)
-{
-	char name[8];
-
-	if (OF_getprop(child, "name", name, sizeof(name)) != -1 &&
-	    strncmp(name, "se", sizeof(name)) == 0) {
-		*node = child;
-		return (0);
-	}
-	return (-1);
-}
-
-static int
-se_cnmap(phandle_t node, phandle_t parent)
-{
-	struct isa_ranges ir[4];
-	struct upa_ranges ur[4];
-	struct isa_regs reg;
-	vm_offset_t child;
-	vm_offset_t dummy;
-	vm_offset_t phys;
-	phandle_t pbus;
-	phandle_t bus;
-	char name[32];
-	int error;
-	int type;
-	int rsz;
-	int bs;
-	int cs;
-	int i;
-
-	if (OF_getprop(node, "reg", &reg, sizeof(reg)) == -1 ||
-	    (rsz = OF_getprop(parent, "ranges", ir, sizeof(ir))) == -1) {
-		return (ENXIO);
-	}
-	phys = ISA_REG_PHYS(&reg);
-	dummy = phys + 8;
-	type = ofw_isa_map_iorange(ir, rsz / sizeof(*ir), &phys, &dummy);
-	if (type == SYS_RES_MEMORY) {
-		cs = PCI_CS_MEM32;
-		bs = PCI_MEMORY_BUS_SPACE;
-	} else {
-		cs = PCI_CS_IO;
-		bs = PCI_IO_BUS_SPACE;
-	}
-	bus = OF_parent(parent);
-	if (OF_getprop(bus, "name", name, sizeof(name)) == -1)
-		return (ENXIO);
-	name[sizeof(name) - 1] = '\0';
-	if (strcmp(name, "pci") != 0)
-		return (ENXIO);
-	while ((pbus = OF_parent(bus)) != 0) {
-		if (OF_getprop(pbus, "name", name, sizeof(name)) != -1) {
-			name[sizeof(name) - 1] = '\0';
-			if (strcmp(name, "pci") != 0)
-				break;
-		}
-		bus = pbus;
-	}
-	if (pbus == 0)
-		return (ENXIO);
-	if ((rsz = OF_getprop(bus, "ranges", ur, sizeof(ur))) == -1)
-		return (ENXIO);
-	error = ENXIO;
-	for (i = 0; i < (rsz / sizeof(ur[0])); i++) {
-		child = UPA_RANGE_CHILD(&ur[i]);
-		if (UPA_RANGE_CS(&ur[i]) == cs && phys >= child &&
-		    phys - child < UPA_RANGE_SIZE(&ur[i])) {
-			se_cnhandle = sparc64_fake_bustag(bs,
-			    UPA_RANGE_PHYS(&ur[i]) + phys, &se_cntag);
-			error = 0;
-			break;
-		}
-	}
-	return (error);
-}
-
-static void
-se_cnprobe(struct consdev *cn)
-{
-	phandle_t parent;
-	phandle_t node;
-	phandle_t root;
-	char name[8];
-	int channel;
-	int disabled;
-	int flags;
-
-	disabled = 0;
-	cn->cn_pri = CN_DEAD;
-	if ((root = OF_peer(0)) == -1 ||
-	    OF_traverse(root, &node, se_cnfind) == -1)
-		return;
-	for (channel = 0; channel < SE_CHANNELS; channel++) {
-		if (resource_int_value("se", channel, "disabled",
-		    &disabled) != 0) {
-			disabled = 0;
-		}
-		if (resource_int_value("se", channel, "flags", &flags) == 0) {
-			if (!disabled && SE_CONSOLE(flags))
-				goto map;
-		}
-	}
-	return;
-
-map:
-	if ((parent = OF_parent(node)) <= 0 ||
-	    OF_getprop(parent, "name", name, sizeof(name)) <= 0)
-		return;
-	if (strncmp(name, "ebus", sizeof(name)) != 0)
-		return;
-	if (se_cnmap(node, parent) != 0)
-		return;
-	se_cnchan = (channel == 0 ? SE_CHA : SE_CHB);
-
-	cn->cn_dev = makedev(CDEV_MAJOR, channel);
-	cn->cn_pri = SE_FORCECONSOLE(flags) || boothowto & RB_SERIAL ?
-	    CN_REMOTE : CN_NORMAL;
-}
-
-static void
-se_cninit(struct consdev *cn)
-{
-	u_char ccr0;
-
-	/*
-	 * Power down the chip for initialization.
-	 */
-	SE_CNWRITE_1(SE_CCR0, 0x0);
-
-	/*
-	 * Now program the chip for polled asynchronous serial io.
-	 */
-	SE_CNWRITE_1(SE_CCR0, CCR0_MCE | CCR0_SM_ASYNC);
-	SE_CNWRITE_1(SE_CMDR, CMDR_RRES | CMDR_XRES);
-	SE_CNWRITE_1(SE_CCR1, CCR1_ODS | CCR1_BCR | CCR1_CM_7);
-	SE_CNWRITE_1(SE_BGR, SE_DIV_9600);
-	SE_CNWRITE_1(SE_CCR2, CCR2_TOE | CCR2_SSEL | CCR2_BDF);
-	SE_CNWRITE_1(SE_CCR3, 0x0);
-	SE_CNWRITE_1(SE_CCR4, CCR4_EBRG | CCR4_MCK4);
-	SE_CNWRITE_1(SE_MODE, MODE_FCTS | MODE_RAC | MODE_RTS);
-	SE_CNWRITE_1(SE_DAFO, DAFO_CHL_8);
-	SE_CNWRITE_1(SE_RFC, RFC_DPS | RFC_RFTH_32);
-	SE_CNWRITE_1(SE_IPC, IPC_VIS);
-
-	/*
-	 * Now power up the chip again.
-	 */
-	ccr0 = SE_CNREAD_1(SE_CCR0);
-	ccr0 |= CCR0_PU;
-	SE_CNWRITE_1(SE_CCR0, ccr0);
-
-	SE_CNWRITE_1(SE_CMDR, CMDR_RRES | CMDR_XRES);
-}
-
-static int
-se_cngetc(dev_t dev)
-{
-	u_char c;
-
-	while ((SE_CNREAD_1(SE_STAR) & (STAR_CEC | STAR_RFNE)) != STAR_RFNE)
-		;
-	SE_CNWRITE_1(SE_CMDR, CMDR_RFRD);
-	while ((SE_CNREAD_1(SE_ISR0) & ISR0_TCD) == 0)
-		;
-	c = SE_CNREAD_1(SE_RFIFO);
-	SE_CNWRITE_1(SE_CMDR, CMDR_RMC);
-	return (c);
-}
-
-static int
-se_cncheckc(dev_t dev)
-{
-	u_char c;
-
-	if ((SE_CNREAD_1(SE_STAR) & STAR_RFNE) != 0) {
-		while ((SE_CNREAD_1(SE_STAR) & STAR_CEC) != 0)
-			;
-		SE_CNWRITE_1(SE_CMDR, CMDR_RFRD);
-		while ((SE_CNREAD_1(SE_ISR0) & ISR0_TCD) == 0)
-			;
-		c = SE_CNREAD_1(SE_RFIFO);
-		SE_CNWRITE_1(SE_CMDR, CMDR_RMC);
-		return (c);
-	}
-	return (-1);
-}
-
-static void
-se_cnputc(dev_t dev, int c)
-{
-
-	while ((SE_CNREAD_1(SE_STAR) & (STAR_CTS | STAR_CEC | STAR_XFW)) !=
-	    (STAR_CTS | STAR_XFW))
-		;
-	SE_CNWRITE_1(SE_XFIFO, c);
-	SE_CNWRITE_1(SE_CMDR, CMDR_XF);
-}
-
-static void
-se_cnregdump(void)
-{
-
-	CTR1(KTR_SE, "se_cnprobe: mode=%#x", SE_CNREAD_1(SE_MODE));
-	CTR1(KTR_SE, "se_cnprobe: timr=%#x", SE_CNREAD_1(SE_TIMR));
-	CTR1(KTR_SE, "se_cnprobe: xon=%#x", SE_CNREAD_1(SE_XON));
-	CTR1(KTR_SE, "se_cnprobe: xoff=%#x", SE_CNREAD_1(SE_XOFF));
-	CTR1(KTR_SE, "se_cnprobe: tcr=%#x", SE_CNREAD_1(SE_TCR));
-	CTR1(KTR_SE, "se_cnprobe: dafo=%#x", SE_CNREAD_1(SE_DAFO));
-	CTR1(KTR_SE, "se_cnprobe: rfc=%#x", SE_CNREAD_1(SE_RFC));
-	CTR1(KTR_SE, "se_cnprobe: ccr0=%#x", SE_CNREAD_1(SE_CCR0));
-	CTR1(KTR_SE, "se_cnprobe: ccr1=%#x", SE_CNREAD_1(SE_CCR1));
-	CTR1(KTR_SE, "se_cnprobe: ccr2=%#x", SE_CNREAD_1(SE_CCR2));
-	CTR1(KTR_SE, "se_cnprobe: ccr3=%#x", SE_CNREAD_1(SE_CCR3));
-	CTR1(KTR_SE, "se_cnprobe: vstr=%#x", SE_CNREAD_1(SE_VSTR));
-	CTR1(KTR_SE, "se_cnprobe: ipc=%#x", SE_CNREAD_1(SE_IPC));
-	CTR1(KTR_SE, "se_cnprobe: ccr4=%#x", SE_CNREAD_1(SE_CCR4));
-}
-
-#endif
diff --git a/sys/dev/se/sereg.h b/sys/dev/se/sereg.h
deleted file mode 100644
index f826bd4..0000000
--- a/sys/dev/se/sereg.h
+++ /dev/null
@@ -1,205 +0,0 @@
-/*-
- * Copyright (c) 2002 Jake Burkholder.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-#ifndef _DEV_SE_SEREG_H_
-#define	_DEV_SE_SEREG_H_
-
-#define	SE_DIV(n, m)	(((m) << 6) | ((n) - 1))
-#define	SE_DIV_9600	SE_DIV(48, 2)
-#define	SE_DIV_19200	SE_DIV(48, 1)
-#define	SE_DIV_38400	SE_DIV(24, 1)
-#define	SE_DIV_115200	SE_DIV(8, 1)
-
-#define	SE_CHA		0x0	/* channel a offset */
-#define	SE_CHB		0x40	/* channel b offset */
-
-#define	SE_RFIFO	0x0	/* receive fifo */
-#define	SE_XFIFO	0x0	/* transmit fifo */
-
-#define	SE_STAR		0x20	/* status register */
-#define	STAR_CTS	0x2	/*  clear to send state */
-#define	STAR_CEC	0x4	/*  command executing */
-#define	STAR_TEC	0x8	/*  tic executing */
-#define	STAR_FCS	0x10	/*  flow control status */
-#define	STAR_RFNE	0x20	/*  receive fifo not empty */
-#define	STAR_XFW	0x40	/*  transmit fifo write enable */
-#define	STAR_XDOV	0x80	/*  transmit data overflow */
-
-#define	SE_CMDR		0x20	/* command register */
-#define	CMDR_XRES	0x1	/*  transmitter reset */
-#define	CMDR_XF		0x8	/*  transmit frame */
-#define	CMDR_STI	0x10	/*  start timer */
-#define	CMDR_RFRD	0x20	/*  receive fifo read enable */
-#define	CMDR_RRES	0x40	/*  reveiver reset */
-#define	CMDR_RMC	0x80	/*  receive message complete */
-
-#define	SE_MODE		0x22	/* mode register */
-#define	MODE_TLP	0x1	/*  test loop */
-#define	MODE_TRS	0x2	/*  timer resolution */
-#define	MODE_RTS	0x4	/*  request to send */
-#define	MODE_RAC	0x8	/*  receiver active */
-#define	MODE_FLON	0x10	/*  flow control on */
-#define	MODE_FCTS	0x20	/*  flow control using cts */
-#define	MODE_FRTS	0x40	/*  flow control using rts */
-
-#define	SE_TIMR		0x23	/* timer register */
-#define	SE_XON		0x24	/* xon character */
-#define	SE_XOFF		0x25	/* xoff character */
-#define	SE_TCR		0x26	/* transmit character register */
-
-#define	SE_DAFO		0x27	/* data format */
-#define	DAFO_CHL	0x2	/*  character length */
-#define	DAFO_CHL_8	0x0	/*   8 bits */
-#define	DAFO_CHL_7	0x1	/*   7 bits */
-#define	DAFO_CHL_6	0x2	/*   6 bits */
-#define	DAFO_CHL_5	0x3	/*   5 bits */
-#define	DAFO_PARE	0x4	/*  parity enable */
-#define	DAFO_PAR	0x18	/*  parity format */
-#define	DAFO_STOP	0x20	/*  stop bit */
-#define	DAFO_XBRK	0x40	/*  transmit break */
-
-#define	SE_RFC		0x28	/* rfifo control register */
-#define	RFC_TCDE	0x1	/*  termination character detection enable */
-#define	RFC_RFTH	0xc	/*  rfifo threshold level */
-#define	RFC_RFTH_2	0x0	/*   2 bytes */
-#define	RFC_RFTH_4	0x4	/*   4 bytes */
-#define	RFC_RFTH_16	0x8	/*   16 bytes */
-#define	RFC_RFTH_32	0xc	/*   32 bytes */
-#define	RFC_RFDF	0x10	/*  rfifo data format */
-#define	RFC_DXS		0x20	/*  disable storage of xon/xoff characters */
-#define	RFC_DPS		0x40	/*  disable parity storage */
-
-#define	SE_RBCL		0x2a	/* receive byte count low */
-#define	SE_XBCL		0x2a	/* transmit byte count low */
-#define	SE_RBCH		0x2b	/* receive byte count high */
-#define	SE_XBCH		0x2b	/* transmit byte count high */
-
-#define	SE_CCR0		0x2c	/* channel configuration register 0 */
-#define	CCR0_SM		0x3	/*  serial mode */
-#define	CCR0_SM_HDLC	0x0	/*   hdlc/sdlc mode */
-#define	CCR0_SM_SDLC	0x1	/*   sdlc loop mode */
-#define	CCR0_SM_BISYNC	0x2	/*   bisync mode */
-#define	CCR0_SM_ASYNC	0x3	/*   async mode */
-#define	CCR0_SC		0x1c	/*  serial configuration */
-#define	CCR0_SC_NRZ	0x0	/*   nrz data encoding */
-#define	CCR0_SC_NRZI	0x2	/*   nrzi data encoding */
-#define	CCR0_SC_FM0	0x4	/*   fm0 data encoding */
-#define	CCR0_SC_FM1	0x5	/*   fm1 data encoding */
-#define	CCR0_SC_MCHSTR	0x6	/*   manchester data encoding */
-#define	CCR0_MCE	0x40	/*  master clock enable */
-#define	CCR0_PU		0x80	/*  power up */
-
-#define	SE_CCR1		0x2d	/* channel configuration register 1 */
-#define	CCR1_CM		0x7	/*  clock mode */
-#define	CCR1_CM_7	0x7	/*   clock mode 7 */
-#define	CCR1_BCR	0x8	/*  bit clock rate */
-#define	CCR1_ODS	0x10	/*  output driver select */
-
-#define	SE_CCR2		0x2e	/* channel configuration register 2 */
-#define	CCR2_DIV	0x1	/*  data inversion */
-#define	CCR2_RWX	0x4	/*  read/write exchange */
-#define	CCR2_TOE	0x8	/*  txclk ouput enable */
-#define	CCR2_SSEL	0x10	/*  clock source select */
-#define	CCR2_BDF	0x20	/*  baud rate division factor */
-#define	CCR2_BR8	0x40	/*  baud rate 8 */
-#define	CCR2_BR9	0x80	/*  baud rate 9 */
-#define	CCR2_RCS0	0x10	/*  receive clock shift 0 (5) */
-#define	CCR2_XCS0	0x20	/*  transmit clock shift 0 (5) */
-#define	CCR2_SOC0	0x40	/*  special output control 0 (0a, 1, 4, 5) */
-#define	CCR2_SOC1	0x80	/*  special output control 1 (0a, 1, 4, 5) */
-
-#define	SE_CCR3		0x2f	/* channel configuration register 3 */
-#define	CCR3_PSD	0x1	/*  dpll phase shift disable */
-
-#define	SE_TSAX		0x30	/* transmit timeslot assignment register */
-#define	SE_TSAR		0x31	/* receive timeslot assignment register */
-#define	SE_XCCR		0x32	/* transmit channel capacity register */
-#define	SE_RCCR		0x33	/* receive channel capacity register */
-
-#define	SE_VSTR		0x34	/* version status register */
-#define	VSTR_VN		0xf	/*  version number 0 */
-#define	VSTR_DPLA	0x40	/*  dpll asynchronous */
-#define	VSTR_CD		0x80	/*  carrier detect */
-
-#define	SE_BGR		0x34	/* baud rate generator register */
-#define	SE_TIC		0x35	/* trasmit immediate character */
-#define	SE_MXN		0x36	/* mask xon character */
-#define	SE_MXF		0x37	/* mask xoff character */
-
-#define	SE_GIS		0x38	/* global interrupt status */
-#define	GIS_ISB0	0x1	/*  interrupt status channel B 0 */
-#define	GIS_ISB1	0x2	/*  interrupt status channel B 1 */
-#define	GIS_ISA0	0x4	/*  interrupt status channel A 0 */
-#define	GIS_ISA1	0x8	/*  interrupt status channel A 1 */
-#define	GIS_PI		0x80	/*  univerisal port interrupt */
-
-#define	SE_IVA		0x38	/* interrupt vector address */
-
-#define	SE_IPC		0x39	/* interrupt port configuration */
-#define	IPC_IC0		0x1	/*  interrupt configuration 0 */
-#define	IPC_IC1		0x2	/*  interrupt configuration 1 */
-#define	IPC_CASM	0x4	/*  cascading mode */
-#define	IPC_SLA0	0x8	/*  slave address 0 */
-#define	IPC_SLA1	0x10	/*  slave address 1 */
-#define	IPC_VIS		0x80	/*  masked interrupts visible */
-
-#define	SE_ISR0		0x3a	/* interrupt status 0 */
-#define	ISR0_RPF	0x1	/*  receive pool full */
-#define	ISR0_RFO	0x2	/*  receive frame overflow */
-#define	ISR0_CDSC	0x4	/*  carrier detect status change */
-#define	ISR0_PLLA	0x8	/*  dpll asynchronous */
-#define	ISR0_FERR	0x10	/*  framing error */
-#define	ISR0_PERR	0x20	/*  parity error */
-#define	ISR0_TIME	0x40	/*  time out */
-#define	ISR0_TCD	0x80	/*  termination character detected */
-
-#define	SE_IMR0		0x3a	/* interrupt mask 0 */
-
-#define	SE_ISR1		0x3b	/* interrupt status 1 */
-#define	ISR1_XPR	0x1	/*  transmit pool ready */
-#define	ISR1_XON	0x2	/*  transmit message repeat */
-#define	ISR1_CSC	0x4	/*  clear to send status change */
-#define	ISR1_TIN	0x8	/*  timer interrupt */
-#define	ISR1_XOFF	0x10	/*  xoff character detected */
-#define	ISR1_ALLS	0x20	/*  all sent */
-#define	ISR1_BRKT	0x40	/*  break terminated */
-#define	ISR1_BRK	0x80	/*  break */
-
-#define	SE_IMR1		0x3b	/* interrupt mask 1 */
-#define	SE_PVR		0x3c	/* port value register */
-#define	SE_PIS		0x3d	/* port interrupt status */
-#define	SE_PIM		0x3d	/* port interrupt mask */
-#define	SE_PCR		0x3e	/* port configuration register */
-
-#define	SE_CCR4		0x3f	/* channel configuration register 4 */
-#define	CCR4_ICD	0x10	/*  invert polarity of carrier detect signal */
-#define	CCR4_TST1	0x20	/*  test pin */
-#define	CCR4_EBRG	0x40	/*  enhanced baud rate generator mode */
-#define	CCR4_MCK4	0x80	/*  master clock divide by 4 */
-
-#endif