diff options
| author | yongari <yongari@FreeBSD.org> | 2010-04-30 00:34:00 +0000 |
|---|---|---|
| committer | yongari <yongari@FreeBSD.org> | 2010-04-30 00:34:00 +0000 |
| commit | a43425e8835983e7c93a15a2d6a42fdb292c1676 (patch) | |
| tree | fdde172623f4225128212d5d9d87a781be1a97b9 /sys | |
| parent | ed0300c12fff75dd5b24a7c1e90c16edee74d17e (diff) | |
| download | FreeBSD-src-a43425e8835983e7c93a15a2d6a42fdb292c1676.zip FreeBSD-src-a43425e8835983e7c93a15a2d6a42fdb292c1676.tar.gz | |
Both RX_GMF_LP_THR and RX_GMF_UP_THR must be 16 bits register. If
it is 8bits register then RX FIFO size can't exceed 2KB which is
not true for almost all Yukon II controller.
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/dev/msk/if_msk.c | 4 | ||||
| -rw-r--r-- | sys/dev/msk/if_mskreg.h | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/sys/dev/msk/if_msk.c b/sys/dev/msk/if_msk.c index c083e1e..9b92435 100644 --- a/sys/dev/msk/if_msk.c +++ b/sys/dev/msk/if_msk.c @@ -3822,9 +3822,9 @@ msk_init_locked(struct msk_if_softc *sc_if) if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) { /* Set Rx Pause threshould. */ - CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), + CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), MSK_ECU_LLPP); - CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), + CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), MSK_ECU_ULPP); /* Configure store-and-forward for Tx. */ msk_set_tx_stfwd(sc_if); diff --git a/sys/dev/msk/if_mskreg.h b/sys/dev/msk/if_mskreg.h index 34cac67..293ca29 100644 --- a/sys/dev/msk/if_mskreg.h +++ b/sys/dev/msk/if_mskreg.h @@ -621,8 +621,8 @@ #define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */ #define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */ #define RX_GMF_TR_THR 0x0c54 /* 32 bit Rx Truncation Threshold (Yukon-2) */ -#define RX_GMF_UP_THR 0x0c58 /* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */ -#define RX_GMF_LP_THR 0x0c5a /* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */ +#define RX_GMF_UP_THR 0x0c58 /* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */ +#define RX_GMF_LP_THR 0x0c5a /* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */ #define RX_GMF_VLAN 0x0c5c /* 32 bit Rx VLAN Type Register (Yukon-2) */ #define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */ #define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */ |
