Add in initial clean room implementation of hypervisor interfaces

4 files changed, 991 insertions, 156 deletions

diff --git a/sys/sun4v/include/hv_api.h b/sys/sun4v/include/hv_api.h
new file mode 100644
index 0000000..55d7bf6
--- /dev/null
+++ b/sys/sun4v/include/hv_api.h
@@ -0,0 +1,177 @@
+/*-
+ * Copyright (c) 2006 Kip Macy
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _MACHINE_HV_API_H
+#define	_MACHINE_HV_API_H
+
+typedef uint64_t devhandle_t;
+typedef uint64_t pci_device_t;
+typedef uint32_t pci_config_offset_t;
+typedef uint8_t pci_config_size_t;
+
+/*
+ * Section 10 Domain Services
+ */
+
+extern uint64_t hv_mach_desc(uint64_t buffer_ra, uint64_t *buffer_sizep);
+extern uint64_t hv_mach_watchdog(uint64_t timeout, uint64_t *time_remaining);
+
+/*
+ * Section 11 CPU Services
+ */
+
+/*
+ * Section 12 MMU Services
+ */
+/*
+ * TSB description structure for MMU_TSB_CTX0 and MMU_TSB_CTXNON0.
+ */
+typedef struct hv_tsb_info {
+	uint16_t	hti_idxpgsz;	/* page size used for index shift in TSB */
+	uint16_t	hti_assoc;	/* associativity of TSB                  */
+	uint32_t	hti_ntte;	/* size of TSB in TTEs                   */
+	uint32_t	hti_ctx_index;  /* context index                         */
+	uint32_t	hti_pgszs;	/* page size bitmasx                     */
+	uint64_t	hti_ra;	        /* real address of TSB base              */
+	uint64_t	hti_rsvd;	/* reserved                              */
+} hv_tsb_info_t;
+
+
+extern uint64_t	hv_tsb_ctx0(uint64_t, uint64_t);
+extern uint64_t	hv_tsb_ctxnon0(uint64_t, uint64_t);
+
+/*
+ * Section 13 Cache and Memory Services
+ */
+
+/*
+ * Section 14 Device Interrupt Services
+ */
+
+/*
+ * Section 15 Time of Day Services
+ */
+
+extern uint64_t hv_tod_get(uint64_t *seconds);
+extern uint64_t hv_tod_set(uint64_t);
+
+/*
+ * Section 16 Console Services
+ */
+
+extern int64_t hv_cons_putchar(uint8_t);
+extern int64_t hv_cons_getchar(uint8_t *);
+extern int64_t hv_cons_write(uint64_t buf_raddr, uint64_t size, uint64_t *nwritten);
+extern int64_t hv_cons_read(uint64_t buf_raddr, uint64_t size, uint64_t *nread);
+
+extern void hv_cnputs(char *);
+
+/*
+ * Section 17 Core Dump Services
+ */
+
+extern uint64_t hv_dump_buf_update(uint64_t, uint64_t, uint64_t *);
+
+
+/*
+ * Section 18 Trap Trace Services
+ */
+
+typedef struct trap_trace_entry {
+	uint8_t		tte_type;	/* Hypervisor or guest entry. */
+	uint8_t		tte_hpstat;	/* Hyper-privileged state. */
+	uint8_t		tte_tl;		/* Trap level. */
+	uint8_t		tte_gl;		/* Global register level. */
+	uint16_t	tte_tt;		/* Trap type.*/
+	uint16_t	tte_tag;	/* Extended trap identifier. */
+	uint64_t	tte_tstate;	/* Trap state. */
+	uint64_t	tte_tick;	/* Tick. */
+	uint64_t	tte_tpc;	/* Trap PC. */
+	uint64_t	tte_f1;		/* Entry specific. */
+	uint64_t	tte_f2;		/* Entry specific. */
+	uint64_t	tte_f3;		/* Entry specific. */
+	uint64_t	tte_f4;		/* Entry specific. */
+} trap_trace_entry_t;
+
+extern uint64_t hv_ttrace_buf_info(uint64_t *, uint64_t *);
+extern uint64_t hv_ttrace_buf_conf(uint64_t, uint64_t, uint64_t *);
+extern uint64_t hv_ttrace_enable(uint64_t, uint64_t *);
+extern uint64_t hv_ttrace_freeze(uint64_t, uint64_t *);
+extern uint64_t hv_ttrace_addentry(uint64_t, uint64_t, uint64_t, uint64_t, uint64_t);
+
+/*
+ * Section 19 Logical Domain Channel Services
+ *
+ */
+typedef struct ldc_state_info {
+	uint64_t lsi_head_offset;
+	uint64_t lsi_tail_offset;
+	uint64_t lsi_channel_state;
+} ldc_state_info_t;
+
+#define LDC_CHANNEL_DOWN     0
+#define LDC_CHANNEL_UP       1
+
+extern uint64_t hvio_ldc_tx_qconf(uint64_t ldc_id, uint64_t base_raddr, uint64_t nentries);
+extern uint64_t hvio_ldc_tx_qinfo(uint64_t ldc_id, uint64_t *base_raddr, uint64_t *nentries);
+extern uint64_t hvio_ldc_tx_get_state(uint64_t ldc_id, ldc_state_info_t *info); 
+extern uint64_t hvio_ldc_tx_set_qtail(uint64_t ldc_id, uint64_t tail_offset);
+extern uint64_t hvio_ldc_rx_get_state(uint64_t ldc_id, ldc_state_info_t *info); 
+extern uint64_t hvio_ldc_rx_qconf(uint64_t ldc_id, uint64_t base_raddr, uint64_t nentries);
+extern uint64_t hvio_ldc_rx_qinfo(uint64_t ldc_id, uint64_t *base_raddr, uint64_t *nentries);
+extern uint64_t hvio_ldc_rx_set_qhead(uint64_t ldc_id, uint64_t head_offset);
+
+
+/*
+ * Section 20 PCI I/O Services
+ *
+ */
+
+
+/*
+ * Section 21 MSI Services
+ *
+ */
+
+/*
+ * Section 22 UltraSPARC T1 Performance Counters
+ *
+ */
+
+/*
+ * Section 23 UltraSPARC T1 MMU Statistics Counters
+ *
+ */
+
+/*
+ * Simulator Services
+ */
+extern void hv_magic_trap_on(void);
+extern void hv_magic_trap_off(void);
+extern int hv_sim_read(uint64_t offset, vm_paddr_t buffer_ra, uint64_t size);
+extern int hv_sim_write(uint64_t offset, vm_paddr_t buffer_ra, uint64_t size);
diff --git a/sys/sun4v/include/hypervisorvar.h b/sys/sun4v/include/hypervisorvar.h
index e237329..14f5124 100644
--- a/sys/sun4v/include/hypervisorvar.h
+++ b/sys/sun4v/include/hypervisorvar.h
@@ -62,6 +62,8 @@
 #define	H_ENOTSUPPORTED		13	/* Function not supported */
 #define	H_ENOMAP		14	/* Mapping is not valid, */
 					/* no translation exists */
+#define H_ETOOMANY              15      /* Too many items specified / limit reached */
+#define H_ECHANNEL              16      /* Invalid LDC channel */
 
 #define	H_BREAK			-1	/* Console Break */
 #define	H_HUP			-2	/* Console Break */
@@ -82,36 +84,51 @@
 /*
  * Function numbers for FAST_TRAP.
  */
-#define	HV_MACH_EXIT		0x00
-#define	HV_MACH_DESC		0x01
-#define HV_MACH_SET_SOFT_STATE  0x03
-#define HV_MACH_GET_SOFT_STATE  0x04
-#define HV_MACH_SET_WATCHDOG    0x05
-
-#define HV_CPU_START            0x10
-#define HV_CPU_STOP             0x11
-#define	HV_CPU_YIELD		0x12
+#define	MACH_EXIT		0x00
+#define	MACH_DESC		0x01
+#define MACH_SET_SOFT_STATE     0x03
+#define MACH_GET_SOFT_STATE     0x04
+#define MACH_SET_WATCHDOG       0x05
+
+#define CPU_START               0x10
+#define CPU_STOP                0x11
+#define	CPU_YIELD		0x12
 #define CPU_QCONF		0x14
 #define CPU_QINFO		0x15
 #define CPU_MYID		0x16
-#define	HV_CPU_STATE		0x17
-#define HV_CPU_SET_RTBA		0x18
-#define HV_CPU_GET_RTBA		0x19
+#define	CPU_STATE		0x17
+#define CPU_SET_RTBA		0x18
+#define CPU_GET_RTBA		0x19
+
+
 #define MMU_TSB_CTX0            0x20
 #define MMU_TSB_CTXNON0		0x21
 #define	MMU_DEMAP_PAGE		0x22
 #define	MMU_DEMAP_CTX		0x23
 #define	MMU_DEMAP_ALL		0x24
 #define	MAP_PERM_ADDR		0x25
-#define	MMU_SET_INFOPTR		0x26
+#define	MMU_MAP_PERM_ADDR	0x26
 #define MMU_ENABLE              0x27
-#define UNMAP_PERM_ADDR         0x28
+#define MMU_UNMAP_PERM_ADDR     0x28
 #define MMU_TSB_CTX0_INFO       0x29
 #define MMU_TSB_CTXNON0_INFO    0x2a
 #define MMU_FAULT_AREA_INFO     0x2b
-#define	HV_MEM_SCRUB		0x31
-#define	HV_MEM_SYNC		0x32
-#define	HV_INTR_SEND		0x42
+
+/*
+ * Bits for MMU functions flags argument:
+ *	arg3 of MMU_MAP_ADDR
+ *	arg3 of MMU_DEMAP_CTX
+ *	arg2 of MMU_DEMAP_ALL
+ */
+#define	MAP_DTLB		0x1
+#define	MAP_ITLB		0x2
+
+
+
+
+#define	MEM_SCRUB		0x31
+#define	MEM_SYNC		0x32
+#define	CPU_MONDO_SEND		0x42
 #define	TOD_GET			0x50
 #define	TOD_SET			0x51
 #define	CONS_GETCHAR		0x60
@@ -133,91 +150,76 @@
 #define	DUMP_BUF_UPDATE		0x94
 #define DUMP_BUF_INFO           0x95
 
-#define	HVIO_INTR_DEVINO2SYSINO	0xa0
-#define	HVIO_INTR_GETENABLED	0xa1
-#define	HVIO_INTR_SETENABLED	0xa2
-#define	HVIO_INTR_GETSTATE	0xa3
-#define	HVIO_INTR_SETSTATE	0xa4
-#define	HVIO_INTR_GETTARGET	0xa5
-#define	HVIO_INTR_SETTARGET	0xa6
-
-#define	HVIO_IOMMU_MAP		0xb0
-#define	HVIO_IOMMU_DEMAP	0xb1
-#define	HVIO_IOMMU_GETMAP	0xb2
-#define	HVIO_IOMMU_GETBYPASS	0xb3
-
-#define	HVIO_CONFIG_GET		0xb4
-#define	HVIO_CONFIG_PUT		0xb5
-
-#define	HVIO_PEEK		0xb6
-#define	HVIO_POKE		0xb7
-
-#define	HVIO_DMA_SYNC		0xb8
-
-#define	HVIO_MSIQ_CONF		0xc0
-#define	HVIO_MSIQ_INFO		0xc1
-#define	HVIO_MSIQ_GETVALID	0xc2
-#define	HVIO_MSIQ_SETVALID	0xc3
-#define	HVIO_MSIQ_GETSTATE	0xc4
-#define	HVIO_MSIQ_SETSTATE	0xc5
-#define	HVIO_MSIQ_GETHEAD	0xc6
-#define	HVIO_MSIQ_SETHEAD	0xc7
-#define	HVIO_MSIQ_GETTAIL	0xc8
-
-#define	HVIO_MSI_GETVALID	0xc9
-#define	HVIO_MSI_SETVALID	0xca
-#define	HVIO_MSI_GETMSIQ	0xcb
-#define	HVIO_MSI_SETMSIQ	0xcc
-#define	HVIO_MSI_GETSTATE	0xcd
-#define	HVIO_MSI_SETSTATE	0xce
-
-#define	HVIO_MSG_GETMSIQ	0xd0
-#define	HVIO_MSG_SETMSIQ	0xd1
-#define	HVIO_MSG_GETVALID	0xd2
-#define	HVIO_MSG_SETVALID	0xd3
-
-#define HVIO_LDC_TX_QCONF       0xe0
-#define HVIO_LDC_TX_QINFO       0xe1
-#define HVIO_LDC_TX_GET_STATE   0xe2
-#define HVIO_LDC_TX_SET_QTAIL   0xe3
-#define HVIO_LDC_RX_QCONF       0xe4
-#define HVIO_LDC_RX_QINFO       0xe5
-#define HVIO_LDC_RX_GET_STATE   0xe6
-#define HVIO_LDC_RX_SET_QHEAD   0xe7
-
-
-#define HVIO_SIM_READ           0xf0
-#define HVIO_SIM_WRITE          0xf1
+#define	INTR_DEVINO2SYSINO	0xa0
+#define	INTR_GETENABLED	        0xa1
+#define	INTR_SETENABLED	        0xa2
+#define	INTR_GETSTATE	        0xa3
+#define	INTR_SETSTATE	        0xa4
+#define	INTR_GETTARGET	        0xa5
+#define	INTR_SETTARGET	        0xa6
+
+#define	PCI_IOMMU_MAP		0xb0
+#define	PCI_IOMMU_DEMAP	        0xb1
+#define	PCI_IOMMU_GETMAP	0xb2
+#define	PCI_IOMMU_GETBYPASS	0xb3
+
+#define	PCI_CONFIG_GET		0xb4
+#define	PCI_CONFIG_PUT		0xb5
+
+#define	PCI_PEEK		0xb6
+#define	PCI_POKE		0xb7
+
+#define	PCI_DMA_SYNC		0xb8
+
+#define	PCI_MSIQ_CONF		0xc0
+#define	PCI_MSIQ_INFO		0xc1
+#define	PCI_MSIQ_GETVALID	0xc2
+#define	PCI_MSIQ_SETVALID	0xc3
+#define	PCI_MSIQ_GETSTATE	0xc4
+#define	PCI_MSIQ_SETSTATE	0xc5
+#define	PCI_MSIQ_GETHEAD	0xc6
+#define	PCI_MSIQ_SETHEAD	0xc7
+#define	PCI_MSIQ_GETTAIL	0xc8
+
+#define	PCI_MSI_GETVALID	0xc9
+#define	PCI_MSI_SETVALID	0xca
+#define	PCI_MSI_GETMSIQ	        0xcb
+#define	PCI_MSI_SETMSIQ	        0xcc
+#define	PCI_MSI_GETSTATE	0xcd
+#define	PCI_MSI_SETSTATE	0xce
+
+#define	PCI_MSG_GETMSIQ	        0xd0
+#define	PCI_MSG_SETMSIQ	        0xd1
+#define	PCI_MSG_GETVALID	0xd2
+#define	PCI_MSG_SETVALID	0xd3
+
+#define LDC_TX_QCONF            0xe0
+#define LDC_TX_QINFO            0xe1
+#define LDC_TX_GET_STATE        0xe2
+#define LDC_TX_SET_QTAIL        0xe3
+#define LDC_RX_QCONF            0xe4
+#define LDC_RX_QINFO            0xe5
+#define LDC_RX_GET_STATE        0xe6
+#define LDC_RX_SET_QHEAD        0xe7
+
+#define LDC_SET_MAP_TABLE       0xea
+#define LDC_GET_MAP_TABLE       0xeb
+#define LDC_COPY                0xec
+#define LDC_MAPIN               0xed
+#define LDC_UNMAP               0xee
+#define LDC_REVOKE              0xef
+
+
+#define SIM_READ                0xf0
+#define SIM_WRITE               0xf1
 
 
-#ifdef SET_MMU_STATS
-#define	MMU_STAT_AREA		0xfc
-#endif /* SET_MMU_STATS */
-
 #define NIAGARA_GET_PERFREG     0x100
 #define NIAGARA_SET_PERFREG     0x101
 
 #define NIAGARA_MMUSTAT_CONF    0x102
 #define NIAGARA_MMUSTAT_INFO    0x103
 
-#define	HV_NCS_REQUEST		0x110
-
-#define	FIRE_GET_PERFREG	0x120
-#define	FIRE_SET_PERFREG	0x121
-
-#define	HV_RA2PA		0x200
-#define	HV_HPRIV		0x201
-
-/*
- * Bits for MMU functions flags argument:
- *	arg3 of MMU_MAP_ADDR
- *	arg3 of MMU_DEMAP_CTX
- *	arg2 of MMU_DEMAP_ALL
- */
-#define	MAP_DTLB		0x1
-#define	MAP_ITLB		0x2
-
-
 /*
  * Interrupt state manipulation definitions.
  */
@@ -231,20 +233,6 @@
 
 #ifndef LOCORE
 
-/*
- * TSB description structure for MMU_TSB_CTX0 and MMU_TSB_CTXNON0.
- */
-typedef struct hv_tsb_info {
-	uint16_t	hvtsb_idxpgsz;	/* page size used to index TSB */
-	uint16_t	hvtsb_assoc;	/* TSB associativity */
-	uint32_t	hvtsb_ntte;	/* TSB size (#TTE entries) */
-	uint32_t	hvtsb_ctx_index; /* context reg index */
-	uint32_t	hvtsb_pgszs;	/* sizes in use */
-	uint64_t	hvtsb_pa;	/* real address of TSB base */
-	uint64_t	hvtsb_rsvd;	/* reserved */
-} hv_tsb_info_t;
-
-#define	HVTSB_SHARE_INDEX	((uint32_t)-1)
 
 #ifdef SET_MMU_STATS
 #ifndef TTE4V_NPGSZ
@@ -338,27 +326,6 @@ struct mmu_stat {
 #define	HVIO_DMA_SYNC_DIR_TO_DEV	0x01
 #define	HVIO_DMA_SYNC_DIR_FROM_DEV	0x02
 
-/*
- * Performance counter register definitions.
- */
-#define	HVIO_FIRE_PERFREG_JBC_SEL	0
-#define	HVIO_FIRE_PERFREG_JBC_CNT0	1
-#define	HVIO_FIRE_PERFREG_JBC_CNT1	2
-#define	HVIO_FIRE_PERFREG_PCIE_IMU_SEL	3
-#define	HVIO_FIRE_PERFREG_PCIE_IMU_CNT0	4
-#define	HVIO_FIRE_PERFREG_PCIE_IMU_CNT1	5
-#define	HVIO_FIRE_PERFREG_PCIE_MMU_SEL	6
-#define	HVIO_FIRE_PERFREG_PCIE_MMU_CNT0	7
-#define	HVIO_FIRE_PERFREG_PCIE_MMU_CNT1	8
-#define	HVIO_FIRE_PERFREG_PCIE_TLU_SEL	9
-#define	HVIO_FIRE_PERFREG_PCIE_TLU_CNT0	10
-#define	HVIO_FIRE_PERFREG_PCIE_TLU_CNT1	11
-#define	HVIO_FIRE_PERFREG_PCIE_TLU_CNT2	12
-#define	HVIO_FIRE_PERFREG_PCIE_LNK_SEL	13
-#define	HVIO_FIRE_PERFREG_PCIE_LNK_CNT1	14
-#define	HVIO_FIRE_PERFREG_PCIE_LNK_CNT2	15
-
-
 #ifdef SIMULATOR
 #define MAGIC_TRAP_ON	ta	0x77
 #define MAGIC_TRAP_OFF	ta	0x78
diff --git a/sys/sun4v/sun4v/hcall.S b/sys/sun4v/sun4v/hcall.S
new file mode 100644
index 0000000..72bedb8
--- /dev/null
+++ b/sys/sun4v/sun4v/hcall.S
@@ -0,0 +1,691 @@
+/*-
+ * Copyright (c) 2006 Kip Macy <kmacy@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include <sys/cdefs.h>
+
+#include <machine/asi.h>
+#include <machine/asmacros.h>
+#include <machine/hv_api.h>
+#include <machine/pstate.h>
+
+#include "assym.s"
+/*
+ * Section 9 API Versioning
+ *
+ */
+	
+
+/*
+ * Section 10 Domain Services
+ *
+ */
+
+ENTRY(hv_mach_exit)
+	mov	MACH_EXIT, %o5
+	ta	FAST_TRAP
+	retl
+	  nop
+END(hv_mach_exit)
+	
+ENTRY(hv_mach_desc)
+	mov     %o1, %o2
+	ldx     [%o1], %o1
+	mov     MACH_DESC, %o5
+	ta      FAST_TRAP
+	retl
+	  stx   %o1, [%o2]
+END(hv_mach_desc)
+
+ENTRY(hv_mach_watchdog)
+	mov	%o1, %o2
+	mov	MACH_SET_WATCHDOG, %o5
+	ta	FAST_TRAP
+	brnz,pn %o0, 1f
+	  nop
+	stx	%o1, [%o2]
+1:	retl
+	  nop
+END(hv_mach_watchdog)
+	
+/*
+ * Section 11 CPU Services
+ * 
+ */
+
+ENTRY(hv_cpu_qconf)
+END(hv_cpu_qconf)
+
+ENTRY(hv_cpu_mondo_send)
+END(hv_cpu_mondo_send)
+
+ENTRY(hv_cpu_myid)
+END(hv_cpu_myid)
+
+ENTRY(hv_cpu_state)
+END(hv_cpu_state)
+	
+/*
+ * Section 12 MMU Services
+ *
+ */
+	
+ENTRY(hv_tsb_ctx0)
+END(hv_tsb_ctx0)
+
+ENTRY(hv_tsb_ctxnon0)
+END(hv_tsb_ctxnon0)
+
+ENTRY(hv_mmu_demap_page)
+END(hv_mmu_demap_page)
+
+ENTRY(hv_mmu_demap_ctx)
+END(hv_mmu_demap_ctx)
+
+ENTRY(hv_mmu_demap_all)
+END(hv_mmu_demap_all)
+
+ENTRY(hv_mmu_map_addr)
+END(hv_mmu_map_addr)
+
+ENTRY(hv_mmu_map_perm_addr)
+END(hv_mmu_map_perm_addr)
+
+ENTRY(hv_mmu_unmap_addr)
+END(hv_mmu_unmap_addr)
+
+ENTRY(hv_mmu_unmap_perm_addr)
+END(hv_mmu_unmap_perm_addr)
+
+ENTRY(hv_mmu_fault_area_conf)
+END(hv_mmu_fault_area_conf)
+
+ENTRY(hv_mmu_enable)
+END(hv_mmu_enable)
+
+ENTRY(hv_mmu_tsb_ctx0_info)
+END(hv_mmu_tsb_ctx0_info)
+
+ENTRY(hv_mmu_tsb_ctxnon0_info)
+END(hv_mmu_tsb_ctxnon0_info)
+
+ENTRY(hv_mmu_fault_area_info)
+END(hv_mmu_fault_area_info)
+
+/*
+ * Section 13 Cache and Memory Services
+ *
+ */
+
+ENTRY(hv_mem_scrub)
+END(hv_mem_scrub)
+
+ENTRY(hv_mem_sync)
+END(hv_mem_sync)
+
+/*
+ * Section 14 Device Interrupt Services
+ *
+ */
+
+ENTRY(hv_intr_devino_to_sysino)	
+END(hv_intr_devino_to_sysino)	
+
+ENTRY(hv_intr_devino_to_sysino)	
+END(hv_intr_devino_to_sysino)
+
+ENTRY(hv_intr_getenabled)
+END(hv_intr_getenabled)
+
+ENTRY(hv_intr_setenabled)
+END(hv_intr_setenabled)
+
+ENTRY(hv_intr_getstate)
+END(hv_intr_getstate)
+
+ENTRY(hv_intr_setstate)
+END(hv_intr_setstate)
+
+ENTRY(hv_intr_gettarget)
+END(hv_intr_gettarget)
+
+ENTRY(hv_intr_settarget)
+END(hv_intr_settarget)
+
+/*
+ * Section 15 Time of Day Services
+ *
+ */
+
+/*
+ * get the current time of day
+ *
+ * ret0 status       (%o0)
+ * ret1 time-of-day  (%o1)
+ * 
+ */
+ENTRY(hv_tod_get)
+	mov	%o0, %o2
+	mov	TOD_GET, %o5
+	ta	FAST_TRAP
+	retl
+	  stx	%o1, [%o2]
+END(hv_tod_get)
+
+/*
+ * set the current time-of-day
+ * arg0 tod          (%o0)
+ *
+ * ret0 status       (%o0)
+ * 
+ */
+ENTRY(hv_tod_set)
+	mov	TOD_SET, %o5
+	ta	FAST_TRAP
+	retl
+	  nop	
+END(hv_tod_set)
+
+/*
+ * Section 16 Console Services
+ *
+ */
+	
+ENTRY(hv_cons_getchar)
+END(hv_cons_getchar)
+	
+ENTRY(hv_cons_putchar)
+END(hv_cons_putchar)
+
+/*
+ * write characters in raddr to console
+ * arg0 raddr        (%o0)
+ * arg1 size         (%o1)
+ *
+ * ret0 status       (%o0)
+ * ret1 char written (%o1)
+ * 
+ */
+ENTRY(hv_cons_write)
+	mov	%o2, %o3
+	mov	CONS_WRITE, %o5
+	ta	FAST_TRAP
+	brnz,a	%o0, 1f		! failure, just return error
+	  mov	1, %o0
+	stx	%o1, [%o3]
+1:	retl
+	  nop
+END(hv_cons_write)
+
+/*
+ * read up to size characters from console in to raddr 
+ * arg0 raddr        (%o0)
+ * arg1 size
+ *
+ * ret0 status       (%o0)
+ * ret1 char written (%o1)
+ * 
+ */
+ENTRY(hv_cons_read)
+	mov	%o2, %o3
+	mov	CONS_READ, %o5
+	ta	FAST_TRAP
+	brnz,a	%o0, 1f		! failure, just return error
+	  mov	1, %o0
+
+	cmp	%o1, H_BREAK
+	be	1f
+	  mov	%o1, %o0
+
+	cmp	%o1, H_HUP
+	be	1f
+	  mov	%o1, %o0
+
+	stx	%o1, [%o3]
+1:	retl
+	  nop
+END(hv_cons_read)
+	
+
+/*
+ * Section 17 Core Dump Services
+ *
+ */
+
+ENTRY(hv_dump_buf_update)
+END(hv_dump_buf_update)
+
+ENTRY(hv_dump_buf_info)
+END(hv_dump_buf_info)
+
+/*
+ * Section 18 Trap Trace Services
+ *
+ */
+
+/*
+ * TTRACE_BUF_CONF Configure
+ * arg0 RA base of buffer (%o0)
+ * arg1 buf size in no. of entries (%o1)
+ * ret0 status (%o0)
+ * ret1 minimum size in no. of entries on failure,
+ * actual size in no. of entries on success (%o1)
+ */
+ENTRY(hv_ttrace_buf_conf)
+	mov	TTRACE_BUF_CONF, %o5
+	ta	FAST_TRAP
+	retl
+	  stx	%o1, [%o2]
+END(hv_ttrace_buf_conf)
+
+ /*
+ * TTRACE_BUF_INFO
+ * ret0 status (%o0)
+ * ret1 RA base of buffer (%o1)
+ * ret2 size in no. of entries (%o2)
+ */
+ENTRY(hv_ttrace_buf_info)
+	mov	%o0, %o3
+	mov	%o1, %o4
+	mov	TTRACE_BUF_INFO, %o5
+	ta	FAST_TRAP
+	stx	%o1, [%o3]
+	retl
+	  stx	%o2, [%o4]
+END(hv_ttrace_buf_info)
+
+/*
+ * TTRACE_ENABLE
+ * arg0 enable/ disable (%o0)
+ * ret0 status (%o0)
+ * ret1 previous enable state (%o1)
+ */
+ENTRY(hv_ttrace_enable)
+	mov	%o1, %o2
+	mov	TTRACE_ENABLE, %o5
+	ta	FAST_TRAP
+	retl
+	  stx	%o1, [%o2]
+END(hv_ttrace_enable)
+
+/*
+ * TTRACE_FREEZE
+ * arg0 enable/ freeze        (%o0)
+ *
+ * ret0 status                (%o0)
+ * ret1 previous freeze state (%o1)
+ *	
+ */
+ENTRY(hv_ttrace_freeze)
+	mov	%o1, %o2
+	mov	TTRACE_FREEZE, %o5
+	ta	FAST_TRAP
+	retl
+	  stx	%o1, [%o2]
+END(hv_ttrace_freeze)
+
+/*
+ * TTRACE_ADDENTRY
+ * arg0 tag (16-bits) (%o0)
+ * arg1 data word 0 (%o1)
+ * arg2 data word 1 (%o2)
+ * arg3 data word 2 (%o3)
+ * arg4 data word 3 (%o4)
+ *
+ * ret0 status (%o0)
+ *
+*/
+ENTRY(hv_ttrace_addentry)
+	ta	TTRACE_ADDENTRY
+	retl
+	  nop	
+END(hv_ttrace_addentry)
+			
+/*
+ * Section 19 Logical Domain Channel Services
+ *
+ */
+	
+/*
+ * configure ldc tx queue
+ * arg0 ldc_id     (%o0)
+ * arg1 base_raddr (%o1)
+ * arg2 nentries   (%o2)
+ *
+ * ret0 status     (%o0)
+ *
+ */
+ENTRY(hv_ldc_tx_qconf)
+	mov	LDC_TX_QCONF, %o5
+	ta	FAST_TRAP
+	retl
+	  nop
+END(hv_ldc_tx_qconf)
+
+/*
+ * return configuration info for ldc tx queue
+ * arg0 ldc_id     (%o0)
+ *
+ * ret0 status     (%o0)
+ * ret1 base_raddr (%o1)
+ * ret2 nentries   (%o2)
+ *
+ */
+ENTRY(hv_ldc_tx_qinfo)
+	mov	%o1, %o3
+	mov	%o2, %o4
+	mov	LDC_TX_QINFO, %o5
+	ta	FAST_TRAP
+	brnz	%o0, 1f
+	  nop
+	stx	%o1, [%o3]
+	stx	%o2, [%o4]
+1:	retl
+	  nop
+END(hv_ldc_tx_qinfo)
+
+/*
+ * get the state of the ldc tx queue
+ * arg0 ldc_id        (%o0)
+ *
+ * ret0 status        (%o0)
+ * ret1 head_offset   (%o1)
+ * ret2 tail_offset   (%o2)
+ * ret3 channel_state (%o3)
+ * 
+ */
+ENTRY(hv_ldc_tx_get_state)
+	mov	%o1, %o4
+	mov	LDC_TX_GET_STATE, %o5
+	ta	FAST_TRAP
+	brnz	%o0, 1f
+	  nop
+	stx	%o1, [%o4]
+	stx	%o2, [%o4 + 8]
+	stx	%o3, [%o4 + 16]
+1:	retl
+	  nop		
+END(hv_ldc_tx_get_state)
+
+/*
+ * update the tail pointer of the ldc tx queue
+ * arg0 ldc_id      (%o0)
+ * arg1 tail_offset (%o1)
+ *
+ * ret0 status      (%o0)
+ *
+ */
+ENTRY(hv_ldc_tx_set_qtail)
+	mov	LDC_TX_SET_QTAIL, %o5
+	ta	FAST_TRAP
+	retl
+	  nop
+END(hv_ldc_tx_set_qtail)
+
+/*
+ * configure ldc rx queue
+ * arg0 ldc_id     (%o0)
+ * arg1 base_raddr (%o1)
+ * arg2 nentries   (%o2)
+ *
+ * ret0 status     (%o0)
+ *
+ */
+ENTRY(hv_ldc_rx_qconf)
+	mov	LDC_RX_QCONF, %o5
+	ta	FAST_TRAP
+	retl
+	  nop	
+END(hv_ldc_rx_qconf)
+
+/*
+ * return configuration info for ldc rx queue
+ * arg0 ldc_id     (%o0)
+ *
+ * ret0 status     (%o0)
+ * ret1 base_raddr (%o1)
+ * ret2 nentries   (%o2)
+ *
+ */
+ENTRY(hv_ldc_rx_qinfo)
+	mov	%o1, %o3
+	mov	%o2, %o4
+	mov	LDC_RX_QINFO, %o5
+	ta	FAST_TRAP
+	brnz	%o0, 1f
+	  nop
+	stx	%o1, [%o3]
+	stx	%o2, [%o4]
+1:	retl
+	  nop
+END(hv_ldc_rx_qinfo)
+
+/*
+ * get the state of the ldc rx queue
+ * arg0 ldc_id        (%o0)
+ *
+ * ret0 status        (%o0)
+ * ret1 head_offset   (%o1)
+ * ret2 tail_offset   (%o2)
+ * ret3 channel_state (%o3)
+ * 
+ */
+ENTRY(hv_ldc_rx_get_state)
+	mov	%o1, %o4
+	mov	LDC_RX_GET_STATE, %o5
+	ta	FAST_TRAP
+	brnz	%o0, 1f
+	  nop
+	stx	%o1, [%o4]
+	stx	%o2, [%o4 + 8]
+	stx	%o3, [%o4 + 16]
+1:	retl
+	  nop		
+END(hv_ldc_rx_get_state)
+
+/*
+ * update the head pointer of the ldc rx queue
+ * arg0 ldc_id      (%o0)
+ * arg1 head_offset (%o1)
+ *
+ * ret0 status      (%o0)
+ *
+ */
+ENTRY(hv_ldc_rx_set_qhead)
+	mov	LDC_RX_SET_QHEAD, %o5
+	ta	FAST_TRAP
+	retl
+	  nop	
+END(hv_ldc_rx_set_qhead)
+
+ENTRY(hv_ldc_get_map_table)
+END(hv_ldc_get_map_table)
+
+ENTRY(hv_ldc_set_map_table)
+END(hv_ldc_set_map_table)
+
+ENTRY(hv_ldc_copy)
+END(hv_ldc_copy)
+
+ENTRY(hv_ldc_mapin)
+END(hv_ldc_mapin)
+
+ENTRY(hv_ldc_unmap)
+END(hv_ldc_unmap)
+
+ENTRY(hv_ldc_revoke
+END(hv_ldc_revoke)
+		
+/*
+ * Section 20 PCI I/O Services
+ *
+ */
+	
+ENTRY(hv_pci_iommu_map)
+END(hv_pci_iommu_map)
+
+ENTRY(hv_pci_iommu_demap)
+END(hv_pci_iommu_demap)
+
+ENTRY(hv_pci_iommu_getmap)
+END(hv_pci_iommu_getmap)
+
+ENTRY(hv_pci_iommu_getbypass)
+END(hv_pci_iommu_getbypass)
+	
+ENTRY(hv_pci_config_get)
+END(hv_pci_config_get)
+
+ENTRY(hv_pci_config_put)
+END(hv_pci_config_put)
+
+ENTRY(hv_pci_peek)
+END(hv_pci_peek)
+
+ENTRY(hv_pci_poke)
+END(hv_pci_poke)
+
+ENTRY(hv_pci_dma_sync)
+END(hv_pci_dma_sync)
+
+/*
+ * Section 21 MSI Services
+ *
+ */
+
+ENTRY(hv_pci_msiq_conf)
+END(hv_pci_msiq_conf)
+
+ENTRY(hv_pci_msiq_info)
+END(hv_pci_msiq_info)
+
+ENTRY(hv_pci_msiq_getvalid)
+END(hv_pci_msiq_getvalid)
+
+ENTRY(hv_pci_msiq_setvalid)
+END(hv_pci_msiq_setvalid)
+
+ENTRY(hv_pci_msiq_getstate)
+END(hv_pci_msiq_getstate)
+
+ENTRY(hv_pci_msiq_setstate)
+END(hv_pci_msiq_setstate)
+
+ENTRY(hv_pci_msiq_gethead)
+END(hv_pci_msiq_gethead)
+
+ENTRY(hv_pci_msiq_sethead)
+END(hv_pci_msiq_sethead)
+
+ENTRY(hv_pci_msiq_gettail)
+END(hv_pci_msiq_gettail)
+
+ENTRY(hv_pci_msi_getvalid)
+END(hv_pci_msi_getvalid)
+
+ENTRY(hv_pci_msi_setvalid)
+END(hv_pci_msi_setvalid)
+
+ENTRY(hv_pci_msi_getmsiq)
+END(hv_pci_msi_getmsiq)
+
+ENTRY(hv_pci_msi_setmsiq)
+END(hv_pci_msi_setmsiq)
+
+ENTRY(hv_pci_msi_getstate)
+END(hv_pci_msi_getstate)
+
+ENTRY(hv_pci_msi_setstate)
+END(hv_pci_msi_setstate)
+
+ENTRY(hv_pci_msg_getmsiq)
+END(hv_pci_msg_getmsiq)
+
+ENTRY(hv_pci_msg_setmsiq)
+END(hv_pci_msg_setmsiq)
+
+ENTRY(hv_pci_msg_getvalid)
+END(hv_pci_msg_getvalid)
+
+ENTRY(hv_pci_msg_setvalid)
+END(hv_pci_msg_setvalid)
+
+/*
+ * Section 22 UltraSPARC T1 Performance Counters
+ *
+ */
+
+ENTRY(hv_niagara_get_perfreg)
+END(hv_niagara_get_perfreg)
+
+ENTRY(hv_niagara_set_perfreg)
+END(hv_niagara_set_perfreg)
+	
+/*
+ * Section 23 UltraSPARC T1 MMU Statistics Counters
+ *
+ */
+
+ENTRY(hv_niagara_mmustat_conf)
+END(hv_niagara_mmustat_conf)
+
+ENTRY(hv_niagara_mmustat_info)
+END(hv_niagara_mmustat_info)
+
+/*
+ * Simulator Services
+ *
+ */
+
+ENTRY(hv_magic_trap_on)
+	ta	0x77
+	retl
+	  nop
+END(hv_magic_trap_on)
+
+ENTRY(hv_magic_trap_off)
+	ta	0x78
+	retl
+	  nop
+END(hv_magic_trap_off)
+
+
+ENTRY(hv_sim_read)
+	mov	SIM_READ, %o5
+	ta	FAST_TRAP
+	retl
+	  nop
+END(hv_read)
+
+ENTRY(hv_sim_write)
+	mov	SIM_WRITE, %o5
+	ta	FAST_TRAP
+	retl
+	  nop
+END(hv_write)
+	
+		
diff --git a/sys/sun4v/sun4v/pmap.c b/sys/sun4v/sun4v/pmap.c
index c91be02..a9e71e6 100644
--- a/sys/sun4v/sun4v/pmap.c
+++ b/sys/sun4v/sun4v/pmap.c
@@ -76,7 +76,7 @@ __FBSDID("$FreeBSD$");
 #include <machine/pstate.h>
 #include <machine/tsb.h>
 
-#include <machine/hypervisor_api.h>
+#include <machine/hv_api.h>
 
 #ifdef TRAP_TRACING
 void trap_trace_report(int);
@@ -623,25 +623,25 @@ pmap_bootstrap(vm_offset_t ekva)
 	if (pa & PAGE_MASK_4M)
 		panic("pmap_bootstrap: tsb unaligned\n");
 	KDPRINTF("tsb_8k_size is 0x%lx, tsb_8k_pa is 0x%lx\n", tsb_8k_size, pa);
-	kernel_td[TSB8K_INDEX].hvtsb_idxpgsz = TTE8K;
-	kernel_td[TSB8K_INDEX].hvtsb_assoc = 1;
-	kernel_td[TSB8K_INDEX].hvtsb_ntte = (tsb_8k_size >> TTE_SHIFT);
-	kernel_td[TSB8K_INDEX].hvtsb_ctx_index = 0;
-	kernel_td[TSB8K_INDEX].hvtsb_pgszs = TSB8K;
-	kernel_td[TSB8K_INDEX].hvtsb_rsvd = 0;
-	kernel_td[TSB8K_INDEX].hvtsb_pa = pa;
+	kernel_td[TSB8K_INDEX].hti_idxpgsz = TTE8K;
+	kernel_td[TSB8K_INDEX].hti_assoc = 1;
+	kernel_td[TSB8K_INDEX].hti_ntte = (tsb_8k_size >> TTE_SHIFT);
+	kernel_td[TSB8K_INDEX].hti_ctx_index = 0;
+	kernel_td[TSB8K_INDEX].hti_pgszs = TSB8K;
+	kernel_td[TSB8K_INDEX].hti_rsvd = 0;
+	kernel_td[TSB8K_INDEX].hti_pa = pa;
 
 	/*
 	 * Initialize kernel's private TSB from 8K page TSB
 	 *
 	 */
-	kernel_pmap->pm_tsb.hvtsb_idxpgsz = TTE8K;
-	kernel_pmap->pm_tsb.hvtsb_assoc = 1;
-	kernel_pmap->pm_tsb.hvtsb_ntte = (tsb_8k_size >> TTE_SHIFT);
-	kernel_pmap->pm_tsb.hvtsb_ctx_index = 0;
-	kernel_pmap->pm_tsb.hvtsb_pgszs = TSB8K;
-	kernel_pmap->pm_tsb.hvtsb_rsvd = 0;
-	kernel_pmap->pm_tsb.hvtsb_pa = pa;
+	kernel_pmap->pm_tsb.hti_idxpgsz = TTE8K;
+	kernel_pmap->pm_tsb.hti_assoc = 1;
+	kernel_pmap->pm_tsb.hti_ntte = (tsb_8k_size >> TTE_SHIFT);
+	kernel_pmap->pm_tsb.hti_ctx_index = 0;
+	kernel_pmap->pm_tsb.hti_pgszs = TSB8K;
+	kernel_pmap->pm_tsb.hti_rsvd = 0;
+	kernel_pmap->pm_tsb.hti_pa = pa;
 	
 	kernel_pmap->pm_tsb_ra = vtophys((vm_offset_t)&kernel_pmap->pm_tsb);
 	tsb_set_scratchpad_kernel(&kernel_pmap->pm_tsb);
@@ -655,13 +655,13 @@ pmap_bootstrap(vm_offset_t ekva)
 	pa = pmap_bootstrap_alloc(tsb_4m_size);
 
 	KDPRINTF("tsb_4m_pa is 0x%lx tsb_4m_size is 0x%lx\n", pa, tsb_4m_size);
-	kernel_td[TSB4M_INDEX].hvtsb_idxpgsz = TTE4M;
-	kernel_td[TSB4M_INDEX].hvtsb_assoc = 1;
-	kernel_td[TSB4M_INDEX].hvtsb_ntte = (tsb_4m_size >> TTE_SHIFT);
-	kernel_td[TSB4M_INDEX].hvtsb_ctx_index = 0;
-	kernel_td[TSB4M_INDEX].hvtsb_pgszs = TSB4M; 
-	kernel_td[TSB4M_INDEX].hvtsb_rsvd = 0;
-	kernel_td[TSB4M_INDEX].hvtsb_pa = pa;
+	kernel_td[TSB4M_INDEX].hti_idxpgsz = TTE4M;
+	kernel_td[TSB4M_INDEX].hti_assoc = 1;
+	kernel_td[TSB4M_INDEX].hti_ntte = (tsb_4m_size >> TTE_SHIFT);
+	kernel_td[TSB4M_INDEX].hti_ctx_index = 0;
+	kernel_td[TSB4M_INDEX].hti_pgszs = TSB4M; 
+	kernel_td[TSB4M_INDEX].hti_rsvd = 0;
+	kernel_td[TSB4M_INDEX].hti_pa = pa;
 
 	/*
 	 * allocate MMU fault status areas for all CPUS
@@ -1966,12 +1966,12 @@ pmap_tsb_reset(pmap_t pmap)
 		pmap->pm_old_tsb_pa[i] = 0;
 	}
 	if (pmap->pm_old_tsb_pa[0] != 0) {
-		vm_paddr_t tsb_pa = pmap->pm_tsb.hvtsb_pa;
+		vm_paddr_t tsb_pa = pmap->pm_tsb.hti_pa;
 		int size = tsb_size(&pmap->pm_tsb);
-		pmap->pm_tsb.hvtsb_ntte = (1 << (TSB_INIT_SHIFT + PAGE_SHIFT - TTE_SHIFT));
-		pmap->pm_tsb.hvtsb_pa = pmap->pm_old_tsb_pa[0];
+		pmap->pm_tsb.hti_ntte = (1 << (TSB_INIT_SHIFT + PAGE_SHIFT - TTE_SHIFT));
+		pmap->pm_tsb.hti_pa = pmap->pm_old_tsb_pa[0];
 		pmap_free_contig_pages((void *)TLB_PHYS_TO_DIRECT(tsb_pa), size);
-		pmap->pm_tsbscratch = pmap->pm_tsb.hvtsb_pa | (uint64_t)TSB_INIT_SHIFT;
+		pmap->pm_tsbscratch = pmap->pm_tsb.hti_pa | (uint64_t)TSB_INIT_SHIFT;
 		pmap->pm_old_tsb_pa[0] = 0;
 	}
 }
@@ -2035,7 +2035,7 @@ pmap_tsb_resize(pmap_t pmap)
 	    cap_miss_count > (miss_count >> 1)) {
 		DPRINTF("resizing tsb for proc=%s pid=%d\n", 
 			curthread->td_proc->p_comm, curthread->td_proc->p_pid);
-		pmap->pm_old_tsb_pa[npages_shift - TSB_INIT_SHIFT] = pmap->pm_tsb.hvtsb_pa;
+		pmap->pm_old_tsb_pa[npages_shift - TSB_INIT_SHIFT] = pmap->pm_tsb.hti_pa;
 
 		/* double TSB size */
 		tsb_init(&hvtsb, &tsbscratch, npages_shift + 1);