Added support for the DEC EB64PLUS systype. (part I)

The new file pci_eb64plus_intr.s deals with the interrupt hardware
on the EB64PLUS and was obtained from NetBSD with the NetBSD
copyright intact

The apecs chipset support code was altered to allow routing interrupts
through pci if we're not running on an avanti.  Avanti's route all
interrupts through isa.

Tested by: Wilko Bulte <wilko@yedi.iaf.nl>
Partially reviewed by: dfr

2 files changed, 114 insertions, 5 deletions

diff --git a/sys/alpha/pci/apecs.c b/sys/alpha/pci/apecs.c
index d7f7b6e..66bedcf 100644
--- a/sys/alpha/pci/apecs.c
+++ b/sys/alpha/pci/apecs.c
@@ -23,7 +23,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- *	$Id: apecs.c,v 1.3 1998/11/15 18:25:16 dfr Exp $
+ *	$Id: apecs.c,v 1.4 1998/12/04 22:54:42 archie Exp $
  */
 /*
  * Copyright (c) 1995, 1996 Carnegie-Mellon University.
@@ -60,13 +60,16 @@
 #include <sys/kernel.h>
 #include <sys/module.h>
 #include <sys/bus.h>
+#include <sys/rman.h>
 
 #include <alpha/pci/apecsreg.h>
 #include <alpha/pci/apecsvar.h>
 #include <alpha/pci/pcibus.h>
 #include <machine/intr.h>
+#include <machine/intrcnt.h>
 #include <machine/cpuconf.h>
 #include <machine/swiz.h>
+#include <machine/rpb.h>
 
 #define KV(pa)			ALPHA_PHYS_TO_K0SEG(pa)
 
@@ -439,9 +442,10 @@ apecs_write_hae(u_int64_t hae)
 
 static int apecs_probe(device_t dev);
 static int apecs_attach(device_t dev);
-static void *apecs_create_intr(device_t dev, device_t child, int irq, driver_intr_t *intr, void *arg);
-static int apecs_connect_intr(device_t dev, void* ih);
-
+static int apecs_setup_intr(device_t dev, device_t child, struct resource *irq,
+			  driver_intr_t *intr, void *arg, void **cookiep);
+static int apecs_teardown_intr(device_t dev, device_t child,
+			     struct resource *irq, void *cookie);
 static device_method_t apecs_methods[] = {
 	/* Device interface */
 	DEVMETHOD(device_probe,		apecs_probe),
@@ -452,6 +456,8 @@ static device_method_t apecs_methods[] = {
 	DEVMETHOD(bus_release_resource,	pci_release_resource),
 	DEVMETHOD(bus_activate_resource, pci_activate_resource),
 	DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
+	DEVMETHOD(bus_setup_intr,	apecs_setup_intr),
+	DEVMETHOD(bus_teardown_intr,	apecs_teardown_intr),
 
 	{ 0, 0 }
 };
@@ -492,6 +498,8 @@ apecs_probe(device_t dev)
 	}
 	apecs_hae_mem = REGVAL(EPIC_HAXR1);
 
+	pci_init_resources();
+
 	isa0 = device_add_child(dev, "isa", 0, 0);
 
 	return 0;
@@ -504,7 +512,15 @@ apecs_attach(device_t dev)
 {
 	struct apecs_softc* sc = APECS_SOFTC(dev);
 	apecs_init();
-	chipset.intrdev = isa0;
+
+	/* 
+	 *  the avanti routes interrupts through the isa interrupt
+	 *  controller, so we need to special case it 
+	 */
+	if(hwrpb->rpb_type == ST_DEC_2100_A50)
+		chipset.intrdev = isa0;
+	else
+		chipset.intrdev = apecs0;
 
 	sc->dmem_base = APECS_PCI_DENSE;
 	sc->smem_base = APECS_PCI_SPARSE;
@@ -525,5 +541,35 @@ apecs_attach(device_t dev)
 	return 0;
 }
 
+static int
+apecs_setup_intr(device_t dev, device_t child,
+	       struct resource *irq,
+	       driver_intr_t *intr, void *arg, void **cookiep)
+{
+	int error;
+	
+	error = rman_activate_resource(irq);
+	if (error)
+		return error;
+
+	error = alpha_setup_intr(0x900 + (irq->r_start << 4),
+			intr, arg, cookiep,
+			&intrcnt[INTRCNT_EB64PLUS_IRQ + irq->r_start]);
+	if (error)
+		return error;
+
+	/* Enable PCI interrupt */
+	platform.pci_intr_enable(irq->r_start);
+	return 0;
+}
+
+static int
+apecs_teardown_intr(device_t dev, device_t child,
+		  struct resource *irq, void *cookie)
+{
+	alpha_teardown_intr(cookie);
+	return rman_deactivate_resource(irq);
+}
+
 DRIVER_MODULE(apecs, root, apecs_driver, apecs_devclass, 0, 0);
 
diff --git a/sys/alpha/pci/pci_eb64plus_intr.s b/sys/alpha/pci/pci_eb64plus_intr.s
new file mode 100644
index 0000000..472d741
--- /dev/null
+++ b/sys/alpha/pci/pci_eb64plus_intr.s
@@ -0,0 +1,63 @@
+/* $NetBSD: pci_eb64plus_intr.s,v 1.2 1997/09/02 13:19:43 thorpej Exp $ */
+
+/*
+ * Copyright (c) 1996 Carnegie-Mellon University.
+ * All rights reserved.
+ *
+ * Author: Chris G. Demetriou
+ * 
+ * Permission to use, copy, modify and distribute this software and
+ * its documentation is hereby granted, provided that both the copyright
+ * notice and this permission notice appear in all copies of the
+ * software, derivative works or modified versions, and any portions
+ * thereof, and that both notices appear in supporting documentation.
+ * 
+ * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 
+ * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 
+ * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
+ * 
+ * Carnegie Mellon requests users of this software to return to
+ *
+ *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
+ *  School of Computer Science
+ *  Carnegie Mellon University
+ *  Pittsburgh PA 15213-3890
+ *
+ * any improvements or extensions that they make and grant Carnegie the
+ * rights to redistribute these changes.
+ */
+
+/*
+ * This file hacked from pci_eb164_intr.s
+ *
+ * These functions were written by disassembling a Digital UNIX kernel's
+ * eb64p_intrdsabl and eb64p_intrenabl functions (because they had
+ * interesting names, and looked like the eb164 versions which were
+ * known to already work), and then playing with them to see how to call
+ * them correctly.
+ *
+ * It looks like the right thing to do is to call them with the interrupt
+ * request that you want to enable or disable (presumably in the range
+ * 0 -> 23, since there are 3 8-bit interrupt-enable bits in the
+ * interrupt mask PLD).
+ */
+
+#include <machine/asm.h>
+
+__KERNEL_RCSID(0, "$NetBSD: pci_eb64plus_intr.s,v 1.2 1997/09/02 13:19:43 thorpej Exp $");
+
+	.text
+LEAF(eb64plus_intr_enable,1)
+	mov	a0, a1
+	ldiq	a0, 0x34
+	call_pal PAL_cserve
+	RET
+	END(eb64plus_intr_enable)
+
+	.text
+LEAF(eb64plus_intr_disable,1)
+	mov	a0, a1
+	ldiq	a0, 0x35
+	call_pal PAL_cserve
+	RET
+	END(eb64plus_intr_enable)