diff options
| author | jake <jake@FreeBSD.org> | 2002-05-11 21:20:05 +0000 |
|---|---|---|
| committer | jake <jake@FreeBSD.org> | 2002-05-11 21:20:05 +0000 |
| commit | 6aad34df02289444642787c1282319835d8defa7 (patch) | |
| tree | 395e13d474abd602396284cd4f7df33a511e8656 /sys | |
| parent | 50d831e58554cd65ec430f27b3c9c9a88424fc95 (diff) | |
| download | FreeBSD-src-6aad34df02289444642787c1282319835d8defa7.zip FreeBSD-src-6aad34df02289444642787c1282319835d8defa7.tar.gz | |
Add a support macro to convert the 5-bit packed register field of
a floating point instruction into a 6-bit register number for
double and quad arguments.
Make use of the new INSFPdq_RN macro where apporpriate; this
is required for correctly handling the "high" fp registers
(>= %f32).
Fix a number of bugs related to the handling of the high registers
which were caused by using __fpu_[gs]etreg() where __fpu_[gs]etreg64()
should be used (the former can only access the low, single-precision,
registers).
Submitted by: tmm
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/sparc64/include/instr.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/sys/sparc64/include/instr.h b/sys/sparc64/include/instr.h index edb300e..51f0300 100644 --- a/sys/sparc64/include/instr.h +++ b/sys/sparc64/include/instr.h @@ -459,6 +459,9 @@ #define INSFP2_FCMP 0x050 /* s, d, q */ #define INSFP2_FCMPE 0x054 /* s, d, q */ +/* Decode 5-bit register field into 6-bit number (for doubles and quads). */ +#define INSFPdq_RN(rn) (((rn) & ~1) | (((rn) & 1) << 5)) + /* IMPLDEP1 for Sun UltraSparc */ #define IIDP1_EDGE8 0x00 #define IIDP1_EDGE8L 0x02 |
