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author | jhb <jhb@FreeBSD.org> | 2013-01-17 21:32:25 +0000 |
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committer | jhb <jhb@FreeBSD.org> | 2013-01-17 21:32:25 +0000 |
commit | 4a3c4478d3346235378985c52457d9bd03d7f401 (patch) | |
tree | 75d5ceedc94644a0695195b809e8f66831fa17ab /sys | |
parent | d8067c27f54c1f0d1bc952da140a4f0b469b19ea (diff) | |
download | FreeBSD-src-4a3c4478d3346235378985c52457d9bd03d7f401.zip FreeBSD-src-4a3c4478d3346235378985c52457d9bd03d7f401.tar.gz |
Don't attempt to use clflush on the local APIC register window. Various
CPUs exhibit bad behavior if this is done (Intel Errata AAJ3, hangs on
Pentium-M, and trashing of the local APIC registers on a VIA C7). The
local APIC is implicitly mapped UC already via MTRRs, so the clflush isn't
necessary anyway.
MFC after: 2 weeks
Diffstat (limited to 'sys')
-rw-r--r-- | sys/amd64/amd64/pmap.c | 9 | ||||
-rw-r--r-- | sys/i386/i386/pmap.c | 11 | ||||
-rw-r--r-- | sys/x86/x86/local_apic.c | 2 |
3 files changed, 21 insertions, 1 deletions
diff --git a/sys/amd64/amd64/pmap.c b/sys/amd64/amd64/pmap.c index 8e06ff9..352cb34 100644 --- a/sys/amd64/amd64/pmap.c +++ b/sys/amd64/amd64/pmap.c @@ -1150,6 +1150,15 @@ pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva) eva - sva < PMAP_CLFLUSH_THRESHOLD) { /* + * XXX: Some CPUs fault, hang, or trash the local APIC + * registers if we use CLFLUSH on the local APIC + * range. The local APIC is always uncached, so we + * don't need to flush for that range anyway. + */ + if (pmap_kextract(sva) == lapic_paddr) + return; + + /* * Otherwise, do per-cache line flush. Use the mfence * instruction to insure that previous stores are * included in the write-back. The processor diff --git a/sys/i386/i386/pmap.c b/sys/i386/i386/pmap.c index f14f215..24c8b24 100644 --- a/sys/i386/i386/pmap.c +++ b/sys/i386/i386/pmap.c @@ -96,6 +96,7 @@ __FBSDID("$FreeBSD$"); * and to when physical maps must be made correct. */ +#include "opt_apic.h" #include "opt_cpu.h" #include "opt_pmap.h" #include "opt_smp.h" @@ -1175,6 +1176,16 @@ pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva) else if ((cpu_feature & CPUID_CLFSH) != 0 && eva - sva < PMAP_CLFLUSH_THRESHOLD) { +#ifdef DEV_APIC + /* + * XXX: Some CPUs fault, hang, or trash the local APIC + * registers if we use CLFLUSH on the local APIC + * range. The local APIC is always uncached, so we + * don't need to flush for that range anyway. + */ + if (pmap_kextract(sva) == lapic_paddr) + return; +#endif /* * Otherwise, do per-cache line flush. Use the mfence * instruction to insure that previous stores are diff --git a/sys/x86/x86/local_apic.c b/sys/x86/x86/local_apic.c index e994172..fc85abf3 100644 --- a/sys/x86/x86/local_apic.c +++ b/sys/x86/x86/local_apic.c @@ -227,8 +227,8 @@ lapic_init(vm_paddr_t addr) /* Map the local APIC and setup the spurious interrupt handler. */ KASSERT(trunc_page(addr) == addr, ("local APIC not aligned on a page boundary")); - lapic = pmap_mapdev(addr, sizeof(lapic_t)); lapic_paddr = addr; + lapic = pmap_mapdev(addr, sizeof(lapic_t)); setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_APIC, SEL_KPL, GSEL_APIC); |