MFC r280451:

Remove from legacy ata(4) driver support for hardware, supported by newer
and more functional drivers ahci(4), siis(4) and mvs(4).

This removes about 3400 lines of code, unused since FreeBSD 9.0 release.

20 files changed, 18 insertions, 3391 deletions

diff --git a/sys/arm/mv/files.mv b/sys/arm/mv/files.mv
index d730c01..5d7488a 100644
--- a/sys/arm/mv/files.mv
+++ b/sys/arm/mv/files.mv
@@ -27,7 +27,6 @@ arm/mv/mv_common.c		standard
 arm/mv/mv_localbus.c		standard
 arm/mv/mv_machdep.c		standard
 arm/mv/mv_pci.c			optional	pci
-arm/mv/mv_sata.c		optional	ata | atamvsata
 arm/mv/mv_ts.c			standard
 arm/mv/timer.c			standard
 arm/mv/twsi.c			optional	iicbus
diff --git a/sys/arm/mv/mv_sata.c b/sys/arm/mv/mv_sata.c
deleted file mode 100644
index 3c6d0d5..0000000
--- a/sys/arm/mv/mv_sata.c
+++ /dev/null
@@ -1,877 +0,0 @@
-/*-
- * Copyright (C) 2008-2009 Semihalf
- * All rights reserved.
- *
- * Initial version developed by Ilya Bakulin. Full functionality and bringup
- * by Piotr Ziecik.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/bus.h>
-#include <sys/lock.h>
-#include <sys/resource.h>
-#include <sys/systm.h>
-#include <sys/rman.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/mutex.h>
-#include <sys/endian.h>
-#include <sys/sema.h>
-#include <sys/taskqueue.h>
-#include <vm/uma.h>
-#include <machine/bus.h>
-#include <machine/resource.h>
-
-#include <sys/ata.h>
-#include <dev/ata/ata-all.h>
-#include <dev/ofw/ofw_bus.h>
-#include <dev/ofw/ofw_bus_subr.h>
-
-#include "ata_if.h"
-
-#include "mvreg.h"
-#include "mvvar.h"
-
-/* Useful macros */
-#define EDMA_TIMEOUT		100000 /* 100 ms */
-#define SATA_INL(sc, reg)	ATA_INL((sc)->sc_mem_res, reg)
-#define SATA_OUTL(sc, reg, val)	ATA_OUTL((sc)->sc_mem_res, reg, val)
-
-/* HW-related data structures */
-struct sata_prdentry {
-	uint32_t	prd_addrlo;
-	uint32_t	prd_count;
-	uint32_t	prd_addrhi;
-	uint32_t	prd_reserved;
-};
-
-struct sata_crqb {
-	uint32_t	crqb_prdlo;
-	uint32_t	crqb_prdhi;
-	uint32_t	crqb_flags;
-	uint16_t	crqb_count;
-	uint16_t	crqb_reserved1[2];
-	uint8_t		crqb_ata_command;
-	uint8_t		crqb_ata_feature;
-	uint8_t		crqb_ata_lba_low;
-	uint8_t		crqb_ata_lba_mid;
-	uint8_t		crqb_ata_lba_high;
-	uint8_t		crqb_ata_device;
-	uint8_t		crqb_ata_lba_low_p;
-	uint8_t		crqb_ata_lba_mid_p;
-	uint8_t		crqb_ata_lba_high_p;
-	uint8_t		crqb_ata_feature_p;
-	uint8_t		crqb_ata_count;
-	uint8_t		crqb_ata_count_p;
-	uint16_t	crqb_reserved2;
-};
-
-struct sata_crpb {
-	uint8_t		crpb_tag;
-	uint8_t		crpb_reserved;
-	uint8_t		crpb_edma_status;
-	uint8_t		crpb_dev_status;
-	uint32_t	crpb_timestamp;
-};
-
-/* Identification section. */
-struct sata_softc {
-	device_t		sc_dev;
-	unsigned int		sc_version;
-	unsigned int		sc_edma_qlen;
-	uint32_t		sc_edma_reqis_mask;
-	uint32_t		sc_edma_resos_mask;
-	struct resource		*sc_mem_res;
-	bus_space_tag_t		sc_mem_res_bustag;
-	bus_space_handle_t	sc_mem_res_bushdl;
-	struct resource		*sc_irq_res;
-	void			*sc_irq_cookiep;
-	struct {
-		void	(*function)(void *);
-		void	*argument;
-	} sc_interrupt[SATA_CHAN_NUM];
-};
-
-/* Controller functions */
-static int	sata_probe(device_t dev);
-static int	sata_attach(device_t dev);
-static int	sata_detach(device_t dev);
-static void	sata_intr(void*);
-static struct resource * sata_alloc_resource(device_t dev, device_t child,
-    int type, int *rid, u_long start, u_long end, u_long count, u_int flags);
-static int	sata_release_resource(device_t dev, device_t child, int type,
-    int rid, struct resource *r);
-static int	sata_setup_intr(device_t dev, device_t child,
-    struct resource *irq, int flags, driver_filter_t *filt,
-    driver_intr_t *function, void *argument, void **cookiep);
-static int	sata_teardown_intr(device_t dev, device_t child,
-    struct resource *irq, void *cookie);
-
-/* Channel functions */
-static int	sata_channel_probe(device_t dev);
-static int	sata_channel_attach(device_t dev);
-static int	sata_channel_detach(device_t dev);
-static int	sata_channel_begin_transaction(struct ata_request *request);
-static int	sata_channel_end_transaction(struct ata_request *request);
-static int	sata_channel_status(device_t dev);
-static int	sata_channel_setmode(device_t dev, int target, int mode);
-static int	sata_channel_getrev(device_t dev, int target);
-static void	sata_channel_reset(device_t dev);
-static void	sata_channel_dmasetprd(void *xsc, bus_dma_segment_t *segs,
-    int nsegs, int error);
-
-/* EDMA functions */
-static int	sata_edma_ctrl(device_t dev, int on);
-static int	sata_edma_is_running(device_t);
-
-static device_method_t sata_methods[] = {
-	/* Device method */
-	DEVMETHOD(device_probe,		sata_probe),
-	DEVMETHOD(device_attach,	sata_attach),
-	DEVMETHOD(device_detach,	sata_detach),
-	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	DEVMETHOD(device_suspend,	bus_generic_suspend),
-	DEVMETHOD(device_resume,	bus_generic_resume),
-
-	/* ATA bus methods. */
-	DEVMETHOD(bus_alloc_resource,		sata_alloc_resource),
-	DEVMETHOD(bus_release_resource,		sata_release_resource),
-	DEVMETHOD(bus_activate_resource,	bus_generic_activate_resource),
-	DEVMETHOD(bus_deactivate_resource,	bus_generic_deactivate_resource),
-	DEVMETHOD(bus_setup_intr,		sata_setup_intr),
-	DEVMETHOD(bus_teardown_intr,		sata_teardown_intr),
-	{ 0, 0 },
-};
-
-static driver_t sata_driver = {
-	"sata",
-	sata_methods,
-	sizeof(struct sata_softc),
-};
-
-devclass_t sata_devclass;
-
-DRIVER_MODULE(sata, simplebus, sata_driver, sata_devclass, 0, 0);
-MODULE_VERSION(sata, 1);
-MODULE_DEPEND(sata, ata, 1, 1, 1);
-
-static int
-sata_probe(device_t dev)
-{
-	struct sata_softc *sc;
-	uint32_t d, r;
-
-	if (!ofw_bus_status_okay(dev))
-		return (ENXIO);
-
-	if (!ofw_bus_is_compatible(dev, "mrvl,sata"))
-		return (ENXIO);
-
-	soc_id(&d, &r);
-	sc = device_get_softc(dev);
-
-	switch(d) {
-	case MV_DEV_88F5182:
-		sc->sc_version = 1;
-		sc->sc_edma_qlen = 128;
-		break;
-	case MV_DEV_88F6281:
-	case MV_DEV_88F6282:
-	case MV_DEV_MV78100:
-	case MV_DEV_MV78100_Z0:
-	case MV_DEV_MV78460:
-		sc->sc_version = 2;
-		sc->sc_edma_qlen = 32;
-		break;
-	default:
-		device_printf(dev, "unsupported SoC (ID: 0x%08X)!\n", d);
-		return (ENXIO);
-	}
-
-	sc->sc_edma_reqis_mask = (sc->sc_edma_qlen - 1) << SATA_EDMA_REQIS_OFS;
-	sc->sc_edma_resos_mask = (sc->sc_edma_qlen - 1) << SATA_EDMA_RESOS_OFS;
-
-	device_set_desc(dev, "Marvell Integrated SATA Controller");
-	return (0);
-}
-
-static int
-sata_attach(device_t dev)
-{
-	struct sata_softc *sc;
-	int mem_id, irq_id, error, i;
-	device_t ata_chan;
-	uint32_t reg;
-
-	sc = device_get_softc(dev);
-	sc->sc_dev = dev;
-	mem_id = 0;
-	irq_id = 0;
-
-	/* Allocate resources */
-	sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
-	    &mem_id, RF_ACTIVE);
-	if (sc->sc_mem_res == NULL) {
-		device_printf(dev, "could not allocate memory.\n");
-		return (ENOMEM);
-	}
-
-	sc->sc_mem_res_bustag = rman_get_bustag(sc->sc_mem_res);
-	sc->sc_mem_res_bushdl = rman_get_bushandle(sc->sc_mem_res);
-	KASSERT(sc->sc_mem_res_bustag && sc->sc_mem_res_bushdl,
-	    ("cannot get bus handle or tag."));
-
-	sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irq_id,
-	    RF_ACTIVE);
-	if (sc->sc_irq_res == NULL) {
-		device_printf(dev, "could not allocate IRQ.\n");
-		error = ENOMEM;
-		goto err;
-	}
-
-	error = bus_setup_intr(dev, sc->sc_irq_res,
-	    INTR_TYPE_BIO | INTR_MPSAFE | INTR_ENTROPY,
-	    NULL, sata_intr, sc, &sc->sc_irq_cookiep);
-	if (error != 0) {
-		device_printf(dev, "could not setup interrupt.\n");
-		goto err;
-	}
-
-	/* Attach channels */
-	for (i = 0; i < SATA_CHAN_NUM; i++) {
-		ata_chan = device_add_child(dev, "ata",
-		    devclass_find_free_unit(ata_devclass, 0));
-
-		if (!ata_chan) {
-			device_printf(dev, "cannot add channel %d.\n", i);
-			error = ENOMEM;
-			goto err;
-		}
-	}
-
-	/* Disable interrupt coalescing */
-	reg = SATA_INL(sc, SATA_CR);
-	for (i = 0; i < SATA_CHAN_NUM; i++)
-		reg |= SATA_CR_COALDIS(i);
-
-	/* Disable DMA byte swapping */
-	if (sc->sc_version == 2)
-		reg |= SATA_CR_NODMABS | SATA_CR_NOEDMABS |
-		    SATA_CR_NOPRDPBS;
-
-	SATA_OUTL(sc, SATA_CR, reg);
-
-	/* Clear and mask all interrupts */
-	SATA_OUTL(sc, SATA_ICR, 0);
-	SATA_OUTL(sc, SATA_MIMR, 0);
-
-	return(bus_generic_attach(dev));
-
-err:
-	sata_detach(dev);
-	return (error);
-}
-
-static int
-sata_detach(device_t dev)
-{
-	struct sata_softc *sc;
-
-	sc = device_get_softc(dev);
-
-	if (device_is_attached(dev))
-		bus_generic_detach(dev);
-
-	if (sc->sc_mem_res != NULL) {
-		bus_release_resource(dev, SYS_RES_MEMORY,
-		    rman_get_rid(sc->sc_mem_res), sc->sc_mem_res);
-		sc->sc_mem_res = NULL;
-	}
-
-	if (sc->sc_irq_res != NULL) {
-		bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_cookiep);
-		bus_release_resource(dev, SYS_RES_IRQ,
-		    rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
-		sc->sc_irq_res = NULL;
-	}
-
-	return (0);
-}
-
-static struct resource *
-sata_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
-{
-	struct sata_softc *sc;
-
-	sc = device_get_softc(dev);
-
-	KASSERT(type == SYS_RES_IRQ && *rid == ATA_IRQ_RID,
-	    ("illegal resource request (type %u, rid %u).",
-	    type, *rid));
-
-	return (sc->sc_irq_res);
-}
-
-static int
-sata_release_resource(device_t dev, device_t child, int type, int rid,
-    struct resource *r)
-{
-
-	KASSERT(type == SYS_RES_IRQ && rid == ATA_IRQ_RID,
-	    ("strange type %u and/or rid %u while releasing resource.", type,
-	    rid));
-
-	return (0);
-}
-
-static int
-sata_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
-    driver_filter_t *filt, driver_intr_t *function, void *argument,
-    void **cookiep)
-{
-	struct sata_softc *sc;
-	struct ata_channel *ch;
-
-	sc = device_get_softc(dev);
-	ch = device_get_softc(child);
-
-	if (filt != NULL) {
-		device_printf(dev, "filter interrupts are not supported.\n");
-		return (EINVAL);
-	}
-
-	sc->sc_interrupt[ch->unit].function = function;
-	sc->sc_interrupt[ch->unit].argument = argument;
-	*cookiep = sc;
-
-	return (0);
-}
-
-static int
-sata_teardown_intr(device_t dev, device_t child, struct resource *irq,
-    void *cookie)
-{
-	struct sata_softc *sc;
-	struct ata_channel *ch;
-
-	sc = device_get_softc(dev);
-	ch = device_get_softc(child);
-
-	sc->sc_interrupt[ch->unit].function = NULL;
-	sc->sc_interrupt[ch->unit].argument = NULL;
-
-	return (0);
-}
-
-static void
-sata_intr(void *xsc)
-{
-	struct sata_softc *sc;
-	int unit;
-
-	sc = xsc;
-
-	/*
-	 * Behave like ata_generic_intr() for PCI controllers.
-	 * Simply invoke ISRs on all channels.
-	 */
-	for (unit = 0; unit < SATA_CHAN_NUM; unit++)
-		if (sc->sc_interrupt[unit].function != NULL)
-			sc->sc_interrupt[unit].function(
-			    sc->sc_interrupt[unit].argument);
-}
-
-static int
-sata_channel_probe(device_t dev)
-{
-
-	device_set_desc(dev, "Marvell Integrated SATA Channel");
-	return (ata_probe(dev));
-}
-
-static int
-sata_channel_attach(device_t dev)
-{
-	struct sata_softc *sc;
-	struct ata_channel *ch;
-	uint64_t work;
-	int error, i;
-
-	sc = device_get_softc(device_get_parent(dev));
-	ch = device_get_softc(dev);
-
-	if (ch->attached)
-		return (0);
-
-	ch->dev = dev;
-	ch->unit = device_get_unit(dev);
-	ch->flags |= ATA_USE_16BIT | ATA_NO_SLAVE | ATA_SATA;
-
-	/* Set legacy ATA resources. */
-	for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
-		ch->r_io[i].res = sc->sc_mem_res;
-		ch->r_io[i].offset = SATA_SHADOWR_BASE(ch->unit) + (i << 2);
-	}
-
-	ch->r_io[ATA_CONTROL].res = sc->sc_mem_res;
-	ch->r_io[ATA_CONTROL].offset = SATA_SHADOWR_CONTROL(ch->unit);
-
-	ch->r_io[ATA_IDX_ADDR].res = sc->sc_mem_res;
-	ata_default_registers(dev);
-
-	/* Set SATA resources. */
-	ch->r_io[ATA_SSTATUS].res = sc->sc_mem_res;
-	ch->r_io[ATA_SSTATUS].offset = SATA_SATA_SSTATUS(ch->unit);
-	ch->r_io[ATA_SERROR].res = sc->sc_mem_res;
-	ch->r_io[ATA_SERROR].offset = SATA_SATA_SERROR(ch->unit);
-	ch->r_io[ATA_SCONTROL].res = sc->sc_mem_res;
-	ch->r_io[ATA_SCONTROL].offset = SATA_SATA_SCONTROL(ch->unit);
-	ata_generic_hw(dev);
-
-	ch->hw.begin_transaction = sata_channel_begin_transaction;
-	ch->hw.end_transaction = sata_channel_end_transaction;
-	ch->hw.status = sata_channel_status;
-
-	/* Set DMA resources */
-	ata_dmainit(dev);
-	ch->dma.setprd = sata_channel_dmasetprd;
-
-	/* Clear work area */
-	KASSERT(sc->sc_edma_qlen * (sizeof(struct sata_crqb) +
-	    sizeof(struct sata_crpb)) <= ch->dma.max_iosize,
-	    ("insufficient DMA memory for request/response queues.\n"));
-	bzero(ch->dma.work, sc->sc_edma_qlen * (sizeof(struct sata_crqb) +
-	    sizeof(struct sata_crpb)));
-	bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
-	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
-
-	/* Turn off EDMA engine */
-	error = sata_edma_ctrl(dev, 0);
-	if (error) {
-		ata_dmafini(dev);
-		return (error);
-	}
-
-	/*
-	 * Initialize EDMA engine:
-	 *	- Native Command Queuing off,
-	 *	- Non-Queued operation,
-	 *	- Host Queue Cache enabled.
-	 */
-	SATA_OUTL(sc, SATA_EDMA_CFG(ch->unit), SATA_EDMA_CFG_HQCACHE |
-	    (sc->sc_version == 1) ? SATA_EDMA_CFG_QL128 : 0);
-
-	/* Set request queue pointers */
-	work = ch->dma.work_bus;
-	SATA_OUTL(sc, SATA_EDMA_REQBAHR(ch->unit), work >> 32);
-	SATA_OUTL(sc, SATA_EDMA_REQIPR(ch->unit), work & 0xFFFFFFFF);
-	SATA_OUTL(sc, SATA_EDMA_REQOPR(ch->unit), work & 0xFFFFFFFF);
-
-	/* Set response queue pointers */
-	work += sc->sc_edma_qlen * sizeof(struct sata_crqb);
-	SATA_OUTL(sc, SATA_EDMA_RESBAHR(ch->unit), work >> 32);
-	SATA_OUTL(sc, SATA_EDMA_RESIPR(ch->unit), work & 0xFFFFFFFF);
-	SATA_OUTL(sc, SATA_EDMA_RESOPR(ch->unit), work & 0xFFFFFFFF);
-
-	/* Clear any outstanding interrupts */
-	ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
-	SATA_OUTL(sc, SATA_SATA_FISICR(ch->unit), 0);
-	SATA_OUTL(sc, SATA_EDMA_IECR(ch->unit), 0);
-	SATA_OUTL(sc, SATA_ICR,
-	    ~(SATA_ICR_DEV(ch->unit) | SATA_ICR_DMADONE(ch->unit)));
-
-	/* Umask channel interrupts */
-	SATA_OUTL(sc, SATA_EDMA_IEMR(ch->unit), 0xFFFFFFFF);
-	SATA_OUTL(sc, SATA_MIMR, SATA_INL(sc, SATA_MIMR) |
-	    SATA_MICR_DONE(ch->unit) | SATA_MICR_DMADONE(ch->unit) |
-	    SATA_MICR_ERR(ch->unit));
-
-	ch->attached = 1;
-
-	return (ata_attach(dev));
-}
-
-static int
-sata_channel_detach(device_t dev)
-{
-	struct sata_softc *sc;
-	struct ata_channel *ch;
-	int error;
-
-	sc = device_get_softc(device_get_parent(dev));
-	ch = device_get_softc(dev);
-
-	if (!ch->attached)
-		return (0);
-
-	/* Turn off EDMA engine */
-	sata_edma_ctrl(dev, 0);
-
-	/* Mask chanel interrupts */
-	SATA_OUTL(sc, SATA_EDMA_IEMR(ch->unit), 0);
-	SATA_OUTL(sc, SATA_MIMR, SATA_INL(sc, SATA_MIMR) & ~(
-	    SATA_MICR_DONE(ch->unit) | SATA_MICR_DMADONE(ch->unit) |
-	    SATA_MICR_ERR(ch->unit)));
-
-	error = ata_detach(dev);
-	ata_dmafini(dev);
-
-	ch->attached = 0;
-
-	return (error);
-}
-
-static int
-sata_channel_begin_transaction(struct ata_request *request)
-{
-	struct sata_softc *sc;
-	struct ata_channel *ch;
-	struct sata_crqb *crqb;
-	uint32_t req_in;
-	int error, slot;
-
-	sc = device_get_softc(device_get_parent(request->parent));
-	ch = device_get_softc(request->parent);
-
-	mtx_assert(&ch->state_mtx, MA_OWNED);
-
-	/* Only DMA R/W goes through the EDMA machine. */
-	if (request->u.ata.command != ATA_READ_DMA &&
-	    request->u.ata.command != ATA_WRITE_DMA &&
-	    request->u.ata.command != ATA_READ_DMA48 &&
-	    request->u.ata.command != ATA_WRITE_DMA48) {
-
-		/* Disable EDMA before accessing legacy registers */
-		if (sata_edma_is_running(request->parent)) {
-			error = sata_edma_ctrl(request->parent, 0);
-			if (error) {
-				request->result = error;
-				return (ATA_OP_FINISHED);
-			}
-		}
-
-		return (ata_begin_transaction(request));
-	}
-
-	/* Prepare data for DMA */
-	if ((error = ch->dma.load(request, NULL, NULL))) {
-		device_printf(request->parent, "setting up DMA failed!\n");
-		request->result = error;
-		return ATA_OP_FINISHED;
-	}
-
-	/* Get next free queue slot */
-	req_in = SATA_INL(sc, SATA_EDMA_REQIPR(ch->unit));
-	slot = (req_in & sc->sc_edma_reqis_mask) >> SATA_EDMA_REQIS_OFS;
-	crqb = (struct sata_crqb *)(ch->dma.work +
-	    (slot << SATA_EDMA_REQIS_OFS));
-
-	/* Fill in request */
-	bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
-	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
-
-	crqb->crqb_prdlo = htole32((uint64_t)request->dma->sg_bus & 0xFFFFFFFF);
-	crqb->crqb_prdhi = htole32((uint64_t)request->dma->sg_bus >> 32);
-	crqb->crqb_flags = htole32((request->flags & ATA_R_READ ? 0x01 : 0x00) |
-	    (request->tag << 1));
-
-	crqb->crqb_ata_command = request->u.ata.command;
-	crqb->crqb_ata_feature = request->u.ata.feature;
-	crqb->crqb_ata_lba_low = request->u.ata.lba;
-	crqb->crqb_ata_lba_mid = request->u.ata.lba >> 8;
-	crqb->crqb_ata_lba_high = request->u.ata.lba >> 16;
-	crqb->crqb_ata_device = ((request->u.ata.lba >> 24) & 0x0F) | (1 << 6);
-	crqb->crqb_ata_lba_low_p = request->u.ata.lba >> 24;
-	crqb->crqb_ata_lba_mid_p = request->u.ata.lba >> 32;
-	crqb->crqb_ata_lba_high_p = request->u.ata.lba >> 40;
-	crqb->crqb_ata_feature_p = request->u.ata.feature >> 8;
-	crqb->crqb_ata_count = request->u.ata.count;
-	crqb->crqb_ata_count_p = request->u.ata.count >> 8;
-
-	bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
-	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
-
-	/* Enable EDMA if disabled */
-	if (!sata_edma_is_running(request->parent)) {
-		error = sata_edma_ctrl(request->parent, 1);
-		if (error) {
-			ch->dma.unload(request);
-			request->result = error;
-			return (ATA_OP_FINISHED);
-		}
-	}
-
-	/* Tell EDMA about new request */
-	req_in = (req_in & ~sc->sc_edma_reqis_mask) | (((slot + 1) <<
-	    SATA_EDMA_REQIS_OFS) & sc->sc_edma_reqis_mask);
-
-	SATA_OUTL(sc, SATA_EDMA_REQIPR(ch->unit), req_in);
-
-	return (ATA_OP_CONTINUES);
-}
-
-static int
-sata_channel_end_transaction(struct ata_request *request)
-{
-	struct sata_softc *sc;
-	struct ata_channel *ch;
-	struct sata_crpb *crpb;
-	uint32_t res_in, res_out, icr;
-	int slot;
-
-	sc = device_get_softc(device_get_parent(request->parent));
-	ch = device_get_softc(request->parent);
-
-	mtx_assert(&ch->state_mtx, MA_OWNED);
-
-	icr = SATA_INL(sc, SATA_ICR);
-	if (icr & SATA_ICR_DMADONE(ch->unit)) {
-		/* Get current response slot */
-		res_out = SATA_INL(sc, SATA_EDMA_RESOPR(ch->unit));
-		slot = (res_out & sc->sc_edma_resos_mask) >>
-		    SATA_EDMA_RESOS_OFS;
-		crpb = (struct sata_crpb *)(ch->dma.work +
-		    (sc->sc_edma_qlen * sizeof(struct sata_crqb)) +
-		    (slot << SATA_EDMA_RESOS_OFS));
-
-		/* Record this request status */
-		bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
-		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
-
-		request->status = crpb->crpb_dev_status;
-		request->error = 0;
-
-		bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
-		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
-
-		/* Update response queue pointer */
-		res_out = (res_out & ~sc->sc_edma_resos_mask) | (((slot + 1) <<
-		    SATA_EDMA_RESOS_OFS) & sc->sc_edma_resos_mask);
-
-		SATA_OUTL(sc, SATA_EDMA_RESOPR(ch->unit), res_out);
-
-		/* Ack DMA interrupt if there is nothing more to do */
-		res_in = SATA_INL(sc, SATA_EDMA_RESIPR(ch->unit));
-		res_in &= sc->sc_edma_resos_mask;
-		res_out &= sc->sc_edma_resos_mask;
-
-		if (res_in == res_out)
-			SATA_OUTL(sc, SATA_ICR,
-			    ~SATA_ICR_DMADONE(ch->unit));
-
-		/* Update progress */
-		if (!(request->status & ATA_S_ERROR) &&
-		    !(request->flags & ATA_R_TIMEOUT))
-			request->donecount = request->bytecount;
-
-		/* Unload DMA data */
-		ch->dma.unload(request);
-
-		return(ATA_OP_FINISHED);
-	}
-
-	/* Legacy ATA interrupt */
-	return (ata_end_transaction(request));
-}
-
-static int
-sata_channel_status(device_t dev)
-{
-	struct sata_softc *sc;
-	struct ata_channel *ch;
-	uint32_t icr, iecr;
-
-	sc = device_get_softc(device_get_parent(dev));
-	ch = device_get_softc(dev);
-
-	icr = SATA_INL(sc, SATA_ICR);
-	iecr = SATA_INL(sc, SATA_EDMA_IECR(ch->unit));
-
-	if ((icr & SATA_ICR_DEV(ch->unit)) || iecr) {
-		/* Disable EDMA before accessing SATA registers */
-		sata_edma_ctrl(dev, 0);
-		ata_sata_phy_check_events(dev, -1);
-
-		/* Ack device and error interrupt */
-		SATA_OUTL(sc, SATA_ICR, ~SATA_ICR_DEV(ch->unit));
-		SATA_OUTL(sc, SATA_EDMA_IECR(ch->unit), 0);
-	}
-
-	icr &= SATA_ICR_DEV(ch->unit) | SATA_ICR_DMADONE(ch->unit);
-	return (icr);
-}
-
-static void
-sata_channel_reset(device_t dev)
-{
-	struct sata_softc *sc;
-	struct ata_channel *ch;
-
-	sc = device_get_softc(device_get_parent(dev));
-	ch = device_get_softc(dev);
-
-	/* Disable EDMA before using legacy registers */
-	sata_edma_ctrl(dev, 0);
-
-	/* Mask all EDMA interrups */
-	SATA_OUTL(sc, SATA_EDMA_IEMR(ch->unit), 0);
-
-	/* Reset EDMA */
-	SATA_OUTL(sc, SATA_EDMA_CMD(ch->unit), SATA_EDMA_CMD_RESET);
-	DELAY(25);
-	SATA_OUTL(sc, SATA_EDMA_CMD(ch->unit), 0);
-
-	/* Reset PHY and device */
-	if (ata_sata_phy_reset(dev, -1, 1))
-		ata_generic_reset(dev);
-	else
-		ch->devices = 0;
-
-	/* Clear EDMA errors */
-	SATA_OUTL(sc, SATA_SATA_FISICR(ch->unit), 0);
-	SATA_OUTL(sc, SATA_EDMA_IECR(ch->unit), 0);
-
-	/* Unmask all EDMA interrups */
-	SATA_OUTL(sc, SATA_EDMA_IEMR(ch->unit), 0xFFFFFFFF);
-}
-
-static int
-sata_channel_setmode(device_t parent, int target, int mode)
-{
-
-	/* Disable EDMA before using legacy registers */
-	sata_edma_ctrl(parent, 0);
-	return (ata_sata_setmode(parent, target, mode));
-}
-
-static int
-sata_channel_getrev(device_t parent, int target)
-{
-
-	/* Disable EDMA before using legacy registers */
-	sata_edma_ctrl(parent, 0);
-	return (ata_sata_getrev(parent, target));
-}
-
-static void
-sata_channel_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs,
-    int error)
-{
-	struct ata_dmasetprd_args *args;
-	struct sata_prdentry *prd;
-	int i;
-
-	args = xsc;
-	prd = args->dmatab;
-
-	if ((args->error = error))
-		return;
-
-	for (i = 0; i < nsegs; i++) {
-		prd[i].prd_addrlo = htole32(segs[i].ds_addr);
-		prd[i].prd_addrhi = htole32((uint64_t)segs[i].ds_addr >> 32);
-		prd[i].prd_count = htole32(segs[i].ds_len);
-	}
-
-	prd[i - 1].prd_count |= htole32(ATA_DMA_EOT);
-	KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries.\n"));
-	args->nsegs = nsegs;
-}
-
-static int
-sata_edma_ctrl(device_t dev, int on)
-{
-	struct sata_softc *sc;
-	struct ata_channel *ch;
-	int bit, timeout;
-	uint32_t reg;
-
-	sc = device_get_softc(device_get_parent(dev));
-	ch = device_get_softc(dev);
-	bit = on ? SATA_EDMA_CMD_ENABLE : SATA_EDMA_CMD_DISABLE;
-	timeout = EDMA_TIMEOUT;
-
-	SATA_OUTL(sc, SATA_EDMA_CMD(ch->unit), bit);
-
-	while (1) {
-		DELAY(1);
-
-		reg = SATA_INL(sc, SATA_EDMA_CMD(ch->unit));
-
-		/* Enable bit will be 1 after disable command completion */
-		if (on && (reg & SATA_EDMA_CMD_ENABLE))
-			break;
-
-		/* Disable bit will be 0 after disable command completion */
-		if (!on && !(reg & SATA_EDMA_CMD_DISABLE))
-			break;
-
-		if (timeout-- <= 0) {
-			device_printf(dev, "EDMA command timeout!\n");
-			return (ETIMEDOUT);
-		}
-	}
-
-	return (0);
-}
-
-static int
-sata_edma_is_running(device_t dev)
-{
-	struct sata_softc *sc;
-	struct ata_channel *ch;
-
-	sc = device_get_softc(device_get_parent(dev));
-	ch = device_get_softc(dev);
-
-	return (SATA_INL(sc, SATA_EDMA_CMD(ch->unit)) & SATA_EDMA_CMD_ENABLE);
-}
-
-static device_method_t sata_channel_methods[] = {
-	/* Device interface. */
-	DEVMETHOD(device_probe,		sata_channel_probe),
-	DEVMETHOD(device_attach,	sata_channel_attach),
-	DEVMETHOD(device_detach,	sata_channel_detach),
-	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
-	DEVMETHOD(device_suspend,	ata_suspend),
-	DEVMETHOD(device_resume,	ata_resume),
-
-	/* ATA channel interface */
-	DEVMETHOD(ata_reset,		sata_channel_reset),
-	DEVMETHOD(ata_setmode,		sata_channel_setmode),
-	DEVMETHOD(ata_getrev,		sata_channel_getrev),
-	{ 0, 0 }
-};
-
-driver_t sata_channel_driver = {
-	"ata",
-	sata_channel_methods,
-	sizeof(struct ata_channel),
-};
-
-DRIVER_MODULE(ata, sata, sata_channel_driver, ata_devclass, 0, 0);
diff --git a/sys/boot/forth/loader.conf b/sys/boot/forth/loader.conf
index 425e671..3499b892 100644
--- a/sys/boot/forth/loader.conf
+++ b/sys/boot/forth/loader.conf
@@ -149,10 +149,8 @@ module_path="/boot/modules"	# Set the module search path
 ### ATA modules ##############################################
 ##############################################################
 
-ataahci_load="NO"		# AHCI SATA
 ataacard_load="NO"		# ACARD
 ataacerlabs_load="NO"		# Acer Labs Inc. (ALI)
-ataadaptec_load="NO"		# Adaptec
 ataamd_load="NO"		# American Micro Devices (AMD)
 ataati_load="NO"		# ATI
 atacenatek_load="NO"		# Cenatek
diff --git a/sys/conf/NOTES b/sys/conf/NOTES
index 2c3c6eb..0792681 100644
--- a/sys/conf/NOTES
+++ b/sys/conf/NOTES
@@ -1719,10 +1719,8 @@ device		ata
 #device		atapci		# PCI bus support; only generic chipset support
 
 # PCI ATA chipsets
-#device		ataahci		# AHCI SATA
 #device		ataacard	# ACARD
 #device		ataacerlabs	# Acer Labs Inc. (ALI)
-#device		ataadaptec	# Adaptec
 #device		ataamd		# American Micro Devices (AMD)
 #device		ataati		# ATI
 #device		atacenatek	# Cenatek
diff --git a/sys/conf/files b/sys/conf/files
index d51cb86..6144019 100644
--- a/sys/conf/files
+++ b/sys/conf/files
@@ -680,12 +680,8 @@ dev/ata/ata-card.c		optional ata pccard | atapccard
 dev/ata/ata-cbus.c		optional ata pc98 | atapc98
 dev/ata/ata-isa.c		optional ata isa | ataisa
 dev/ata/ata-pci.c		optional ata pci | atapci
-dev/ata/chipsets/ata-ahci.c	optional ata pci | ataahci | ataacerlabs | \
-					 ataati | ataintel | atajmicron | \
-					 atavia | atanvidia
 dev/ata/chipsets/ata-acard.c	optional ata pci | ataacard
 dev/ata/chipsets/ata-acerlabs.c	optional ata pci | ataacerlabs
-dev/ata/chipsets/ata-adaptec.c	optional ata pci | ataadaptec
 dev/ata/chipsets/ata-amd.c	optional ata pci | ataamd
 dev/ata/chipsets/ata-ati.c	optional ata pci | ataati
 dev/ata/chipsets/ata-cenatek.c	optional ata pci | atacenatek
@@ -695,7 +691,7 @@ dev/ata/chipsets/ata-highpoint.c	optional ata pci | atahighpoint
 dev/ata/chipsets/ata-intel.c	optional ata pci | ataintel
 dev/ata/chipsets/ata-ite.c	optional ata pci | ataite
 dev/ata/chipsets/ata-jmicron.c	optional ata pci | atajmicron
-dev/ata/chipsets/ata-marvell.c	optional ata pci | atamarvell | ataadaptec
+dev/ata/chipsets/ata-marvell.c	optional ata pci | atamarvell
 dev/ata/chipsets/ata-micron.c	optional ata pci | atamicron
 dev/ata/chipsets/ata-national.c	optional ata pci | atanational
 dev/ata/chipsets/ata-netcell.c	optional ata pci | atanetcell
diff --git a/sys/dev/ata/ata-all.h b/sys/dev/ata/ata-all.h
index c9e666c..19cb7ef 100644
--- a/sys/dev/ata/ata-all.h
+++ b/sys/dev/ata/ata-all.h
@@ -150,139 +150,6 @@
 
 #define ATA_SACTIVE                     16
 
-/* SATA AHCI v1.0 register defines */
-#define ATA_AHCI_CAP                    0x00
-#define		ATA_AHCI_CAP_NPMASK	0x0000001f
-#define		ATA_AHCI_CAP_SXS	0x00000020
-#define		ATA_AHCI_CAP_EMS	0x00000040
-#define		ATA_AHCI_CAP_CCCS	0x00000080
-#define		ATA_AHCI_CAP_NCS	0x00001F00
-#define		ATA_AHCI_CAP_NCS_SHIFT	8
-#define		ATA_AHCI_CAP_PSC	0x00002000
-#define		ATA_AHCI_CAP_SSC	0x00004000
-#define		ATA_AHCI_CAP_PMD	0x00008000
-#define		ATA_AHCI_CAP_FBSS	0x00010000
-#define		ATA_AHCI_CAP_SPM	0x00020000
-#define		ATA_AHCI_CAP_SAM	0x00080000
-#define		ATA_AHCI_CAP_ISS	0x00F00000
-#define		ATA_AHCI_CAP_ISS_SHIFT	20
-#define		ATA_AHCI_CAP_SCLO	0x01000000
-#define		ATA_AHCI_CAP_SAL	0x02000000
-#define		ATA_AHCI_CAP_SALP	0x04000000
-#define		ATA_AHCI_CAP_SSS	0x08000000
-#define		ATA_AHCI_CAP_SMPS	0x10000000
-#define		ATA_AHCI_CAP_SSNTF	0x20000000
-#define		ATA_AHCI_CAP_SNCQ	0x40000000
-#define		ATA_AHCI_CAP_64BIT	0x80000000
-
-#define ATA_AHCI_GHC                    0x04
-#define         ATA_AHCI_GHC_AE         0x80000000
-#define         ATA_AHCI_GHC_IE         0x00000002
-#define         ATA_AHCI_GHC_HR         0x00000001
-
-#define ATA_AHCI_IS                     0x08
-#define ATA_AHCI_PI                     0x0c
-#define ATA_AHCI_VS                     0x10
-
-#define ATA_AHCI_OFFSET                 0x80
-
-#define ATA_AHCI_P_CLB                  0x100
-#define ATA_AHCI_P_CLBU                 0x104
-#define ATA_AHCI_P_FB                   0x108
-#define ATA_AHCI_P_FBU                  0x10c
-#define ATA_AHCI_P_IS                   0x110
-#define ATA_AHCI_P_IE                   0x114
-#define         ATA_AHCI_P_IX_DHR       0x00000001
-#define         ATA_AHCI_P_IX_PS        0x00000002
-#define         ATA_AHCI_P_IX_DS        0x00000004
-#define         ATA_AHCI_P_IX_SDB       0x00000008
-#define         ATA_AHCI_P_IX_UF        0x00000010
-#define         ATA_AHCI_P_IX_DP        0x00000020
-#define         ATA_AHCI_P_IX_PC        0x00000040
-#define         ATA_AHCI_P_IX_DI        0x00000080
-
-#define         ATA_AHCI_P_IX_PRC       0x00400000
-#define         ATA_AHCI_P_IX_IPM       0x00800000
-#define         ATA_AHCI_P_IX_OF        0x01000000
-#define         ATA_AHCI_P_IX_INF       0x04000000
-#define         ATA_AHCI_P_IX_IF        0x08000000
-#define         ATA_AHCI_P_IX_HBD       0x10000000
-#define         ATA_AHCI_P_IX_HBF       0x20000000
-#define         ATA_AHCI_P_IX_TFE       0x40000000
-#define         ATA_AHCI_P_IX_CPD       0x80000000
-
-#define ATA_AHCI_P_CMD                  0x118
-#define         ATA_AHCI_P_CMD_ST       0x00000001
-#define         ATA_AHCI_P_CMD_SUD      0x00000002
-#define         ATA_AHCI_P_CMD_POD      0x00000004
-#define         ATA_AHCI_P_CMD_CLO      0x00000008
-#define         ATA_AHCI_P_CMD_FRE      0x00000010
-#define         ATA_AHCI_P_CMD_CCS_MASK 0x00001f00
-#define         ATA_AHCI_P_CMD_ISS      0x00002000
-#define         ATA_AHCI_P_CMD_FR       0x00004000
-#define         ATA_AHCI_P_CMD_CR       0x00008000
-#define         ATA_AHCI_P_CMD_CPS      0x00010000
-#define         ATA_AHCI_P_CMD_PMA      0x00020000
-#define         ATA_AHCI_P_CMD_HPCP     0x00040000
-#define         ATA_AHCI_P_CMD_ISP      0x00080000
-#define         ATA_AHCI_P_CMD_CPD      0x00100000
-#define         ATA_AHCI_P_CMD_ATAPI    0x01000000
-#define         ATA_AHCI_P_CMD_DLAE     0x02000000
-#define         ATA_AHCI_P_CMD_ALPE     0x04000000
-#define         ATA_AHCI_P_CMD_ASP      0x08000000
-#define         ATA_AHCI_P_CMD_ICC_MASK 0xf0000000
-#define         ATA_AHCI_P_CMD_NOOP     0x00000000
-#define         ATA_AHCI_P_CMD_ACTIVE   0x10000000
-#define         ATA_AHCI_P_CMD_PARTIAL  0x20000000
-#define         ATA_AHCI_P_CMD_SLUMBER  0x60000000
-
-#define ATA_AHCI_P_TFD                  0x120
-#define ATA_AHCI_P_SIG                  0x124
-#define ATA_AHCI_P_SSTS                 0x128
-#define ATA_AHCI_P_SCTL                 0x12c
-#define ATA_AHCI_P_SERR                 0x130
-#define ATA_AHCI_P_SACT                 0x134
-#define ATA_AHCI_P_CI                   0x138
-#define ATA_AHCI_P_SNTF                 0x13C
-#define ATA_AHCI_P_FBS                  0x140
-
-#define ATA_AHCI_CL_SIZE                32
-#define ATA_AHCI_CL_OFFSET              0
-#define ATA_AHCI_FB_OFFSET              (ATA_AHCI_CL_SIZE * 32)
-#define ATA_AHCI_CT_OFFSET              (ATA_AHCI_FB_OFFSET + 4096)
-#define ATA_AHCI_CT_SIZE                (2176 + 128)
-
-struct ata_ahci_dma_prd {
-    u_int64_t                   dba;
-    u_int32_t                   reserved;
-    u_int32_t                   dbc;            /* 0 based */
-#define ATA_AHCI_PRD_MASK       0x003fffff      /* max 4MB */
-#define ATA_AHCI_PRD_IPC        (1<<31)
-} __packed;
-
-struct ata_ahci_cmd_tab {
-    u_int8_t                    cfis[64];
-    u_int8_t                    acmd[32];
-    u_int8_t                    reserved[32];
-#define ATA_AHCI_DMA_ENTRIES            129
-    struct ata_ahci_dma_prd     prd_tab[ATA_AHCI_DMA_ENTRIES];
-} __packed;
-
-struct ata_ahci_cmd_list {
-    u_int16_t                   cmd_flags;
-#define ATA_AHCI_CMD_ATAPI		0x0020
-#define ATA_AHCI_CMD_WRITE		0x0040
-#define ATA_AHCI_CMD_PREFETCH		0x0080
-#define ATA_AHCI_CMD_RESET		0x0100
-#define ATA_AHCI_CMD_BIST		0x0200
-#define ATA_AHCI_CMD_CLR_BUSY		0x0400
-
-    u_int16_t                   prd_length;     /* PRD entries */
-    u_int32_t                   bytecount;
-    u_int64_t                   cmd_table_phys; /* 128byte aligned */
-} __packed;
-
-
 /* DMA register defines */
 #define ATA_DMA_ENTRIES                 256
 #define ATA_DMA_EOT                     0x80000000
diff --git a/sys/dev/ata/ata-pci.h b/sys/dev/ata/ata-pci.h
index c8942d1..7872e95 100644
--- a/sys/dev/ata/ata-pci.h
+++ b/sys/dev/ata/ata-pci.h
@@ -169,93 +169,49 @@ struct ata_pci_controller {
 #define ATA_I6300ESB_R1         0x25b08086
 #define ATA_I63XXESB2           0x269e8086
 #define ATA_I63XXESB2_S1        0x26808086
-#define ATA_I63XXESB2_S2        0x26818086
-#define ATA_I63XXESB2_R1        0x26828086
-#define ATA_I63XXESB2_R2        0x26838086
 #define ATA_I82801FB            0x266f8086
 #define ATA_I82801FB_S1         0x26518086
 #define ATA_I82801FB_R1         0x26528086
 #define ATA_I82801FBM           0x26538086
 #define ATA_I82801GB            0x27df8086
 #define ATA_I82801GB_S1         0x27c08086
-#define ATA_I82801GB_AH         0x27c18086
-#define ATA_I82801GB_R1         0x27c38086
 #define ATA_I82801GBM_S1        0x27c48086
-#define ATA_I82801GBM_AH        0x27c58086
-#define ATA_I82801GBM_R1        0x27c68086
 #define ATA_I82801HB_S1         0x28208086
-#define ATA_I82801HB_AH6        0x28218086
-#define ATA_I82801HB_R1         0x28228086
-#define ATA_I82801HB_AH4        0x28248086
 #define ATA_I82801HB_S2         0x28258086
 #define ATA_I82801HBM           0x28508086
 #define ATA_I82801HBM_S1        0x28288086
-#define ATA_I82801HBM_S2        0x28298086
-#define ATA_I82801HBM_S3        0x282a8086
 #define ATA_I82801IB_S1         0x29208086
 #define ATA_I82801IB_S3         0x29218086
-#define ATA_I82801IB_AH6        0x29228086
-#define ATA_I82801IB_AH4        0x29238086
 #define ATA_I82801IB_R1         0x29258086
 #define ATA_I82801IB_S2         0x29268086
 #define ATA_I82801IBM_S1        0x29288086
-#define ATA_I82801IBM_AH        0x29298086
-#define ATA_I82801IBM_R1        0x292a8086
 #define ATA_I82801IBM_S2        0x292d8086
 #define ATA_I82801JIB_S1        0x3a208086
-#define ATA_I82801JIB_AH        0x3a228086
-#define ATA_I82801JIB_R1        0x3a258086
 #define ATA_I82801JIB_S2        0x3a268086
 #define ATA_I82801JD_S1         0x3a008086
-#define ATA_I82801JD_AH         0x3a028086
-#define ATA_I82801JD_R1         0x3a058086
 #define ATA_I82801JD_S2         0x3a068086
 #define ATA_I82801JI_S1         0x3a208086
-#define ATA_I82801JI_AH         0x3a228086
-#define ATA_I82801JI_R1         0x3a258086
 #define ATA_I82801JI_S2         0x3a268086
 
 #define ATA_5Series_S1          0x3b208086
 #define ATA_5Series_S2          0x3b218086
-#define ATA_5Series_AH1         0x3b228086
-#define ATA_5Series_AH2         0x3b238086
-#define ATA_5Series_R1          0x3b258086
 #define ATA_5Series_S3          0x3b268086
 #define ATA_5Series_S4          0x3b288086
-#define ATA_5Series_AH3         0x3b298086
-#define ATA_5Series_R2          0x3b2c8086
 #define ATA_5Series_S5          0x3b2d8086
 #define ATA_5Series_S6          0x3b2e8086
-#define ATA_5Series_AH4         0x3b2f8086
 
 #define ATA_CPT_S1              0x1c008086
 #define ATA_CPT_S2              0x1c018086
-#define ATA_CPT_AH1             0x1c028086
-#define ATA_CPT_AH2             0x1c038086
-#define ATA_CPT_R1              0x1c048086
-#define ATA_CPT_R2              0x1c058086
 #define ATA_CPT_S3              0x1c088086
 #define ATA_CPT_S4              0x1c098086
 
 #define ATA_PBG_S1		0x1d008086
-#define ATA_PBG_AH1		0x1d028086
-#define ATA_PBG_R1		0x1d048086
-#define ATA_PBG_R2		0x1d068086
-#define ATA_PBG_R3		0x28268086
 #define ATA_PBG_S2		0x1d088086
 
 #define ATA_PPT_S1		0x1e008086
 #define ATA_PPT_S2		0x1e018086
-#define ATA_PPT_AH1		0x1e028086
-#define ATA_PPT_AH2		0x1e038086
-#define ATA_PPT_R1		0x1e048086
-#define ATA_PPT_R2		0x1e058086
-#define ATA_PPT_R3		0x1e068086
-#define ATA_PPT_R4		0x1e078086
 #define ATA_PPT_S3		0x1e088086
 #define ATA_PPT_S4		0x1e098086
-#define ATA_PPT_R5		0x1e0e8086
-#define ATA_PPT_R6		0x1e0f8086
 
 #define ATA_AVOTON_S1		0x1f208086
 #define ATA_AVOTON_S2		0x1f218086
@@ -264,29 +220,13 @@ struct ata_pci_controller {
 
 #define ATA_LPT_S1		0x8c008086
 #define ATA_LPT_S2		0x8c018086
-#define ATA_LPT_AH1		0x8c028086
-#define ATA_LPT_AH2		0x8c038086
-#define ATA_LPT_R1		0x8c048086
-#define ATA_LPT_R2		0x8c058086
-#define ATA_LPT_R3		0x8c068086
-#define ATA_LPT_R4		0x8c078086
 #define ATA_LPT_S3		0x8c088086
 #define ATA_LPT_S4		0x8c098086
-#define ATA_LPT_R5		0x8c0e8086
-#define ATA_LPT_R6		0x8c0f8086
 
 #define ATA_WCPT_S1		0x8c808086
 #define ATA_WCPT_S2		0x8c818086
-#define ATA_WCPT_AH1		0x8c828086
-#define ATA_WCPT_AH2		0x8c838086
-#define ATA_WCPT_R1		0x8c848086
-#define ATA_WCPT_R2		0x8c858086
-#define ATA_WCPT_R3		0x8c868086
-#define ATA_WCPT_R4		0x8c878086
 #define ATA_WCPT_S3		0x8c888086
 #define ATA_WCPT_S4		0x8c898086
-#define ATA_WCPT_R5		0x8c8e8086
-#define ATA_WCPT_R6		0x8c8f8086
 
 #define ATA_WELLS_S1		0x8d008086
 #define ATA_WELLS_S2		0x8d088086
@@ -300,9 +240,7 @@ struct ata_pci_controller {
 
 #define ATA_I31244              0x32008086
 #define ATA_ISCH                0x811a8086
-#define ATA_DH89XXCC            0x23238086
 
-#define ATA_COLETOCRK_AH1       0x23a38086
 #define ATA_COLETOCRK_S1        0x23a18086
 #define ATA_COLETOCRK_S2        0x23a68086
 
@@ -322,14 +260,6 @@ struct ata_pci_controller {
 #define ATA_JMB368_2            0x0368197b
 
 #define ATA_MARVELL_ID          0x11ab
-#define ATA_M88SX5040           0x504011ab
-#define ATA_M88SX5041           0x504111ab
-#define ATA_M88SX5080           0x508011ab
-#define ATA_M88SX5081           0x508111ab
-#define ATA_M88SX6041           0x604111ab
-#define ATA_M88SX6042           0x604211ab
-#define ATA_M88SX6081           0x608111ab
-#define ATA_M88SX7042           0x704211ab
 #define ATA_M88SE6101           0x610111ab
 #define ATA_M88SE6102           0x610211ab
 #define ATA_M88SE6111           0x611111ab
@@ -505,10 +435,6 @@ struct ata_pci_controller {
 #define ATA_SII3512             0x35121095
 #define ATA_SII3112             0x31121095
 #define ATA_SII3112_1           0x02401095
-#define ATA_SII3124		0x31241095
-#define ATA_SII3132		0x31321095
-#define ATA_SII3132_1		0x02421095
-#define ATA_SII3132_2		0x02441095
 #define ATA_SII0680             0x06801095
 #define ATA_CMD646              0x06461095
 #define ATA_CMD648              0x06481095
@@ -631,8 +557,6 @@ const struct ata_chip_id *ata_find_chip(device_t dev, const struct ata_chip_id *
 int ata_mode2idx(int mode);
 
 /* global prototypes from chipsets/ata-*.c */
-int ata_ahci_chipinit(device_t);
-int ata_marvell_edma_chipinit(device_t);
 int ata_sii_chipinit(device_t);
 
 /* externs */
diff --git a/sys/dev/ata/chipsets/ata-acerlabs.c b/sys/dev/ata/chipsets/ata-acerlabs.c
index cb30e63..3aab779 100644
--- a/sys/dev/ata/chipsets/ata-acerlabs.c
+++ b/sys/dev/ata/chipsets/ata-acerlabs.c
@@ -117,11 +117,6 @@ ata_ali_chipinit(device_t dev)
 	ctlr->setmode = ata_sata_setmode;
 	ctlr->getrev = ata_sata_getrev;
 
-	/* AHCI mode is correctly supported only on the ALi 5288. */
-	if ((ctlr->chip->chipid == ATA_ALI_5288) &&
-	    (ata_ahci_chipinit(dev) != ENXIO))
-            return 0;
-
 	/* Allocate resources for later use by channel attach routines. */
 	res = malloc(sizeof(struct ali_sata_resources), M_ATAPCI, M_WAITOK);
 	for (i = 0; i < 4; i++) {
@@ -347,4 +342,3 @@ ata_ali_setmode(device_t dev, int target, int mode)
 }
 
 ATA_DECLARE_DRIVER(ata_ali);
-MODULE_DEPEND(ata_ali, ata_ahci, 1, 1, 1);
diff --git a/sys/dev/ata/chipsets/ata-adaptec.c b/sys/dev/ata/chipsets/ata-adaptec.c
deleted file mode 100644
index 8654af3..0000000
--- a/sys/dev/ata/chipsets/ata-adaptec.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*-
- * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer,
- *    without modification, immediately at the beginning of the file.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/module.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/ata.h>
-#include <sys/bus.h>
-#include <sys/endian.h>
-#include <sys/malloc.h>
-#include <sys/lock.h>
-#include <sys/mutex.h>
-#include <sys/sema.h>
-#include <sys/taskqueue.h>
-#include <vm/uma.h>
-#include <machine/stdarg.h>
-#include <machine/resource.h>
-#include <machine/bus.h>
-#include <sys/rman.h>
-#include <dev/pci/pcivar.h>
-#include <dev/pci/pcireg.h>
-#include <dev/ata/ata-all.h>
-#include <dev/ata/ata-pci.h>
-#include <ata_if.h>
-
-/* misc defines */
-#define MV_60XX		60		//must match ata_marvell.c's definition
-#define MV_7042		72		//must match ata_marvell.c's definition
-
-/*
- * Adaptec chipset support functions
- */
-static int
-ata_adaptec_probe(device_t dev)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(dev);
-    static const struct ata_chip_id ids[] =
-    {{ ATA_ADAPTEC_1420, 0, 4, MV_60XX, ATA_SA300, "1420SA" },
-     { ATA_ADAPTEC_1430, 0, 4, MV_7042, ATA_SA300, "1430SA" },
-     { 0, 0, 0, 0, 0, 0}};
-
-    if (pci_get_vendor(dev) != ATA_ADAPTEC_ID)
-	return ENXIO;
-
-    if (!(ctlr->chip = ata_match_chip(dev, ids)))
-	return ENXIO;
-
-    ata_set_desc(dev);
-    ctlr->chipinit = ata_marvell_edma_chipinit;
-
-    return (BUS_PROBE_LOW_PRIORITY);
-}
-
-ATA_DECLARE_DRIVER(ata_adaptec);
-MODULE_DEPEND(ata_adaptec, ata_marvell, 1, 1, 1);
diff --git a/sys/dev/ata/chipsets/ata-ahci.c b/sys/dev/ata/chipsets/ata-ahci.c
deleted file mode 100644
index e0e7f3a..0000000
--- a/sys/dev/ata/chipsets/ata-ahci.c
+++ /dev/null
@@ -1,1068 +0,0 @@
-/*-
- * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer,
- *    without modification, immediately at the beginning of the file.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/module.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/ata.h>
-#include <sys/bus.h>
-#include <sys/endian.h>
-#include <sys/malloc.h>
-#include <sys/lock.h>
-#include <sys/mutex.h>
-#include <sys/sema.h>
-#include <sys/taskqueue.h>
-#include <vm/uma.h>
-#include <machine/stdarg.h>
-#include <machine/resource.h>
-#include <machine/bus.h>
-#include <sys/rman.h>
-#include <dev/pci/pcivar.h>
-#include <dev/pci/pcireg.h>
-#include <dev/ata/ata-all.h>
-#include <dev/ata/ata-pci.h>
-#include <ata_if.h>
-
-/* local prototypes */
-static int ata_ahci_ch_attach(device_t dev);
-static int ata_ahci_ch_detach(device_t dev);
-static int ata_ahci_ch_suspend(device_t dev);
-static int ata_ahci_ch_resume(device_t dev);
-static int ata_ahci_ctlr_reset(device_t dev);
-static void ata_ahci_reset(device_t dev);
-static int ata_ahci_suspend(device_t dev);
-static int ata_ahci_status(device_t dev);
-static int ata_ahci_begin_transaction(struct ata_request *request);
-static int ata_ahci_end_transaction(struct ata_request *request);
-static int ata_ahci_pm_read(device_t dev, int port, int reg, u_int32_t *result);
-static int ata_ahci_pm_write(device_t dev, int port, int reg, u_int32_t result);
-static int ata_ahci_hardreset(device_t dev, int port, uint32_t *signature);
-static u_int32_t ata_ahci_softreset(device_t dev, int port);
-static void ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
-static int ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *equest);
-static void ata_ahci_dmainit(device_t dev);
-static void ata_ahci_start(device_t dev);
-static void ata_ahci_stop(device_t dev);
-static void ata_ahci_clo(device_t dev);
-static void ata_ahci_start_fr(device_t dev);
-static void ata_ahci_stop_fr(device_t dev);
-
-/*
- * AHCI v1.x compliant SATA chipset support functions
- */
-static int
-ata_ahci_probe(device_t dev)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(dev);
-    char buffer[64];
-
-    /* is this a possible AHCI candidate ? */
-    if (pci_get_class(dev) != PCIC_STORAGE ||
-	pci_get_subclass(dev) != PCIS_STORAGE_SATA)
-	    return (ENXIO);
-
-    /* is this PCI device flagged as an AHCI compliant chip ? */
-    if (pci_get_progif(dev) != PCIP_STORAGE_SATA_AHCI_1_0)
-	return (ENXIO);
-
-    if (bootverbose)
-	sprintf(buffer, "%s (ID=%08x) AHCI controller", 
-		ata_pcivendor2str(dev), pci_get_devid(dev));
-    else
-	sprintf(buffer, "%s AHCI controller", ata_pcivendor2str(dev));
-    device_set_desc_copy(dev, buffer);
-    ctlr->chipinit = ata_ahci_chipinit;
-    return (BUS_PROBE_GENERIC);
-}
-
-static int
-ata_ahci_ata_probe(device_t dev)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(dev);
-
-    if ((intptr_t)device_get_ivars(dev) >= 0)
-	    return (ENXIO);
-    device_set_desc_copy(dev, "AHCI SATA controller");
-    ctlr->chipinit = ata_ahci_chipinit;
-    return (BUS_PROBE_GENERIC);
-}
-
-static int
-ata_ahci_ata_attach(device_t dev)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(dev);
-    device_t child;
-    int unit;
-
-    /* do chipset specific setups only needed once */
-    ctlr->legacy = 0;
-    ctlr->ichannels = -1;
-    ctlr->ch_attach = ata_pci_ch_attach;
-    ctlr->ch_detach = ata_pci_ch_detach;
-    ctlr->dev = dev;
-    if (ctlr->chipinit(dev))
-	return ENXIO;
-    /* attach all channels on this controller */
-    for (unit = 0; unit < ctlr->channels; unit++) {
-	if ((ctlr->ichannels & (1 << unit)) == 0)
-	    continue;
-	child = device_add_child(dev, "ata",
-	    ((unit == 0 || unit == 1) && ctlr->legacy) ?
-	    unit : devclass_find_free_unit(ata_devclass, 2));
-	if (child == NULL)
-	    device_printf(dev, "failed to add ata child device\n");
-	else
-	    device_set_ivars(child, (void *)(intptr_t)unit);
-    }
-    bus_generic_attach(dev);
-    return 0;
-}
-
-int
-ata_ahci_chipinit(device_t dev)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(dev);
-    int error, speed;
-    u_int32_t caps, version;
-
-    /* if we have a memory BAR(5) we are likely on an AHCI part */
-    ctlr->r_type2 = SYS_RES_MEMORY;
-    ctlr->r_rid2 = PCIR_BAR(5);
-    if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
-					       &ctlr->r_rid2, RF_ACTIVE)))
-	return ENXIO;
-
-    /* setup interrupt delivery if not done allready by a vendor driver */
-    if (!ctlr->r_irq) {
-	if (ata_setup_interrupt(dev, ata_generic_intr)) {
-	    bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
-	    return ENXIO;
-	}
-    }
-    else
-	device_printf(dev, "AHCI called from vendor specific driver\n");
-
-    /* reset controller */
-    if ((error = ata_ahci_ctlr_reset(dev)) != 0) {
-	bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
-	return (error);
-    };
-
-    /* get the number of HW channels */
-    ctlr->ichannels = ATA_INL(ctlr->r_res2, ATA_AHCI_PI);
-    ctlr->channels = MAX(flsl(ctlr->ichannels),
-	    (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_NPMASK) + 1);
-    if (pci_get_devid(dev) == ATA_M88SE6111)
-	    ctlr->channels = 1;
-    else if (pci_get_devid(dev) == ATA_M88SE6121)
-	    ctlr->channels = 2;
-    else if (pci_get_devid(dev) == ATA_M88SE6141 ||
-	pci_get_devid(dev) == ATA_M88SE6145)
-	    ctlr->channels = 4;
-
-    ctlr->reset = ata_ahci_reset;
-    ctlr->ch_attach = ata_ahci_ch_attach;
-    ctlr->ch_detach = ata_ahci_ch_detach;
-    ctlr->ch_suspend = ata_ahci_ch_suspend;
-    ctlr->ch_resume = ata_ahci_ch_resume;
-    ctlr->setmode = ata_sata_setmode;
-    ctlr->getrev = ata_sata_getrev;
-    ctlr->suspend = ata_ahci_suspend;
-    ctlr->resume = ata_ahci_ctlr_reset;
-
-	/* announce we support the HW */
-	version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS);
-	caps = ATA_INL(ctlr->r_res2, ATA_AHCI_CAP);
-	speed = (caps & ATA_AHCI_CAP_ISS) >> ATA_AHCI_CAP_ISS_SHIFT;
-	device_printf(dev,
-		    "AHCI v%x.%02x controller with %d %sGbps ports, PM %s\n",
-		    ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f),
-		    ((version >> 4) & 0xf0) + (version & 0x0f),
-		    (caps & ATA_AHCI_CAP_NPMASK) + 1,
-		    ((speed == 1) ? "1.5":((speed == 2) ? "3":
-		    ((speed == 3) ? "6":"?"))),
-		    (caps & ATA_AHCI_CAP_SPM) ?
-		    "supported" : "not supported");
-	if (bootverbose) {
-		device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps",
-		    (caps & ATA_AHCI_CAP_64BIT) ? " 64bit":"",
-		    (caps & ATA_AHCI_CAP_SNCQ) ? " NCQ":"",
-		    (caps & ATA_AHCI_CAP_SSNTF) ? " SNTF":"",
-		    (caps & ATA_AHCI_CAP_SMPS) ? " MPS":"",
-		    (caps & ATA_AHCI_CAP_SSS) ? " SS":"",
-		    (caps & ATA_AHCI_CAP_SALP) ? " ALP":"",
-		    (caps & ATA_AHCI_CAP_SAL) ? " AL":"",
-		    (caps & ATA_AHCI_CAP_SCLO) ? " CLO":"",
-		    ((speed == 1) ? "1.5":((speed == 2) ? "3":
-		    ((speed == 3) ? "6":"?"))));
-		printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n",
-		    (caps & ATA_AHCI_CAP_SAM) ? " AM":"",
-		    (caps & ATA_AHCI_CAP_SPM) ? " PM":"",
-		    (caps & ATA_AHCI_CAP_FBSS) ? " FBS":"",
-		    (caps & ATA_AHCI_CAP_PMD) ? " PMD":"",
-		    (caps & ATA_AHCI_CAP_SSC) ? " SSC":"",
-		    (caps & ATA_AHCI_CAP_PSC) ? " PSC":"",
-		    ((caps & ATA_AHCI_CAP_NCS) >> ATA_AHCI_CAP_NCS_SHIFT) + 1,
-		    (caps & ATA_AHCI_CAP_CCCS) ? " CCC":"",
-		    (caps & ATA_AHCI_CAP_EMS) ? " EM":"",
-		    (caps & ATA_AHCI_CAP_SXS) ? " eSATA":"",
-		    (caps & ATA_AHCI_CAP_NPMASK) + 1);
-	}
-	return 0;
-}
-
-static int
-ata_ahci_ctlr_reset(device_t dev)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(dev);
-    int timeout;
-
-    /* enable AHCI mode */
-    ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);
-
-    /* reset AHCI controller */
-    ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE|ATA_AHCI_GHC_HR);
-    for (timeout = 1000; timeout > 0; timeout--) {
-	    DELAY(1000);
-	    if ((ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) == 0)
-		    break;
-    }
-    if (timeout == 0) {
-	device_printf(dev, "AHCI controller reset failure\n");
-	return ENXIO;
-    }
-
-    /* reenable AHCI mode */
-    ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);
-
-    /* clear interrupts */
-    ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS));
-
-    /* enable AHCI interrupts */
-    ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
-	     ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE);
-
-    return 0;
-}
-
-static int
-ata_ahci_suspend(device_t dev)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(dev);
-
-    /* disable interupts so the state change(s) doesn't trigger */
-    ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
-             ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & (~ATA_AHCI_GHC_IE));
-    return 0;
-}
-
-static int
-ata_ahci_ch_attach(device_t dev)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
-    struct ata_channel *ch = device_get_softc(dev);
-    int offset = ch->unit << 7;
-
-    ata_ahci_dmainit(dev);
-
-    /* set the SATA resources */
-    ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
-    ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset;
-    ch->r_io[ATA_SERROR].res = ctlr->r_res2;
-    ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset;
-    ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
-    ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset;
-    ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
-    ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset;
-
-    ch->hw.status = ata_ahci_status;
-    ch->hw.begin_transaction = ata_ahci_begin_transaction;
-    ch->hw.end_transaction = ata_ahci_end_transaction;
-    ch->hw.command = NULL;      /* not used here */
-    ch->hw.softreset = ata_ahci_softreset;
-    ch->hw.pm_read = ata_ahci_pm_read;
-    ch->hw.pm_write = ata_ahci_pm_write;
-    ch->flags |= ATA_NO_SLAVE;
-    ch->flags |= ATA_SATA;
-
-    ata_ahci_ch_resume(dev);
-    return 0;
-}
-
-static int
-ata_ahci_ch_detach(device_t dev)
-{
-    struct ata_channel *ch = device_get_softc(dev);
- 
-    if (ch->dma.work_tag && ch->dma.work_map)
-	bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
-	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
-    ata_ahci_ch_suspend(dev);
-    ata_dmafini(dev);
-    return (0);
-}
-
-static int
-ata_ahci_ch_suspend(device_t dev)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
-    struct ata_channel *ch = device_get_softc(dev);
-    int offset = ch->unit << 7;
-
-    /* Disable port interrupts. */
-    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0);
-    /* Reset command register. */
-    ata_ahci_stop(dev);
-    ata_ahci_stop_fr(dev);
-    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 0);
-
-    /* Allow everything including partial and slumber modes. */
-    ATA_IDX_OUTL(ch, ATA_SCONTROL, 0);
-    /* Request slumber mode transition and give some time to get there. */
-    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, ATA_AHCI_P_CMD_SLUMBER);
-    DELAY(100);
-    /* Disable PHY. */
-    ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_DISABLE);
-
-    return (0);
-}
-
-static int
-ata_ahci_ch_resume(device_t dev)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
-    struct ata_channel *ch = device_get_softc(dev);
-    uint64_t work;
-    int offset = ch->unit << 7;
-
-    /* Disable port interrupts */
-    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0);
-
-    /* setup work areas */
-    work = ch->dma.work_bus + ATA_AHCI_CL_OFFSET;
-    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset, work & 0xffffffff);
-    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, work >> 32);
-
-    work = ch->dma.work_bus + ATA_AHCI_FB_OFFSET;
-    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset, work & 0xffffffff); 
-    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, work >> 32);
-
-    /* activate the channel and power/spin up device */
-    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
-	     (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD |
-	     ((ch->pm_level > 1) ? ATA_AHCI_P_CMD_ALPE : 0) |
-	     ((ch->pm_level > 2) ? ATA_AHCI_P_CMD_ASP : 0 )));
-    ata_ahci_start_fr(dev);
-    ata_ahci_start(dev);
-
-    return (0);
-}
-
-static int
-ata_ahci_status(device_t dev)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
-    struct ata_channel *ch = device_get_softc(dev);
-    u_int32_t action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS);
-    int offset = ch->unit << 7;
-
-#define ATA_AHCI_STATBITS \
-	(ATA_AHCI_P_IX_IF|ATA_AHCI_P_IX_HBD|ATA_AHCI_P_IX_HBF|ATA_AHCI_P_IX_TFE)
-
-    if (action & (1 << ch->unit)) {
-	u_int32_t istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset);
-	u_int32_t cstatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset);
-
-	/* clear interrupt(s) */
-	ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, istatus);
-	ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, 1 << ch->unit);
-
-	/* do we have any PHY events ? */
-	if (istatus & (ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC))
-	    ata_sata_phy_check_events(dev, -1);
-
-	/* do we have a potentially hanging engine to take care of? */
-	/* XXX SOS what todo on NCQ */
-	if ((istatus & ATA_AHCI_STATBITS) && (cstatus & 1)) {
-
-	    u_int32_t cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
-	    int timeout = 0;
-
-	    /* kill off all activity on this channel */
-	    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
-		     cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
-
-	    /* XXX SOS this is not entirely wrong */
-	    do {
-		DELAY(1000);
-		if (timeout++ > 1000) {
-		    device_printf(dev, "stopping AHCI engine failed\n");
-		    break;
-		}
-    	    } while (ATA_INL(ctlr->r_res2,
-			     ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
-
-	    /* start operations on this channel */
-	    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
-		     cmd | (ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
-
-	    return 1;
-	}
-	else
-	    /* XXX SOS what todo on NCQ */
-	    return (!(cstatus & 1));
-    }
-    return 0;
-}
-
-/* must be called with ATA channel locked and state_mtx held */
-static int
-ata_ahci_begin_transaction(struct ata_request *request)
-{
-    struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
-    struct ata_channel *ch = device_get_softc(request->parent);
-    struct ata_ahci_cmd_tab *ctp;
-    struct ata_ahci_cmd_list *clp;
-    int offset = ch->unit << 7;
-    int port = request->unit & 0x0f;
-    int entries = 0;
-    int fis_size;
-	
-    /* get a piece of the workspace for this request */
-    ctp = (struct ata_ahci_cmd_tab *)
-	  (ch->dma.work + ATA_AHCI_CT_OFFSET);
-
-    /* setup the FIS for this request */
-    if (!(fis_size = ata_ahci_setup_fis(ctp, request))) {
-	device_printf(request->parent, "setting up SATA FIS failed\n");
-	request->result = EIO;
-	return ATA_OP_FINISHED;
-    }
-
-    /* if request moves data setup and load SG list */
-    if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
-	if (ch->dma.load(request, ctp->prd_tab, &entries)) {
-	    device_printf(request->parent, "setting up DMA failed\n");
-	    request->result = EIO;
-	    return ATA_OP_FINISHED;
-	}
-    }
-
-    /* setup the command list entry */
-    clp = (struct ata_ahci_cmd_list *)
-	  (ch->dma.work + ATA_AHCI_CL_OFFSET);
-
-    clp->prd_length = entries;
-    clp->cmd_flags = (request->flags & ATA_R_WRITE ? ATA_AHCI_CMD_WRITE : 0) |
-		     (request->flags & ATA_R_ATAPI ?
-		      (ATA_AHCI_CMD_ATAPI | ATA_AHCI_CMD_PREFETCH) : 0) |
-		     (fis_size / sizeof(u_int32_t)) |
-    		     (port << 12);
-    clp->bytecount = 0;
-    clp->cmd_table_phys = htole64(ch->dma.work_bus + ATA_AHCI_CT_OFFSET);
-
-    /* set command type bit */
-    if (request->flags & ATA_R_ATAPI)
-	ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
-		 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) |
-		 ATA_AHCI_P_CMD_ATAPI);
-    else
-	ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
-		 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) &
-		 ~ATA_AHCI_P_CMD_ATAPI);
-
-    bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
-	BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
-
-    /* issue command to controller */
-    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, 1);
-    
-    if (!(request->flags & ATA_R_ATAPI)) {
-	/* device reset doesn't interrupt */
-	if (request->u.ata.command == ATA_DEVICE_RESET) {
-	    u_int32_t tf_data;
-	    int timeout = 1000000;
-
-	    do {
-		DELAY(10);
-		tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit<<7));
-	    } while ((tf_data & ATA_S_BUSY) && timeout--);
-	    if (bootverbose)
-		device_printf(ch->dev, "device_reset timeout=%dus\n",
-			      (1000000-timeout)*10);
-	    request->status = tf_data;
-	    if (request->status & ATA_S_ERROR)
-		request->error = tf_data >> 8;
-	    return ATA_OP_FINISHED;
-	}
-    }
-
-    /* start the timeout */
-    callout_reset(&request->callout, request->timeout * hz,
-		  (timeout_t*)ata_timeout, request);
-    return ATA_OP_CONTINUES;
-}
-
-/* must be called with ATA channel locked and state_mtx held */
-static int
-ata_ahci_end_transaction(struct ata_request *request)
-{
-    struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
-    struct ata_channel *ch = device_get_softc(request->parent);
-    struct ata_ahci_cmd_list *clp;
-    u_int32_t tf_data;
-    int offset = ch->unit << 7;
-
-    /* kill the timeout */
-    callout_stop(&request->callout);
-
-    bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
-	BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
-
-    /* get status */
-    tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset);
-    request->status = tf_data;
-
-    /* if error status get details */
-    if (request->status & ATA_S_ERROR)  
-	request->error = tf_data >> 8;
-
-    /* Read back registers to the request struct. */
-    if ((request->flags & ATA_R_ATAPI) == 0 &&
-	((request->status & ATA_S_ERROR) ||
-	 (request->flags & (ATA_R_CONTROL | ATA_R_NEEDRESULT)))) {
-	u_int8_t *fis = ch->dma.work + ATA_AHCI_FB_OFFSET + 0x40;
-
-	request->u.ata.count = fis[12] | ((u_int16_t)fis[13] << 8);
-	request->u.ata.lba = fis[4] | ((u_int64_t)fis[5] << 8) |
-			     ((u_int64_t)fis[6] << 16);
-	if (request->flags & ATA_R_48BIT)
-	    request->u.ata.lba |= ((u_int64_t)fis[8] << 24) |
-				  ((u_int64_t)fis[9] << 32) |
-				  ((u_int64_t)fis[10] << 40);
-	else
-	    request->u.ata.lba |= ((u_int64_t)(fis[7] & 0x0f) << 24);
-    }
-
-    /* record how much data we actually moved */
-    clp = (struct ata_ahci_cmd_list *)
-	  (ch->dma.work + ATA_AHCI_CL_OFFSET);
-    request->donecount = le32toh(clp->bytecount);
-
-    /* release SG list etc */
-    ch->dma.unload(request);
-
-    return ATA_OP_FINISHED;
-}
-
-static int
-ata_ahci_issue_cmd(device_t dev, u_int16_t flags, int timeout)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
-    struct ata_channel *ch = device_get_softc(dev);
-    struct ata_ahci_cmd_list *clp =
-	(struct ata_ahci_cmd_list *)(ch->dma.work + ATA_AHCI_CL_OFFSET);
-    struct ata_ahci_cmd_tab *ctp =
-	(struct ata_ahci_cmd_tab *)(ch->dma.work + ATA_AHCI_CT_OFFSET);
-    u_int32_t status = 0;
-    int offset = ch->unit << 7;
-    int port = (ctp->cfis[1] & 0x0f);
-    int count;
-
-    clp->prd_length = 0;
-    clp->cmd_flags = (20 / sizeof(u_int32_t)) | flags | (port << 12);
-    clp->bytecount = 0;
-    clp->cmd_table_phys = htole64(ch->dma.work_bus + ATA_AHCI_CT_OFFSET);
-
-    bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
-	BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
-
-    /* issue command to controller */
-    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, 1);
-
-    /* poll for command finished */
-    for (count = 0; count < timeout; count++) {
-        DELAY(1000);
-        if (!((status = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset)) & 1))
-            break;
-    }
-
-    bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
-	BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
-
-    /* clear interrupts */
-    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset,
-	    ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset));
-
-    if (timeout && (count >= timeout)) {
-	if (bootverbose) {
-	    device_printf(dev, "ahci_issue_cmd timeout: %d of %dms, status=%08x\n",
-		      count, timeout, status);
-	}
-	return EIO;
-    }
-
-    return 0;
-}
-
-static int
-ata_ahci_pm_read(device_t dev, int port, int reg, u_int32_t *result)
-{
-    struct ata_channel *ch = device_get_softc(dev);
-    struct ata_ahci_cmd_tab *ctp =
-	(struct ata_ahci_cmd_tab *)(ch->dma.work + ATA_AHCI_CT_OFFSET);
-    u_int8_t *fis = ch->dma.work + ATA_AHCI_FB_OFFSET + 0x40;
-
-    if (port < 0) {
-	*result = ATA_IDX_INL(ch, reg);
-	return (0);
-    }
-    if (port < ATA_PM) {
-	switch (reg) {
-	case ATA_SSTATUS:
-	    reg = 0;
-	    break;
-	case ATA_SERROR:
-	    reg = 1;
-	    break;
-	case ATA_SCONTROL:
-	    reg = 2;
-	    break;
-	default:
-	    return (EINVAL);
-	}
-    }
-    bzero(ctp->cfis, 64);
-    ctp->cfis[0] = 0x27;	/* host to device */
-    ctp->cfis[1] = 0x8f;	/* command FIS to PM port */
-    ctp->cfis[2] = ATA_READ_PM;
-    ctp->cfis[3] = reg;
-    ctp->cfis[7] = port | ATA_D_LBA;
-    ctp->cfis[15] = ATA_A_4BIT;
-
-    if (ata_ahci_issue_cmd(dev, 0, 10)) {
-	device_printf(dev, "error reading PM port\n");
-	return EIO;
-    }
-
-    *result = fis[12] | (fis[4] << 8) | (fis[5] << 16) | (fis[6] << 24);
-    return 0;
-}
-
-static int
-ata_ahci_pm_write(device_t dev, int port, int reg, u_int32_t value)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
-    struct ata_channel *ch = device_get_softc(dev);
-    struct ata_ahci_cmd_tab *ctp =
-	(struct ata_ahci_cmd_tab *)(ch->dma.work + ATA_AHCI_CT_OFFSET);
-    int offset = ch->unit << 7;
-
-    if (port < 0) {
-	ATA_IDX_OUTL(ch, reg, value);
-	return (0);
-    }
-    if (port < ATA_PM) {
-	switch (reg) {
-	case ATA_SSTATUS:
-	    reg = 0;
-	    break;
-	case ATA_SERROR:
-	    reg = 1;
-	    break;
-	case ATA_SCONTROL:
-	    reg = 2;
-	    break;
-	default:
-	    return (EINVAL);
-	}
-    }
-    bzero(ctp->cfis, 64);
-    ctp->cfis[0] = 0x27;	/* host to device */
-    ctp->cfis[1] = 0x8f;	/* command FIS to PM port */
-    ctp->cfis[2] = ATA_WRITE_PM;
-    ctp->cfis[3] = reg;
-    ctp->cfis[7] = port | ATA_D_LBA;
-    ctp->cfis[12] = value & 0xff;
-    ctp->cfis[4] = (value >> 8) & 0xff;
-    ctp->cfis[5] = (value >> 16) & 0xff;
-    ctp->cfis[6] = (value >> 24) & 0xff;
-    ctp->cfis[15] = ATA_A_4BIT;
-
-    if (ata_ahci_issue_cmd(dev, 0, 100)) {
-	device_printf(dev, "error writing PM port\n");
-	return ATA_E_ABORT;
-    }
-
-    return (ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset) >> 8) & 0xff;
-}
-
-static void
-ata_ahci_stop(device_t dev)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
-    struct ata_channel *ch = device_get_softc(dev);
-    u_int32_t cmd;
-    int offset = ch->unit << 7;
-    int timeout;
-
-    /* kill off all activity on this channel */
-    cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
-    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
-	     cmd & ~ATA_AHCI_P_CMD_ST);
-
-    /* XXX SOS this is not entirely wrong */
-    timeout = 0;
-    do {
-	DELAY(1000);
-	if (timeout++ > 1000) {
-	    device_printf(dev, "stopping AHCI engine failed\n");
-	    break;
-	}
-    }
-    while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
-}
-
-static void
-ata_ahci_clo(device_t dev)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
-    struct ata_channel *ch = device_get_softc(dev);
-    u_int32_t cmd;
-    int offset = ch->unit << 7;
-    int timeout;
-
-    /* issue Command List Override if supported */ 
-    if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_SCLO) {
-	cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
-	cmd |= ATA_AHCI_P_CMD_CLO;
-	ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd);
-	timeout = 0;
-	do {
-	    DELAY(1000);
-	    if (timeout++ > 1000) {
-		device_printf(dev, "executing CLO failed\n");
-		break;
-	    }
-        }
-	while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO);
-    }
-}
-
-static void
-ata_ahci_start(device_t dev)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
-    struct ata_channel *ch = device_get_softc(dev);
-    u_int32_t cmd;
-    int offset = ch->unit << 7;
-
-    /* clear SATA error register */
-    ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
-
-    /* clear any interrupts pending on this channel */
-    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset,
-	     ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset));
-
-    /* start operations on this channel */
-    cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
-    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
-	     cmd | ATA_AHCI_P_CMD_ST |
-	     (ch->devices & ATA_PORTMULTIPLIER ? ATA_AHCI_P_CMD_PMA : 0));
-}
-
-static void
-ata_ahci_stop_fr(device_t dev)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
-    struct ata_channel *ch = device_get_softc(dev);
-    u_int32_t cmd;
-    int offset = ch->unit << 7;
-    int timeout;
-
-    /* kill off all activity on this channel */
-    cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
-    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd & ~ATA_AHCI_P_CMD_FRE);
-
-    timeout = 0;
-    do {
-	DELAY(1000);
-	if (timeout++ > 1000) {
-	    device_printf(dev, "stopping AHCI FR engine failed\n");
-	    break;
-	}
-    }
-    while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_FR);
-}
-
-static void
-ata_ahci_start_fr(device_t dev)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
-    struct ata_channel *ch = device_get_softc(dev);
-    u_int32_t cmd;
-    int offset = ch->unit << 7;
-
-    /* start FIS reception on this channel */
-    cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
-    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd | ATA_AHCI_P_CMD_FRE);
-}
-
-static int
-ata_ahci_wait_ready(device_t dev, int t)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
-    struct ata_channel *ch = device_get_softc(dev);
-    int offset = ch->unit << 7;
-    int timeout = 0;
-    uint32_t val;
-
-    while ((val = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset)) &
-	(ATA_S_BUSY | ATA_S_DRQ)) {
-	    DELAY(1000);
-	    if (timeout++ > t) {
-		device_printf(dev, "port is not ready (timeout %dms) tfd = %08x\n", t, val);
-		return (EBUSY);
-	    }
-    } 
-    if (bootverbose)
-	device_printf(dev, "ready wait time=%dms\n", timeout);
-    return (0);
-}
-
-static int
-ata_ahci_hardreset(device_t dev, int port, uint32_t *signature)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
-    struct ata_channel *ch = device_get_softc(dev);
-    int offset = ch->unit << 7;
-
-    *signature = 0xffffffff;
-    ata_ahci_stop(dev);
-    /* Reset port */
-    if (!ata_sata_phy_reset(dev, port, 0))
-	return (ENOENT);
-    /* Wait for clearing busy status. */
-    if (ata_ahci_wait_ready(dev, 15000)) {
-	device_printf(dev, "hardware reset timeout\n");
-	return (EBUSY);
-    }
-    *signature = ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset);
-    ata_ahci_start(dev);
-    return (0);
-}
-
-static u_int32_t
-ata_ahci_softreset(device_t dev, int port)
-{
-    struct ata_channel *ch = device_get_softc(dev);
-    struct ata_ahci_cmd_tab *ctp =
-	(struct ata_ahci_cmd_tab *)(ch->dma.work + ATA_AHCI_CT_OFFSET);
-    u_int8_t *fis = ch->dma.work + ATA_AHCI_FB_OFFSET + 0x40;
-
-    if (bootverbose)
-	device_printf(dev, "software reset port %d...\n", port);
-
-    /* kick controller into sane state */
-    ata_ahci_stop(dev);
-    ata_ahci_clo(dev);
-    ata_ahci_start(dev);
-
-    /* pull reset active */
-    bzero(ctp->cfis, 64);
-    ctp->cfis[0] = 0x27;
-    ctp->cfis[1] = port & 0x0f;
-    //ctp->cfis[7] = ATA_D_LBA | ATA_D_IBM;
-    ctp->cfis[15] = (ATA_A_4BIT | ATA_A_RESET);
-
-    if (ata_ahci_issue_cmd(dev, ATA_AHCI_CMD_RESET | ATA_AHCI_CMD_CLR_BUSY,100)) {
-	device_printf(dev, "software reset set timeout\n");
-	return (-1);
-    }
-
-    ata_udelay(50);
-
-    /* pull reset inactive -> device softreset */
-    bzero(ctp->cfis, 64);
-    ctp->cfis[0] = 0x27;
-    ctp->cfis[1] = port & 0x0f;
-    //ctp->cfis[7] = ATA_D_LBA | ATA_D_IBM;
-    ctp->cfis[15] = ATA_A_4BIT;
-    ata_ahci_issue_cmd(dev, 0, 3000);
-
-    if (ata_ahci_wait_ready(dev, 0)) {
-	device_printf(dev, "software reset clear timeout\n");
-	return (-1);
-    }
-
-    return (((u_int32_t)fis[6] << 24) |
-	    ((u_int32_t)fis[5] << 16) |
-	    ((u_int32_t)fis[4] << 8) |
-	     (u_int32_t)fis[12]);
-}
-
-static void
-ata_ahci_reset(device_t dev)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
-    struct ata_channel *ch = device_get_softc(dev);
-    u_int32_t signature;
-    int offset = ch->unit << 7;
-
-    if (bootverbose)
-        device_printf(dev, "AHCI reset...\n");
-
-    /* Disable port interrupts */
-    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0);
-
-    if (ata_ahci_hardreset(dev, -1, &signature)) {
-	if (bootverbose)
-	    device_printf(dev, "AHCI reset done: phy reset found no device\n");
-	ch->devices = 0;
-
-	/* enable wanted port interrupts */
-	ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset,
-	     (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC));
-	return;
-    }
-
-    /* enable wanted port interrupts */
-    ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset,
-	     (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF |
-	      ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF |
-	      ((ch->pm_level == 0) ? ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC : 0) |
-	      ATA_AHCI_P_IX_DP | ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB |
-	      ATA_AHCI_P_IX_DS | ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR));
-    /*
-     * Only probe for PortMultiplier if HW has support.
-     * Ignore Marvell, which is not working,
-     */
-    if ((ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_SPM) &&
-	    pci_get_vendor(ctlr->dev) != 0x11ab) {
-	signature = ata_ahci_softreset(dev, ATA_PM);
-	/* Workaround for some ATI chips, failing to soft-reset
-	 * when port multiplicator supported, but absent.
-	 * XXX: We can also check PxIS.IPMS==1 here to be sure. */
-	if (signature == 0xffffffff)
-	    signature = ata_ahci_softreset(dev, 0);
-    } else {
-	signature = ata_ahci_softreset(dev, 0);
-    }
-    if (bootverbose)
-	device_printf(dev, "SIGNATURE: %08x\n", signature);
-
-    switch (signature >> 16) {
-    case 0x0000:
-	ch->devices = ATA_ATA_MASTER;
-	break;
-    case 0x9669:
-	ch->devices = ATA_PORTMULTIPLIER;
-	ata_pm_identify(dev);
-	break;
-    case 0xeb14:
-	ch->devices = ATA_ATAPI_MASTER;
-	break;
-    default: /* SOS XXX */
-	if (bootverbose)
-	    device_printf(dev, "Unknown signature, assuming disk device\n");
-	ch->devices = ATA_ATA_MASTER;
-    }
-    if (bootverbose)
-        device_printf(dev, "AHCI reset done: devices=%08x\n", ch->devices);
-}
-
-static void
-ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
-{    
-    struct ata_dmasetprd_args *args = xsc;
-    struct ata_ahci_dma_prd *prd = args->dmatab;
-    int i;
-
-    if (!(args->error = error)) {
-	for (i = 0; i < nsegs; i++) {
-	    prd[i].dba = htole64(segs[i].ds_addr);
-	    prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK);
-	}
-    }
-
-    KASSERT(nsegs <= ATA_AHCI_DMA_ENTRIES, ("too many DMA segment entries\n"));
-    args->nsegs = nsegs;
-}
-
-static void
-ata_ahci_dmainit(device_t dev)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
-    struct ata_channel *ch = device_get_softc(dev);
-
-    /* note start and stop are not used here */
-    ch->dma.setprd = ata_ahci_dmasetprd;
-    ch->dma.max_iosize = (ATA_AHCI_DMA_ENTRIES - 1) * PAGE_SIZE;
-    if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_64BIT)
-	ch->dma.max_address = BUS_SPACE_MAXADDR;
-    ata_dmainit(dev);
-}
-
-static int
-ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request)
-{
-    bzero(ctp->cfis, 64);
-    if (request->flags & ATA_R_ATAPI) {
-	bzero(ctp->acmd, 32);
-	bcopy(request->u.atapi.ccb, ctp->acmd, 16);
-    }
-    return ata_request2fis_h2d(request, &ctp->cfis[0]);
-}
-
-ATA_DECLARE_DRIVER(ata_ahci);
-static device_method_t ata_ahci_ata_methods[] = {
-    DEVMETHOD(device_probe,     ata_ahci_ata_probe),
-    DEVMETHOD(device_attach,    ata_ahci_ata_attach),
-    DEVMETHOD(device_detach,    ata_pci_detach),
-    DEVMETHOD(device_suspend,   ata_pci_suspend),
-    DEVMETHOD(device_resume,    ata_pci_resume),
-    DEVMETHOD(device_shutdown,  bus_generic_shutdown),
-    DEVMETHOD(bus_read_ivar,		ata_pci_read_ivar),
-    DEVMETHOD(bus_write_ivar,		ata_pci_write_ivar),
-    DEVMETHOD(bus_alloc_resource,       ata_pci_alloc_resource),
-    DEVMETHOD(bus_release_resource,     ata_pci_release_resource),
-    DEVMETHOD(bus_activate_resource,    bus_generic_activate_resource),
-    DEVMETHOD(bus_deactivate_resource,  bus_generic_deactivate_resource),
-    DEVMETHOD(bus_setup_intr,           ata_pci_setup_intr),
-    DEVMETHOD(bus_teardown_intr,        ata_pci_teardown_intr),
-    DEVMETHOD_END
-};
-static driver_t ata_ahci_ata_driver = {
-        "atapci",
-        ata_ahci_ata_methods,
-        sizeof(struct ata_pci_controller)
-};
-DRIVER_MODULE(ata_ahci_ata, atapci, ata_ahci_ata_driver, ata_pci_devclass,
-    NULL, NULL);
diff --git a/sys/dev/ata/chipsets/ata-ati.c b/sys/dev/ata/chipsets/ata-ati.c
index 8aef8e8..150685e 100644
--- a/sys/dev/ata/chipsets/ata-ati.c
+++ b/sys/dev/ata/chipsets/ata-ati.c
@@ -64,9 +64,6 @@ static int ata_ati_setmode(device_t dev, int target, int mode);
 #define ATI_PATA	0x02
 #define ATI_AHCI	0x04
 
-static int force_ahci = 1;
-TUNABLE_INT("hw.ahci.force", &force_ahci);
-
 /*
  * ATI chipset support functions
  */
@@ -104,8 +101,6 @@ ata_ati_probe(device_t dev)
     if (!(ctlr->chip = ata_match_chip(dev, ids)))
 	return ENXIO;
 
-    ata_set_desc(dev);
-
     switch (ctlr->chip->cfg1) {
     case ATI_PATA:
 	ctlr->chipinit = ata_ati_chipinit;
@@ -117,12 +112,13 @@ ata_ati_probe(device_t dev)
 	ctlr->chipinit = ata_sii_chipinit;
 	break;
     case ATI_AHCI:
-	if (force_ahci == 1 || pci_get_subclass(dev) != PCIS_STORAGE_IDE)
-		ctlr->chipinit = ata_ahci_chipinit;
-	else
-		ctlr->chipinit = ata_ati_chipinit;
+	if (pci_get_subclass(dev) != PCIS_STORAGE_IDE)
+		return (ENXIO);
+	ctlr->chipinit = ata_ati_chipinit;
 	break;
     }
+
+    ata_set_desc(dev);
     return (BUS_PROBE_LOW_PRIORITY);
 }
 
@@ -264,5 +260,4 @@ ata_ati_setmode(device_t dev, int target, int mode)
 }
 
 ATA_DECLARE_DRIVER(ata_ati);
-MODULE_DEPEND(ata_ati, ata_ahci, 1, 1, 1);
 MODULE_DEPEND(ata_ati, ata_sii, 1, 1, 1);
diff --git a/sys/dev/ata/chipsets/ata-intel.c b/sys/dev/ata/chipsets/ata-intel.c
index eaf5823..9acc6f1 100644
--- a/sys/dev/ata/chipsets/ata-intel.c
+++ b/sys/dev/ata/chipsets/ata-intel.c
@@ -80,7 +80,6 @@ static void ata_intel_31244_tf_write(struct ata_request *request);
 static void ata_intel_31244_reset(device_t dev);
 
 /* misc defines */
-#define INTEL_AHCI	1
 #define INTEL_ICH5	2
 #define INTEL_6CH	4
 #define INTEL_6CH2	8
@@ -127,118 +126,57 @@ ata_intel_probe(device_t dev)
      { ATA_I6300ESB_S1,  0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" },
      { ATA_I6300ESB_R1,  0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" },
      { ATA_I82801FB,     0,          0, 2, ATA_UDMA5, "ICH6" },
-     { ATA_I82801FB_S1,  0, INTEL_AHCI, 0, ATA_SA150, "ICH6" },
-     { ATA_I82801FB_R1,  0, INTEL_AHCI, 0, ATA_SA150, "ICH6" },
-     { ATA_I82801FBM,    0, INTEL_AHCI, 0, ATA_SA150, "ICH6M" },
+     { ATA_I82801FB_S1,  0,          0, 0, ATA_SA150, "ICH6" },
+     { ATA_I82801FB_R1,  0,          0, 0, ATA_SA150, "ICH6" },
+     { ATA_I82801FBM,    0,          0, 0, ATA_SA150, "ICH6M" },
      { ATA_I82801GB,     0,          0, 1, ATA_UDMA5, "ICH7" },
      { ATA_I82801GB_S1,  0, INTEL_ICH7, 0, ATA_SA300, "ICH7" },
-     { ATA_I82801GB_R1,  0, INTEL_AHCI, 0, ATA_SA300, "ICH7" },
-     { ATA_I82801GB_AH,  0, INTEL_AHCI, 0, ATA_SA300, "ICH7" },
      { ATA_I82801GBM_S1, 0, INTEL_ICH7, 0, ATA_SA150, "ICH7M" },
-     { ATA_I82801GBM_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" },
-     { ATA_I82801GBM_AH, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" },
      { ATA_I63XXESB2,    0,          0, 1, ATA_UDMA5, "63XXESB2" },
      { ATA_I63XXESB2_S1, 0,          0, 0, ATA_SA300, "63XXESB2" },
-     { ATA_I63XXESB2_S2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" },
-     { ATA_I63XXESB2_R1, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" },
-     { ATA_I63XXESB2_R2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" },
      { ATA_I82801HB_S1,  0, INTEL_6CH,  0, ATA_SA300, "ICH8" },
      { ATA_I82801HB_S2,  0, INTEL_6CH2, 0, ATA_SA300, "ICH8" },
-     { ATA_I82801HB_R1,  0, INTEL_AHCI, 0, ATA_SA300, "ICH8" },
-     { ATA_I82801HB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" },
-     { ATA_I82801HB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" },
      { ATA_I82801HBM,    0,          0, 1, ATA_UDMA5, "ICH8M" },
      { ATA_I82801HBM_S1, 0, INTEL_6CH,  0, ATA_SA300, "ICH8M" },
-     { ATA_I82801HBM_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" },
-     { ATA_I82801HBM_S3, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" },
      { ATA_I82801IB_S1,  0, INTEL_6CH,  0, ATA_SA300, "ICH9" },
      { ATA_I82801IB_S2,  0, INTEL_6CH2, 0, ATA_SA300, "ICH9" },
      { ATA_I82801IB_S3,  0, INTEL_6CH2, 0, ATA_SA300, "ICH9" },
-     { ATA_I82801IB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
-     { ATA_I82801IB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
-     { ATA_I82801IB_R1,  0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
      { ATA_I82801IBM_S1, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" },
-     { ATA_I82801IBM_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9M" },
-     { ATA_I82801IBM_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9M" },
      { ATA_I82801IBM_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" },
      { ATA_I82801JIB_S1, 0, INTEL_6CH,  0, ATA_SA300, "ICH10" },
-     { ATA_I82801JIB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
-     { ATA_I82801JIB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
      { ATA_I82801JIB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" },
      { ATA_I82801JD_S1,  0, INTEL_6CH,  0, ATA_SA300, "ICH10" },
-     { ATA_I82801JD_AH,  0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
-     { ATA_I82801JD_R1,  0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
      { ATA_I82801JD_S2,  0, INTEL_6CH2, 0, ATA_SA300, "ICH10" },
      { ATA_I82801JI_S1,  0, INTEL_6CH,  0, ATA_SA300, "ICH10" },
-     { ATA_I82801JI_AH,  0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
-     { ATA_I82801JI_R1,  0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
      { ATA_I82801JI_S2,  0, INTEL_6CH2, 0, ATA_SA300, "ICH10" },
      { ATA_5Series_S1,   0, INTEL_6CH,  0, ATA_SA300, "5 Series/3400 Series PCH" },
      { ATA_5Series_S2,   0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" },
-     { ATA_5Series_AH1,  0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
-     { ATA_5Series_AH2,  0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
-     { ATA_5Series_R1,   0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
      { ATA_5Series_S3,   0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" },
      { ATA_5Series_S4,   0, INTEL_6CH,  0, ATA_SA300, "5 Series/3400 Series PCH" },
-     { ATA_5Series_AH3,  0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
-     { ATA_5Series_R2,   0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
      { ATA_5Series_S5,   0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" },
      { ATA_5Series_S6,   0, INTEL_6CH,  0, ATA_SA300, "5 Series/3400 Series PCH" },
-     { ATA_5Series_AH4,  0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
      { ATA_CPT_S1,       0, INTEL_6CH,  0, ATA_SA300, "Cougar Point" },
      { ATA_CPT_S2,       0, INTEL_6CH,  0, ATA_SA300, "Cougar Point" },
-     { ATA_CPT_AH1,      0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
-     { ATA_CPT_AH2,      0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
-     { ATA_CPT_R1,       0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
-     { ATA_CPT_R2,       0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
      { ATA_CPT_S3,       0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" },
      { ATA_CPT_S4,       0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" },
      { ATA_PBG_S1,       0, INTEL_6CH,  0, ATA_SA300, "Patsburg" },
-     { ATA_PBG_AH1,      0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" },
-     { ATA_PBG_R1,       0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" },
-     { ATA_PBG_R2,       0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" },
-     { ATA_PBG_R3,       0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" },
      { ATA_PBG_S2,       0, INTEL_6CH2, 0, ATA_SA300, "Patsburg" },
      { ATA_PPT_S1,       0, INTEL_6CH,  0, ATA_SA300, "Panther Point" },
      { ATA_PPT_S2,       0, INTEL_6CH,  0, ATA_SA300, "Panther Point" },
-     { ATA_PPT_AH1,      0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
-     { ATA_PPT_AH2,      0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
-     { ATA_PPT_R1,       0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
-     { ATA_PPT_R2,       0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
-     { ATA_PPT_R3,       0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
-     { ATA_PPT_R4,       0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
      { ATA_PPT_S3,       0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" },
      { ATA_PPT_S4,       0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" },
-     { ATA_PPT_R5,       0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
-     { ATA_PPT_R6,       0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
      { ATA_AVOTON_S1,    0, INTEL_6CH,  0, ATA_SA300, "Avoton" },
      { ATA_AVOTON_S2,    0, INTEL_6CH,  0, ATA_SA300, "Avoton" },
      { ATA_AVOTON_S3,    0, INTEL_6CH2, 0, ATA_SA300, "Avoton" },
      { ATA_AVOTON_S4,    0, INTEL_6CH2, 0, ATA_SA300, "Avoton" },
      { ATA_LPT_S1,       0, INTEL_6CH,  0, ATA_SA300, "Lynx Point" },
      { ATA_LPT_S2,       0, INTEL_6CH,  0, ATA_SA300, "Lynx Point" },
-     { ATA_LPT_AH1,      0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
-     { ATA_LPT_AH2,      0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
-     { ATA_LPT_R1,       0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
-     { ATA_LPT_R2,       0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
-     { ATA_LPT_R3,       0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
-     { ATA_LPT_R4,       0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
      { ATA_LPT_S3,       0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point" },
      { ATA_LPT_S4,       0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point" },
-     { ATA_LPT_R5,       0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
-     { ATA_LPT_R6,       0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" },
      { ATA_WCPT_S1,      0, INTEL_6CH,  0, ATA_SA300, "Wildcat Point" },
      { ATA_WCPT_S2,      0, INTEL_6CH,  0, ATA_SA300, "Wildcat Point" },
-     { ATA_WCPT_AH1,     0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" },
-     { ATA_WCPT_AH2,     0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" },
-     { ATA_WCPT_R1,      0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" },
-     { ATA_WCPT_R2,      0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" },
-     { ATA_WCPT_R3,      0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" },
-     { ATA_WCPT_R4,      0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" },
      { ATA_WCPT_S3,      0, INTEL_6CH2, 0, ATA_SA300, "Wildcat Point" },
      { ATA_WCPT_S4,      0, INTEL_6CH2, 0, ATA_SA300, "Wildcat Point" },
-     { ATA_WCPT_R5,      0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" },
-     { ATA_WCPT_R6,      0, INTEL_AHCI, 0, ATA_SA300, "Wildcat Point" },
      { ATA_WELLS_S1,     0, INTEL_6CH,  0, ATA_SA300, "Wellsburg" },
      { ATA_WELLS_S2,     0, INTEL_6CH2, 0, ATA_SA300, "Wellsburg" },
      { ATA_WELLS_S3,     0, INTEL_6CH,  0, ATA_SA300, "Wellsburg" },
@@ -249,10 +187,8 @@ ata_intel_probe(device_t dev)
      { ATA_LPTLP_S4,     0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point-LP" },
      { ATA_I31244,       0,          0, 2, ATA_SA150, "31244" },
      { ATA_ISCH,         0,          0, 1, ATA_UDMA5, "SCH" },
-     { ATA_DH89XXCC,     0, INTEL_AHCI, 0, ATA_SA300, "DH89xxCC" },
      { ATA_COLETOCRK_S1, 0, INTEL_6CH2, 0, ATA_SA300, "COLETOCRK" },
      { ATA_COLETOCRK_S2, 0, INTEL_6CH2, 0, ATA_SA300, "COLETOCRK" },
-     { ATA_COLETOCRK_AH1,0, INTEL_AHCI, 0, ATA_SA300, "COLETOCRK" },
      { 0, 0, 0, 0, 0, 0}};
 
     if (pci_get_vendor(dev) != ATA_INTEL_ID)
@@ -326,15 +262,6 @@ ata_intel_chipinit(device_t dev)
 	ctlr->ch_detach = ata_pci_ch_detach;
 	ctlr->reset = ata_intel_reset;
 
-	/* 
-	 * if we have AHCI capability and AHCI or RAID mode enabled
-	 * in BIOS we try for AHCI mode
-	 */ 
-	if ((ctlr->chip->cfg1 & INTEL_AHCI) &&
-	    (pci_read_config(dev, 0x90, 1) & 0xc0) &&
-	    (ata_ahci_chipinit(dev) != ENXIO))
-	    return 0;
-
 	/* BAR(5) may point to SATA interface registers */
 	if ((ctlr->chip->cfg1 & INTEL_ICH7)) {
 		ctlr->r_type2 = SYS_RES_MEMORY;
@@ -995,4 +922,3 @@ ata_intel_31244_reset(device_t dev)
 }
 
 ATA_DECLARE_DRIVER(ata_intel);
-MODULE_DEPEND(ata_intel, ata_ahci, 1, 1, 1);
diff --git a/sys/dev/ata/chipsets/ata-jmicron.c b/sys/dev/ata/chipsets/ata-jmicron.c
index d1279a6..498c16e 100644
--- a/sys/dev/ata/chipsets/ata-jmicron.c
+++ b/sys/dev/ata/chipsets/ata-jmicron.c
@@ -100,11 +100,7 @@ ata_jmicron_chipinit(device_t dev)
 
     /* do we have multiple PCI functions ? */
     if (pci_read_config(dev, 0xdf, 1) & 0x40) {
-	/* are we on the AHCI part ? */
-	if (ata_ahci_chipinit(dev) != ENXIO)
-	    return 0;
-
-	/* otherwise we are on the PATA part */
+	/* If this was not claimed by AHCI, then we are on the PATA part */
 	ctlr->ch_attach = ata_jmicron_ch_attach;
 	ctlr->ch_detach = ata_pci_ch_detach;
 	ctlr->reset = ata_generic_reset;
@@ -160,4 +156,3 @@ ata_jmicron_setmode(device_t dev, int target, int mode)
 }
 
 ATA_DECLARE_DRIVER(ata_jmicron);
-MODULE_DEPEND(ata_jmicron, ata_ahci, 1, 1, 1);
diff --git a/sys/dev/ata/chipsets/ata-marvell.c b/sys/dev/ata/chipsets/ata-marvell.c
index d81634f..60d6d46 100644
--- a/sys/dev/ata/chipsets/ata-marvell.c
+++ b/sys/dev/ata/chipsets/ata-marvell.c
@@ -55,20 +55,8 @@ static int ata_marvell_chipinit(device_t dev);
 static int ata_marvell_ch_attach(device_t dev);
 static int ata_marvell_setmode(device_t dev, int target, int mode);
 static int ata_marvell_dummy_chipinit(device_t dev);
-static int ata_marvell_edma_ch_attach(device_t dev);
-static int ata_marvell_edma_ch_detach(device_t dev);
-static int ata_marvell_edma_status(device_t dev);
-static int ata_marvell_edma_begin_transaction(struct ata_request *request);
-static int ata_marvell_edma_end_transaction(struct ata_request *request);
-static void ata_marvell_edma_reset(device_t dev);
-static void ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
-static void ata_marvell_edma_dmainit(device_t dev);
 
 /* misc defines */
-#define MV_50XX		50
-#define MV_60XX		60
-#define MV_6042		62
-#define MV_7042		72
 #define MV_61XX		61
 #define MV_91XX		91
 
@@ -99,15 +87,7 @@ ata_marvell_probe(device_t dev)
 {
     struct ata_pci_controller *ctlr = device_get_softc(dev);
     static const struct ata_chip_id ids[] =
-    {{ ATA_M88SX5040, 0, 4, MV_50XX, ATA_SA150, "88SX5040" },
-     { ATA_M88SX5041, 0, 4, MV_50XX, ATA_SA150, "88SX5041" },
-     { ATA_M88SX5080, 0, 8, MV_50XX, ATA_SA150, "88SX5080" },
-     { ATA_M88SX5081, 0, 8, MV_50XX, ATA_SA150, "88SX5081" },
-     { ATA_M88SX6041, 0, 4, MV_60XX, ATA_SA300, "88SX6041" },
-     { ATA_M88SX6042, 0, 4, MV_6042, ATA_SA300, "88SX6042" },
-     { ATA_M88SX6081, 0, 8, MV_60XX, ATA_SA300, "88SX6081" },
-     { ATA_M88SX7042, 0, 4, MV_7042, ATA_SA300, "88SX7042" },
-     { ATA_M88SE6101, 0, 0, MV_61XX, ATA_UDMA6, "88SE6101" },
+    {{ ATA_M88SE6101, 0, 0, MV_61XX, ATA_UDMA6, "88SE6101" },
      { ATA_M88SE6102, 0, 0, MV_61XX, ATA_UDMA6, "88SE6102" },
      { ATA_M88SE6111, 0, 1, MV_61XX, ATA_UDMA6, "88SE6111" },
      { ATA_M88SE6121, 0, 2, MV_61XX, ATA_UDMA6, "88SE6121" },
@@ -126,12 +106,6 @@ ata_marvell_probe(device_t dev)
     ata_set_desc(dev);
 
     switch (ctlr->chip->cfg2) {
-    case MV_50XX:
-    case MV_60XX:
-    case MV_6042:
-    case MV_7042:
-	ctlr->chipinit = ata_marvell_edma_chipinit;
-	break;
     case MV_61XX:
 	ctlr->chipinit = ata_marvell_chipinit;
 	break;
@@ -205,425 +179,4 @@ ata_marvell_dummy_chipinit(device_t dev)
         return (0);
 }
 
-int
-ata_marvell_edma_chipinit(device_t dev)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(dev);
-
-    if (ata_setup_interrupt(dev, ata_generic_intr))
-	return ENXIO;
-
-    ctlr->r_type1 = SYS_RES_MEMORY;
-    ctlr->r_rid1 = PCIR_BAR(0);
-    if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
-						&ctlr->r_rid1, RF_ACTIVE)))
-	return ENXIO;
-
-    /* mask all host controller interrupts */
-    ATA_OUTL(ctlr->r_res1, 0x01d64, 0x00000000);
-
-    /* mask all PCI interrupts */
-    ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x00000000);
-
-    ctlr->ch_attach = ata_marvell_edma_ch_attach;
-    ctlr->ch_detach = ata_marvell_edma_ch_detach;
-    ctlr->reset = ata_marvell_edma_reset;
-    ctlr->setmode = ata_sata_setmode;
-    ctlr->getrev = ata_sata_getrev;
-    ctlr->channels = ctlr->chip->cfg1;
-
-    /* clear host controller interrupts */
-    ATA_OUTL(ctlr->r_res1, 0x20014, 0x00000000);
-    if (ctlr->chip->cfg1 > 4)
-	ATA_OUTL(ctlr->r_res1, 0x30014, 0x00000000);
-
-    /* clear PCI interrupts */
-    ATA_OUTL(ctlr->r_res1, 0x01d58, 0x00000000);
-
-    /* unmask PCI interrupts we want */
-    ATA_OUTL(ctlr->r_res1, 0x01d5c, 0x007fffff);
-
-    /* unmask host controller interrupts we want */
-    ATA_OUTL(ctlr->r_res1, 0x01d64, 0x000000ff/*HC0*/ | 0x0001fe00/*HC1*/ |
-	     /*(1<<19) | (1<<20) | (1<<21) |*/(1<<22) | (1<<24) | (0x7f << 25));
-
-    return 0;
-}
-
-static int
-ata_marvell_edma_ch_attach(device_t dev)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
-    struct ata_channel *ch = device_get_softc(dev);
-    u_int64_t work;
-    int i;
-
-    ata_marvell_edma_dmainit(dev);
-    work = ch->dma.work_bus;
-    /* clear work area */
-    bzero(ch->dma.work, 1024+256);
-    bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
-	BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
-
-    /* set legacy ATA resources */
-    for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
-	ch->r_io[i].res = ctlr->r_res1;
-	ch->r_io[i].offset = 0x02100 + (i << 2) + ATA_MV_EDMA_BASE(ch);
-    }
-    ch->r_io[ATA_CONTROL].res = ctlr->r_res1;
-    ch->r_io[ATA_CONTROL].offset = 0x02120 + ATA_MV_EDMA_BASE(ch);
-    ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res1;
-    ata_default_registers(dev);
-
-    /* set SATA resources */
-    switch (ctlr->chip->cfg2) {
-    case MV_50XX:
-	ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
-	ch->r_io[ATA_SSTATUS].offset =  0x00100 + ATA_MV_HOST_BASE(ch);
-	ch->r_io[ATA_SERROR].res = ctlr->r_res1;
-	ch->r_io[ATA_SERROR].offset = 0x00104 + ATA_MV_HOST_BASE(ch);
-	ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
-	ch->r_io[ATA_SCONTROL].offset = 0x00108 + ATA_MV_HOST_BASE(ch);
-	break;
-    case MV_60XX:
-    case MV_6042:
-    case MV_7042:
-	ch->r_io[ATA_SSTATUS].res = ctlr->r_res1;
-	ch->r_io[ATA_SSTATUS].offset =  0x02300 + ATA_MV_EDMA_BASE(ch);
-	ch->r_io[ATA_SERROR].res = ctlr->r_res1;
-	ch->r_io[ATA_SERROR].offset = 0x02304 + ATA_MV_EDMA_BASE(ch);
-	ch->r_io[ATA_SCONTROL].res = ctlr->r_res1;
-	ch->r_io[ATA_SCONTROL].offset = 0x02308 + ATA_MV_EDMA_BASE(ch);
-	ch->r_io[ATA_SACTIVE].res = ctlr->r_res1;
-	ch->r_io[ATA_SACTIVE].offset = 0x02350 + ATA_MV_EDMA_BASE(ch);
-	break;
-    }
-
-    ch->flags |= ATA_NO_SLAVE;
-    ch->flags |= ATA_USE_16BIT; /* XXX SOS needed ? */
-    ch->flags |= ATA_SATA;
-    ata_generic_hw(dev);
-    ch->hw.begin_transaction = ata_marvell_edma_begin_transaction;
-    ch->hw.end_transaction = ata_marvell_edma_end_transaction;
-    ch->hw.status = ata_marvell_edma_status;
-
-    /* disable the EDMA machinery */
-    ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
-    DELAY(100000);       /* SOS should poll for disabled */
-
-    /* set configuration to non-queued 128b read transfers stop on error */
-    ATA_OUTL(ctlr->r_res1, 0x02000 + ATA_MV_EDMA_BASE(ch), (1<<11) | (1<<13));
-
-    /* request queue base high */
-    ATA_OUTL(ctlr->r_res1, 0x02010 + ATA_MV_EDMA_BASE(ch), work >> 32);
-
-    /* request queue in ptr */
-    ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
-
-    /* request queue out ptr */
-    ATA_OUTL(ctlr->r_res1, 0x02018 + ATA_MV_EDMA_BASE(ch), 0x0);
-
-    /* response queue base high */
-    work += 1024;
-    ATA_OUTL(ctlr->r_res1, 0x0201c + ATA_MV_EDMA_BASE(ch), work >> 32);
-
-    /* response queue in ptr */
-    ATA_OUTL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch), 0x0);
-
-    /* response queue out ptr */
-    ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), work & 0xffffffff);
-
-    /* clear SATA error register */
-    ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
-
-    /* clear any outstanding error interrupts */
-    ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
-
-    /* unmask all error interrupts */
-    ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
-    
-    /* enable EDMA machinery */
-    ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
-    return 0;
-}
-
-static int
-ata_marvell_edma_ch_detach(device_t dev)
-{
-    struct ata_channel *ch = device_get_softc(dev);
-
-    if (ch->dma.work_tag && ch->dma.work_map)
-	bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
-	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
-    ata_dmafini(dev);
-    return (0);
-}
-
-static int
-ata_marvell_edma_status(device_t dev)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
-    struct ata_channel *ch = device_get_softc(dev);
-    u_int32_t cause = ATA_INL(ctlr->r_res1, 0x01d60);
-    int shift = (ch->unit << 1) + (ch->unit > 3);
-
-    if (cause & (1 << shift)) {
-
-	/* clear interrupt(s) */
-	ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
-
-	/* do we have any PHY events ? */
-	ata_sata_phy_check_events(dev, -1);
-    }
-
-    /* do we have any device action ? */
-    return (cause & (2 << shift));
-}
-
-/* must be called with ATA channel locked and state_mtx held */
-static int
-ata_marvell_edma_begin_transaction(struct ata_request *request)
-{
-    struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
-    struct ata_channel *ch = device_get_softc(request->parent);
-    u_int32_t req_in;
-    u_int8_t *bytep;
-    int i;
-    int error, slot;
-
-    /* only DMA R/W goes through the EMDA machine */
-    if (request->u.ata.command != ATA_READ_DMA &&
-	request->u.ata.command != ATA_WRITE_DMA &&
-	request->u.ata.command != ATA_READ_DMA48 &&
-	request->u.ata.command != ATA_WRITE_DMA48) {
-
-	/* disable the EDMA machinery */
-	if (ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)
-	    ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
-	return ata_begin_transaction(request);
-    }
-
-    /* check sanity, setup SG list and DMA engine */
-    if ((error = ch->dma.load(request, NULL, NULL))) {
-	device_printf(request->parent, "setting up DMA failed\n");
-	request->result = error;
-	return ATA_OP_FINISHED;
-    }
-
-    /* get next free request queue slot */
-    req_in = ATA_INL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch));
-    slot = (((req_in & ~0xfffffc00) >> 5) + 0) & 0x1f;
-    bytep = (u_int8_t *)(ch->dma.work);
-    bytep += (slot << 5);
-
-    /* fill in this request */
-    le32enc(bytep + 0 * sizeof(u_int32_t),
-	request->dma->sg_bus & 0xffffffff);
-    le32enc(bytep + 1 * sizeof(u_int32_t),
-	(u_int64_t)request->dma->sg_bus >> 32);
-    if (ctlr->chip->cfg2 != MV_6042 && ctlr->chip->cfg2 != MV_7042) {
-	    le16enc(bytep + 4 * sizeof(u_int16_t),
-		(request->flags & ATA_R_READ ? 0x01 : 0x00) | (request->tag << 1));
-
-	    i = 10;
-	    bytep[i++] = (request->u.ata.count >> 8) & 0xff;
-	    bytep[i++] = 0x10 | ATA_COUNT;
-	    bytep[i++] = request->u.ata.count & 0xff;
-	    bytep[i++] = 0x10 | ATA_COUNT;
-
-	    bytep[i++] = (request->u.ata.lba >> 24) & 0xff;
-	    bytep[i++] = 0x10 | ATA_SECTOR;
-	    bytep[i++] = request->u.ata.lba & 0xff;
-	    bytep[i++] = 0x10 | ATA_SECTOR;
-
-	    bytep[i++] = (request->u.ata.lba >> 32) & 0xff;
-	    bytep[i++] = 0x10 | ATA_CYL_LSB;
-	    bytep[i++] = (request->u.ata.lba >> 8) & 0xff;
-	    bytep[i++] = 0x10 | ATA_CYL_LSB;
-
-	    bytep[i++] = (request->u.ata.lba >> 40) & 0xff;
-	    bytep[i++] = 0x10 | ATA_CYL_MSB;
-	    bytep[i++] = (request->u.ata.lba >> 16) & 0xff;
-	    bytep[i++] = 0x10 | ATA_CYL_MSB;
-
-	    bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0xf);
-	    bytep[i++] = 0x10 | ATA_DRIVE;
-
-	    bytep[i++] = request->u.ata.command;
-	    bytep[i++] = 0x90 | ATA_COMMAND;
-    } else {
-	    le32enc(bytep + 2 * sizeof(u_int32_t),
-		(request->flags & ATA_R_READ ? 0x01 : 0x00) | (request->tag << 1));
-
-	    i = 16;
-	    bytep[i++] = 0;
-	    bytep[i++] = 0;
-	    bytep[i++] = request->u.ata.command;
-	    bytep[i++] = request->u.ata.feature & 0xff;
-
-	    bytep[i++] = request->u.ata.lba & 0xff;
-	    bytep[i++] = (request->u.ata.lba >> 8) & 0xff;
-	    bytep[i++] = (request->u.ata.lba >> 16) & 0xff;
-	    bytep[i++] = ATA_D_LBA | ATA_D_IBM | ((request->u.ata.lba >> 24) & 0x0f);
-
-	    bytep[i++] = (request->u.ata.lba >> 24) & 0xff;
-	    bytep[i++] = (request->u.ata.lba >> 32) & 0xff;
-	    bytep[i++] = (request->u.ata.lba >> 40) & 0xff;
-	    bytep[i++] = (request->u.ata.feature >> 8) & 0xff;
-
-	    bytep[i++] = request->u.ata.count & 0xff;
-	    bytep[i++] = (request->u.ata.count >> 8) & 0xff;
-	    bytep[i++] = 0;
-	    bytep[i++] = 0;
-    }
-
-    bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
-	BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
-
-    /* enable EDMA machinery if needed */
-    if (!(ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001)) {
-	ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
-	while (!(ATA_INL(ctlr->r_res1,
-			 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
-	    DELAY(10);
-    }
-
-    /* tell EDMA it has a new request */
-    slot = (((req_in & ~0xfffffc00) >> 5) + 1) & 0x1f;
-    req_in &= 0xfffffc00;
-    req_in += (slot << 5);
-    ATA_OUTL(ctlr->r_res1, 0x02014 + ATA_MV_EDMA_BASE(ch), req_in);
-   
-    return ATA_OP_CONTINUES;
-}
-
-/* must be called with ATA channel locked and state_mtx held */
-static int
-ata_marvell_edma_end_transaction(struct ata_request *request)
-{
-    struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
-    struct ata_channel *ch = device_get_softc(request->parent);
-    int offset = (ch->unit > 3 ? 0x30014 : 0x20014);
-    u_int32_t icr = ATA_INL(ctlr->r_res1, offset);
-    int res;
-
-    /* EDMA interrupt */
-    if ((icr & (0x0001 << (ch->unit & 3)))) {
-	struct ata_marvell_response *response;
-	u_int32_t rsp_in, rsp_out;
-	int slot;
-
-	/* stop timeout */
-	callout_stop(&request->callout);
-
-	/* get response ptr's */
-	rsp_in = ATA_INL(ctlr->r_res1, 0x02020 + ATA_MV_EDMA_BASE(ch));
-	rsp_out = ATA_INL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch));
-	slot = (((rsp_in & ~0xffffff00) >> 3)) & 0x1f;
-	rsp_out &= 0xffffff00;
-	rsp_out += (slot << 3);
-	bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
-	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
-	response = (struct ata_marvell_response *)
-		   (ch->dma.work + 1024 + (slot << 3));
-
-	/* record status for this request */
-	request->status = response->dev_status;
-	request->error = 0; 
-
-	/* ack response */
-	ATA_OUTL(ctlr->r_res1, 0x02024 + ATA_MV_EDMA_BASE(ch), rsp_out);
-
-	/* update progress */
-	if (!(request->status & ATA_S_ERROR) &&
-	    !(request->flags & ATA_R_TIMEOUT))
-	    request->donecount = request->bytecount;
-
-	/* unload SG list */
-	ch->dma.unload(request);
-
-	res = ATA_OP_FINISHED;
-    }
-
-    /* legacy ATA interrupt */
-    else {
-	res = ata_end_transaction(request);
-    }
-
-    /* ack interrupt */
-    ATA_OUTL(ctlr->r_res1, offset, ~(icr & (0x0101 << (ch->unit & 3))));
-    return res;
-}
-
-static void
-ata_marvell_edma_reset(device_t dev)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
-    struct ata_channel *ch = device_get_softc(dev);
-
-    /* disable the EDMA machinery */
-    ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000002);
-    while ((ATA_INL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch)) & 0x00000001))
-	DELAY(10);
-
-    /* clear SATA error register */
-    ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
-
-    /* clear any outstanding error interrupts */
-    ATA_OUTL(ctlr->r_res1, 0x02008 + ATA_MV_EDMA_BASE(ch), 0x0);
-
-    /* unmask all error interrupts */
-    ATA_OUTL(ctlr->r_res1, 0x0200c + ATA_MV_EDMA_BASE(ch), ~0x0);
-
-    /* enable channel and test for devices */
-    if (ata_sata_phy_reset(dev, -1, 1))
-	ata_generic_reset(dev);
-    else
-	ch->devices = 0;
-
-    /* enable EDMA machinery */
-    ATA_OUTL(ctlr->r_res1, 0x02028 + ATA_MV_EDMA_BASE(ch), 0x00000001);
-}
-
-static void
-ata_marvell_edma_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs,
-			   int error)
-{
-    struct ata_dmasetprd_args *args = xsc;
-    struct ata_marvell_dma_prdentry *prd = args->dmatab;
-    int i;
-
-    if ((args->error = error))
-	return;
-
-    for (i = 0; i < nsegs; i++) {
-	prd[i].addrlo = htole32(segs[i].ds_addr);
-	prd[i].count = htole32(segs[i].ds_len);
-	prd[i].addrhi = htole32((u_int64_t)segs[i].ds_addr >> 32);
-	prd[i].reserved = 0;
-    }
-    prd[i - 1].count |= htole32(ATA_DMA_EOT);
-    KASSERT(nsegs <= ATA_DMA_ENTRIES, ("too many DMA segment entries\n"));
-    args->nsegs = nsegs;
-}
-
-static void
-ata_marvell_edma_dmainit(device_t dev)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
-    struct ata_channel *ch = device_get_softc(dev);
-
-    /* note start and stop are not used here */
-    ch->dma.setprd = ata_marvell_edma_dmasetprd;
-	
-    /* if 64bit support present adjust max address used */
-    if (ATA_INL(ctlr->r_res1, 0x00d00) & 0x00000004)
-	ch->dma.max_address = BUS_SPACE_MAXADDR;
-
-    /* chip does not reliably do 64K DMA transfers */
-    if (ctlr->chip->cfg2 == MV_50XX || ctlr->chip->cfg2 == MV_60XX)
-	ch->dma.max_iosize = 64 * DEV_BSIZE;
-    ata_dmainit(dev);
-}
-
 ATA_DECLARE_DRIVER(ata_marvell);
diff --git a/sys/dev/ata/chipsets/ata-nvidia.c b/sys/dev/ata/chipsets/ata-nvidia.c
index 5a7a381..1d17981 100644
--- a/sys/dev/ata/chipsets/ata-nvidia.c
+++ b/sys/dev/ata/chipsets/ata-nvidia.c
@@ -62,10 +62,6 @@ static int ata_nvidia_setmode(device_t dev, int target, int mode);
 #define NV4             0x01
 #define NVQ             0x02
 #define NVAHCI          0x04
-#define NVNOFORCE       0x08
-
-static int force_ahci = 1;
-TUNABLE_INT("hw.ahci.force", &force_ahci);
 
 /*
  * nVidia chipset support functions
@@ -161,7 +157,7 @@ ata_nvidia_probe(device_t dev)
      { ATA_NFORCE_MCP79_AA, 0, NVAHCI,  0, ATA_SA300, "nForce MCP79" },
      { ATA_NFORCE_MCP79_AB, 0, NVAHCI,  0, ATA_SA300, "nForce MCP79" },
      { ATA_NFORCE_MCP89_A0, 0, NVAHCI,  0, ATA_SA300, "nForce MCP89" },
-     { ATA_NFORCE_MCP89_A1, 0, NVAHCI|NVNOFORCE, 0, ATA_SA300, "nForce MCP89" },
+     { ATA_NFORCE_MCP89_A1, 0, NVAHCI,  0, ATA_SA300, "nForce MCP89" },
      { ATA_NFORCE_MCP89_A2, 0, NVAHCI,  0, ATA_SA300, "nForce MCP89" },
      { ATA_NFORCE_MCP89_A3, 0, NVAHCI,  0, ATA_SA300, "nForce MCP89" },
      { ATA_NFORCE_MCP89_A4, 0, NVAHCI,  0, ATA_SA300, "nForce MCP89" },
@@ -180,13 +176,12 @@ ata_nvidia_probe(device_t dev)
     if (!(ctlr->chip = ata_match_chip(dev, ids)))
 	return ENXIO;
 
-    ata_set_desc(dev);
     if ((ctlr->chip->cfg1 & NVAHCI) &&
-	((force_ahci == 1 && (ctlr->chip->cfg1 & NVNOFORCE) == 0) ||
-	 pci_get_subclass(dev) != PCIS_STORAGE_IDE))
-	ctlr->chipinit = ata_ahci_chipinit;
-    else
-	ctlr->chipinit = ata_nvidia_chipinit;
+	    pci_get_subclass(dev) != PCIS_STORAGE_IDE)
+	return (ENXIO);
+
+    ata_set_desc(dev);
+    ctlr->chipinit = ata_nvidia_chipinit;
     return (BUS_PROBE_LOW_PRIORITY);
 }
 
@@ -351,4 +346,3 @@ ata_nvidia_setmode(device_t dev, int target, int mode)
 }
 
 ATA_DECLARE_DRIVER(ata_nvidia);
-MODULE_DEPEND(ata_nvidia, ata_ahci, 1, 1, 1);
diff --git a/sys/dev/ata/chipsets/ata-siliconimage.c b/sys/dev/ata/chipsets/ata-siliconimage.c
index bf431a1..f48ecdf 100644
--- a/sys/dev/ata/chipsets/ata-siliconimage.c
+++ b/sys/dev/ata/chipsets/ata-siliconimage.c
@@ -59,21 +59,9 @@ static int ata_sii_ch_detach(device_t dev);
 static int ata_sii_status(device_t dev);
 static void ata_sii_reset(device_t dev);
 static int ata_sii_setmode(device_t dev, int target, int mode);
-static int ata_siiprb_ch_attach(device_t dev);
-static int ata_siiprb_ch_detach(device_t dev);
-static int ata_siiprb_status(device_t dev);
-static int ata_siiprb_begin_transaction(struct ata_request *request);
-static int ata_siiprb_end_transaction(struct ata_request *request);
-static int ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result);
-static int ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t result);
-static u_int32_t ata_siiprb_softreset(device_t dev, int port);
-static void ata_siiprb_reset(device_t dev);
-static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
-static void ata_siiprb_dmainit(device_t dev);
 
 /* misc defines */
 #define SII_MEMIO	1
-#define SII_PRBIO	2
 #define SII_INTR	0x01
 #define SII_SETCLK	0x02
 #define SII_BUG		0x04
@@ -94,10 +82,6 @@ ata_sii_probe(device_t dev)
      { ATA_SII3512,   0x00, SII_MEMIO, SII_BUG,    ATA_SA150, "3512" },
      { ATA_SII3112,   0x00, SII_MEMIO, SII_BUG,    ATA_SA150, "3112" },
      { ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG,    ATA_SA150, "3112" },
-     { ATA_SII3124,   0x00, SII_PRBIO, SII_4CH,    ATA_SA300, "3124" },
-     { ATA_SII3132,   0x00, SII_PRBIO, 0,          ATA_SA300, "3132" },
-     { ATA_SII3132_1, 0x00, SII_PRBIO, 0,          ATA_SA300, "3132" },
-     { ATA_SII3132_2, 0x00, SII_PRBIO, 0,          ATA_SA300, "3132" },
      { ATA_SII0680,   0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "680" },
      { ATA_CMD649,    0x00, 0,         SII_INTR,   ATA_UDMA5, "(CMD) 649" },
      { ATA_CMD648,    0x00, 0,         SII_INTR,   ATA_UDMA4, "(CMD) 648" },
@@ -125,44 +109,6 @@ ata_sii_chipinit(device_t dev)
 	return ENXIO;
 
     switch (ctlr->chip->cfg1) {
-    case SII_PRBIO:
-	ctlr->r_type1 = SYS_RES_MEMORY;
-	ctlr->r_rid1 = PCIR_BAR(0);
-	if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
-						    &ctlr->r_rid1, RF_ACTIVE)))
-	    return ENXIO;
-
-	ctlr->r_rid2 = PCIR_BAR(2);
-	ctlr->r_type2 = SYS_RES_MEMORY;
-	if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
-						    &ctlr->r_rid2, RF_ACTIVE))){
-	    bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
-	    return ENXIO;
-	}
-#ifdef __sparc64__
-	if (!bus_space_map(rman_get_bustag(ctlr->r_res2),
-	    rman_get_bushandle(ctlr->r_res2), rman_get_size(ctlr->r_res2),
-	    BUS_SPACE_MAP_LINEAR, NULL)) {
-	    	bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,
-		    ctlr->r_res1);
-		bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2,
-		    ctlr->r_res2);
-		return (ENXIO);
-	}
-#endif
-	ctlr->ch_attach = ata_siiprb_ch_attach;
-	ctlr->ch_detach = ata_siiprb_ch_detach;
-	ctlr->reset = ata_siiprb_reset;
-	ctlr->setmode = ata_sata_setmode;
-	ctlr->getrev = ata_sata_getrev;
-	ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2;
-
-	/* reset controller */
-	ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000);
-	DELAY(10000);
-	ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f);
-	break;
-
     case SII_MEMIO:
 	ctlr->r_type2 = SYS_RES_MEMORY;
 	ctlr->r_rid2 = PCIR_BAR(5);
@@ -446,509 +392,4 @@ ata_sii_setmode(device_t dev, int target, int mode)
 	return (mode);
 }
 
-struct ata_siiprb_dma_prdentry {
-    u_int64_t addr;
-    u_int32_t count;
-    u_int32_t control;
-} __packed;
-
-#define ATA_SIIPRB_DMA_ENTRIES		129
-struct ata_siiprb_ata_command {
-    struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES];
-} __packed;
-
-struct ata_siiprb_atapi_command {
-    u_int8_t ccb[16];
-    struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES];
-} __packed;
-
-struct ata_siiprb_command {
-    u_int16_t control;
-    u_int16_t protocol_override;
-    u_int32_t transfer_count;
-    u_int8_t fis[24];
-    union {
-	struct ata_siiprb_ata_command ata;
-	struct ata_siiprb_atapi_command atapi;
-    } u;
-} __packed;
-
-static int
-ata_siiprb_ch_attach(device_t dev)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
-    struct ata_channel *ch = device_get_softc(dev);
-    int offset = ch->unit * 0x2000;
-
-    ata_siiprb_dmainit(dev);
-
-    /* set the SATA resources */
-    ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
-    ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset;
-    ch->r_io[ATA_SERROR].res = ctlr->r_res2;
-    ch->r_io[ATA_SERROR].offset = 0x1f08 + offset;
-    ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
-    ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset;
-    ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
-    ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset;
-   
-    ch->hw.status = ata_siiprb_status;
-    ch->hw.begin_transaction = ata_siiprb_begin_transaction;
-    ch->hw.end_transaction = ata_siiprb_end_transaction;
-    ch->hw.command = NULL;	/* not used here */
-    ch->hw.softreset = ata_siiprb_softreset;
-    ch->hw.pm_read = ata_siiprb_pm_read;
-    ch->hw.pm_write = ata_siiprb_pm_write;
-    ch->flags |= ATA_NO_SLAVE;
-    ch->flags |= ATA_SATA;
-    return 0;
-}
-
-static int
-ata_siiprb_ch_detach(device_t dev)
-{
-    struct ata_channel *ch = device_get_softc(dev);
-
-    if (ch->dma.work_tag && ch->dma.work_map)
-	bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
-	    BUS_DMASYNC_POSTWRITE);
-    ata_dmafini(dev);
-    return 0;
-}
-
-static int
-ata_siiprb_status(device_t dev)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
-    struct ata_channel *ch = device_get_softc(dev);
-    u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044);
-    int offset = ch->unit * 0x2000;
-
-    if (action & (1 << ch->unit)) {
-	u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset);
-
-	/* do we have any PHY events ? */
-	ata_sata_phy_check_events(dev, -1);
-
-	/* clear interrupt(s) */
-	ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus);
-
-	/* do we have any device action ? */
-	return (istatus & 0x00000003);
-    }
-    return 0;
-}
-
-static int
-ata_siiprb_begin_transaction(struct ata_request *request)
-{
-    struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
-    struct ata_channel *ch = device_get_softc(request->parent);
-    struct ata_siiprb_command *prb;
-    struct ata_siiprb_dma_prdentry *prd;
-    int offset = ch->unit * 0x2000;
-    u_int64_t prb_bus;
-
-    /* SOS XXX */
-    if (request->u.ata.command == ATA_DEVICE_RESET) {
-        request->result = 0;
-        return ATA_OP_FINISHED;
-    }
-
-    /* get a piece of the workspace for this request */
-    prb = (struct ata_siiprb_command *)ch->dma.work;
-
-    /* clear the prb structure */
-    bzero(prb, sizeof(struct ata_siiprb_command));
-
-    /* setup the FIS for this request */
-    if (!ata_request2fis_h2d(request, &prb->fis[0])) {
-        device_printf(request->parent, "setting up SATA FIS failed\n");
-        request->result = EIO;
-        return ATA_OP_FINISHED;
-    }
-
-    /* setup transfer type */
-    if (request->flags & ATA_R_ATAPI) {
-	bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16);
-	if (request->flags & ATA_R_ATAPI16)
-	    ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020);
-	else
-	    ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020);
-	if (request->flags & ATA_R_READ)
-	    prb->control = htole16(0x0010);
-	if (request->flags & ATA_R_WRITE)
-	    prb->control = htole16(0x0020);
-	prd = &prb->u.atapi.prd[0];
-    }
-    else
-	prd = &prb->u.ata.prd[0];
-
-    /* if request moves data setup and load SG list */
-    if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
-	if (ch->dma.load(request, prd, NULL)) {
-	    device_printf(request->parent, "setting up DMA failed\n");
-	    request->result = EIO;
-	    return ATA_OP_FINISHED;
-	}
-    }
-
-    bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_PREWRITE);
-
-    /* activate the prb */
-    prb_bus = ch->dma.work_bus;
-    ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus);
-    ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus>>32);
-
-    /* start the timeout */
-    callout_reset(&request->callout, request->timeout * hz,
-                  (timeout_t*)ata_timeout, request);
-    return ATA_OP_CONTINUES;
-}
-
-static int
-ata_siiprb_end_transaction(struct ata_request *request)
-{
-    struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
-    struct ata_channel *ch = device_get_softc(request->parent);
-    struct ata_siiprb_command *prb;
-    int offset = ch->unit * 0x2000;
-    int error, timeout;
-
-    /* kill the timeout */
-    callout_stop(&request->callout);
-
-    bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_POSTWRITE);
-
-    prb = (struct ata_siiprb_command *)
-	((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
-
-    /* any controller errors flagged ? */
-    if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) {
-	if (bootverbose)
-	    printf("ata_siiprb_end_transaction %s error=%08x\n",
-		   ata_cmd2str(request), error);
-
-	/* if device error status get details */
-	if (error == 1 || error == 2) {
-	    request->status = prb->fis[2];
-	    if (request->status & ATA_S_ERROR)
-		request->error = prb->fis[3];
-	}
-
- 	/* SOS XXX handle other controller errors here */
-
-	/* initialize port */
-	ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004);
-
-	/* poll for port ready */
-	for (timeout = 0; timeout < 1000; timeout++) {
-	    DELAY(1000);
-            if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000)
-        	break;
-	}
-	if (bootverbose) {
-	    if (timeout >= 1000)
-		device_printf(ch->dev, "port initialize timeout\n");
-	    else
-		device_printf(ch->dev, "port initialize time=%dms\n", timeout);
-	}
-    }
-
-    /* Read back registers to the request struct. */
-    if ((request->flags & ATA_R_ATAPI) == 0 &&
-	((request->status & ATA_S_ERROR) ||
-	 (request->flags & (ATA_R_CONTROL | ATA_R_NEEDRESULT)))) {
-	request->u.ata.count = prb->fis[12] | ((u_int16_t)prb->fis[13] << 8);
-	request->u.ata.lba = prb->fis[4] | ((u_int64_t)prb->fis[5] << 8) |
-			     ((u_int64_t)prb->fis[6] << 16);
-	if (request->flags & ATA_R_48BIT)
-	    request->u.ata.lba |= ((u_int64_t)prb->fis[8] << 24) |
-				  ((u_int64_t)prb->fis[9] << 32) |
-				  ((u_int64_t)prb->fis[10] << 40);
-	else
-	    request->u.ata.lba |= ((u_int64_t)(prb->fis[7] & 0x0f) << 24);
-    }
-
-    /* update progress */
-    if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) {
-	if (request->flags & ATA_R_READ)
-	    request->donecount = le32toh(prb->transfer_count);
-	else
-	    request->donecount = request->bytecount;
-    }
-
-    /* release SG list etc */
-    ch->dma.unload(request);
-
-    return ATA_OP_FINISHED;
-}
-
-static int
-ata_siiprb_issue_cmd(device_t dev)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
-    struct ata_channel *ch = device_get_softc(dev);
-    u_int64_t prb_bus = ch->dma.work_bus;
-    u_int32_t status;
-    int offset = ch->unit * 0x2000;
-    int timeout;
-
-    bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_PREWRITE);
-
-    /* issue command to chip */
-    ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus);
-    ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus >> 32);
-
-    /* poll for command finished */
-    for (timeout = 0; timeout < 10000; timeout++) {
-        DELAY(1000);
-        if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000)
-            break;
-    }
-
-    bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_POSTWRITE);
-
-    // SOS XXX ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x00010000);
-    ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x08ff08ff);
-
-    if (timeout >= 1000)
-	return EIO;
-
-    if (bootverbose)
-	device_printf(dev, "siiprb_issue_cmd time=%dms status=%08x\n",
-		      timeout, status);
-    return 0;
-}
-
-static int
-ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
-    struct ata_channel *ch = device_get_softc(dev);
-    struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
-    int offset = ch->unit * 0x2000;
-
-    if (port < 0) {
-	*result = ATA_IDX_INL(ch, reg);
-	return (0);
-    }
-    if (port < ATA_PM) {
-	switch (reg) {
-	case ATA_SSTATUS:
-	    reg = 0;
-	    break;
-	case ATA_SERROR:
-	    reg = 1;
-	    break;
-	case ATA_SCONTROL:
-	    reg = 2;
-	    break;
-	default:
-	    return (EINVAL);
-	}
-    }
-    bzero(prb, sizeof(struct ata_siiprb_command));
-    prb->fis[0] = 0x27;	/* host to device */
-    prb->fis[1] = 0x8f;	/* command FIS to PM port */
-    prb->fis[2] = ATA_READ_PM;
-    prb->fis[3] = reg;
-    prb->fis[7] = port;
-    if (ata_siiprb_issue_cmd(dev)) {
-	device_printf(dev, "error reading PM port\n");
-	return EIO;
-    }
-    prb = (struct ata_siiprb_command *)
-	((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
-    *result = prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
-    return 0;
-}
-
-static int
-ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t value)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
-    struct ata_channel *ch = device_get_softc(dev);
-    struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
-    int offset = ch->unit * 0x2000;
-
-    if (port < 0) {
-	ATA_IDX_OUTL(ch, reg, value);
-	return (0);
-    }
-    if (port < ATA_PM) {
-	switch (reg) {
-	case ATA_SSTATUS:
-	    reg = 0;
-	    break;
-	case ATA_SERROR:
-	    reg = 1;
-	    break;
-	case ATA_SCONTROL:
-	    reg = 2;
-	    break;
-	default:
-	    return (EINVAL);
-	}
-    }
-    bzero(prb, sizeof(struct ata_siiprb_command));
-    prb->fis[0] = 0x27;	/* host to device */
-    prb->fis[1] = 0x8f;	/* command FIS to PM port */
-    prb->fis[2] = ATA_WRITE_PM;
-    prb->fis[3] = reg;
-    prb->fis[7] = port;
-    prb->fis[12] = value & 0xff;
-    prb->fis[4] = (value >> 8) & 0xff;
-    prb->fis[5] = (value >> 16) & 0xff;
-    prb->fis[6] = (value >> 24) & 0xff;
-    if (ata_siiprb_issue_cmd(dev)) {
-	device_printf(dev, "error writing PM port\n");
-	return ATA_E_ABORT;
-    }
-    prb = (struct ata_siiprb_command *)
-	((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
-    return prb->fis[3];
-}
-
-static u_int32_t
-ata_siiprb_softreset(device_t dev, int port)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
-    struct ata_channel *ch = device_get_softc(dev);
-    struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
-    u_int32_t signature;
-    int offset = ch->unit * 0x2000;
-
-    /* setup the workspace for a soft reset command */
-    bzero(prb, sizeof(struct ata_siiprb_command));
-    prb->control = htole16(0x0080);
-    prb->fis[1] = port & 0x0f;
-
-    /* issue soft reset */
-    if (ata_siiprb_issue_cmd(dev))
-	return -1;
-
-    ata_udelay(150000);
-
-    /* get possible signature */
-    prb = (struct ata_siiprb_command *)
-	((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
-    signature=prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
-
-    /* clear error bits/interrupt */
-    ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff);
-
-    return signature;
-}
-
-static void
-ata_siiprb_reset(device_t dev)
-{
-    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
-    struct ata_channel *ch = device_get_softc(dev);
-    int offset = ch->unit * 0x2000;
-    u_int32_t status, signature;
-    int timeout;
-
-    /* disable interrupts */
-    ATA_OUTL(ctlr->r_res2, 0x1014 + offset, 0x000000ff);
-
-    /* reset channel HW */
-    ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001);
-    DELAY(1000);
-    ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001);
-    DELAY(10000);
-
-    /* poll for channel ready */
-    for (timeout = 0; timeout < 1000; timeout++) {
-        if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000)
-            break;
-        DELAY(1000);
-    }
-
-    if (bootverbose) {
-	if (timeout >= 1000)
-	    device_printf(dev, "channel HW reset timeout\n");
-	else
-	    device_printf(dev, "channel HW reset time=%dms\n", timeout);
-    }
-
-    /* reset phy */
-    if (!ata_sata_phy_reset(dev, -1, 1)) {
-	if (bootverbose)
-	    device_printf(dev, "phy reset found no device\n");
-	ch->devices = 0;
-	goto finish;
-    }
-
-    /* issue soft reset */
-    signature = ata_siiprb_softreset(dev, ATA_PM);
-    if (bootverbose)
-	device_printf(dev, "SIGNATURE=%08x\n", signature);
-
-    /* figure out whats there */
-    switch (signature >> 16) {
-    case 0x0000:
-	ch->devices = ATA_ATA_MASTER;
-	break;
-    case 0x9669:
-	ch->devices = ATA_PORTMULTIPLIER;
-	ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x2000); /* enable PM support */
-	//SOS XXX need to clear all PM status and interrupts!!!!
-	ata_pm_identify(dev);
-	break;
-    case 0xeb14:
-	ch->devices = ATA_ATAPI_MASTER;
-	break;
-    default:
-	ch->devices = 0;
-    }
-    if (bootverbose)
-        device_printf(dev, "siiprb_reset devices=%08x\n", ch->devices);
-
-finish:
-    /* clear interrupt(s) */
-    ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff);
-
-    /* require explicit interrupt ack */
-    ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008);
-
-    /* 64bit mode */
-    ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400);
-
-    /* enable interrupts wanted */
-    ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff);
-}
-
-static void
-ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
-{
-    struct ata_dmasetprd_args *args = xsc;
-    struct ata_siiprb_dma_prdentry *prd = args->dmatab;
-    int i;
-
-    if ((args->error = error))
-	return;
-
-    for (i = 0; i < nsegs; i++) {
-	prd[i].addr = htole64(segs[i].ds_addr);
-	prd[i].count = htole32(segs[i].ds_len);
-    }
-    prd[i - 1].control = htole32(ATA_DMA_EOT);
-    KASSERT(nsegs <= ATA_SIIPRB_DMA_ENTRIES,("too many DMA segment entries\n"));
-    args->nsegs = nsegs;
-}
-
-static void
-ata_siiprb_dmainit(device_t dev)
-{
-    struct ata_channel *ch = device_get_softc(dev);
-
-    /* note start and stop are not used here */
-    ch->dma.setprd = ata_siiprb_dmasetprd;
-    ch->dma.max_address = BUS_SPACE_MAXADDR;
-    ch->dma.max_iosize = (ATA_SIIPRB_DMA_ENTRIES - 1) * PAGE_SIZE;
-    ata_dmainit(dev);
-}
-
 ATA_DECLARE_DRIVER(ata_sii);
diff --git a/sys/dev/ata/chipsets/ata-via.c b/sys/dev/ata/chipsets/ata-via.c
index f56d707..db1a879 100644
--- a/sys/dev/ata/chipsets/ata-via.c
+++ b/sys/dev/ata/chipsets/ata-via.c
@@ -78,7 +78,6 @@ static int ata_via_sata_status(device_t dev);
 #define VIACLK          0x01
 #define VIABUG          0x02
 #define VIABAR          0x04
-#define VIAAHCI         0x08
 #define VIASATA         0x10
 
 /*
@@ -120,7 +119,6 @@ ata_via_probe(device_t dev)
      { ATA_VIA8237S,  0x00, 7,      0x00,    ATA_SA150, "8237S" },
      { ATA_VIA8237_5372, 0x00, 7,   0x00,    ATA_SA300, "8237" },
      { ATA_VIA8237_7372, 0x00, 7,   0x00,    ATA_SA300, "8237" },
-     { ATA_VIA8251,   0x00, 0,      VIAAHCI, ATA_SA300, "8251" },
      { 0, 0, 0, 0, 0, 0 }};
 
     if (pci_get_vendor(dev) != ATA_VIA_ID)
@@ -152,11 +150,6 @@ ata_via_chipinit(device_t dev)
     if (ata_setup_interrupt(dev, ata_generic_intr))
 	return ENXIO;
 
-    /* AHCI SATA */
-    if (ctlr->chip->cfg2 & VIAAHCI) {
-	if (ata_ahci_chipinit(dev) != ENXIO)
-	    return (0);
-    }
     /* 2 SATA with "SATA registers" at PCI config space + PATA on secondary */
     if (ctlr->chip->cfg2 & VIASATA) {
 	ctlr->ch_attach = ata_via_sata_ch_attach;
@@ -554,4 +547,3 @@ ata_via_sata_status(device_t dev)
 }
 
 ATA_DECLARE_DRIVER(ata_via);
-MODULE_DEPEND(ata_via, ata_ahci, 1, 1, 1);
diff --git a/sys/modules/ata/atapci/chipsets/Makefile b/sys/modules/ata/atapci/chipsets/Makefile
index 5468359..c2166566 100644
--- a/sys/modules/ata/atapci/chipsets/Makefile
+++ b/sys/modules/ata/atapci/chipsets/Makefile
@@ -1,5 +1,5 @@
 # $FreeBSD$
 
-SUBDIR += ataacard ataacerlabs ataadaptec ataahci ataamd ataati atacenatek atacypress atacyrix atahighpoint ataintel ataite atajmicron atamarvell atamicron atanational atanetcell atanvidia atapromise ataserverworks atasiliconimage atasis atavia
+SUBDIR += ataacard ataacerlabs ataamd ataati atacenatek atacypress atacyrix atahighpoint ataintel ataite atajmicron atamarvell atamicron atanational atanetcell atanvidia atapromise ataserverworks atasiliconimage atasis atavia
 
 .include <bsd.subdir.mk>
diff --git a/sys/modules/ata/atapci/chipsets/ataadaptec/Makefile b/sys/modules/ata/atapci/chipsets/ataadaptec/Makefile
deleted file mode 100644
index c0664a9..0000000
--- a/sys/modules/ata/atapci/chipsets/ataadaptec/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-# $FreeBSD$
-
-.PATH: ${.CURDIR}/../../../../../dev/ata/chipsets
-
-KMOD=	ataadaptec
-SRCS=	ata-adaptec.c
-SRCS+=	ata_if.h bus_if.h device_if.h pci_if.h
-
-.include <bsd.kmod.mk>
diff --git a/sys/modules/ata/atapci/chipsets/ataahci/Makefile b/sys/modules/ata/atapci/chipsets/ataahci/Makefile
deleted file mode 100644
index e8a5d32..0000000
--- a/sys/modules/ata/atapci/chipsets/ataahci/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-# $FreeBSD$
-
-.PATH: ${.CURDIR}/../../../../../dev/ata/chipsets
-
-KMOD=	ataahci
-SRCS=	ata-ahci.c
-SRCS+=	ata_if.h bus_if.h device_if.h pci_if.h
-
-.include <bsd.kmod.mk>