Do a trivial reformatting of the comment, to record the proper commit

message for r238973:

Rdtsc instruction is not synchronized, it seems on some Intel cores it
can bypass even the locked instructions.  As a result, rdtsc executed
on different cores may return unordered TSC values even when the rdtsc
appearance in the instruction sequences is provably ordered.

Similarly to what has been done in r238755 for TSC synchronization
test, add explicit fences right before rdtsc in the timecounters 'get'
functions.  Intel recommends to use LFENCE, while AMD refers to
MFENCE. For VIA follow what Linux does and use LFENCE.  With this
change, I see no reordered reads of TSC on Nehalem.

Change the rmb() to inlined CPUID in the SMP TSC synchronization test.
On i386, locked instruction is used for rmb(), and as noted earlier,
it is not enough. Since i386 machine may not support SSE2, do simplest
possible synchronization with CPUID.

MFC after:	  1 week
Discussed with:	  avg, bde, jkim

1 files changed, 1 insertions, 2 deletions

diff --git a/sys/x86/x86/tsc.c b/sys/x86/x86/tsc.c
index 3d8bd30..94bd520 100644
--- a/sys/x86/x86/tsc.c
+++ b/sys/x86/x86/tsc.c
@@ -354,8 +354,7 @@ init_TSC(void)
  * timecounters use MFENCE for AMD CPUs, and LFENCE for others (Intel
  * and VIA) when SSE2 is present, and nothing on older machines which
  * also do not issue RDTSC prematurely.  There, testing for SSE2 and
- * vendor is too cumbersome, and we learn about TSC presence from
- * CPUID.
+ * vendor is too cumbersome, and we learn about TSC presence from CPUID.
  *
  * Do not use do_cpuid(), since we do not need CPUID results, which
  * have to be written into memory with do_cpuid().