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| author | kib <kib@FreeBSD.org> | 2016-04-23 07:36:13 +0000 |
|---|---|---|
| committer | kib <kib@FreeBSD.org> | 2016-04-23 07:36:13 +0000 |
| commit | c82ec6211c20f1a8235d1eb37d69e925f5040a13 (patch) | |
| tree | c3e83a88a3c27a798f95ccd65679604216bfa90b /sys/x86 | |
| parent | 48f1966681c54559cfb75a24922874dca996bb6a (diff) | |
| download | FreeBSD-src-c82ec6211c20f1a8235d1eb37d69e925f5040a13.zip FreeBSD-src-c82ec6211c20f1a8235d1eb37d69e925f5040a13.tar.gz | |
MFC r298101:
Add x86 CPU features definitions published in the Intel SDM rev. 58.
Diffstat (limited to 'sys/x86')
| -rw-r--r-- | sys/x86/include/specialreg.h | 14 | ||||
| -rw-r--r-- | sys/x86/x86/identcpu.c | 14 |
2 files changed, 26 insertions, 2 deletions
diff --git a/sys/x86/include/specialreg.h b/sys/x86/include/specialreg.h index 5e7658b..3846efc 100644 --- a/sys/x86/include/specialreg.h +++ b/sys/x86/include/specialreg.h @@ -331,6 +331,7 @@ */ #define CPUID_STDEXT_FSGSBASE 0x00000001 #define CPUID_STDEXT_TSC_ADJUST 0x00000002 +#define CPUID_STDEXT_SGX 0x00000004 #define CPUID_STDEXT_BMI1 0x00000008 #define CPUID_STDEXT_HLE 0x00000010 #define CPUID_STDEXT_AVX2 0x00000020 @@ -340,7 +341,10 @@ #define CPUID_STDEXT_ERMS 0x00000200 #define CPUID_STDEXT_INVPCID 0x00000400 #define CPUID_STDEXT_RTM 0x00000800 +#define CPUID_STDEXT_PQM 0x00001000 +#define CPUID_STDEXT_NFPUSG 0x00002000 #define CPUID_STDEXT_MPX 0x00004000 +#define CPUID_STDEXT_PQE 0x00008000 #define CPUID_STDEXT_AVX512F 0x00010000 #define CPUID_STDEXT_RDSEED 0x00040000 #define CPUID_STDEXT_ADX 0x00080000 @@ -353,6 +357,16 @@ #define CPUID_STDEXT_SHA 0x20000000 /* + * CPUID instruction 7 Structured Extended Features, leaf 0 ecx info + */ +#define CPUID_STDEXT2_PREFETCHWT1 0x00000001 +#define CPUID_STDEXT2_UMIP 0x00000004 +#define CPUID_STDEXT2_PKU 0x00000008 +#define CPUID_STDEXT2_OSPKE 0x00000010 +#define CPUID_STDEXT2_RDPID 0x00400000 +#define CPUID_STDEXT2_SGXLC 0x40000000 + +/* * CPUID manufacturers identifiers */ #define AMD_VENDOR_ID "AuthenticAMD" diff --git a/sys/x86/x86/identcpu.c b/sys/x86/x86/identcpu.c index 59c8783..69a978f 100644 --- a/sys/x86/x86/identcpu.c +++ b/sys/x86/x86/identcpu.c @@ -888,6 +888,7 @@ printcpuinfo(void) /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ "\001FSGSBASE" "\002TSCADJ" + "\003SGX" /* Bit Manipulation Instructions */ "\004BMI1" /* Hardware Lock Elision */ @@ -907,9 +908,9 @@ printcpuinfo(void) "\014RTM" "\015PQM" "\016NFPUSG" - "\020PQE" /* Intel Memory Protection Extensions */ "\017MPX" + "\020PQE" /* AVX512 Foundation */ "\021AVX512F" /* Enhanced NRBG */ @@ -932,8 +933,11 @@ printcpuinfo(void) cpu_stdext_feature2, "\020" "\001PREFETCHWT1" + "\003UMIP" "\004PKU" "\005OSPKE" + "\027RDPID" + "\037SGXLC" ); } @@ -1880,7 +1884,10 @@ print_INTEL_TLB(u_int data) printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n"); break; case 0x63: - printf("Data TLB: 1 GByte pages, 4-way set associative, 4 entries\n"); + printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n"); + break; + case 0x64: + printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n"); break; case 0x66: printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n"); @@ -1996,6 +2003,9 @@ print_INTEL_TLB(u_int data) case 0xc3: printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n"); break; + case 0xc4: + printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n"); + break; case 0xca: printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n"); break; |
