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| author | sbruno <sbruno@FreeBSD.org> | 2015-09-04 15:40:19 +0000 |
|---|---|---|
| committer | sbruno <sbruno@FreeBSD.org> | 2015-09-04 15:40:19 +0000 |
| commit | c3f28072a721507c668befdc47e94d5760893be5 (patch) | |
| tree | 43b02f506c2d518455e0f8686ceec2525aabfe41 /sys/x86 | |
| parent | 7179ae751dd8ae4fd9cbbd5e3be417f8995f6bc0 (diff) | |
| download | FreeBSD-src-c3f28072a721507c668befdc47e94d5760893be5.zip FreeBSD-src-c3f28072a721507c668befdc47e94d5760893be5.tar.gz | |
MFC r276834
Update Features2 to display SDBG capability of processor. This is
showing up on Haswell-class CPUs
From the Intel SDM, "Table 3-20. Feature Information Returned in the
ECX Register"
11 | SDBG | A value of 1 indicates the processor supports
IA32_DEBUG_INTERFACE MSR for silicon debug.
Submitted by: jiashiun@gmail.com
Diffstat (limited to 'sys/x86')
| -rw-r--r-- | sys/x86/include/specialreg.h | 1 | ||||
| -rw-r--r-- | sys/x86/x86/identcpu.c | 2 |
2 files changed, 2 insertions, 1 deletions
diff --git a/sys/x86/include/specialreg.h b/sys/x86/include/specialreg.h index 8148f14..1de4f1f 100644 --- a/sys/x86/include/specialreg.h +++ b/sys/x86/include/specialreg.h @@ -157,6 +157,7 @@ #define CPUID2_TM2 0x00000100 #define CPUID2_SSSE3 0x00000200 #define CPUID2_CNXTID 0x00000400 +#define CPUID2_SDBG 0x00000800 #define CPUID2_FMA 0x00001000 #define CPUID2_CX16 0x00002000 #define CPUID2_XTPR 0x00004000 diff --git a/sys/x86/x86/identcpu.c b/sys/x86/x86/identcpu.c index 8e5f5c3..1804595 100644 --- a/sys/x86/x86/identcpu.c +++ b/sys/x86/x86/identcpu.c @@ -781,7 +781,7 @@ printcpuinfo(void) "\011TM2" /* Thermal Monitor 2 */ "\012SSSE3" /* SSSE3 */ "\013CNXT-ID" /* L1 context ID available */ - "\014<b11>" + "\014SDBG" /* IA32 silicon debug */ "\015FMA" /* Fused Multiply Add */ "\016CX16" /* CMPXCHG16B Instruction */ "\017xTPR" /* Send Task Priority Messages*/ |
