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| author | kib <kib@FreeBSD.org> | 2015-03-26 10:44:16 +0000 |
|---|---|---|
| committer | kib <kib@FreeBSD.org> | 2015-03-26 10:44:16 +0000 |
| commit | 6414d2bba420ab8e40bb150d1ac37850558957e6 (patch) | |
| tree | d5495dab7a5da8f532f6ffcd9889da996cd477f4 /sys/x86 | |
| parent | bc8d9c80f509c57810a7baabb93803620f6d88dd (diff) | |
| download | FreeBSD-src-6414d2bba420ab8e40bb150d1ac37850558957e6.zip FreeBSD-src-6414d2bba420ab8e40bb150d1ac37850558957e6.tar.gz | |
MFC r280254:
Provide definitions for all descriptors types in the DMAR invalidation
queue.
Diffstat (limited to 'sys/x86')
| -rw-r--r-- | sys/x86/iommu/intel_reg.h | 27 |
1 files changed, 21 insertions, 6 deletions
diff --git a/sys/x86/iommu/intel_reg.h b/sys/x86/iommu/intel_reg.h index c709403..33e37ac 100644 --- a/sys/x86/iommu/intel_reg.h +++ b/sys/x86/iommu/intel_reg.h @@ -180,7 +180,7 @@ typedef struct dmar_irte { /* IOTLB Register Offset */ #define DMAR_ECAP_SC (1 << 7) /* Snoop Control */ #define DMAR_ECAP_PT (1 << 6) /* Pass Through */ -#define DMAR_ECAP_EIM (1 << 4) /* Extended Interrupt Mode */ +#define DMAR_ECAP_EIM (1 << 4) /* Extended Interrupt Mode (x2APIC) */ #define DMAR_ECAP_IR (1 << 3) /* Interrupt Remapping */ #define DMAR_ECAP_DI (1 << 2) /* Device IOTLB */ #define DMAR_ECAP_QI (1 << 1) /* Queued Invalidation */ @@ -320,8 +320,8 @@ typedef struct dmar_irte { #define DMAR_IQ_DESCR_SZ (1 << DMAR_IQ_DESCR_SZ_SHIFT) /* Descriptor size */ -#define DMAR_IQ_DESCR_CTX_INV 0x1 /* Context-cache Invalidate - Descriptor */ +/* Context-cache Invalidate Descriptor */ +#define DMAR_IQ_DESCR_CTX_INV 0x1 #define DMAR_IQ_DESCR_CTX_GLOB (0x1 << 4) /* Granularity: Global */ #define DMAR_IQ_DESCR_CTX_DOM (0x2 << 4) /* Granularity: Domain */ #define DMAR_IQ_DESCR_CTX_DEV (0x3 << 4) /* Granularity: Device */ @@ -329,7 +329,8 @@ typedef struct dmar_irte { #define DMAR_IQ_DESCR_CTX_SRC(x) (((uint64_t)(x)) << 32) /* Source Id */ #define DMAR_IQ_DESCR_CTX_FM(x) (((uint64_t)(x)) << 48) /* Function Mask */ -#define DMAR_IQ_DESCR_IOTLB_INV 0x2 /* IOTLB Invalidate Descriptor */ +/* IOTLB Invalidate Descriptor */ +#define DMAR_IQ_DESCR_IOTLB_INV 0x2 #define DMAR_IQ_DESCR_IOTLB_GLOB (0x1 << 4) /* Granularity: Global */ #define DMAR_IQ_DESCR_IOTLB_DOM (0x2 << 4) /* Granularity: Domain */ #define DMAR_IQ_DESCR_IOTLB_PAGE (0x3 << 4) /* Granularity: Page */ @@ -337,17 +338,31 @@ typedef struct dmar_irte { #define DMAR_IQ_DESCR_IOTLB_DR (1 << 7) /* Drain Reads */ #define DMAR_IQ_DESCR_IOTLB_DID(x) (((uint32_t)(x)) << 16) /* Domain Id */ -#define DMAR_IQ_DESCR_IEC_INV 0x4 /* Invalidate Interrupt Entry Cache */ +/* Device-TLB Invalidate Descriptor */ +#define DMAR_IQ_DESCR_DTLB_INV 0x3 + +/* Invalidate Interrupt Entry Cache */ +#define DMAR_IQ_DESCR_IEC_INV 0x4 #define DMAR_IQ_DESCR_IEC_IDX (1 << 4) /* Index-Selective Invalidation */ #define DMAR_IQ_DESCR_IEC_IIDX(x) (((uint64_t)x) << 32) /* Interrupt Index */ #define DMAR_IQ_DESCR_IEC_IM(x) ((x) << 27) /* Index Mask */ -#define DMAR_IQ_DESCR_WAIT_ID 0x5 /* Invalidation Wait Descriptor */ +/* Invalidation Wait Descriptor */ +#define DMAR_IQ_DESCR_WAIT_ID 0x5 #define DMAR_IQ_DESCR_WAIT_IF (1 << 4) /* Interrupt Flag */ #define DMAR_IQ_DESCR_WAIT_SW (1 << 5) /* Status Write */ #define DMAR_IQ_DESCR_WAIT_FN (1 << 6) /* Fence */ #define DMAR_IQ_DESCR_WAIT_SD(x) (((uint64_t)(x)) << 32) /* Status Data */ +/* Extended IOTLB Invalidate Descriptor */ +#define DMAR_IQ_DESCR_EIOTLB_INV 0x6 + +/* PASID-Cache Invalidate Descriptor */ +#define DMAR_IQ_DESCR_PASIDC_INV 0x7 + +/* Extended Device-TLB Invalidate Descriptor */ +#define DMAR_IQ_DESCR_EDTLB_INV 0x8 + /* Invalidation Queue Head register */ #define DMAR_IQH_REG 0x80 #define DMAR_IQH_MASK 0x7fff0 /* Next cmd index mask */ |
