Use atomic load & store for TSC frequency. It may be overkill for amd64 but

safer for i386 because it can be easily over 4 GHz now.  More worse, it can
be easily changed by user with 'machdep.tsc_freq' tunable (directly) or
cpufreq(4) (indirectly).  Note it is intentionally not used in performance
critical paths to avoid performance regression (but we should, in theory).
Alternatively, we may add "virtual TSC" with lower frequency if maximum
frequency overflows 32 bits (and ignore possible incoherency as we do now).

1 files changed, 6 insertions, 4 deletions

diff --git a/sys/x86/isa/clock.c b/sys/x86/isa/clock.c
index f0016b2..87d906a 100644
--- a/sys/x86/isa/clock.c
+++ b/sys/x86/isa/clock.c
@@ -246,13 +246,13 @@ getit(void)
 }
 
 static __inline void
-delay_tsc(int n)
+delay_tsc(int n, uint64_t freq)
 {
 	uint64_t start, end, now;
 
 	sched_pin();
 	start = rdtsc();
-	end = start + (tsc_freq * n) / 1000000;
+	end = start + (freq * n) / 1000000;
 	do {
 		cpu_spinwait();
 		now = rdtsc();
@@ -290,6 +290,7 @@ void
 DELAY(int n)
 {
 	struct timecounter *tc;
+	uint64_t freq;
 	int delta, prev_tick, tick, ticks_left;
 
 #ifdef DELAYDEBUG
@@ -298,8 +299,9 @@ DELAY(int n)
 	static int state = 0;
 #endif
 
-	if (tsc_freq != 0) {
-		delay_tsc(n);
+	freq = atomic_load_acq_64(&tsc_freq);
+	if (freq != 0) {
+		delay_tsc(n, freq);
 		return;
 	}
 	tc = timecounter;