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author | rstone <rstone@FreeBSD.org> | 2015-03-01 04:22:06 +0000 |
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committer | rstone <rstone@FreeBSD.org> | 2015-03-01 04:22:06 +0000 |
commit | 0b55a8c80a8931d02374a071f01ad9db0ef81d38 (patch) | |
tree | 446f913517294e1706cb75904e32f64162cd9d7d /sys/x86/iommu/intel_drv.c | |
parent | 058f9df18735c3a34032de747c66a1b31569903d (diff) | |
download | FreeBSD-src-0b55a8c80a8931d02374a071f01ad9db0ef81d38.zip FreeBSD-src-0b55a8c80a8931d02374a071f01ad9db0ef81d38.tar.gz |
MFC r264007,r264008,r264009,r264011,r264012,r264013
MFC support for PCI Alternate RID Interpretation. ARI is an optional PCIe
feature that allows PCI devices to present up to 256 functions on a bus.
This is effectively a prerequisite for PCI SR-IOV support.
r264007:
Add a method to get the PCI RID for a device.
Reviewed by: kib
MFC after: 2 months
Sponsored by: Sandvine Inc.
r264008:
Re-implement the DMAR I/O MMU code in terms of PCI RIDs
Under the hood the VT-d spec is really implemented in terms of
PCI RIDs instead of bus/slot/function, even though the spec makes
pains to convert back to bus/slot/function in examples. However
working with bus/slot/function is not correct when PCI ARI is
in use, so convert to using RIDs in most cases. bus/slot/function
will only be used when reporting errors to a user.
Reviewed by: kib
MFC after: 2 months
Sponsored by: Sandvine Inc.
r264009:
Re-write bhyve's I/O MMU handling in terms of PCI RID.
Reviewed by: neel
MFC after: 2 months
Sponsored by: Sandvine Inc.
r264011:
Add support for PCIe ARI
PCIe Alternate RID Interpretation (ARI) is an optional feature that
allows devices to have up to 256 different functions. It is
implemented by always setting the PCI slot number to 0 and
re-purposing the 5 bits used to encode the slot number to instead
contain the function number. Combined with the original 3 bits
allocated for the function number, this allows for 256 functions.
This is enabled by default, but it's expected to be a no-op on currently
supported hardware. It's a prerequisite for supporting PCI SR-IOV, and
I want the ARI support to go in early to help shake out any bugs in it.
ARI can be disabled by setting the tunable hw.pci.enable_ari=0.
Reviewed by: kib
MFC after: 2 months
Sponsored by: Sandvine Inc.
r264012:
Print status of ARI capability in pciconf -c
Teach pciconf how to print out the status (enabled/disabled) of the ARI
capability on PCI Root Complexes and Downstream Ports.
MFC after: 2 months
Sponsored by: Sandvine Inc.
r264013:
Add missing copyright date.
MFC after: 2 months
Diffstat (limited to 'sys/x86/iommu/intel_drv.c')
-rw-r--r-- | sys/x86/iommu/intel_drv.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/sys/x86/iommu/intel_drv.c b/sys/x86/iommu/intel_drv.c index c7c6bf1..59e54e7 100644 --- a/sys/x86/iommu/intel_drv.c +++ b/sys/x86/iommu/intel_drv.c @@ -1006,7 +1006,9 @@ dmar_print_ctx(struct dmar_ctx *ctx, bool show_mappings) db_printf( " @%p pci%d:%d:%d dom %d mgaw %d agaw %d pglvl %d end %jx\n" " refs %d flags %x pgobj %p map_ents %u loads %lu unloads %lu\n", - ctx, ctx->bus, ctx->slot, ctx->func, ctx->domain, ctx->mgaw, + ctx, pci_get_bus(ctx->ctx_tag.owner), + pci_get_slot(ctx->ctx_tag.owner), + pci_get_function(ctx->ctx_tag.owner), ctx->domain, ctx->mgaw, ctx->agaw, ctx->pglvl, (uintmax_t)ctx->end, ctx->refs, ctx->flags, ctx->pgtbl_obj, ctx->entries_cnt, ctx->loads, ctx->unloads); @@ -1079,8 +1081,10 @@ DB_FUNC(dmar_ctx, db_dmar_print_ctx, db_show_table, CS_OWN, NULL) for (i = 0; i < dmar_devcnt; i++) { unit = device_get_softc(dmar_devs[i]); LIST_FOREACH(ctx, &unit->contexts, link) { - if (domain == unit->segment && bus == ctx->bus && - device == ctx->slot && function == ctx->func) { + if (domain == unit->segment && + bus == pci_get_bus(ctx->ctx_tag.owner) && + device == pci_get_slot(ctx->ctx_tag.owner) && + function == pci_get_function(ctx->ctx_tag.owner)) { dmar_print_ctx(ctx, show_mappings); goto out; } |