Delete the unused/not really used sparc64 (as in sun4u) cache.h,

iommureg.h (which already began to bitrot) and iommuvar.h from the
sun4v source and adjust some of the source which is shared between
sparc64 and sun4v as appropriate.

4 files changed, 0 insertions, 405 deletions

diff --git a/sys/sun4v/include/cache.h b/sys/sun4v/include/cache.h
deleted file mode 100644
index 9e83f95..0000000
--- a/sys/sun4v/include/cache.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*-
- * Copyright (c) 1996
- * 	The President and Fellows of Harvard College. All rights reserved.
- * Copyright (c) 1992, 1993
- *	The Regents of the University of California.  All rights reserved.
- *
- * This software was developed by the Computer Systems Engineering group
- * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
- * contributed to Berkeley.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by Aaron Brown and
- *	Harvard University.
- * 4. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- *	from: @(#)cache.h	8.1 (Berkeley) 6/11/93
- *	from: NetBSD: cache.h,v 1.3 2000/08/01 00:28:02 eeh Exp
- *
- * $FreeBSD$
- */
-
-#ifndef _MACHINE_CACHE_H_
-#define _MACHINE_CACHE_H_
-
-#include <dev/ofw/openfirm.h>
-
-#ifdef SUN4V
-#define DCACHE_COLOR_BITS       (0)
-#else
-#define DCACHE_COLOR_BITS       (1)
-#endif
-
-#define DCACHE_COLORS           (1 << DCACHE_COLOR_BITS)
-
-#define	DC_TAG_SHIFT	2
-#define	DC_VALID_SHIFT	0
-
-#define	DC_TAG_BITS	28
-#define	DC_VALID_BITS	2
-
-#define	DC_TAG_MASK	((1 << DC_TAG_BITS) - 1)
-#define	DC_VALID_MASK	((1 << DC_VALID_BITS) - 1)
-
-#define	IC_TAG_SHIFT	7
-#define	IC_VALID_SHIFT	36
-
-#define	IC_TAG_BITS	28
-#define	IC_VALID_BITS	1
-
-#define	IC_TAG_MASK	((1 << IC_TAG_BITS) - 1)
-#define	IC_VALID_MASK	((1 << IC_VALID_BITS) - 1)
-
-/*
- * Cache control information.
- */
-struct cacheinfo {
-	u_int	c_enabled;		/* true => cache is enabled */
-	u_int 	ic_size;		/* instruction cache */
-	u_int	ic_set;
-	u_int	ic_l2set;
-	u_int 	ic_assoc;
-	u_int 	ic_linesize;
-	u_int 	dc_size;		/* data cache */
-	u_int	dc_l2size;
-	u_int 	dc_assoc;
-	u_int 	dc_linesize;
-	u_int	ec_size;		/* external cache info */
-	u_int 	ec_assoc;
-	u_int	ec_l2set;
-	u_int	ec_linesize;
-	u_int	ec_l2linesize;
-};
-
-#ifdef _KERNEL
-
-typedef void cache_enable_t(void);
-typedef void cache_flush_t(void);
-typedef void dcache_page_inval_t(vm_paddr_t pa);
-typedef void icache_page_inval_t(vm_paddr_t pa);
-
-void	cache_init(phandle_t node);
-
-cache_enable_t cheetah_cache_enable;
-cache_flush_t cheetah_cache_flush;
-dcache_page_inval_t cheetah_dcache_page_inval;
-icache_page_inval_t cheetah_icache_page_inval;
-
-cache_enable_t spitfire_cache_enable;
-cache_flush_t spitfire_cache_flush;
-dcache_page_inval_t spitfire_dcache_page_inval;
-icache_page_inval_t spitfire_icache_page_inval;
-
-extern cache_enable_t *cache_enable;
-extern cache_flush_t *cache_flush;
-extern dcache_page_inval_t *dcache_page_inval;
-extern icache_page_inval_t *icache_page_inval;
-
-extern struct cacheinfo cache;
-
-#endif
-
-#endif	/* !_MACHINE_CACHE_H_ */
diff --git a/sys/sun4v/include/iommureg.h b/sys/sun4v/include/iommureg.h
deleted file mode 100644
index e36d837..0000000
--- a/sys/sun4v/include/iommureg.h
+++ /dev/null
@@ -1,180 +0,0 @@
-/*-
- * Copyright (c) 1992, 1993
- *	The Regents of the University of California.  All rights reserved.
- *
- * This software was developed by the Computer Systems Engineering group
- * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
- * contributed to Berkeley.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 4. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- *	from: @(#)sbusreg.h	8.1 (Berkeley) 6/11/93
- *	from: NetBSD: iommureg.h,v 1.6 2001/07/20 00:07:13 eeh Exp
- *
- * $FreeBSD$
- */
-
-#ifndef _MACHINE_IOMMUREG_H_
-#define _MACHINE_IOMMUREG_H_
-
-/*
- * UltraSPARC IOMMU registers, common to both the sbus and PCI
- * controllers.
- */
-
-/* iommmu registers */
-#define	IMR_CTL		0x0000	/* IOMMU control register */
-#define	IMR_TSB		0x0008	/* IOMMU TSB base register */
-#define	IMR_FLUSH	0x0010	/* IOMMU flush register */
-
-/* streaming buffer registers */
-#define	ISR_CTL		0x0000	/* streaming buffer control reg */
-#define	ISR_PGFLUSH	0x0008	/* streaming buffer page flush */
-#define	ISR_FLUSHSYNC	0x0010	/* streaming buffer flush sync */
-
-/* streaming buffer diagnostics registers. */
-#define	ISD_DATA_DIAG	0x0000	/* streaming buffer data RAM diag 0..127 */
-#define	ISD_ERROR_DIAG	0x0400	/* streaming buffer error status diag 0..127 */
-#define	ISD_PG_TAG_DIAG	0x0800	/* streaming buffer page tag diag 0..15 */
-#define	ISD_LN_TAG_DIAG	0x0900	/* streaming buffer line tag diag 0..15 */
-
-/* streaming buffer control register */
-#define STRBUF_EN		0x0000000000000001UL
-#define STRBUF_D		0x0000000000000002UL
-
-#define	IOMMU_BITS		34
-#define	IOMMU_MAXADDR		(1UL << IOMMU_BITS)
-
-/*
- * control register bits
- */
-/* Nummber of entries in IOTSB */
-#define	IOMMUCR_TSBSZ_SHIFT	16
-#define IOMMUCR_TSB1K		0x0000000000000000UL
-#define IOMMUCR_TSB2K		0x0000000000010000UL
-#define IOMMUCR_TSB4K		0x0000000000020000UL
-#define IOMMUCR_TSB8K		0x0000000000030000UL
-#define IOMMUCR_TSB16K		0x0000000000040000UL
-#define IOMMUCR_TSB32K		0x0000000000050000UL
-#define IOMMUCR_TSB64K		0x0000000000060000UL
-#define IOMMUCR_TSB128K		0x0000000000070000UL
-/* Mask for above */
-#define IOMMUCR_TSBMASK		0xfffffffffff8ffffUL
-/* 8K iommu page size */
-#define IOMMUCR_8KPG		0x0000000000000000UL
-/* 64K iommu page size */
-#define IOMMUCR_64KPG		0x0000000000000004UL
-/* Diag enable */
-#define IOMMUCR_DE		0x0000000000000002UL
-/* Enable IOMMU */
-#define IOMMUCR_EN		0x0000000000000001UL
-
-/*
- * Diagnostic register definitions.
- */
-#define	IOMMU_DTAG_VPNBITS	19
-#define	IOMMU_DTAG_VPNMASK	((1 << IOMMU_DTAG_VPNBITS) - 1)
-#define	IOMMU_DTAG_VPNSHIFT	13
-#define IOMMU_DTAG_ERRBITS	3
-#define	IOMMU_DTAG_ERRSHIFT	22
-#define	IOMMU_DTAG_ERRMASK \
-	(((1 << IOMMU_DTAG_ERRBITS) - 1) << IOMMU_DTAG_ERRSHIFT)
-
-#define	IOMMU_DDATA_PGBITS	21
-#define	IOMMU_DDATA_PGMASK	((1 << IOMMU_DDATA_PGBITS) - 1)
-#define	IOMMU_DDATA_PGSHIFT	13
-#define	IOMMU_DDATA_C		(1 << 28)
-#define	IOMMU_DDATA_V		(1 << 30)
-
-/*
- * IOMMU stuff
- */
-/* Entry valid */
-#define	IOTTE_V			0x8000000000000000UL
-/* 8K or 64K page? */
-#define IOTTE_64K		0x2000000000000000UL
-#define IOTTE_8K		0x0000000000000000UL
-/* Is page streamable? */
-#define IOTTE_STREAM		0x1000000000000000UL
-/* Accesses to same bus segment? */
-#define	IOTTE_LOCAL		0x0800000000000000UL
-/* Let's assume this is correct */
-#define IOTTE_PAMASK		0x000001ffffffe000UL
-/* Accesses to cacheable space */
-#define IOTTE_C			0x0000000000000010UL
-/* Writeable */
-#define IOTTE_W			0x0000000000000002UL
-
-/* log2 of the IOMMU TTE size. */
-#define	IOTTE_SHIFT		3
-
-/* Streaming buffer line size. */
-#define	STRBUF_LINESZ		64
-
-/*
- * Number of bytes written by a stream buffer flushsync operation to indicate
- * completion.
- */
-#define	STRBUF_FLUSHSYNC_NBYTES	STRBUF_LINESZ
-
-/*
- * On sun4u each bus controller has a separate IOMMU.  The IOMMU has 
- * a TSB which must be page aligned and physically contiguous.  Mappings
- * can be of 8K IOMMU pages or 64K IOMMU pages.  We use 8K for compatibility
- * with the CPU's MMU.
- *
- * On sysio, psycho, and psycho+, IOMMU TSBs using 8K pages can map the
- * following size segments:
- *
- *	VA size		VA base		TSB size	tsbsize
- *	--------	--------	---------	-------
- *	8MB		ff800000	8K		0
- *	16MB		ff000000	16K		1
- *	32MB		fe000000	32K		2
- *	64MB		fc000000	64K		3
- *	128MB		f8000000	128K		4
- *	256MB		f0000000	256K		5
- *	512MB		e0000000	512K		6
- *	1GB		c0000000	1MB		7
- *
- * Unfortunately, sabres on UltraSPARC IIi and IIe processors does not use
- * this scheme to determine the IOVA base address.  Instead, bits 31-29 are
- * used to check against the Target Address Space register in the IIi and
- * the the IOMMU is used if they hit.  God knows what goes on in the IIe.
- *
- */
-
-#define	IOTSB_BASESZ		(1024 << IOTTE_SHIFT)
-#define IOTSB_VEND		(~IO_PAGE_MASK)
-#define IOTSB_VSTART(sz)	(u_int)(IOTSB_VEND << ((sz) + 10)) 
-
-#define MAKEIOTTE(pa,w,c,s)						\
-	(((pa) & IOTTE_PAMASK) | ((w) ? IOTTE_W : 0) |			\
-	((c) ? IOTTE_C : 0) | ((s) ? IOTTE_STREAM : 0) |		\
-	(IOTTE_V | IOTTE_8K))
-#define IOTSBSLOT(va)						\
-	((u_int)(((vm_offset_t)(va)) - (is->is_dvmabase)) >> IO_PAGE_SHIFT)
-
-#endif /* !_MACHINE_IOMMUREG_H_ */
diff --git a/sys/sun4v/include/iommuvar.h b/sys/sun4v/include/iommuvar.h
deleted file mode 100644
index 9c290c0..0000000
--- a/sys/sun4v/include/iommuvar.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*-
- * Copyright (c) 1999 Matthew R. Green
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- *	from: NetBSD: iommuvar.h,v 1.9 2001/07/20 00:07:13 eeh Exp
- *
- * $FreeBSD$
- */
-
-#ifndef _MACHINE_IOMMUVAR_H_
-#define _MACHINE_IOMMUVAR_H_
-
-#define	IO_PAGE_SIZE		PAGE_SIZE_8K
-#define	IO_PAGE_MASK		PAGE_MASK_8K
-#define	IO_PAGE_SHIFT		PAGE_SHIFT_8K
-#define	round_io_page(x)	round_page(x)
-#define	trunc_io_page(x)	trunc_page(x)
-
-/*
- * Per-IOMMU state. The parenthesized comments indicate the locking strategy:
- *	i - protected by iommu_mtx.
- *	r - read-only after initialization.
- *	* - comment refers to pointer target / target hardware registers
- *	    (for bus_addr_t).
- * iommu_map_lruq is also locked by iommu_mtx. Elements of iommu_tsb may only
- * be accessed from functions operating on the map owning the corresponding
- * resource, so the locking the user is required to do to protect the map is
- * sufficient. As soon as the TSBs are divorced, these will be moved into struct
- * iommu_state, and each state struct will get its own lock.
- * iommu_dvma_rman needs to be moved there too, but has its own internal lock.
- */
-struct iommu_state {
-	int			is_tsbsize;	/* (r) 0 = 8K, ... */
-	u_int64_t		is_dvmabase;	/* (r) */
-	int64_t			is_cr;		/* (r) Control reg value */
-
-	vm_paddr_t		is_flushpa[2];	/* (r) */
-	volatile int64_t	*is_flushva[2];	/* (r, *i) */
-	/*
-	 * (i)
-	 * When a flush is completed, 64 bytes will be stored at the given
-	 * location, the first double word being 1, to indicate completion.
-	 * The lower 6 address bits are ignored, so the addresses need to be
-	 * suitably aligned; over-allocate a large enough margin to be able
-	 * to adjust it.
-	 * Two such buffers are needed.
-	 */
-	volatile char		is_flush[STRBUF_FLUSHSYNC_NBYTES * 3 - 1];
-
-	/* copies of our parents state, to allow us to be self contained */
-	bus_space_tag_t		is_bustag;	/* (r) Our bus tag */
-	bus_space_handle_t	is_bushandle;	/* (r) */
-	bus_addr_t		is_iommu;	/* (r, *i) IOMMU registers */
-	bus_addr_t		is_sb[2];	/* (r, *i) Streaming buffer */
-	/* Tag diagnostics access */
-	bus_addr_t		is_dtag;	/* (r, *r) */
-	/* Data RAM diagnostic access */
-	bus_addr_t		is_ddram;	/* (r, *r) */
-	/* LRU queue diag. access */
-	bus_addr_t		is_dqueue;	/* (r, *r) */
-	/* Virtual address diagnostics register */
-	bus_addr_t		is_dva;		/* (r, *r) */
-	/* Tag compare diagnostics access */
-	bus_addr_t		is_dtcmp;	/* (r, *r) */
-
-	STAILQ_ENTRY(iommu_state)	is_link;	/* (r) */
-};
-
-/* interfaces for PCI/SBUS code */
-void iommu_init(char *, struct iommu_state *, int, u_int32_t, int);
-void iommu_reset(struct iommu_state *);
-void iommu_decode_fault(struct iommu_state *, vm_offset_t);
-
-extern struct bus_dma_methods iommu_dma_methods;
-
-#endif /* !_MACHINE_IOMMUVAR_H_ */
diff --git a/sys/sun4v/include/pmap.h b/sys/sun4v/include/pmap.h
index 8390937..3390e99 100644
--- a/sys/sun4v/include/pmap.h
+++ b/sys/sun4v/include/pmap.h
@@ -43,7 +43,6 @@
 #include <sys/queue.h>
 #include <sys/_lock.h>
 #include <sys/_mutex.h>
-#include <machine/cache.h>
 #include <machine/hv_api.h>
 
 #define TSB_INIT_SHIFT          3