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author | scottl <scottl@FreeBSD.org> | 2004-06-10 05:11:39 +0000 |
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committer | scottl <scottl@FreeBSD.org> | 2004-06-10 05:11:39 +0000 |
commit | 1154159183e80dfcf7a52dc4b4ba8d5db88bca1e (patch) | |
tree | 907cdedb826accd7ccb9399e3a5a3281d4e86864 /sys/sparc64 | |
parent | fe56c5bdd9a68195f81addc0c76aec6f142d1da0 (diff) | |
download | FreeBSD-src-1154159183e80dfcf7a52dc4b4ba8d5db88bca1e.zip FreeBSD-src-1154159183e80dfcf7a52dc4b4ba8d5db88bca1e.tar.gz |
Port the NetBSD esp(4) driver. This only includes the sbus front-end, so
its primary use is for the FEPS/FAS366 SCSI found in Sun Ultra 1e and 2
machines. Once the pci front-end is ported, this driver can replace the
amd(4) driver.
The code as-is is fairly stable. I've disabled tagged-queueing until I can
figure out a corruption bug related to it. I'm importing it now so that
people with these machines can (finally) stop netbooting and report bugs
before 5.3.
Diffstat (limited to 'sys/sparc64')
-rw-r--r-- | sys/sparc64/sbus/lsi64854.c | 722 | ||||
-rw-r--r-- | sys/sparc64/sbus/lsi64854reg.h | 205 | ||||
-rw-r--r-- | sys/sparc64/sbus/lsi64854var.h | 114 |
3 files changed, 1041 insertions, 0 deletions
diff --git a/sys/sparc64/sbus/lsi64854.c b/sys/sparc64/sbus/lsi64854.c new file mode 100644 index 0000000..dca8526f7 --- /dev/null +++ b/sys/sparc64/sbus/lsi64854.c @@ -0,0 +1,722 @@ +/*- + * Copyright (c) 2004 Scott Long + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +/* $NetBSD: lsi64854.c,v 1.22 2002/10/01 07:07:03 petrov Exp $ */ + +/*- + * Copyright (c) 1998 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Paul Kranenburg. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/kernel.h> +#include <sys/resource.h> +#include <sys/lock.h> +#include <sys/mutex.h> + +#include <machine/bus.h> + +#include <cam/cam.h> +#include <cam/cam_ccb.h> +#include <cam/scsi/scsi_all.h> + +#include <dev/esp/lsi64854reg.h> +#include <dev/esp/lsi64854var.h> + +#include <dev/esp/ncr53c9xreg.h> +#include <dev/esp/ncr53c9xvar.h> + +void lsi64854_reset(struct lsi64854_softc *); +int lsi64854_setup(struct lsi64854_softc *, caddr_t *, size_t *, + int, size_t *); +int lsi64854_setup_pp(struct lsi64854_softc *, caddr_t *, size_t *, + int, size_t *); + +#ifdef DEBUG +#define LDB_SCSI 1 +#define LDB_ENET 2 +#define LDB_PP 4 +#define LDB_ANY 0xff +int lsi64854debug = 0; +#define DPRINTF(a,x) do { if (lsi64854debug & (a)) printf x ; } while (0) +#else +#define DPRINTF(a,x) +#endif + +#define MAX_DMA_SZ (16*1024*1024) + +/* + * Finish attaching this DMA device. + * Front-end must fill in these fields: + * sc_regs + * sc_burst + * sc_channel (one of SCSI, ENET, PP) + * sc_client (one of SCSI, ENET, PP `soft_c' pointers) + */ +void +lsi64854_attach(struct lsi64854_softc *sc) +{ + u_int32_t csr; + + sc->dv_name = device_get_nameunit(sc->sc_dev); + + /* Indirect functions */ + switch (sc->sc_channel) { + case L64854_CHANNEL_SCSI: + sc->intr = lsi64854_scsi_intr; + sc->setup = lsi64854_setup; + break; + case L64854_CHANNEL_ENET: + sc->intr = lsi64854_enet_intr; + break; + case L64854_CHANNEL_PP: + sc->setup = lsi64854_setup_pp; + break; + default: + printf("%s: unknown channel\n", sc->dv_name); + } + sc->reset = lsi64854_reset; + + /* Allocate a dmamap */ + if (bus_dma_tag_create(sc->sc_parent_dmat, /* parent */ + 1, 0, /* algnment, boundary */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + MAX_DMA_SZ, /* maxsize */ + 1, /* nsegments */ + MAX_DMA_SZ, /* maxsegsize */ + BUS_DMA_ALLOCNOW, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->sc_buffer_dmat)) { + printf("%s: can't allocate buffer DMA tag\n", sc->dv_name); + return; + } + + if (bus_dmamap_create(sc->sc_buffer_dmat, 0, &sc->sc_dmamap) != 0) { + printf("%s: DMA map create failed\n", sc->dv_name); + return; + } + + csr = L64854_GCSR(sc); + sc->sc_rev = csr & L64854_DEVID; + if (sc->sc_rev == DMAREV_HME) { + return; + } + printf(": DMA rev "); + switch (sc->sc_rev) { + case DMAREV_0: + printf("0"); + break; + case DMAREV_ESC: + printf("esc"); + break; + case DMAREV_1: + printf("1"); + break; + case DMAREV_PLUS: + printf("1+"); + break; + case DMAREV_2: + printf("2"); + break; + default: + printf("unknown (0x%x)", sc->sc_rev); + } + + DPRINTF(LDB_ANY, (", burst 0x%x, csr 0x%x", sc->sc_burst, csr)); + printf("\n"); +} + +/* + * DMAWAIT waits while condition is true + */ +#define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \ + int count = 500000; \ + while ((COND) && --count > 0) DELAY(1); \ + if (count == 0) { \ + printf("%s: line %d: CSR = 0x%lx\n", __FILE__, __LINE__, \ + (u_long)L64854_GCSR(SC)); \ + if (DONTPANIC) \ + printf(MSG); \ + else \ + panic(MSG); \ + } \ +} while (0) + +#define DMA_DRAIN(sc, dontpanic) do { \ + u_int32_t csr; \ + /* \ + * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ + * and "drain" bits while it is still thinking about a \ + * request. \ + * other revs: D_ESC_R_PEND bit reads as 0 \ + */ \ + DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ + if (sc->sc_rev != DMAREV_HME) { \ + /* \ + * Select drain bit based on revision \ + * also clears errors and D_TC flag \ + */ \ + csr = L64854_GCSR(sc); \ + if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \ + csr |= D_ESC_DRAIN; \ + else \ + csr |= L64854_INVALIDATE; \ + \ + L64854_SCSR(sc,csr); \ + } \ + /* \ + * Wait for draining to finish \ + * rev0 & rev1 call this PACKCNT \ + */ \ + DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", dontpanic);\ +} while(0) + +#define DMA_FLUSH(sc, dontpanic) do { \ + u_int32_t csr; \ + /* \ + * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ + * and "drain" bits while it is still thinking about a \ + * request. \ + * other revs: D_ESC_R_PEND bit reads as 0 \ + */ \ + DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ + csr = L64854_GCSR(sc); \ + csr &= ~(L64854_WRITE|L64854_EN_DMA); /* no-ops on ENET */ \ + csr |= L64854_INVALIDATE; /* XXX FAS ? */ \ + L64854_SCSR(sc,csr); \ +} while(0) + +void +lsi64854_reset(struct lsi64854_softc *sc) +{ + u_int32_t csr; + + DMA_FLUSH(sc, 1); + csr = L64854_GCSR(sc); + + DPRINTF(LDB_ANY, ("lsi64854_reset: csr 0x%x\n", csr)); + + /* + * XXX is sync needed? + if (sc->sc_dmamap->dm_nsegs > 0) + bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap); + */ + + if (sc->sc_rev == DMAREV_HME) + L64854_SCSR(sc, csr | D_HW_RESET_FAS366); + + + csr |= L64854_RESET; /* reset DMA */ + L64854_SCSR(sc, csr); + DELAY(200); /* > 10 Sbus clocks(?) */ + + /*DMAWAIT1(sc); why was this here? */ + csr = L64854_GCSR(sc); + csr &= ~L64854_RESET; /* de-assert reset line */ + L64854_SCSR(sc, csr); + DELAY(5); /* allow a few ticks to settle */ + + csr = L64854_GCSR(sc); + csr |= L64854_INT_EN; /* enable interrupts */ + if (sc->sc_rev > DMAREV_1 && sc->sc_channel == L64854_CHANNEL_SCSI) { + if (sc->sc_rev == DMAREV_HME) + csr |= D_TWO_CYCLE; + else + csr |= D_FASTER; + } + + /* Set burst */ + switch (sc->sc_rev) { + case DMAREV_HME: + case DMAREV_2: + csr &= ~L64854_BURST_SIZE; + if (sc->sc_burst == 32) { + csr |= L64854_BURST_32; + } else if (sc->sc_burst == 16) { + csr |= L64854_BURST_16; + } else { + csr |= L64854_BURST_0; + } + break; + case DMAREV_ESC: + csr |= D_ESC_AUTODRAIN; /* Auto-drain */ + if (sc->sc_burst == 32) { + csr &= ~D_ESC_BURST; + } else + csr |= D_ESC_BURST; + break; + default: + break; + } + L64854_SCSR(sc, csr); + + if (sc->sc_rev == DMAREV_HME) { + bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR, 0); + sc->sc_dmactl = csr; + } + sc->sc_active = 0; + + DPRINTF(LDB_ANY, ("lsi64854_reset: done, csr 0x%x\n", csr)); +} + +static void +lsi64854_map_scsi(void *arg, bus_dma_segment_t *segs, int nseg, int error) +{ + struct lsi64854_softc *sc; + + sc = (struct lsi64854_softc *)arg; + + if (nseg != 1) + panic("%s: cannot map %d segments\n", sc->dv_name, nseg); + + bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap, sc->sc_datain ? + BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); + bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR, + segs[0].ds_addr); +} + + +#define DMAMAX(a) (MAX_DMA_SZ - ((a) & (MAX_DMA_SZ-1))) +/* + * setup a DMA transfer + */ +int +lsi64854_setup(struct lsi64854_softc *sc, caddr_t *addr, size_t *len, + int datain, size_t *dmasize) +{ + u_int32_t csr; + + DMA_FLUSH(sc, 0); + +#if 0 + DMACSR(sc) &= ~D_INT_EN; +#endif + sc->sc_dmaaddr = addr; + sc->sc_dmalen = len; + sc->sc_datain = datain; + + /* + * the rules say we cannot transfer more than the limit + * of this DMA chip (64k for old and 16Mb for new), + * and we cannot cross a 16Mb boundary. + */ + *dmasize = sc->sc_dmasize = + min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); + + DPRINTF(LDB_ANY, ("dma_setup: dmasize = %ld\n", (long)sc->sc_dmasize)); + + /* + * XXX what length? + */ + if (sc->sc_rev == DMAREV_HME) { + + L64854_SCSR(sc, sc->sc_dmactl | L64854_RESET); + L64854_SCSR(sc, sc->sc_dmactl); + + bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_CNT, *dmasize); + } + + /* Program the DMA address */ + if (sc->sc_dmasize) { + if (bus_dmamap_load(sc->sc_buffer_dmat, sc->sc_dmamap, + *sc->sc_dmaaddr, sc->sc_dmasize, + lsi64854_map_scsi, sc, 0) != 0) + panic("%s: cannot allocate DVMA address", sc->dv_name); + } + + if (sc->sc_rev == DMAREV_ESC) { + /* DMA ESC chip bug work-around */ + long bcnt = sc->sc_dmasize; + long eaddr = bcnt + (long)*sc->sc_dmaaddr; + if ((eaddr & PAGE_MASK_8K) != 0) + bcnt = roundup(bcnt, PAGE_SIZE_8K); + bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_CNT, + bcnt); + } + + /* Setup DMA control register */ + csr = L64854_GCSR(sc); + + if (datain) + csr |= L64854_WRITE; + else + csr &= ~L64854_WRITE; + csr |= L64854_INT_EN; + + if (sc->sc_rev == DMAREV_HME) { + csr |= (D_DSBL_SCSI_DRN | D_EN_DMA); + } + + L64854_SCSR(sc, csr); + + return (0); +} + +/* + * Pseudo (chained) interrupt from the esp driver to kick the + * current running DMA transfer. Called from ncr53c9x_intr() + * for now. + * + * return 1 if it was a DMA continue. + */ +int +lsi64854_scsi_intr(void *arg) +{ + struct lsi64854_softc *sc = arg; + struct ncr53c9x_softc *nsc = sc->sc_client; + int trans, resid; + u_int32_t csr; + + csr = L64854_GCSR(sc); + + DPRINTF(LDB_SCSI, ("%s: dmaintr: addr 0x%x, csr %b\n", sc->dv_name, + bus_space_read_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR), + csr, DDMACSR_BITS)); + + if (csr & (D_ERR_PEND|D_SLAVE_ERR)) { + printf("%s: error: csr=%b\n", sc->dv_name, csr, DDMACSR_BITS); + csr &= ~D_EN_DMA; /* Stop DMA */ + /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ + csr |= D_INVALIDATE|D_SLAVE_ERR; + L64854_SCSR(sc, csr); + return (-1); + } + + /* This is an "assertion" :) */ + if (sc->sc_active == 0) + panic("dmaintr: DMA wasn't active"); + + DMA_DRAIN(sc, 0); + + /* DMA has stopped */ + csr &= ~D_EN_DMA; + L64854_SCSR(sc, csr); + sc->sc_active = 0; + + if (sc->sc_dmasize == 0) { + /* A "Transfer Pad" operation completed */ + DPRINTF(LDB_SCSI, ("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", + NCR_READ_REG(nsc, NCR_TCL) | + (NCR_READ_REG(nsc, NCR_TCM) << 8), + NCR_READ_REG(nsc, NCR_TCL), + NCR_READ_REG(nsc, NCR_TCM))); + return 0; + } + + resid = 0; + /* + * If a transfer onto the SCSI bus gets interrupted by the device + * (e.g. for a SAVEPOINTER message), the data in the FIFO counts + * as residual since the NCR53C9X counter registers get decremented + * as bytes are clocked into the FIFO. + */ + if (!(csr & D_WRITE) && + (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { + DPRINTF(LDB_SCSI, ("dmaintr: empty esp FIFO of %d ", resid)); + if (nsc->sc_rev == NCR_VARIANT_FAS366 && + (NCR_READ_REG(nsc, NCR_CFG3) & NCRFASCFG3_EWIDE)) + resid <<= 1; + } + + if ((nsc->sc_espstat & NCRSTAT_TC) == 0) { + /* + * `Terminal count' is off, so read the residue + * out of the NCR53C9X counter registers. + */ + resid += (NCR_READ_REG(nsc, NCR_TCL) | + (NCR_READ_REG(nsc, NCR_TCM) << 8) | + ((nsc->sc_cfg2 & NCRCFG2_FE) + ? (NCR_READ_REG(nsc, NCR_TCH) << 16) + : 0)); + + if (resid == 0 && sc->sc_dmasize == 65536 && + (nsc->sc_cfg2 & NCRCFG2_FE) == 0) + /* A transfer of 64K is encoded as `TCL=TCM=0' */ + resid = 65536; + } + + trans = sc->sc_dmasize - resid; + if (trans < 0) { /* transferred < 0 ? */ +#if 0 + /* + * This situation can happen in perfectly normal operation + * if the ESP is reselected while using DMA to select + * another target. As such, don't print the warning. + */ + printf("%s: xfer (%d) > req (%d)\n", sc->dv_name, trans, + sc->sc_dmasize); +#endif + trans = sc->sc_dmasize; + } + + DPRINTF(LDB_SCSI, ("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", + NCR_READ_REG(nsc, NCR_TCL), + NCR_READ_REG(nsc, NCR_TCM), + (nsc->sc_cfg2 & NCRCFG2_FE) + ? NCR_READ_REG(nsc, NCR_TCH) : 0, + trans, resid)); + +#if 0 /* XXX */ + if (sc->sc_dmamap->dm_nsegs > 0) { + bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap, + (csr & D_WRITE) != 0 + ? BUS_DMASYNC_POSTREAD + : BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap); + } +#endif + + *sc->sc_dmalen -= trans; + *sc->sc_dmaaddr += trans; + +#if 0 /* this is not normal operation just yet */ + if (*sc->sc_dmalen == 0 || + nsc->sc_phase != nsc->sc_prevphase) + return 0; + + /* and again */ + dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE); + return 1; +#endif + return 0; +} + +/* + * Pseudo (chained) interrupt to le driver to handle DMA errors. + */ +int +lsi64854_enet_intr(void *arg) +{ + struct lsi64854_softc *sc = arg; + u_int32_t csr; + static int dodrain = 0; + int rv; + + csr = L64854_GCSR(sc); + + /* If the DMA logic shows an interrupt, claim it */ + rv = ((csr & E_INT_PEND) != 0) ? 1 : 0; + + if (csr & (E_ERR_PEND|E_SLAVE_ERR)) { + printf("%s: error: csr=%b\n", sc->dv_name, csr, EDMACSR_BITS); + csr &= ~L64854_EN_DMA; /* Stop DMA */ + /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ + csr |= E_INVALIDATE|E_SLAVE_ERR; + L64854_SCSR(sc, csr); + DMA_RESET(sc); + dodrain = 1; + return (1); + } + + if (dodrain) { /* XXX - is this necessary with D_DSBL_WRINVAL on? */ + int i = 10; + csr |= E_DRAIN; + L64854_SCSR(sc, csr); + while (i-- > 0 && (L64854_GCSR(sc) & D_DRAINING)) + DELAY(1); + } + + return (rv | (*sc->sc_intrchain)(sc->sc_intrchainarg)); +} + +static void +lsi64854_map_pp(void *arg, bus_dma_segment_t *segs, int nsegs, int error) +{ + struct lsi64854_softc *sc; + + sc = (struct lsi64854_softc *)arg; + + if (nsegs != 1) + panic("%s: cannot map %d segments\n", sc->dv_name, nsegs); + + bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap, sc->sc_datain + ? BUS_DMASYNC_PREREAD + : BUS_DMASYNC_PREWRITE); + bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR, + segs[0].ds_addr); + + bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_CNT, + sc->sc_dmasize); +} + +/* + * setup a DMA transfer + */ +int +lsi64854_setup_pp(struct lsi64854_softc *sc, caddr_t *addr, size_t *len, + int datain, size_t *dmasize) +{ + u_int32_t csr; + + DMA_FLUSH(sc, 0); + + sc->sc_dmaaddr = addr; + sc->sc_dmalen = len; + sc->sc_datain = datain; + + DPRINTF(LDB_PP, ("%s: pp start %ld@%p,%d\n", sc->dv_name, + (long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0)); + + /* + * the rules say we cannot transfer more than the limit + * of this DMA chip (64k for old and 16Mb for new), + * and we cannot cross a 16Mb boundary. + */ + *dmasize = sc->sc_dmasize = + min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); + + DPRINTF(LDB_PP, ("dma_setup_pp: dmasize = %ld\n", (long)sc->sc_dmasize)); + + /* Program the DMA address */ + if (sc->sc_dmasize) { + if (bus_dmamap_load(sc->sc_buffer_dmat, sc->sc_dmamap, + *sc->sc_dmaaddr, sc->sc_dmasize, + lsi64854_map_pp, sc, 0) != 0) + panic("%s: pp cannot allocate DVMA address", + sc->dv_name); + } + + /* Setup DMA control register */ + csr = L64854_GCSR(sc); + csr &= ~L64854_BURST_SIZE; + if (sc->sc_burst == 32) { + csr |= L64854_BURST_32; + } else if (sc->sc_burst == 16) { + csr |= L64854_BURST_16; + } else { + csr |= L64854_BURST_0; + } + csr |= P_EN_DMA|P_INT_EN|P_EN_CNT; +#if 0 + /* This bit is read-only in PP csr register */ + if (datain) + csr |= P_WRITE; + else + csr &= ~P_WRITE; +#endif + L64854_SCSR(sc, csr); + + return (0); +} +/* + * Parallel port DMA interrupt. + */ +int +lsi64854_pp_intr(void *arg) +{ + struct lsi64854_softc *sc = arg; + int ret, trans, resid = 0; + u_int32_t csr; + + csr = L64854_GCSR(sc); + + DPRINTF(LDB_PP, ("%s: pp intr: addr 0x%x, csr %b\n", sc->dv_name, + bus_space_read_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR), + csr, PDMACSR_BITS)); + + if (csr & (P_ERR_PEND|P_SLAVE_ERR)) { + resid = bus_space_read_4(sc->sc_regt, sc->sc_regh, + L64854_REG_CNT); + printf("%s: pp error: resid %d csr=%b\n", sc->dv_name, resid, + csr, PDMACSR_BITS); + csr &= ~P_EN_DMA; /* Stop DMA */ + /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ + csr |= P_INVALIDATE|P_SLAVE_ERR; + L64854_SCSR(sc, csr); + return (1); + } + + ret = (csr & P_INT_PEND) != 0; + + if (sc->sc_active != 0) { + DMA_DRAIN(sc, 0); + resid = bus_space_read_4(sc->sc_regt, sc->sc_regh, + L64854_REG_CNT); + } + + /* DMA has stopped */ + csr &= ~D_EN_DMA; + L64854_SCSR(sc, csr); + sc->sc_active = 0; + + trans = sc->sc_dmasize - resid; + if (trans < 0) { /* transferred < 0 ? */ + trans = sc->sc_dmasize; + } + *sc->sc_dmalen -= trans; + *sc->sc_dmaaddr += trans; + +#if 0 /* XXX */ + if (sc->sc_dmamap->dm_nsegs > 0) { + bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap, + (csr & D_WRITE) != 0 + ? BUS_DMASYNC_POSTREAD + : BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap); + } +#endif + + return (ret != 0); +} diff --git a/sys/sparc64/sbus/lsi64854reg.h b/sys/sparc64/sbus/lsi64854reg.h new file mode 100644 index 0000000..763d312 --- /dev/null +++ b/sys/sparc64/sbus/lsi64854reg.h @@ -0,0 +1,205 @@ +/* $NetBSD: lsi64854reg.h,v 1.4 1998/09/21 21:26:52 pk Exp $ */ + +/*- + * Copyright (c) 1998 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Paul Kranenburg. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* $FreeBSD$ */ + +/* + * LSI 64854 DMA engine. Contains three independent channels + * designed to interface with (a) a NCR539X SCSI controller, + * (b) a AM7990 Ethernet controller, (c) Parallel port hardware.. + */ + +/* + * Register offsets to bus handle. + */ +#define L64854_REG_CSR 0 /* Control bits */ +#define L64854_REG_ADDR 4 /* DMA Address */ +#define L64854_REG_CNT 8 /* DMA count */ +#define L64854_REG_CNT_MASK 0x00ffffff /* only 24 bits */ +#define L64854_REG_ENBAR 12 /* ENET Base register */ +#define L64854_REG_TEST 12 /* SCSI Test register */ +#define L64854_REG_HCR 16 /* PP Hardware Configuration */ +#define L64854_REG_OCR 18 /* PP Operation Configuration */ +#define L64854_REG_DR 20 /* PP Data register */ +#define L64854_REG_TCR 21 /* PP Transfer Control */ +#define L64854_REG_OR 22 /* PP Output register */ +#define L64854_REG_IR 23 /* PP Input register */ +#define L64854_REG_ICR 24 /* PP Interrupt Control */ + + +/* + * Control bits common to all three channels. + */ +#define L64854_INT_PEND 0x00000001 /* Interrupt pending */ +#define L64854_ERR_PEND 0x00000002 /* Error pending */ +#define L64854_DRAINING 0x0000000c /* FIFO draining */ +#define L64854_INT_EN 0x00000010 /* Interrupt enable */ +#define L64854_INVALIDATE 0x00000020 /* Invalidate FIFO */ +#define L64854_SLAVE_ERR 0x00000040 /* Slave access size error */ +#define L64854_RESET 0x00000080 /* Reset device */ +#define L64854_WRITE 0x00000100 /* 1: xfer to memory */ +#define L64854_EN_DMA 0x00000200 /* enable DMA transfers */ + +#define L64854_BURST_SIZE 0x000c0000 /* Read/write burst size */ +#define L64854_BURST_0 0x00080000 /* no bursts (SCSI-only) */ +#define L64854_BURST_16 0x00000000 /* 16-byte bursts */ +#define L64854_BURST_32 0x00040000 /* 32-byte bursts */ +#define L64854_BURST_64 0x000c0000 /* 64-byte bursts (fas) */ + +#define L64854_RST_FAS366 0x08000000 /* FAS366 hardware reset */ + +#define L64854_DEVID 0xf0000000 /* device ID bits */ + +/* + * SCSI DMA control bits. + */ +#define D_INT_PEND L64854_INT_PEND /* interrupt pending */ +#define D_ERR_PEND L64854_ERR_PEND /* error pending */ +#define D_DRAINING L64854_DRAINING /* fifo draining */ +#define D_INT_EN L64854_INT_EN /* interrupt enable */ +#define D_INVALIDATE L64854_INVALIDATE/* invalidate fifo */ +#define D_SLAVE_ERR L64854_SLAVE_ERR/* slave access size error */ +#define D_RESET L64854_RESET /* reset scsi */ +#define D_WRITE L64854_WRITE /* 1 = dev -> mem */ +#define D_EN_DMA L64854_EN_DMA /* enable DMA requests */ +#define D_EN_CNT 0x00002000 /* enable byte counter */ +#define D_TC 0x00004000 /* terminal count */ +#define D_WIDE_EN 0x00008000 /* enable wide mode SBUS DMA (fas) */ +#define D_DSBL_CSR_DRN 0x00010000 /* disable fifo drain on csr */ +#define D_DSBL_SCSI_DRN 0x00020000 /* disable fifo drain on reg */ + +#define D_DIAG 0x00100000 /* disable fifo drain on addr */ +#define D_TWO_CYCLE 0x00200000 /* 2 clocks per transfer */ +#define D_FASTER 0x00400000 /* 3 clocks per transfer */ +#define D_TCI_DIS 0x00800000 /* disable intr on D_TC */ +#define D_EN_NEXT 0x01000000 /* enable auto next address */ +#define D_DMA_ON 0x02000000 /* enable dma from scsi XXX */ +#define D_DSBL_PARITY_CHK \ + 0x02000000 /* disable checking for parity on bus (default 1:fas) */ +#define D_A_LOADED 0x04000000 /* address loaded */ +#define D_NA_LOADED 0x08000000 /* next address loaded */ +#define D_HW_RESET_FAS366 \ + 0x08000000 /* hardware reset FAS366 (fas) */ +#define D_DEV_ID L64854_DEVID /* device ID */ +#define DMAREV_0 0x00000000 /* Sunray DMA */ +#define DMAREV_ESC 0x40000000 /* DMA ESC array */ +#define DMAREV_1 0x80000000 /* 'DMA' */ +#define DMAREV_PLUS 0x90000000 /* 'DMA+' */ +#define DMAREV_2 0xa0000000 /* 'DMA2' */ +#define DMAREV_HME 0xb0000000 /* 'HME' */ + +/* + * revisions 0,1 and ESC have different bits. + */ +#define D_ESC_DRAIN 0x00000040 /* rev0,1,esc: drain fifo */ +#define D_ESC_R_PEND 0x00000400 /* rev0,1: request pending */ +#define D_ESC_BURST 0x00000800 /* DMA ESC: 16 byte bursts */ +#define D_ESC_AUTODRAIN 0x00040000 /* DMA ESC: Auto-drain */ + +#define DDMACSR_BITS "\177\020" \ + "b\00INT\0b\01ERR\0f\02\02DRAINING\0b\04IEN\0" \ + "b\06SLVERR\0b\07RST\0b\10WRITE\0b\11ENDMA\0" \ + "b\15ENCNT\0b\16TC\0\b\20DSBL_CSR_DRN\0" \ + "b\21DSBL_SCSI_DRN\0f\22\2BURST\0b\25TWOCYCLE\0" \ + "b\26FASTER\0b\27TCIDIS\0b\30ENNXT\0b\031DMAON\0" \ + "b\32ALOADED\0b\33NALOADED\0" + + +/* + * ENET DMA control bits. + */ +#define E_INT_PEND L64854_INT_PEND /* interrupt pending */ +#define E_ERR_PEND L64854_ERR_PEND /* error pending */ +#define E_DRAINING L64854_DRAINING /* fifo draining */ +#define E_INT_EN L64854_INT_EN /* interrupt enable */ +#define E_INVALIDATE L64854_INVALIDATE/* invalidate fifo */ +#define E_SLAVE_ERR L64854_SLAVE_ERR/* slave access size error */ +#define E_RESET L64854_RESET /* reset ENET */ +#define E_reserved1 0x00000300 /* */ +#define E_DRAIN 0x00000400 /* force Ecache drain */ +#define E_DSBL_WR_DRN 0x00000800 /* disable Ecache drain on .. */ +#define E_DSBL_RD_DRN 0x00001000 /* disable Ecache drain on .. */ +#define E_reserved2 0x00006000 /* */ +#define E_ILACC 0x00008000 /* ... */ +#define E_DSBL_BUF_WR 0x00010000 /* no buffering of slave writes */ +#define E_DSBL_WR_INVAL 0x00020000 /* no Ecache invalidate on slave writes */ + +#define E_reserved3 0x00100000 /* */ +#define E_LOOP_TEST 0x00200000 /* loopback mode */ +#define E_TP_AUI 0x00400000 /* 1 for TP, 0 for AUI */ +#define E_reserved4 0x0c800000 /* */ +#define E_DEV_ID L64854_DEVID /* ID bits */ + +#define EDMACSR_BITS "\177\020" \ + "b\00INT\0b\01ERR\0f\02\02DRAINING\0b\04IEN\0" \ + "b\06SLVERR\0b\07RST\0b\10WRITE\0b\12DRAIN\0" \ + "b\13DSBL_WR_DRN\0b\14DSBL_RD_DRN\0b\17ILACC\0" \ + "b\20DSBL_BUF_WR\0b\21DSBL_WR_INVAL\0" \ + "b\25LOOPTEST\0b\26TP\0" + +/* + * PP DMA control bits. + */ +#define P_INT_PEND L64854_INT_PEND /* interrupt pending */ +#define P_ERR_PEND L64854_ERR_PEND /* error pending */ +#define P_DRAINING L64854_DRAINING /* fifo draining */ +#define P_INT_EN L64854_INT_EN /* interrupt enable */ +#define P_INVALIDATE L64854_INVALIDATE/* invalidate fifo */ +#define P_SLAVE_ERR L64854_SLAVE_ERR/* slave access size error */ +#define P_RESET L64854_RESET /* reset PP */ +#define P_WRITE L64854_WRITE /* 1: xfer to memory */ +#define P_EN_DMA L64854_EN_DMA /* enable DMA transfers */ +#define P_reserved1 0x00001c00 /* */ +#define P_EN_CNT 0x00002000 /* enable counter */ +#define P_TC 0x00004000 /* terminal count */ +#define P_reserved2 0x00038000 /* */ + +#define P_DIAG 0x00100000 /* ... */ +#define P_reserved3 0x00600000 /* */ +#define P_TCI_DIS 0x00800000 /* no interrupt on terminal count */ +#define P_EN_NEXT 0x01000000 /* enable DMA chaining */ +#define P_DMA_ON 0x02000000 /* DMA xfers enabled */ +#define P_A_LOADED 0x04000000 /* addr and byte count valid */ +#define P_NA_LOADED 0x08000000 /* next addr & count valid but not used */ +#define P_DEV_ID L64854_DEVID /* ID bits */ + +#define PDMACSR_BITS "\177\020" \ + "b\00INT\0b\01ERR\0f\02\02DRAINING\0b\04IEN\0" \ + "b\06SLVERR\0b\07RST\0b\10WRITE\0b\11ENDMA\0" \ + "b\15ENCNT\0b\16TC\0\b\24DIAG\0b\27TCIDIS\0" \ + "b\30ENNXT\0b\031DMAON\0b\32ALOADED\0b\33NALOADED\0" diff --git a/sys/sparc64/sbus/lsi64854var.h b/sys/sparc64/sbus/lsi64854var.h new file mode 100644 index 0000000..04b2297 --- /dev/null +++ b/sys/sparc64/sbus/lsi64854var.h @@ -0,0 +1,114 @@ +/* $NetBSD: lsi64854var.h,v 1.4 2001/03/29 02:58:39 petrov Exp $ */ + +/*- + * Copyright (c) 1998 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Paul Kranenburg. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* $FreeBSD$ */ + +struct lsi64854_softc { + device_t sc_dev; + const char *dv_name; + + int sc_rid; + struct resource *sc_res; + bus_space_handle_t sc_regh; + bus_space_tag_t sc_regt; + u_int sc_rev; /* revision */ + int sc_burst; /* max suported burst size */ + + int sc_channel; +#define L64854_CHANNEL_SCSI 1 +#define L64854_CHANNEL_ENET 2 +#define L64854_CHANNEL_PP 3 + void *sc_client; + + int sc_active; /* DMA active ? */ + bus_dmamap_t sc_dmamap; /* DMA map for bus_dma_* */ + + bus_dma_tag_t sc_parent_dmat; + bus_dma_tag_t sc_buffer_dmat; + int sc_datain; + size_t sc_dmasize; + caddr_t *sc_dmaaddr; + size_t *sc_dmalen; + + void (*reset)(struct lsi64854_softc *);/* reset routine */ + int (*setup)(struct lsi64854_softc *, caddr_t *, size_t *, + int, size_t *); /* DMA setup */ + int (*intr)(void *); /* interrupt handler */ + + int (*sc_intrchain)(void *); /* next handler in intr chain */ + void *sc_intrchainarg; /* arg for next intr handler */ + + u_int sc_dmactl; +}; + +#define L64854_GCSR(sc) \ + (bus_space_read_4((sc)->sc_regt, (sc)->sc_regh, L64854_REG_CSR)) + +#define L64854_SCSR(sc, csr) \ + bus_space_write_4((sc)->sc_regt, (sc)->sc_regh, L64854_REG_CSR, csr) + + +/* + * DMA engine interface functions. + */ +#define DMA_RESET(sc) (((sc)->reset)(sc)) +#define DMA_INTR(sc) (((sc)->intr)(sc)) +#define DMA_SETUP(sc, a, l, d, s) (((sc)->setup)(sc, a, l, d, s)) + +#define DMA_ISACTIVE(sc) ((sc)->sc_active) + +#define DMA_ENINTR(sc) do { \ + u_int32_t csr = L64854_GCSR(sc); \ + csr |= L64854_INT_EN; \ + L64854_SCSR(sc, csr); \ +} while (0) + +#define DMA_ISINTR(sc) (L64854_GCSR(sc) & (D_INT_PEND|D_ERR_PEND)) + +#define DMA_GO(sc) do { \ + u_int32_t csr = L64854_GCSR(sc); \ + csr |= D_EN_DMA; \ + L64854_SCSR(sc, csr); \ + sc->sc_active = 1; \ +} while (0) + + +void lsi64854_attach(struct lsi64854_softc *); +int lsi64854_scsi_intr(void *); +int lsi64854_enet_intr(void *); +int lsi64854_pp_intr(void *); |