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authorandrew <andrew@FreeBSD.org>2015-04-11 17:16:23 +0000
committerandrew <andrew@FreeBSD.org>2015-04-11 17:16:23 +0000
commite2a65d5cfa2a52472daa9b9658f4fa10f742291f (patch)
tree3242f4dc9f4677a166d03c3acecc2475385f4f3d /sys/sparc64
parent7f65d178b4fad420cb01a2ff4b3163278d3025dc (diff)
downloadFreeBSD-src-e2a65d5cfa2a52472daa9b9658f4fa10f742291f.zip
FreeBSD-src-e2a65d5cfa2a52472daa9b9658f4fa10f742291f.tar.gz
Add support for the uart classes to set their default register shift value.
This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week
Diffstat (limited to 'sys/sparc64')
-rw-r--r--sys/sparc64/pci/sbbc.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/sys/sparc64/pci/sbbc.c b/sys/sparc64/pci/sbbc.c
index c19fb71..f1e7fab 100644
--- a/sys/sparc64/pci/sbbc.c
+++ b/sys/sparc64/pci/sbbc.c
@@ -813,7 +813,8 @@ struct uart_class uart_sbbc_class = {
sizeof(struct uart_softc),
.uc_ops = &sbbc_uart_ops,
.uc_range = 1,
- .uc_rclk = 0x5bbc /* arbitrary */
+ .uc_rclk = 0x5bbc, /* arbitrary */
+ .uc_rshift = 0
};
#define SIGCHG(c, i, s, d) \
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