- In the spirit of r212559 add a comment describing what will eventually

  lower the PIL.
- Just as with the AP ensure that the (S)TICK timer(s) are in a known
  state when starting BSPs.

1 files changed, 11 insertions, 1 deletions

diff --git a/sys/sparc64/sparc64/mp_machdep.c b/sys/sparc64/sparc64/mp_machdep.c
index 29c7434..5a4bba6 100644
--- a/sys/sparc64/sparc64/mp_machdep.c
+++ b/sys/sparc64/sparc64/mp_machdep.c
@@ -433,6 +433,12 @@ cpu_mp_bootstrap(struct pcpu *pc)
 	 */
 	cache_enable(pc->pc_impl);
 
+	/*
+	 * Clear (S)TICK timer(s) (including NPT) and ensure they are stopped.
+	 */
+	tick_clear(pc->pc_impl);
+	tick_stop(pc->pc_impl);
+
 	/* Lock the kernel TSB in the TLB. */
 	pmap_map_tsb();
 
@@ -445,7 +451,11 @@ cpu_mp_bootstrap(struct pcpu *pc)
 	/* Initialize global registers. */
 	cpu_setregs(pc);
 
-	/* Enable interrupts. */
+	/*
+	 * Enable interrupts.
+	 * Note that the PIL we be lowered indirectly via sched_throw(NULL)
+	 * when fake spinlock held by the idle thread eventually is released.
+	 */
 	wrpr(pstate, 0, PSTATE_KERNEL);
 
 	smp_cpus++;