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| author | marius <marius@FreeBSD.org> | 2008-08-23 20:53:27 +0000 |
|---|---|---|
| committer | marius <marius@FreeBSD.org> | 2008-08-23 20:53:27 +0000 |
| commit | 5f4692e243513a891d9fecdfa191882717341244 (patch) | |
| tree | 4cfbec1e1a9fd171e83e0e3259b4baf42defc1cf /sys/sparc64 | |
| parent | d95796acc990d45215e1c389657324a320cffd8a (diff) | |
| download | FreeBSD-src-5f4692e243513a891d9fecdfa191882717341244.zip FreeBSD-src-5f4692e243513a891d9fecdfa191882717341244.tar.gz | |
Update the comment regarding the workaround for the BlackBird
TICK_COMPARE bug and the instruction alignment used for it based
on information found in the OpenSolaris source.
MFC after: 3 days
Diffstat (limited to 'sys/sparc64')
| -rw-r--r-- | sys/sparc64/include/cpufunc.h | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/sys/sparc64/include/cpufunc.h b/sys/sparc64/include/cpufunc.h index fca87e5..fca5984 100644 --- a/sys/sparc64/include/cpufunc.h +++ b/sys/sparc64/include/cpufunc.h @@ -177,14 +177,16 @@ int fasword32(u_long asi, void *addr, uint32_t *val); * Macro intended to be used instead of wr(asr23, val, xor) for writing to * the TICK_COMPARE register in order to avoid a bug in BlackBird CPUs that * can cause these writes to fail under certain condidtions which in turn - * causes the hardclock to stop. The workaround is to perform the write - * at the beginning of an I-Cache line directly followed by a dummy read. + * causes the hardclock to stop. The workaround is to read the TICK_COMPARE + * register back immediately after writing to it with these two instructions + * aligned to a quadword boundary in order to ensure that I$ misses won't + * split them up. */ #define wrtickcmpr(val, xor) ({ \ __asm __volatile( \ " ba,pt %%xcc, 1f ; " \ " nop ; " \ - " .align 64 ; " \ + " .align 128 ; " \ "1: wr %0, %1, %%asr23 ; " \ " rd %%asr23, %%g0 ; " \ : : "r" (val), "rI" (xor)); \ |
